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MODDMA/MODDMA.h@0:08a4d61cd84c, 2011-09-20 (annotated)

Committer:
mark2r2
Date:
Tue Sep 20 12:46:26 2011 +0000
Revision:
0:08a4d61cd84c
V1.0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mark2r2 0:08a4d61cd84c 1 /*
mark2r2 0:08a4d61cd84c 2 Copyright (c) 2010 Andy Kirkham
mark2r2 0:08a4d61cd84c 3
mark2r2 0:08a4d61cd84c 4 Permission is hereby granted, free of charge, to any person obtaining a copy
mark2r2 0:08a4d61cd84c 5 of this software and associated documentation files (the "Software"), to deal
mark2r2 0:08a4d61cd84c 6 in the Software without restriction, including without limitation the rights
mark2r2 0:08a4d61cd84c 7 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
mark2r2 0:08a4d61cd84c 8 copies of the Software, and to permit persons to whom the Software is
mark2r2 0:08a4d61cd84c 9 furnished to do so, subject to the following conditions:
mark2r2 0:08a4d61cd84c 10
mark2r2 0:08a4d61cd84c 11 The above copyright notice and this permission notice shall be included in
mark2r2 0:08a4d61cd84c 12 all copies or substantial portions of the Software.
mark2r2 0:08a4d61cd84c 13
mark2r2 0:08a4d61cd84c 14 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
mark2r2 0:08a4d61cd84c 15 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
mark2r2 0:08a4d61cd84c 16 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
mark2r2 0:08a4d61cd84c 17 AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
mark2r2 0:08a4d61cd84c 18 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
mark2r2 0:08a4d61cd84c 19 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
mark2r2 0:08a4d61cd84c 20 THE SOFTWARE.
mark2r2 0:08a4d61cd84c 21
mark2r2 0:08a4d61cd84c 22 @file MODDMA.h
mark2r2 0:08a4d61cd84c 23 @purpose Adds DMA controller and multiple transfer configurations
mark2r2 0:08a4d61cd84c 24 @version see ChangeLog.c
mark2r2 0:08a4d61cd84c 25 @date Nov 2010
mark2r2 0:08a4d61cd84c 26 @author Andy Kirkham
mark2r2 0:08a4d61cd84c 27 */
mark2r2 0:08a4d61cd84c 28
mark2r2 0:08a4d61cd84c 29 #ifndef MODDMA_H
mark2r2 0:08a4d61cd84c 30 #define MODDMA_H
mark2r2 0:08a4d61cd84c 31
mark2r2 0:08a4d61cd84c 32 /** @defgroup API The MODDMA API */
mark2r2 0:08a4d61cd84c 33 /** @defgroup MISC Misc MODSERIAL functions */
mark2r2 0:08a4d61cd84c 34 /** @defgroup INTERNALS MODSERIAL Internals */
mark2r2 0:08a4d61cd84c 35
mark2r2 0:08a4d61cd84c 36 #include "mbed.h"
mark2r2 0:08a4d61cd84c 37 #include "iomacros.h"
mark2r2 0:08a4d61cd84c 38
mark2r2 0:08a4d61cd84c 39 namespace AjK {
mark2r2 0:08a4d61cd84c 40
mark2r2 0:08a4d61cd84c 41 /**
mark2r2 0:08a4d61cd84c 42 * @brief The MODDMA configuration system
mark2r2 0:08a4d61cd84c 43 * @author Andy Kirkham
mark2r2 0:08a4d61cd84c 44 * @see http://mbed.org/cookbook/MODDMA_Config
mark2r2 0:08a4d61cd84c 45 * @see MODDMA
mark2r2 0:08a4d61cd84c 46 * @see API
mark2r2 0:08a4d61cd84c 47 *
mark2r2 0:08a4d61cd84c 48 * <b>MODDMA_Config</b> defines a configuration that can be passed to the MODDMA controller
mark2r2 0:08a4d61cd84c 49 * instance to perform a GPDMA data transfer.
mark2r2 0:08a4d61cd84c 50 */
mark2r2 0:08a4d61cd84c 51 class MODDMA_Config {
mark2r2 0:08a4d61cd84c 52 protected:
mark2r2 0:08a4d61cd84c 53
mark2r2 0:08a4d61cd84c 54 // *****************************************
mark2r2 0:08a4d61cd84c 55 // From GPDMA by NXP MCU SW Application Team
mark2r2 0:08a4d61cd84c 56 // *****************************************
mark2r2 0:08a4d61cd84c 57
mark2r2 0:08a4d61cd84c 58 uint32_t ChannelNum; //!< DMA channel number, should be in range from 0 to 7.
mark2r2 0:08a4d61cd84c 59 uint32_t TransferSize; //!< Length/Size of transfer
mark2r2 0:08a4d61cd84c 60 uint32_t TransferWidth; //!< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_m2m only
mark2r2 0:08a4d61cd84c 61 uint32_t SrcMemAddr; //!< Physical Src Addr, used in case TransferType is chosen as MODDMA::GPDMA_TRANSFERTYPE::m2m or MODDMA::GPDMA_TRANSFERTYPE::m2p
mark2r2 0:08a4d61cd84c 62 uint32_t DstMemAddr; //!< Physical Destination Address, used in case TransferType is chosen as MODDMA::GPDMA_TRANSFERTYPE::m2m or MODDMA::GPDMA_TRANSFERTYPE::p2m
mark2r2 0:08a4d61cd84c 63 uint32_t TransferType; //!< Transfer Type
mark2r2 0:08a4d61cd84c 64 uint32_t SrcConn; //!< Peripheral Source Connection type, used in case TransferType is chosen as
mark2r2 0:08a4d61cd84c 65 uint32_t DstConn; //!< Peripheral Destination Connection type, used in case TransferType is chosen as
mark2r2 0:08a4d61cd84c 66 uint32_t DMALLI; //!< Linker List Item structure data address if there's no Linker List, set as '0'
mark2r2 0:08a4d61cd84c 67 uint32_t DMACSync; //!< DMACSync if required.
mark2r2 0:08a4d61cd84c 68
mark2r2 0:08a4d61cd84c 69 // Mbed specifics.
mark2r2 0:08a4d61cd84c 70
mark2r2 0:08a4d61cd84c 71 public:
mark2r2 0:08a4d61cd84c 72
mark2r2 0:08a4d61cd84c 73 MODDMA_Config() {
mark2r2 0:08a4d61cd84c 74 isrIntTCStat = new FunctionPointer;
mark2r2 0:08a4d61cd84c 75 isrIntErrStat = new FunctionPointer;
mark2r2 0:08a4d61cd84c 76 ChannelNum = 0xFFFF;
mark2r2 0:08a4d61cd84c 77 TransferSize = 0;
mark2r2 0:08a4d61cd84c 78 TransferWidth = 0;
mark2r2 0:08a4d61cd84c 79 SrcMemAddr = 0;
mark2r2 0:08a4d61cd84c 80 DstMemAddr = 0;
mark2r2 0:08a4d61cd84c 81 TransferType = 0;
mark2r2 0:08a4d61cd84c 82 SrcConn = 0;
mark2r2 0:08a4d61cd84c 83 DstConn = 0;
mark2r2 0:08a4d61cd84c 84 DMALLI = 0;
mark2r2 0:08a4d61cd84c 85 DMACSync = 0;
mark2r2 0:08a4d61cd84c 86 }
mark2r2 0:08a4d61cd84c 87
mark2r2 0:08a4d61cd84c 88 ~MODDMA_Config() {
mark2r2 0:08a4d61cd84c 89 delete(isrIntTCStat);
mark2r2 0:08a4d61cd84c 90 delete(isrIntErrStat);
mark2r2 0:08a4d61cd84c 91 }
mark2r2 0:08a4d61cd84c 92
mark2r2 0:08a4d61cd84c 93 class MODDMA_Config * channelNum(uint32_t n) { ChannelNum = n & 0x7; return this; }
mark2r2 0:08a4d61cd84c 94 class MODDMA_Config * transferSize(uint32_t n) { TransferSize = n; return this; }
mark2r2 0:08a4d61cd84c 95 class MODDMA_Config * transferWidth(uint32_t n) { TransferWidth = n; return this; }
mark2r2 0:08a4d61cd84c 96 class MODDMA_Config * srcMemAddr(uint32_t n) { SrcMemAddr = n; return this; }
mark2r2 0:08a4d61cd84c 97 class MODDMA_Config * dstMemAddr(uint32_t n) { DstMemAddr = n; return this; }
mark2r2 0:08a4d61cd84c 98 class MODDMA_Config * transferType(uint32_t n) { TransferType = n; return this; }
mark2r2 0:08a4d61cd84c 99 class MODDMA_Config * srcConn(uint32_t n) { SrcConn = n; return this; }
mark2r2 0:08a4d61cd84c 100 class MODDMA_Config * dstConn(uint32_t n) { DstConn = n; return this; }
mark2r2 0:08a4d61cd84c 101 class MODDMA_Config * dmaLLI(uint32_t n) { DMALLI = n; return this; }
mark2r2 0:08a4d61cd84c 102 class MODDMA_Config * dmacSync(uint32_t n) { DMACSync = n; return this; }
mark2r2 0:08a4d61cd84c 103
mark2r2 0:08a4d61cd84c 104 uint32_t channelNum(void) { return ChannelNum; }
mark2r2 0:08a4d61cd84c 105 uint32_t transferSize(void) { return TransferSize; }
mark2r2 0:08a4d61cd84c 106 uint32_t transferWidth(void) { return TransferWidth; }
mark2r2 0:08a4d61cd84c 107 uint32_t srcMemAddr(void) { return SrcMemAddr; }
mark2r2 0:08a4d61cd84c 108 uint32_t dstMemAddr(void) { return DstMemAddr; }
mark2r2 0:08a4d61cd84c 109 uint32_t transferType(void) { return TransferType; }
mark2r2 0:08a4d61cd84c 110 uint32_t srcConn(void) { return SrcConn; }
mark2r2 0:08a4d61cd84c 111 uint32_t dstConn(void) { return DstConn; }
mark2r2 0:08a4d61cd84c 112 uint32_t dmaLLI(void) { return DMALLI; }
mark2r2 0:08a4d61cd84c 113 uint32_t dmacSync(void) { return DMACSync; }
mark2r2 0:08a4d61cd84c 114
mark2r2 0:08a4d61cd84c 115 /**
mark2r2 0:08a4d61cd84c 116 * Attach a callback to the TC IRQ configuration.
mark2r2 0:08a4d61cd84c 117 *
mark2r2 0:08a4d61cd84c 118 * @param fptr A function pointer to call
mark2r2 0:08a4d61cd84c 119 * @return this
mark2r2 0:08a4d61cd84c 120 */
mark2r2 0:08a4d61cd84c 121 class MODDMA_Config * attach_tc(void (*fptr)(void)) {
mark2r2 0:08a4d61cd84c 122 isrIntTCStat->attach(fptr);
mark2r2 0:08a4d61cd84c 123 return this;
mark2r2 0:08a4d61cd84c 124 }
mark2r2 0:08a4d61cd84c 125
mark2r2 0:08a4d61cd84c 126 /**
mark2r2 0:08a4d61cd84c 127 * Attach a callback to the ERR IRQ configuration.
mark2r2 0:08a4d61cd84c 128 *
mark2r2 0:08a4d61cd84c 129 * @param fptr A function pointer to call
mark2r2 0:08a4d61cd84c 130 * @return this
mark2r2 0:08a4d61cd84c 131 */
mark2r2 0:08a4d61cd84c 132 class MODDMA_Config * attach_err(void (*fptr)(void)) {
mark2r2 0:08a4d61cd84c 133 isrIntErrStat->attach(fptr);
mark2r2 0:08a4d61cd84c 134 return this;
mark2r2 0:08a4d61cd84c 135 }
mark2r2 0:08a4d61cd84c 136
mark2r2 0:08a4d61cd84c 137 /**
mark2r2 0:08a4d61cd84c 138 * Attach a callback to the TC IRQ configuration.
mark2r2 0:08a4d61cd84c 139 *
mark2r2 0:08a4d61cd84c 140 * @param tptr A template pointer to the calling object
mark2r2 0:08a4d61cd84c 141 * @param mptr A method pointer within the object to call.
mark2r2 0:08a4d61cd84c 142 * @return this
mark2r2 0:08a4d61cd84c 143 */
mark2r2 0:08a4d61cd84c 144 template<typename T>
mark2r2 0:08a4d61cd84c 145 class MODDMA_Config * attach_tc(T* tptr, void (T::*mptr)(void)) {
mark2r2 0:08a4d61cd84c 146 if((mptr != NULL) && (tptr != NULL)) {
mark2r2 0:08a4d61cd84c 147 isrIntTCStat->attach(tptr, mptr);
mark2r2 0:08a4d61cd84c 148 }
mark2r2 0:08a4d61cd84c 149 return this;
mark2r2 0:08a4d61cd84c 150 }
mark2r2 0:08a4d61cd84c 151
mark2r2 0:08a4d61cd84c 152 /**
mark2r2 0:08a4d61cd84c 153 * Attach a callback to the ERR IRQ configuration.
mark2r2 0:08a4d61cd84c 154 *
mark2r2 0:08a4d61cd84c 155 * @param tptr A template pointer to the calling object
mark2r2 0:08a4d61cd84c 156 * @param mptr A method pointer within the object to call.
mark2r2 0:08a4d61cd84c 157 * @return this
mark2r2 0:08a4d61cd84c 158 */
mark2r2 0:08a4d61cd84c 159 template<typename T>
mark2r2 0:08a4d61cd84c 160 class MODDMA_Config * attach_err(T* tptr, void (T::*mptr)(void)) {
mark2r2 0:08a4d61cd84c 161 if((mptr != NULL) && (tptr != NULL)) {
mark2r2 0:08a4d61cd84c 162 isrIntErrStat->attach(tptr, mptr);
mark2r2 0:08a4d61cd84c 163 }
mark2r2 0:08a4d61cd84c 164 return this;
mark2r2 0:08a4d61cd84c 165 }
mark2r2 0:08a4d61cd84c 166 FunctionPointer *isrIntTCStat;
mark2r2 0:08a4d61cd84c 167 FunctionPointer *isrIntErrStat;
mark2r2 0:08a4d61cd84c 168 };
mark2r2 0:08a4d61cd84c 169
mark2r2 0:08a4d61cd84c 170 /**
mark2r2 0:08a4d61cd84c 171 * @brief The MODDMA configuration system (linked list items)
mark2r2 0:08a4d61cd84c 172 * @author Andy Kirkham
mark2r2 0:08a4d61cd84c 173 * @see http://mbed.org/cookbook/MODDMA_Config
mark2r2 0:08a4d61cd84c 174 * @see MODDMA
mark2r2 0:08a4d61cd84c 175 * @see MODDMA_Config
mark2r2 0:08a4d61cd84c 176 * @see API
mark2r2 0:08a4d61cd84c 177 */
mark2r2 0:08a4d61cd84c 178 class MODDMA_LLI {
mark2r2 0:08a4d61cd84c 179 public:
mark2r2 0:08a4d61cd84c 180 class MODDMA_LLI *srcAddr(uint32_t n) { SrcAddr = n; return this; }
mark2r2 0:08a4d61cd84c 181 class MODDMA_LLI *dstAddr(uint32_t n) { DstAddr = n; return this; }
mark2r2 0:08a4d61cd84c 182 class MODDMA_LLI *nextLLI(uint32_t n) { NextLLI = n; return this; }
mark2r2 0:08a4d61cd84c 183 class MODDMA_LLI *control(uint32_t n) { Control = n; return this; }
mark2r2 0:08a4d61cd84c 184 uint32_t srcAddr(void) { return SrcAddr; }
mark2r2 0:08a4d61cd84c 185 uint32_t dstAddr(void) { return DstAddr; }
mark2r2 0:08a4d61cd84c 186 uint32_t nextLLI(void) { return NextLLI; }
mark2r2 0:08a4d61cd84c 187 uint32_t control(void) { return Control; }
mark2r2 0:08a4d61cd84c 188
mark2r2 0:08a4d61cd84c 189 uint32_t SrcAddr; //!< Source Address
mark2r2 0:08a4d61cd84c 190 uint32_t DstAddr; //!< Destination address
mark2r2 0:08a4d61cd84c 191 uint32_t NextLLI; //!< Next LLI address, otherwise set to '0'
mark2r2 0:08a4d61cd84c 192 uint32_t Control; //!< GPDMA Control of this LLI
mark2r2 0:08a4d61cd84c 193 };
mark2r2 0:08a4d61cd84c 194
mark2r2 0:08a4d61cd84c 195
mark2r2 0:08a4d61cd84c 196
mark2r2 0:08a4d61cd84c 197 /**
mark2r2 0:08a4d61cd84c 198 * @brief MODDMA GPDMA Controller
mark2r2 0:08a4d61cd84c 199 * @author Andy Kirkham
mark2r2 0:08a4d61cd84c 200 * @see http://mbed.org/cookbook/MODDMA
mark2r2 0:08a4d61cd84c 201 * @see example1.cpp
mark2r2 0:08a4d61cd84c 202 * @see API
mark2r2 0:08a4d61cd84c 203 *
mark2r2 0:08a4d61cd84c 204 * <b>MODDMA</b> defines a GPDMA controller and multiple DMA configurations that allow for DMA
mark2r2 0:08a4d61cd84c 205 * transfers from memory to memory, memory to peripheral or peripheral to memory.
mark2r2 0:08a4d61cd84c 206 *
mark2r2 0:08a4d61cd84c 207 * At the heart of the library is the MODDMA class that defines a single instance controller that
mark2r2 0:08a4d61cd84c 208 * manages all the GPDMA hardware registers and interrupts. The controller can accept multiple
mark2r2 0:08a4d61cd84c 209 * configurations that define the channel transfers. Each configuration specifies the source and
mark2r2 0:08a4d61cd84c 210 * destination information and other associated parts to maintain the transfer process.
mark2r2 0:08a4d61cd84c 211 *
mark2r2 0:08a4d61cd84c 212 * Standard example:
mark2r2 0:08a4d61cd84c 213 * @code
mark2r2 0:08a4d61cd84c 214 * #include "mbed.h"
mark2r2 0:08a4d61cd84c 215 * #include "MODDMA.h"
mark2r2 0:08a4d61cd84c 216 *
mark2r2 0:08a4d61cd84c 217 * DigitalOut led1(LED1);
mark2r2 0:08a4d61cd84c 218 * Serial pc(USBTX, USBRX); // tx, rx
mark2r2 0:08a4d61cd84c 219 * MODDMA dma;
mark2r2 0:08a4d61cd84c 220 *
mark2r2 0:08a4d61cd84c 221 * int main() {
mark2r2 0:08a4d61cd84c 222 *
mark2r2 0:08a4d61cd84c 223 * // Create a string buffer to send directly to a Uart/Serial
mark2r2 0:08a4d61cd84c 224 * char s[] = "***DMA*** ABCDEFGHIJKLMNOPQRSTUVWXYZ ***DMA***";
mark2r2 0:08a4d61cd84c 225 *
mark2r2 0:08a4d61cd84c 226 * // Create a transfer configuarion
mark2r2 0:08a4d61cd84c 227 * MODDMA_Config *config = new MODDMA_Config;
mark2r2 0:08a4d61cd84c 228 *
mark2r2 0:08a4d61cd84c 229 * // Provide a "minimal" setup for demo purposes.
mark2r2 0:08a4d61cd84c 230 * config
mark2r2 0:08a4d61cd84c 231 * ->channelNum ( MODDMA::Channel_0 ) // The DMA channel to use.
mark2r2 0:08a4d61cd84c 232 * ->srcMemAddr ( (uint32_t) &s ) // A pointer to the buffer to send.
mark2r2 0:08a4d61cd84c 233 * ->transferSize ( sizeof(s) ) // The size of that buffer.
mark2r2 0:08a4d61cd84c 234 * ->transferType ( MODDMA::m2p ) // Source is memory, destination is peripheral
mark2r2 0:08a4d61cd84c 235 * ->dstConn ( MODDMA::UART0_Tx ) // Specifically, peripheral is Uart0 TX (USBTX, USBRX)
mark2r2 0:08a4d61cd84c 236 * ; // config end.
mark2r2 0:08a4d61cd84c 237 *
mark2r2 0:08a4d61cd84c 238 * // Pass the configuration to the MODDMA controller.
mark2r2 0:08a4d61cd84c 239 * dma.Setup( config );
mark2r2 0:08a4d61cd84c 240 *
mark2r2 0:08a4d61cd84c 241 * // Enable the channel and begin transfer.
mark2r2 0:08a4d61cd84c 242 * dma.Enable( config->channelNum() );
mark2r2 0:08a4d61cd84c 243 *
mark2r2 0:08a4d61cd84c 244 * while(1) {
mark2r2 0:08a4d61cd84c 245 * led1 = !led1;
mark2r2 0:08a4d61cd84c 246 * wait(0.25);
mark2r2 0:08a4d61cd84c 247 * }
mark2r2 0:08a4d61cd84c 248 * }
mark2r2 0:08a4d61cd84c 249 * @endcode
mark2r2 0:08a4d61cd84c 250 */
mark2r2 0:08a4d61cd84c 251 class MODDMA
mark2r2 0:08a4d61cd84c 252 {
mark2r2 0:08a4d61cd84c 253 public:
mark2r2 0:08a4d61cd84c 254
mark2r2 0:08a4d61cd84c 255 //! Channel definitions.
mark2r2 0:08a4d61cd84c 256 enum CHANNELS {
mark2r2 0:08a4d61cd84c 257 Channel_0 = 0 /*!< Channel 0 */
mark2r2 0:08a4d61cd84c 258 , Channel_1 /*!< Channel 1 */
mark2r2 0:08a4d61cd84c 259 , Channel_2 /*!< Channel 2 */
mark2r2 0:08a4d61cd84c 260 , Channel_3 /*!< Channel 3 */
mark2r2 0:08a4d61cd84c 261 , Channel_4 /*!< Channel 4 */
mark2r2 0:08a4d61cd84c 262 , Channel_5 /*!< Channel 5 */
mark2r2 0:08a4d61cd84c 263 , Channel_6 /*!< Channel 6 */
mark2r2 0:08a4d61cd84c 264 , Channel_7 /*!< Channel 7 */
mark2r2 0:08a4d61cd84c 265 };
mark2r2 0:08a4d61cd84c 266
mark2r2 0:08a4d61cd84c 267 //! Interrupt callback types.
mark2r2 0:08a4d61cd84c 268 enum IrqType_t {
mark2r2 0:08a4d61cd84c 269 TcIrq = 0 /*!< Terminal Count interrupt */
mark2r2 0:08a4d61cd84c 270 , ErrIrq /*!< Error interrupt */
mark2r2 0:08a4d61cd84c 271 };
mark2r2 0:08a4d61cd84c 272
mark2r2 0:08a4d61cd84c 273 //! Return status codes.
mark2r2 0:08a4d61cd84c 274 enum Status {
mark2r2 0:08a4d61cd84c 275 Ok = 0 /*!< Ok, suceeded */
mark2r2 0:08a4d61cd84c 276 , Error = -1 /*!< General error */
mark2r2 0:08a4d61cd84c 277 , ErrChInUse = -2 /*!< Specific error, channel in use */
mark2r2 0:08a4d61cd84c 278 };
mark2r2 0:08a4d61cd84c 279
mark2r2 0:08a4d61cd84c 280 //! DMA Connection number definitions
mark2r2 0:08a4d61cd84c 281 enum GPDMA_CONNECTION {
mark2r2 0:08a4d61cd84c 282 SSP0_Tx = 0UL /*!< SSP0 Tx */
mark2r2 0:08a4d61cd84c 283 , SSP0_Rx = 1UL /*!< SSP0 Rx */
mark2r2 0:08a4d61cd84c 284 , SSP1_Tx = 2UL /*!< SSP1 Tx */
mark2r2 0:08a4d61cd84c 285 , SSP1_Rx = 3UL /*!< SSP1 Rx */
mark2r2 0:08a4d61cd84c 286 , ADC = 4UL /*!< ADC */
mark2r2 0:08a4d61cd84c 287 , I2S_Channel_0 = 5UL /*!< I2S channel 0 */
mark2r2 0:08a4d61cd84c 288 , I2S_Channel_1 = 6UL /*!< I2S channel 1 */
mark2r2 0:08a4d61cd84c 289 , DAC = 7UL /*!< DAC */
mark2r2 0:08a4d61cd84c 290 , UART0_Tx = 8UL /*!< UART0 Tx */
mark2r2 0:08a4d61cd84c 291 , UART0_Rx = 9UL /*!< UART0 Rx */
mark2r2 0:08a4d61cd84c 292 , UART1_Tx = 10UL /*!< UART1 Tx */
mark2r2 0:08a4d61cd84c 293 , UART1_Rx = 11UL /*!< UART1 Rx */
mark2r2 0:08a4d61cd84c 294 , UART2_Tx = 12UL /*!< UART2 Tx */
mark2r2 0:08a4d61cd84c 295 , UART2_Rx = 13UL /*!< UART2 Rx */
mark2r2 0:08a4d61cd84c 296 , UART3_Tx = 14UL /*!< UART3 Tx */
mark2r2 0:08a4d61cd84c 297 , UART3_Rx = 15UL /*!< UART3 Rx */
mark2r2 0:08a4d61cd84c 298 , MAT0_0 = 16UL /*!< MAT0.0 */
mark2r2 0:08a4d61cd84c 299 , MAT0_1 = 17UL /*!< MAT0.1 */
mark2r2 0:08a4d61cd84c 300 , MAT1_0 = 18UL /*!< MAT1.0 */
mark2r2 0:08a4d61cd84c 301 , MAT1_1 = 19UL /*!< MAT1.1 */
mark2r2 0:08a4d61cd84c 302 , MAT2_0 = 20UL /**< MAT2.0 */
mark2r2 0:08a4d61cd84c 303 , MAT2_1 = 21UL /*!< MAT2.1 */
mark2r2 0:08a4d61cd84c 304 , MAT3_0 = 22UL /*!< MAT3.0 */
mark2r2 0:08a4d61cd84c 305 , MAT3_1 = 23UL /*!< MAT3.1 */
mark2r2 0:08a4d61cd84c 306 };
mark2r2 0:08a4d61cd84c 307
mark2r2 0:08a4d61cd84c 308 //! GPDMA Transfer type definitions
mark2r2 0:08a4d61cd84c 309 enum GPDMA_TRANSFERTYPE {
mark2r2 0:08a4d61cd84c 310 m2m = 0UL /*!< Memory to memory - DMA control */
mark2r2 0:08a4d61cd84c 311 , m2p = 1UL /*!< Memory to peripheral - DMA control */
mark2r2 0:08a4d61cd84c 312 , p2m = 2UL /*!< Peripheral to memory - DMA control */
mark2r2 0:08a4d61cd84c 313 , p2p = 3UL /*!< Src peripheral to dest peripheral - DMA control */
mark2r2 0:08a4d61cd84c 314 , g2m = 4UL /*!< Psuedo special case for reading "peripheral GPIO" that's memory mapped. */
mark2r2 0:08a4d61cd84c 315 , m2g = 5UL /*!< Psuedo Special case for writing "peripheral GPIO" that's memory mapped. */
mark2r2 0:08a4d61cd84c 316 };
mark2r2 0:08a4d61cd84c 317
mark2r2 0:08a4d61cd84c 318 //! Burst size in Source and Destination definitions */
mark2r2 0:08a4d61cd84c 319 enum GPDMA_BSIZE {
mark2r2 0:08a4d61cd84c 320 _1 = 0UL /*!< Burst size = 1 */
mark2r2 0:08a4d61cd84c 321 , _4 = 1UL /*!< Burst size = 4 */
mark2r2 0:08a4d61cd84c 322 , _8 = 2UL /*!< Burst size = 8 */
mark2r2 0:08a4d61cd84c 323 , _16 = 3UL /*!< Burst size = 16 */
mark2r2 0:08a4d61cd84c 324 , _32 = 4UL /*!< Burst size = 32 */
mark2r2 0:08a4d61cd84c 325 , _64 = 5UL /*!< Burst size = 64 */
mark2r2 0:08a4d61cd84c 326 , _128 = 6UL /*!< Burst size = 128 */
mark2r2 0:08a4d61cd84c 327 , _256 = 7UL /*!< Burst size = 256 */
mark2r2 0:08a4d61cd84c 328 };
mark2r2 0:08a4d61cd84c 329
mark2r2 0:08a4d61cd84c 330 //! Width in Src transfer width and Dest transfer width definitions */
mark2r2 0:08a4d61cd84c 331 enum GPDMA_WIDTH {
mark2r2 0:08a4d61cd84c 332 byte = 0UL /*!< Width = 1 byte */
mark2r2 0:08a4d61cd84c 333 , halfword = 1UL /*!< Width = 2 bytes */
mark2r2 0:08a4d61cd84c 334 , word = 2UL /*!< Width = 4 bytes */
mark2r2 0:08a4d61cd84c 335 };
mark2r2 0:08a4d61cd84c 336
mark2r2 0:08a4d61cd84c 337 //! DMA Request Select Mode definitions. */
mark2r2 0:08a4d61cd84c 338 enum GPDMA_REQSEL {
mark2r2 0:08a4d61cd84c 339 uart = 0UL /*!< UART TX/RX is selected */
mark2r2 0:08a4d61cd84c 340 , timer = 1UL /*!< Timer match is selected */
mark2r2 0:08a4d61cd84c 341 };
mark2r2 0:08a4d61cd84c 342
mark2r2 0:08a4d61cd84c 343 //! GPDMA Control register bits.
mark2r2 0:08a4d61cd84c 344 enum Config {
mark2r2 0:08a4d61cd84c 345 _E = 1 /*!< DMA Controller enable */
mark2r2 0:08a4d61cd84c 346 , _M = 2 /*!< AHB Master endianness configuration */
mark2r2 0:08a4d61cd84c 347 };
mark2r2 0:08a4d61cd84c 348
mark2r2 0:08a4d61cd84c 349 //! GPDMA Channel config register bits.
mark2r2 0:08a4d61cd84c 350 enum CConfig {
mark2r2 0:08a4d61cd84c 351 _CE = (1UL << 0) /*!< Channel enable */
mark2r2 0:08a4d61cd84c 352 , _IE = (1UL << 14) /*!< Interrupt error mask */
mark2r2 0:08a4d61cd84c 353 , _ITC = (1UL << 15) /*!< Terminal count interrupt mask */
mark2r2 0:08a4d61cd84c 354 , _L = (1UL << 16) /*!< Lock */
mark2r2 0:08a4d61cd84c 355 , _A = (1UL << 17) /*!< Active */
mark2r2 0:08a4d61cd84c 356 , _H = (1UL << 18) /*!< Halt */
mark2r2 0:08a4d61cd84c 357 };
mark2r2 0:08a4d61cd84c 358
mark2r2 0:08a4d61cd84c 359 /**
mark2r2 0:08a4d61cd84c 360 * The MODDMA constructor is used to initialise the DMA controller object.
mark2r2 0:08a4d61cd84c 361 */
mark2r2 0:08a4d61cd84c 362 MODDMA() { init(true); }
mark2r2 0:08a4d61cd84c 363
mark2r2 0:08a4d61cd84c 364 /**
mark2r2 0:08a4d61cd84c 365 * The MODDMA destructor.
mark2r2 0:08a4d61cd84c 366 */
mark2r2 0:08a4d61cd84c 367 ~MODDMA() {}
mark2r2 0:08a4d61cd84c 368
mark2r2 0:08a4d61cd84c 369 /**
mark2r2 0:08a4d61cd84c 370 * Used to setup the DMA controller to prepare for a data transfer.
mark2r2 0:08a4d61cd84c 371 *
mark2r2 0:08a4d61cd84c 372 * @ingroup API
mark2r2 0:08a4d61cd84c 373 * @param isConstructorCalling Set true when called from teh constructor
mark2r2 0:08a4d61cd84c 374 * @param
mark2r2 0:08a4d61cd84c 375 */
mark2r2 0:08a4d61cd84c 376 void init(bool isConstructorCalling, int Channels = 0xFF, int Tc = 0xFF, int Err = 0xFF);
mark2r2 0:08a4d61cd84c 377
mark2r2 0:08a4d61cd84c 378 /**
mark2r2 0:08a4d61cd84c 379 * Used to setup and enable the DMA controller.
mark2r2 0:08a4d61cd84c 380 *
mark2r2 0:08a4d61cd84c 381 * @see Setup
mark2r2 0:08a4d61cd84c 382 * @see Enable
mark2r2 0:08a4d61cd84c 383 * @ingroup API
mark2r2 0:08a4d61cd84c 384 * @param c A pointer to an instance of MODDMA_Config to setup.
mark2r2 0:08a4d61cd84c 385 */
mark2r2 0:08a4d61cd84c 386 uint32_t Prepare(MODDMA_Config *c) {
mark2r2 0:08a4d61cd84c 387 uint32_t u = Setup(c);
mark2r2 0:08a4d61cd84c 388 if (u) Enable(c);
mark2r2 0:08a4d61cd84c 389 return u;
mark2r2 0:08a4d61cd84c 390 }
mark2r2 0:08a4d61cd84c 391
mark2r2 0:08a4d61cd84c 392 /**
mark2r2 0:08a4d61cd84c 393 * Used to setup the DMA controller to prepare for a data transfer.
mark2r2 0:08a4d61cd84c 394 *
mark2r2 0:08a4d61cd84c 395 * @ingroup API
mark2r2 0:08a4d61cd84c 396 * @param c A pointer to an instance of MODDMA_Config to setup.
mark2r2 0:08a4d61cd84c 397 */
mark2r2 0:08a4d61cd84c 398 uint32_t Setup(MODDMA_Config *c);
mark2r2 0:08a4d61cd84c 399
mark2r2 0:08a4d61cd84c 400 /**
mark2r2 0:08a4d61cd84c 401 * Enable and begin data transfer.
mark2r2 0:08a4d61cd84c 402 *
mark2r2 0:08a4d61cd84c 403 * @ingroup API
mark2r2 0:08a4d61cd84c 404 * @param ChannelNumber Type CHANNELS, the channel number to enable
mark2r2 0:08a4d61cd84c 405 */
mark2r2 0:08a4d61cd84c 406 void Enable(CHANNELS ChannelNumber);
mark2r2 0:08a4d61cd84c 407
mark2r2 0:08a4d61cd84c 408 /**
mark2r2 0:08a4d61cd84c 409 * Enable and begin data transfer (overloaded function)
mark2r2 0:08a4d61cd84c 410 *
mark2r2 0:08a4d61cd84c 411 * @ingroup API
mark2r2 0:08a4d61cd84c 412 * @param ChannelNumber Type uin32_t, the channel number to enable
mark2r2 0:08a4d61cd84c 413 */
mark2r2 0:08a4d61cd84c 414 void Enable(uint32_t ChannelNumber) { Enable((CHANNELS)(ChannelNumber & 0x7)); }
mark2r2 0:08a4d61cd84c 415
mark2r2 0:08a4d61cd84c 416 /**
mark2r2 0:08a4d61cd84c 417 * Enable and begin data transfer (overloaded function)
mark2r2 0:08a4d61cd84c 418 *
mark2r2 0:08a4d61cd84c 419 * @ingroup API
mark2r2 0:08a4d61cd84c 420 * @param config A pointer to teh configuration
mark2r2 0:08a4d61cd84c 421 */
mark2r2 0:08a4d61cd84c 422 void Enable(MODDMA_Config *config) { Enable( config->channelNum() ); }
mark2r2 0:08a4d61cd84c 423
mark2r2 0:08a4d61cd84c 424
mark2r2 0:08a4d61cd84c 425 /**
mark2r2 0:08a4d61cd84c 426 * Disable a channel and end data transfer.
mark2r2 0:08a4d61cd84c 427 *
mark2r2 0:08a4d61cd84c 428 * @ingroup API
mark2r2 0:08a4d61cd84c 429 * @param ChannelNumber Type CHANNELS, the channel number to enable
mark2r2 0:08a4d61cd84c 430 */
mark2r2 0:08a4d61cd84c 431 void Disable(CHANNELS ChannelNumber);
mark2r2 0:08a4d61cd84c 432
mark2r2 0:08a4d61cd84c 433 /**
mark2r2 0:08a4d61cd84c 434 * Disable a channel and end data transfer (overloaded function)
mark2r2 0:08a4d61cd84c 435 *
mark2r2 0:08a4d61cd84c 436 * @ingroup API
mark2r2 0:08a4d61cd84c 437 * @param ChannelNumber Type uin32_t, the channel number to disable
mark2r2 0:08a4d61cd84c 438 */
mark2r2 0:08a4d61cd84c 439 void Disable(uint32_t ChannelNumber) { Disable((CHANNELS)(ChannelNumber & 0x7)); }
mark2r2 0:08a4d61cd84c 440
mark2r2 0:08a4d61cd84c 441 /**
mark2r2 0:08a4d61cd84c 442 * Is the specified channel enabled?
mark2r2 0:08a4d61cd84c 443 *
mark2r2 0:08a4d61cd84c 444 * @ingroup API
mark2r2 0:08a4d61cd84c 445 * @param ChannelNumber Type CHANNELS, the channel number to test
mark2r2 0:08a4d61cd84c 446 * @return bool true if enabled, false otherwise.
mark2r2 0:08a4d61cd84c 447 */
mark2r2 0:08a4d61cd84c 448 bool Enabled(CHANNELS ChannelNumber);
mark2r2 0:08a4d61cd84c 449
mark2r2 0:08a4d61cd84c 450 /**
mark2r2 0:08a4d61cd84c 451 * Is the specified channel enabled? (overloaded function)
mark2r2 0:08a4d61cd84c 452 *
mark2r2 0:08a4d61cd84c 453 * @ingroup API
mark2r2 0:08a4d61cd84c 454 * @param ChannelNumber Type uin32_t, the channel number to test
mark2r2 0:08a4d61cd84c 455 * @return bool true if enabled, false otherwise.
mark2r2 0:08a4d61cd84c 456 */
mark2r2 0:08a4d61cd84c 457 bool Enabled(uint32_t ChannelNumber) { return Enabled((CHANNELS)(ChannelNumber & 0x7)); }
mark2r2 0:08a4d61cd84c 458
mark2r2 0:08a4d61cd84c 459 __INLINE uint32_t IntStat(uint32_t n) { return (1UL << n) & 0xFF; }
mark2r2 0:08a4d61cd84c 460 __INLINE uint32_t IntTCStat_Ch(uint32_t n) { return (1UL << n) & 0xFF; }
mark2r2 0:08a4d61cd84c 461 __INLINE uint32_t IntTCClear_Ch(uint32_t n) { return (1UL << n) & 0xFF; }
mark2r2 0:08a4d61cd84c 462 __INLINE uint32_t IntErrStat_Ch(uint32_t n) { return (1UL << n) & 0xFF; }
mark2r2 0:08a4d61cd84c 463 __INLINE uint32_t IntErrClr_Ch(uint32_t n) { return (1UL << n) & 0xFF; }
mark2r2 0:08a4d61cd84c 464 __INLINE uint32_t RawIntErrStat_Ch(uint32_t n) { return (1UL << n) & 0xFF; }
mark2r2 0:08a4d61cd84c 465 __INLINE uint32_t EnbldChns_Ch(uint32_t n) { return (1UL << n) & 0xFF; }
mark2r2 0:08a4d61cd84c 466 __INLINE uint32_t SoftBReq_Src(uint32_t n) { return (1UL << n) & 0xFFFF; }
mark2r2 0:08a4d61cd84c 467 __INLINE uint32_t SoftSReq_Src(uint32_t n) { return (1UL << n) & 0xFFFF; }
mark2r2 0:08a4d61cd84c 468 __INLINE uint32_t SoftLBReq_Src(uint32_t n) { return (1UL << n) & 0xFFFF; }
mark2r2 0:08a4d61cd84c 469 __INLINE uint32_t SoftLSReq_Src(uint32_t n) { return (1UL << n) & 0xFFFF; }
mark2r2 0:08a4d61cd84c 470 __INLINE uint32_t Sync_Src(uint32_t n) { return (1UL << n) & 0xFFFF; }
mark2r2 0:08a4d61cd84c 471 __INLINE uint32_t ReqSel_Input(uint32_t n) { return (1UL << (n - 8)) & 0xFF; }
mark2r2 0:08a4d61cd84c 472
mark2r2 0:08a4d61cd84c 473
mark2r2 0:08a4d61cd84c 474 __INLINE uint32_t CxControl_TransferSize(uint32_t n) { return (n & 0xFFF) << 0; }
mark2r2 0:08a4d61cd84c 475 __INLINE uint32_t CxControl_SBSize(uint32_t n) { return (n & 0x7) << 12; }
mark2r2 0:08a4d61cd84c 476 __INLINE uint32_t CxControl_DBSize(uint32_t n) { return (n & 0x7) << 15; }
mark2r2 0:08a4d61cd84c 477 __INLINE uint32_t CxControl_SWidth(uint32_t n) { return (n & 0x7) << 18; }
mark2r2 0:08a4d61cd84c 478 __INLINE uint32_t CxControl_DWidth(uint32_t n) { return (n & 0x7) << 21; }
mark2r2 0:08a4d61cd84c 479 __INLINE uint32_t CxControl_SI() { return (1UL << 26); }
mark2r2 0:08a4d61cd84c 480 __INLINE uint32_t CxControl_DI() { return (1UL << 27); }
mark2r2 0:08a4d61cd84c 481 __INLINE uint32_t CxControl_Prot1() { return (1UL << 28); }
mark2r2 0:08a4d61cd84c 482 __INLINE uint32_t CxControl_Prot2() { return (1UL << 29); }
mark2r2 0:08a4d61cd84c 483 __INLINE uint32_t CxControl_Prot3() { return (1UL << 30); }
mark2r2 0:08a4d61cd84c 484 __INLINE uint32_t CxControl_I() { return (1UL << 31); }
mark2r2 0:08a4d61cd84c 485 __INLINE uint32_t CxControl_E() { return (1UL << 0); }
mark2r2 0:08a4d61cd84c 486 __INLINE uint32_t CxConfig_SrcPeripheral(uint32_t n) { return (n & 0x1F) << 1; }
mark2r2 0:08a4d61cd84c 487 __INLINE uint32_t CxConfig_DestPeripheral(uint32_t n) { return (n & 0x1F) << 6; }
mark2r2 0:08a4d61cd84c 488 __INLINE uint32_t CxConfig_TransferType(uint32_t n) { return (n & 0x7) << 11; }
mark2r2 0:08a4d61cd84c 489 __INLINE uint32_t CxConfig_IE() { return (1UL << 14); }
mark2r2 0:08a4d61cd84c 490 __INLINE uint32_t CxConfig_ITC() { return (1UL << 15); }
mark2r2 0:08a4d61cd84c 491 __INLINE uint32_t CxConfig_L() { return (1UL << 16); }
mark2r2 0:08a4d61cd84c 492 __INLINE uint32_t CxConfig_A() { return (1UL << 17); }
mark2r2 0:08a4d61cd84c 493 __INLINE uint32_t CxConfig_H() { return (1UL << 18); }
mark2r2 0:08a4d61cd84c 494
mark2r2 0:08a4d61cd84c 495 /**
mark2r2 0:08a4d61cd84c 496 * A store for up to 8 (8 channels) of configurations.
mark2r2 0:08a4d61cd84c 497 * @see MODDMA_Config
mark2r2 0:08a4d61cd84c 498 */
mark2r2 0:08a4d61cd84c 499 MODDMA_Config *setups[8];
mark2r2 0:08a4d61cd84c 500
mark2r2 0:08a4d61cd84c 501 /**
mark2r2 0:08a4d61cd84c 502 * Get a pointer to the current configuration the ISR is servicing.
mark2r2 0:08a4d61cd84c 503 *
mark2r2 0:08a4d61cd84c 504 * @ingroup API
mark2r2 0:08a4d61cd84c 505 * @return MODDMA_Config * A pointer to the setup the ISR is currently servicing.
mark2r2 0:08a4d61cd84c 506 */
mark2r2 0:08a4d61cd84c 507 MODDMA_Config *getConfig(void) { return setups[IrqProcessingChannel]; }
mark2r2 0:08a4d61cd84c 508
mark2r2 0:08a4d61cd84c 509 /**
mark2r2 0:08a4d61cd84c 510 * Set which channel the ISR is currently servicing.
mark2r2 0:08a4d61cd84c 511 *
mark2r2 0:08a4d61cd84c 512 * *** USED INTERNALLY. DO NOT CALL FROM USER PROGRAMS ***
mark2r2 0:08a4d61cd84c 513 *
mark2r2 0:08a4d61cd84c 514 * Must be public so the extern "C" ISR can use it.
mark2r2 0:08a4d61cd84c 515 */
mark2r2 0:08a4d61cd84c 516 void setIrqProcessingChannel(CHANNELS n) { IrqProcessingChannel = n; }
mark2r2 0:08a4d61cd84c 517
mark2r2 0:08a4d61cd84c 518 /**
mark2r2 0:08a4d61cd84c 519 * Gets which channel the ISR is currently servicing.
mark2r2 0:08a4d61cd84c 520 *
mark2r2 0:08a4d61cd84c 521 * @ingroup API
mark2r2 0:08a4d61cd84c 522 * @return CHANNELS The current channel the ISR is servicing.
mark2r2 0:08a4d61cd84c 523 */
mark2r2 0:08a4d61cd84c 524 CHANNELS irqProcessingChannel(void) { return IrqProcessingChannel; }
mark2r2 0:08a4d61cd84c 525
mark2r2 0:08a4d61cd84c 526 /**
mark2r2 0:08a4d61cd84c 527 * Sets which type of IRQ the ISR is making a callback for.
mark2r2 0:08a4d61cd84c 528 *
mark2r2 0:08a4d61cd84c 529 * *** USED INTERNALLY. DO NOT CALL FROM USER PROGRAMS ***
mark2r2 0:08a4d61cd84c 530 *
mark2r2 0:08a4d61cd84c 531 * Must be public so the extern "C" ISR can use it.
mark2r2 0:08a4d61cd84c 532 */
mark2r2 0:08a4d61cd84c 533 void setIrqType(IrqType_t n) { IrqType = n; }
mark2r2 0:08a4d61cd84c 534
mark2r2 0:08a4d61cd84c 535 /**
mark2r2 0:08a4d61cd84c 536 * Get which type of IRQ the ISR is calling you about,
mark2r2 0:08a4d61cd84c 537 * terminal count or error.
mark2r2 0:08a4d61cd84c 538 */
mark2r2 0:08a4d61cd84c 539 IrqType_t irqType(void) { return IrqType; }
mark2r2 0:08a4d61cd84c 540
mark2r2 0:08a4d61cd84c 541 /**
mark2r2 0:08a4d61cd84c 542 * Clear the interrupt after handling.
mark2r2 0:08a4d61cd84c 543 *
mark2r2 0:08a4d61cd84c 544 * @param CHANNELS The channel the IQR occured on.
mark2r2 0:08a4d61cd84c 545 */
mark2r2 0:08a4d61cd84c 546 void clearTcIrq(CHANNELS n) { LPC_GPDMA->DMACIntTCClear = (uint32_t)(1UL << n); }
mark2r2 0:08a4d61cd84c 547
mark2r2 0:08a4d61cd84c 548 /**
mark2r2 0:08a4d61cd84c 549 * Clear the interrupt the ISR is currently handing..
mark2r2 0:08a4d61cd84c 550 */
mark2r2 0:08a4d61cd84c 551 void clearTcIrq(void) { clearTcIrq( IrqProcessingChannel ); }
mark2r2 0:08a4d61cd84c 552
mark2r2 0:08a4d61cd84c 553 /**
mark2r2 0:08a4d61cd84c 554 * Clear the error interrupt after handling.
mark2r2 0:08a4d61cd84c 555 *
mark2r2 0:08a4d61cd84c 556 * @ingroup API
mark2r2 0:08a4d61cd84c 557 * @param CHANNELS The channel the IQR occured on.
mark2r2 0:08a4d61cd84c 558 */
mark2r2 0:08a4d61cd84c 559 void clearErrIrq(CHANNELS n) { LPC_GPDMA->DMACIntTCClear = (uint32_t)(1UL << n); }
mark2r2 0:08a4d61cd84c 560
mark2r2 0:08a4d61cd84c 561 /**
mark2r2 0:08a4d61cd84c 562 * Clear the error interrupt the ISR is currently handing.
mark2r2 0:08a4d61cd84c 563 * @ingroup API
mark2r2 0:08a4d61cd84c 564 */
mark2r2 0:08a4d61cd84c 565 void clearErrIrq(void) { clearErrIrq( IrqProcessingChannel ); }
mark2r2 0:08a4d61cd84c 566
mark2r2 0:08a4d61cd84c 567 /**
mark2r2 0:08a4d61cd84c 568 * Is the supplied channel currently active?
mark2r2 0:08a4d61cd84c 569 *
mark2r2 0:08a4d61cd84c 570 * @ingroup API
mark2r2 0:08a4d61cd84c 571 * @param CHANNELS The channel to inquire about.
mark2r2 0:08a4d61cd84c 572 * @return bool true if active, false otherwise.
mark2r2 0:08a4d61cd84c 573 */
mark2r2 0:08a4d61cd84c 574 bool isActive(CHANNELS ChannelNumber);
mark2r2 0:08a4d61cd84c 575
mark2r2 0:08a4d61cd84c 576 /**
mark2r2 0:08a4d61cd84c 577 * Halt the supplied channel.
mark2r2 0:08a4d61cd84c 578 *
mark2r2 0:08a4d61cd84c 579 * @ingroup API
mark2r2 0:08a4d61cd84c 580 * @param CHANNELS The channel to halt.
mark2r2 0:08a4d61cd84c 581 */
mark2r2 0:08a4d61cd84c 582 void haltChannel(CHANNELS ChannelNumber);
mark2r2 0:08a4d61cd84c 583
mark2r2 0:08a4d61cd84c 584 /**
mark2r2 0:08a4d61cd84c 585 * get a channels control register.
mark2r2 0:08a4d61cd84c 586 *
mark2r2 0:08a4d61cd84c 587 * @ingroup API
mark2r2 0:08a4d61cd84c 588 * @param CHANNELS The channel to get the control register for.
mark2r2 0:08a4d61cd84c 589 */
mark2r2 0:08a4d61cd84c 590 uint32_t getControl(CHANNELS ChannelNumber);
mark2r2 0:08a4d61cd84c 591
mark2r2 0:08a4d61cd84c 592 /**
mark2r2 0:08a4d61cd84c 593 * Wait for channel transfer to complete and then halt.
mark2r2 0:08a4d61cd84c 594 *
mark2r2 0:08a4d61cd84c 595 * @ingroup API
mark2r2 0:08a4d61cd84c 596 * @param CHANNELS The channel to wait for then halt.
mark2r2 0:08a4d61cd84c 597 */
mark2r2 0:08a4d61cd84c 598 void haltAndWaitChannelComplete(CHANNELS n) { haltChannel(n); while (isActive(n)); }
mark2r2 0:08a4d61cd84c 599
mark2r2 0:08a4d61cd84c 600 /**
mark2r2 0:08a4d61cd84c 601 * Attach a callback to the TC IRQ controller.
mark2r2 0:08a4d61cd84c 602 *
mark2r2 0:08a4d61cd84c 603 * @ingroup API
mark2r2 0:08a4d61cd84c 604 * @param fptr A function pointer to call
mark2r2 0:08a4d61cd84c 605 * @return this
mark2r2 0:08a4d61cd84c 606 */
mark2r2 0:08a4d61cd84c 607 void attach_tc(void (*fptr)(void)) {
mark2r2 0:08a4d61cd84c 608 isrIntTCStat.attach(fptr);
mark2r2 0:08a4d61cd84c 609 }
mark2r2 0:08a4d61cd84c 610
mark2r2 0:08a4d61cd84c 611 /**
mark2r2 0:08a4d61cd84c 612 * Attach a callback to the TC IRQ controller.
mark2r2 0:08a4d61cd84c 613 *
mark2r2 0:08a4d61cd84c 614 * @ingroup API
mark2r2 0:08a4d61cd84c 615 * @param tptr A template pointer to the calling object
mark2r2 0:08a4d61cd84c 616 * @param mptr A method pointer within the object to call.
mark2r2 0:08a4d61cd84c 617 * @return this
mark2r2 0:08a4d61cd84c 618 */
mark2r2 0:08a4d61cd84c 619 template<typename T>
mark2r2 0:08a4d61cd84c 620 void attach_tc(T* tptr, void (T::*mptr)(void)) {
mark2r2 0:08a4d61cd84c 621 if((mptr != NULL) && (tptr != NULL)) {
mark2r2 0:08a4d61cd84c 622 isrIntTCStat.attach(tptr, mptr);
mark2r2 0:08a4d61cd84c 623 }
mark2r2 0:08a4d61cd84c 624 }
mark2r2 0:08a4d61cd84c 625
mark2r2 0:08a4d61cd84c 626 /**
mark2r2 0:08a4d61cd84c 627 * The MODDMA controllers terminal count interrupt callback.
mark2r2 0:08a4d61cd84c 628 */
mark2r2 0:08a4d61cd84c 629 FunctionPointer isrIntTCStat;
mark2r2 0:08a4d61cd84c 630
mark2r2 0:08a4d61cd84c 631 /**
mark2r2 0:08a4d61cd84c 632 * Attach a callback to the ERR IRQ controller.
mark2r2 0:08a4d61cd84c 633 *
mark2r2 0:08a4d61cd84c 634 * @ingroup API
mark2r2 0:08a4d61cd84c 635 * @param fptr A function pointer to call
mark2r2 0:08a4d61cd84c 636 * @return this
mark2r2 0:08a4d61cd84c 637 */
mark2r2 0:08a4d61cd84c 638 void attach_err(void (*fptr)(void)) {
mark2r2 0:08a4d61cd84c 639 isrIntErrStat.attach(fptr);
mark2r2 0:08a4d61cd84c 640 }
mark2r2 0:08a4d61cd84c 641
mark2r2 0:08a4d61cd84c 642 /**
mark2r2 0:08a4d61cd84c 643 * Attach a callback to the ERR IRQ controller.
mark2r2 0:08a4d61cd84c 644 *
mark2r2 0:08a4d61cd84c 645 * @ingroup API
mark2r2 0:08a4d61cd84c 646 * @param tptr A template pointer to the calling object
mark2r2 0:08a4d61cd84c 647 * @param mptr A method pointer within the object to call.
mark2r2 0:08a4d61cd84c 648 * @return this
mark2r2 0:08a4d61cd84c 649 */
mark2r2 0:08a4d61cd84c 650 template<typename T>
mark2r2 0:08a4d61cd84c 651 void attach_err(T* tptr, void (T::*mptr)(void)) {
mark2r2 0:08a4d61cd84c 652 if((mptr != NULL) && (tptr != NULL)) {
mark2r2 0:08a4d61cd84c 653 isrIntErrStat.attach(tptr, mptr);
mark2r2 0:08a4d61cd84c 654 }
mark2r2 0:08a4d61cd84c 655 }
mark2r2 0:08a4d61cd84c 656
mark2r2 0:08a4d61cd84c 657 /**
mark2r2 0:08a4d61cd84c 658 * Get the Linked List index regsiter for the requested channel.
mark2r2 0:08a4d61cd84c 659 *
mark2r2 0:08a4d61cd84c 660 * @param channelNum The channel number.
mark2r2 0:08a4d61cd84c 661 * @return uint32_t The value of the DMACCLLI register
mark2r2 0:08a4d61cd84c 662 */
mark2r2 0:08a4d61cd84c 663 uint32_t lli(CHANNELS ChannelNumber, MODDMA_LLI *set = 0) {
mark2r2 0:08a4d61cd84c 664 LPC_GPDMACH_TypeDef *pChannel = (LPC_GPDMACH_TypeDef *)Channel_p( ChannelNumber & 0x7 );
mark2r2 0:08a4d61cd84c 665 if (set) pChannel->DMACCLLI = (uint32_t)set;
mark2r2 0:08a4d61cd84c 666 return pChannel->DMACCLLI;
mark2r2 0:08a4d61cd84c 667 }
mark2r2 0:08a4d61cd84c 668
mark2r2 0:08a4d61cd84c 669 /**
mark2r2 0:08a4d61cd84c 670 * The MODDMA controllers error interrupt callback.
mark2r2 0:08a4d61cd84c 671 */
mark2r2 0:08a4d61cd84c 672 FunctionPointer isrIntErrStat;
mark2r2 0:08a4d61cd84c 673
mark2r2 0:08a4d61cd84c 674 uint32_t Channel_p(int channel);
mark2r2 0:08a4d61cd84c 675
mark2r2 0:08a4d61cd84c 676 protected:
mark2r2 0:08a4d61cd84c 677
mark2r2 0:08a4d61cd84c 678 // Data LUTs.
mark2r2 0:08a4d61cd84c 679 uint32_t LUTPerAddr(int n);
mark2r2 0:08a4d61cd84c 680 uint8_t LUTPerBurst(int n);
mark2r2 0:08a4d61cd84c 681 uint8_t LUTPerWid(int n);
mark2r2 0:08a4d61cd84c 682 //uint32_t Channel_p(int channel);
mark2r2 0:08a4d61cd84c 683
mark2r2 0:08a4d61cd84c 684 CHANNELS IrqProcessingChannel;
mark2r2 0:08a4d61cd84c 685
mark2r2 0:08a4d61cd84c 686 IrqType_t IrqType;
mark2r2 0:08a4d61cd84c 687 };
mark2r2 0:08a4d61cd84c 688
mark2r2 0:08a4d61cd84c 689 }; // namespace AjK ends.
mark2r2 0:08a4d61cd84c 690
mark2r2 0:08a4d61cd84c 691 using namespace AjK;
mark2r2 0:08a4d61cd84c 692
mark2r2 0:08a4d61cd84c 693 #endif