http://http://diytec.web.fc2.com/mark2r2/
Dependencies: EthernetNetIf NTPClient_NetServices mbed ConfigFile
MODDMA/SETUP.cpp@0:08a4d61cd84c, 2011-09-20 (annotated)
- Committer:
- mark2r2
- Date:
- Tue Sep 20 12:46:26 2011 +0000
- Revision:
- 0:08a4d61cd84c
V1.0
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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mark2r2 | 0:08a4d61cd84c | 1 | /* |
mark2r2 | 0:08a4d61cd84c | 2 | Copyright (c) 2010 Andy Kirkham |
mark2r2 | 0:08a4d61cd84c | 3 | |
mark2r2 | 0:08a4d61cd84c | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy |
mark2r2 | 0:08a4d61cd84c | 5 | of this software and associated documentation files (the "Software"), to deal |
mark2r2 | 0:08a4d61cd84c | 6 | in the Software without restriction, including without limitation the rights |
mark2r2 | 0:08a4d61cd84c | 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
mark2r2 | 0:08a4d61cd84c | 8 | copies of the Software, and to permit persons to whom the Software is |
mark2r2 | 0:08a4d61cd84c | 9 | furnished to do so, subject to the following conditions: |
mark2r2 | 0:08a4d61cd84c | 10 | |
mark2r2 | 0:08a4d61cd84c | 11 | The above copyright notice and this permission notice shall be included in |
mark2r2 | 0:08a4d61cd84c | 12 | all copies or substantial portions of the Software. |
mark2r2 | 0:08a4d61cd84c | 13 | |
mark2r2 | 0:08a4d61cd84c | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
mark2r2 | 0:08a4d61cd84c | 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
mark2r2 | 0:08a4d61cd84c | 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
mark2r2 | 0:08a4d61cd84c | 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
mark2r2 | 0:08a4d61cd84c | 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
mark2r2 | 0:08a4d61cd84c | 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
mark2r2 | 0:08a4d61cd84c | 20 | THE SOFTWARE. |
mark2r2 | 0:08a4d61cd84c | 21 | */ |
mark2r2 | 0:08a4d61cd84c | 22 | |
mark2r2 | 0:08a4d61cd84c | 23 | #include "MODDMA.h" |
mark2r2 | 0:08a4d61cd84c | 24 | |
mark2r2 | 0:08a4d61cd84c | 25 | namespace AjK { |
mark2r2 | 0:08a4d61cd84c | 26 | |
mark2r2 | 0:08a4d61cd84c | 27 | uint32_t |
mark2r2 | 0:08a4d61cd84c | 28 | MODDMA::Setup(MODDMA_Config *config) |
mark2r2 | 0:08a4d61cd84c | 29 | { |
mark2r2 | 0:08a4d61cd84c | 30 | LPC_GPDMACH_TypeDef *pChannel = (LPC_GPDMACH_TypeDef *)Channel_p( config->channelNum() ); |
mark2r2 | 0:08a4d61cd84c | 31 | |
mark2r2 | 0:08a4d61cd84c | 32 | setups[config->channelNum() & 0x7] = config; |
mark2r2 | 0:08a4d61cd84c | 33 | |
mark2r2 | 0:08a4d61cd84c | 34 | // Reset the Interrupt status |
mark2r2 | 0:08a4d61cd84c | 35 | LPC_GPDMA->DMACIntTCClear = IntTCClear_Ch( config->channelNum() ); |
mark2r2 | 0:08a4d61cd84c | 36 | LPC_GPDMA->DMACIntErrClr = IntErrClr_Ch ( config->channelNum() ); |
mark2r2 | 0:08a4d61cd84c | 37 | |
mark2r2 | 0:08a4d61cd84c | 38 | // Clear DMA configure |
mark2r2 | 0:08a4d61cd84c | 39 | pChannel->DMACCControl = 0x00; |
mark2r2 | 0:08a4d61cd84c | 40 | pChannel->DMACCConfig = 0x00; |
mark2r2 | 0:08a4d61cd84c | 41 | |
mark2r2 | 0:08a4d61cd84c | 42 | // Assign Linker List Item value |
mark2r2 | 0:08a4d61cd84c | 43 | pChannel->DMACCLLI = config->dmaLLI(); |
mark2r2 | 0:08a4d61cd84c | 44 | |
mark2r2 | 0:08a4d61cd84c | 45 | // Set value to Channel Control Registers |
mark2r2 | 0:08a4d61cd84c | 46 | switch (config->transferType()) { |
mark2r2 | 0:08a4d61cd84c | 47 | |
mark2r2 | 0:08a4d61cd84c | 48 | // Memory to memory |
mark2r2 | 0:08a4d61cd84c | 49 | case m2m: |
mark2r2 | 0:08a4d61cd84c | 50 | // Assign physical source and destination address |
mark2r2 | 0:08a4d61cd84c | 51 | pChannel->DMACCSrcAddr = config->srcMemAddr(); |
mark2r2 | 0:08a4d61cd84c | 52 | pChannel->DMACCDestAddr = config->dstMemAddr(); |
mark2r2 | 0:08a4d61cd84c | 53 | pChannel->DMACCControl |
mark2r2 | 0:08a4d61cd84c | 54 | = CxControl_TransferSize(config->transferSize()) |
mark2r2 | 0:08a4d61cd84c | 55 | | CxControl_SBSize(_32) |
mark2r2 | 0:08a4d61cd84c | 56 | | CxControl_DBSize(_32) |
mark2r2 | 0:08a4d61cd84c | 57 | | CxControl_SWidth(config->transferWidth()) |
mark2r2 | 0:08a4d61cd84c | 58 | | CxControl_DWidth(config->transferWidth()) |
mark2r2 | 0:08a4d61cd84c | 59 | | CxControl_SI() |
mark2r2 | 0:08a4d61cd84c | 60 | | CxControl_DI() |
mark2r2 | 0:08a4d61cd84c | 61 | | CxControl_I(); |
mark2r2 | 0:08a4d61cd84c | 62 | break; |
mark2r2 | 0:08a4d61cd84c | 63 | |
mark2r2 | 0:08a4d61cd84c | 64 | // Memory to peripheral |
mark2r2 | 0:08a4d61cd84c | 65 | case m2p: |
mark2r2 | 0:08a4d61cd84c | 66 | // Assign physical source |
mark2r2 | 0:08a4d61cd84c | 67 | pChannel->DMACCSrcAddr = config->srcMemAddr(); |
mark2r2 | 0:08a4d61cd84c | 68 | // Assign peripheral destination address |
mark2r2 | 0:08a4d61cd84c | 69 | pChannel->DMACCDestAddr = (uint32_t)LUTPerAddr(config->dstConn()); |
mark2r2 | 0:08a4d61cd84c | 70 | pChannel->DMACCControl |
mark2r2 | 0:08a4d61cd84c | 71 | = CxControl_TransferSize((uint32_t)config->transferSize()) |
mark2r2 | 0:08a4d61cd84c | 72 | | CxControl_SBSize((uint32_t)LUTPerBurst(config->dstConn())) |
mark2r2 | 0:08a4d61cd84c | 73 | | CxControl_DBSize((uint32_t)LUTPerBurst(config->dstConn())) |
mark2r2 | 0:08a4d61cd84c | 74 | | CxControl_SWidth((uint32_t)LUTPerWid(config->dstConn())) |
mark2r2 | 0:08a4d61cd84c | 75 | | CxControl_DWidth((uint32_t)LUTPerWid(config->dstConn())) |
mark2r2 | 0:08a4d61cd84c | 76 | | CxControl_SI() |
mark2r2 | 0:08a4d61cd84c | 77 | | CxControl_I(); |
mark2r2 | 0:08a4d61cd84c | 78 | break; |
mark2r2 | 0:08a4d61cd84c | 79 | |
mark2r2 | 0:08a4d61cd84c | 80 | // Peripheral to memory |
mark2r2 | 0:08a4d61cd84c | 81 | case p2m: |
mark2r2 | 0:08a4d61cd84c | 82 | // Assign peripheral source address |
mark2r2 | 0:08a4d61cd84c | 83 | pChannel->DMACCSrcAddr = (uint32_t)LUTPerAddr(config->srcConn()); |
mark2r2 | 0:08a4d61cd84c | 84 | // Assign memory destination address |
mark2r2 | 0:08a4d61cd84c | 85 | pChannel->DMACCDestAddr = config->dstMemAddr(); |
mark2r2 | 0:08a4d61cd84c | 86 | pChannel->DMACCControl |
mark2r2 | 0:08a4d61cd84c | 87 | = CxControl_TransferSize((uint32_t)config->transferSize()) |
mark2r2 | 0:08a4d61cd84c | 88 | | CxControl_SBSize((uint32_t)LUTPerBurst(config->srcConn())) |
mark2r2 | 0:08a4d61cd84c | 89 | | CxControl_DBSize((uint32_t)LUTPerBurst(config->srcConn())) |
mark2r2 | 0:08a4d61cd84c | 90 | | CxControl_SWidth((uint32_t)LUTPerWid(config->srcConn())) |
mark2r2 | 0:08a4d61cd84c | 91 | | CxControl_DWidth((uint32_t)LUTPerWid(config->srcConn())) |
mark2r2 | 0:08a4d61cd84c | 92 | | CxControl_DI() |
mark2r2 | 0:08a4d61cd84c | 93 | | CxControl_I(); |
mark2r2 | 0:08a4d61cd84c | 94 | break; |
mark2r2 | 0:08a4d61cd84c | 95 | |
mark2r2 | 0:08a4d61cd84c | 96 | // Peripheral to peripheral |
mark2r2 | 0:08a4d61cd84c | 97 | case p2p: |
mark2r2 | 0:08a4d61cd84c | 98 | // Assign peripheral source address |
mark2r2 | 0:08a4d61cd84c | 99 | pChannel->DMACCSrcAddr = (uint32_t)LUTPerAddr(config->srcConn()); |
mark2r2 | 0:08a4d61cd84c | 100 | // Assign peripheral destination address |
mark2r2 | 0:08a4d61cd84c | 101 | pChannel->DMACCDestAddr = (uint32_t)LUTPerAddr(config->dstConn()); |
mark2r2 | 0:08a4d61cd84c | 102 | pChannel->DMACCControl |
mark2r2 | 0:08a4d61cd84c | 103 | = CxControl_TransferSize((uint32_t)config->transferSize()) |
mark2r2 | 0:08a4d61cd84c | 104 | | CxControl_SBSize((uint32_t)LUTPerBurst(config->srcConn())) |
mark2r2 | 0:08a4d61cd84c | 105 | | CxControl_DBSize((uint32_t)LUTPerBurst(config->dstConn())) |
mark2r2 | 0:08a4d61cd84c | 106 | | CxControl_SWidth((uint32_t)LUTPerWid(config->srcConn())) |
mark2r2 | 0:08a4d61cd84c | 107 | | CxControl_DWidth((uint32_t)LUTPerWid(config->dstConn())) |
mark2r2 | 0:08a4d61cd84c | 108 | | CxControl_I(); |
mark2r2 | 0:08a4d61cd84c | 109 | break; |
mark2r2 | 0:08a4d61cd84c | 110 | |
mark2r2 | 0:08a4d61cd84c | 111 | // GPIO to memory |
mark2r2 | 0:08a4d61cd84c | 112 | case g2m: |
mark2r2 | 0:08a4d61cd84c | 113 | // Assign GPIO source address |
mark2r2 | 0:08a4d61cd84c | 114 | pChannel->DMACCSrcAddr = config->srcMemAddr(); |
mark2r2 | 0:08a4d61cd84c | 115 | // Assign memory destination address |
mark2r2 | 0:08a4d61cd84c | 116 | pChannel->DMACCDestAddr = config->dstMemAddr(); |
mark2r2 | 0:08a4d61cd84c | 117 | pChannel->DMACCControl |
mark2r2 | 0:08a4d61cd84c | 118 | = CxControl_TransferSize((uint32_t)config->transferSize()) |
mark2r2 | 0:08a4d61cd84c | 119 | | CxControl_SBSize((uint32_t)LUTPerBurst(config->srcConn())) |
mark2r2 | 0:08a4d61cd84c | 120 | | CxControl_DBSize((uint32_t)LUTPerBurst(config->srcConn())) |
mark2r2 | 0:08a4d61cd84c | 121 | | CxControl_SWidth((uint32_t)LUTPerWid(config->srcConn())) |
mark2r2 | 0:08a4d61cd84c | 122 | | CxControl_DWidth((uint32_t)LUTPerWid(config->srcConn())) |
mark2r2 | 0:08a4d61cd84c | 123 | | CxControl_DI() |
mark2r2 | 0:08a4d61cd84c | 124 | | CxControl_I(); |
mark2r2 | 0:08a4d61cd84c | 125 | break; |
mark2r2 | 0:08a4d61cd84c | 126 | |
mark2r2 | 0:08a4d61cd84c | 127 | // Memory to GPIO |
mark2r2 | 0:08a4d61cd84c | 128 | case m2g: |
mark2r2 | 0:08a4d61cd84c | 129 | // Assign physical source |
mark2r2 | 0:08a4d61cd84c | 130 | pChannel->DMACCSrcAddr = config->srcMemAddr(); |
mark2r2 | 0:08a4d61cd84c | 131 | // Assign peripheral destination address |
mark2r2 | 0:08a4d61cd84c | 132 | pChannel->DMACCDestAddr = config->dstMemAddr(); |
mark2r2 | 0:08a4d61cd84c | 133 | pChannel->DMACCControl |
mark2r2 | 0:08a4d61cd84c | 134 | = CxControl_TransferSize((uint32_t)config->transferSize()) |
mark2r2 | 0:08a4d61cd84c | 135 | | CxControl_SBSize((uint32_t)LUTPerBurst(config->dstConn())) |
mark2r2 | 0:08a4d61cd84c | 136 | | CxControl_DBSize((uint32_t)LUTPerBurst(config->dstConn())) |
mark2r2 | 0:08a4d61cd84c | 137 | | CxControl_SWidth((uint32_t)LUTPerWid(config->dstConn())) |
mark2r2 | 0:08a4d61cd84c | 138 | | CxControl_DWidth((uint32_t)LUTPerWid(config->dstConn())) |
mark2r2 | 0:08a4d61cd84c | 139 | | CxControl_SI() |
mark2r2 | 0:08a4d61cd84c | 140 | | CxControl_I(); |
mark2r2 | 0:08a4d61cd84c | 141 | break; |
mark2r2 | 0:08a4d61cd84c | 142 | |
mark2r2 | 0:08a4d61cd84c | 143 | // Do not support any more transfer type, return ERROR |
mark2r2 | 0:08a4d61cd84c | 144 | default: |
mark2r2 | 0:08a4d61cd84c | 145 | return 0; |
mark2r2 | 0:08a4d61cd84c | 146 | } |
mark2r2 | 0:08a4d61cd84c | 147 | |
mark2r2 | 0:08a4d61cd84c | 148 | // Re-Configure DMA Request Select for source peripheral |
mark2r2 | 0:08a4d61cd84c | 149 | if (config->srcConn() > 15) { |
mark2r2 | 0:08a4d61cd84c | 150 | LPC_SC->RESERVED9 |= (1 << (config->srcConn() - 16)); |
mark2r2 | 0:08a4d61cd84c | 151 | } |
mark2r2 | 0:08a4d61cd84c | 152 | else { |
mark2r2 | 0:08a4d61cd84c | 153 | LPC_SC->RESERVED9 &= ~(1 << (config->srcConn() - 8)); |
mark2r2 | 0:08a4d61cd84c | 154 | } |
mark2r2 | 0:08a4d61cd84c | 155 | |
mark2r2 | 0:08a4d61cd84c | 156 | // Re-Configure DMA Request Select for destination peripheral |
mark2r2 | 0:08a4d61cd84c | 157 | if (config->dstConn() > 15) { |
mark2r2 | 0:08a4d61cd84c | 158 | LPC_SC->RESERVED9 |= (1 << (config->dstConn() - 16)); |
mark2r2 | 0:08a4d61cd84c | 159 | } |
mark2r2 | 0:08a4d61cd84c | 160 | else { |
mark2r2 | 0:08a4d61cd84c | 161 | LPC_SC->RESERVED9 &= ~(1 << (config->dstConn() - 8)); |
mark2r2 | 0:08a4d61cd84c | 162 | } |
mark2r2 | 0:08a4d61cd84c | 163 | |
mark2r2 | 0:08a4d61cd84c | 164 | // Enable DMA channels, little endian |
mark2r2 | 0:08a4d61cd84c | 165 | LPC_GPDMA->DMACConfig = _E; |
mark2r2 | 0:08a4d61cd84c | 166 | while (!(LPC_GPDMA->DMACConfig & _E)); |
mark2r2 | 0:08a4d61cd84c | 167 | |
mark2r2 | 0:08a4d61cd84c | 168 | // Calculate absolute value for Connection number |
mark2r2 | 0:08a4d61cd84c | 169 | uint32_t tmp1 = config->srcConn(); tmp1 = ((tmp1 > 15) ? (tmp1 - 8) : tmp1); |
mark2r2 | 0:08a4d61cd84c | 170 | uint32_t tmp2 = config->dstConn(); tmp2 = ((tmp2 > 15) ? (tmp2 - 8) : tmp2); |
mark2r2 | 0:08a4d61cd84c | 171 | |
mark2r2 | 0:08a4d61cd84c | 172 | if (config->dmacSync()) { |
mark2r2 | 0:08a4d61cd84c | 173 | uint32_t tmp3 = config->dmacSync(); tmp3 = ((tmp3 > 15) ? (tmp3 - 8) : tmp3); |
mark2r2 | 0:08a4d61cd84c | 174 | LPC_GPDMA->DMACSync |= Sync_Src( tmp3 ); |
mark2r2 | 0:08a4d61cd84c | 175 | } |
mark2r2 | 0:08a4d61cd84c | 176 | |
mark2r2 | 0:08a4d61cd84c | 177 | uint32_t tfer_type = (uint32_t)config->transferType(); |
mark2r2 | 0:08a4d61cd84c | 178 | if (tfer_type == g2m || tfer_type == m2g) { |
mark2r2 | 0:08a4d61cd84c | 179 | tfer_type -= 2; // Adjust psuedo transferType to a real transferType. |
mark2r2 | 0:08a4d61cd84c | 180 | } |
mark2r2 | 0:08a4d61cd84c | 181 | |
mark2r2 | 0:08a4d61cd84c | 182 | // Configure DMA Channel, enable Error Counter and Terminate counter |
mark2r2 | 0:08a4d61cd84c | 183 | pChannel->DMACCConfig |
mark2r2 | 0:08a4d61cd84c | 184 | = CxConfig_IE() |
mark2r2 | 0:08a4d61cd84c | 185 | | CxConfig_ITC() |
mark2r2 | 0:08a4d61cd84c | 186 | | CxConfig_TransferType(tfer_type) |
mark2r2 | 0:08a4d61cd84c | 187 | | CxConfig_SrcPeripheral(tmp1) |
mark2r2 | 0:08a4d61cd84c | 188 | | CxConfig_DestPeripheral(tmp2); |
mark2r2 | 0:08a4d61cd84c | 189 | |
mark2r2 | 0:08a4d61cd84c | 190 | return pChannel->DMACCControl; |
mark2r2 | 0:08a4d61cd84c | 191 | } |
mark2r2 | 0:08a4d61cd84c | 192 | |
mark2r2 | 0:08a4d61cd84c | 193 | }; // namespace AjK ends |
mark2r2 | 0:08a4d61cd84c | 194 |