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targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc_ex.h@532:fe11edbda85c, 2015-04-30 (annotated)

Committer:: mbed_official
Date:: Thu Apr 30 13:45:11 2015 +0100
Revision:: 532:fe11edbda85c
Parent:: 380:510f0c3515e3
Child:: 613:bc40b8d2aec4

Synchronized with git revision 8c95d60d0a0c337e8161211fd1eded577e79e00b



Full URL: https://github.com/mbedmicro/mbed/commit/8c95d60d0a0c337e8161211fd1eded577e79e00b/



Stm32cubef4 update

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User	Revision	Line number	New contents of line
mbed_official	235:685d5f11838f	1	/**
mbed_official	235:685d5f11838f	2	******************************************************************************
mbed_official	235:685d5f11838f	3	* @file stm32f4xx_hal_rcc_ex.h
mbed_official	235:685d5f11838f	4	* @author MCD Application Team
mbed_official	532:fe11edbda85c	5	* @version V1.3.0
mbed_official	532:fe11edbda85c	6	* @date 09-March-2015
mbed_official	235:685d5f11838f	7	* @brief Header file of RCC HAL Extension module.
mbed_official	235:685d5f11838f	8	******************************************************************************
mbed_official	235:685d5f11838f	9	* @attention
mbed_official	235:685d5f11838f	10	*
mbed_official	532:fe11edbda85c	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official	235:685d5f11838f	12	*
mbed_official	235:685d5f11838f	13	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	235:685d5f11838f	14	* are permitted provided that the following conditions are met:
mbed_official	235:685d5f11838f	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	235:685d5f11838f	16	* this list of conditions and the following disclaimer.
mbed_official	235:685d5f11838f	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	235:685d5f11838f	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	235:685d5f11838f	19	* and/or other materials provided with the distribution.
mbed_official	235:685d5f11838f	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	235:685d5f11838f	21	* may be used to endorse or promote products derived from this software
mbed_official	235:685d5f11838f	22	* without specific prior written permission.
mbed_official	235:685d5f11838f	23	*
mbed_official	235:685d5f11838f	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	235:685d5f11838f	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	235:685d5f11838f	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	235:685d5f11838f	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	235:685d5f11838f	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	235:685d5f11838f	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	235:685d5f11838f	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	235:685d5f11838f	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	235:685d5f11838f	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	235:685d5f11838f	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	235:685d5f11838f	34	*
mbed_official	235:685d5f11838f	35	******************************************************************************
mbed_official	235:685d5f11838f	36	*/
mbed_official	235:685d5f11838f	37
mbed_official	235:685d5f11838f	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	235:685d5f11838f	39	#ifndef __STM32F4xx_HAL_RCC_EX_H
mbed_official	235:685d5f11838f	40	#define __STM32F4xx_HAL_RCC_EX_H
mbed_official	235:685d5f11838f	41
mbed_official	235:685d5f11838f	42	#ifdef __cplusplus
mbed_official	235:685d5f11838f	43	extern "C" {
mbed_official	235:685d5f11838f	44	#endif
mbed_official	235:685d5f11838f	45
mbed_official	235:685d5f11838f	46	/* Includes ------------------------------------------------------------------*/
mbed_official	235:685d5f11838f	47	#include "stm32f4xx_hal_def.h"
mbed_official	235:685d5f11838f	48
mbed_official	235:685d5f11838f	49	/** @addtogroup STM32F4xx_HAL_Driver
mbed_official	235:685d5f11838f	50	* @{
mbed_official	235:685d5f11838f	51	*/
mbed_official	235:685d5f11838f	52
mbed_official	235:685d5f11838f	53	/** @addtogroup RCCEx
mbed_official	235:685d5f11838f	54	* @{
mbed_official	235:685d5f11838f	55	*/
mbed_official	235:685d5f11838f	56
mbed_official	532:fe11edbda85c	57	/* Exported types ------------------------------------------------------------*/
mbed_official	532:fe11edbda85c	58	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
mbed_official	532:fe11edbda85c	59	* @{
mbed_official	532:fe11edbda85c	60	*/
mbed_official	532:fe11edbda85c	61
mbed_official	532:fe11edbda85c	62	/**
mbed_official	532:fe11edbda85c	63	* @brief RCC PLL configuration structure definition
mbed_official	532:fe11edbda85c	64	*/
mbed_official	532:fe11edbda85c	65	typedef struct
mbed_official	532:fe11edbda85c	66	{
mbed_official	532:fe11edbda85c	67	uint32_t PLLState; /*!< The new state of the PLL.
mbed_official	532:fe11edbda85c	68	This parameter can be a value of @ref RCC_PLL_Config */
mbed_official	532:fe11edbda85c	69
mbed_official	532:fe11edbda85c	70	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
mbed_official	532:fe11edbda85c	71	This parameter must be a value of @ref RCC_PLL_Clock_Source */
mbed_official	532:fe11edbda85c	72
mbed_official	532:fe11edbda85c	73	uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
mbed_official	532:fe11edbda85c	74	This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
mbed_official	532:fe11edbda85c	75
mbed_official	532:fe11edbda85c	76	uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
mbed_official	532:fe11edbda85c	77	This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
mbed_official	532:fe11edbda85c	78
mbed_official	532:fe11edbda85c	79	uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
mbed_official	532:fe11edbda85c	80	This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
mbed_official	532:fe11edbda85c	81
mbed_official	532:fe11edbda85c	82	uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
mbed_official	532:fe11edbda85c	83	This parameter must be a number between Min_Data = 4 and Max_Data = 15 */
mbed_official	532:fe11edbda85c	84	#if defined(STM32F446xx)
mbed_official	532:fe11edbda85c	85	uint32_t PLLR; /*!< PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
mbed_official	532:fe11edbda85c	86	This parameter is only available in STM32F446xx devices.
mbed_official	532:fe11edbda85c	87	This parameter must be a number between Min_Data = 2 and Max_Data = 7 */
mbed_official	532:fe11edbda85c	88	#endif /* STM32F446xx */
mbed_official	532:fe11edbda85c	89	}RCC_PLLInitTypeDef;
mbed_official	532:fe11edbda85c	90
mbed_official	532:fe11edbda85c	91	#if defined(STM32F446xx)
mbed_official	532:fe11edbda85c	92	/**
mbed_official	532:fe11edbda85c	93	* @brief PLLI2S Clock structure definition
mbed_official	532:fe11edbda85c	94	*/
mbed_official	532:fe11edbda85c	95	typedef struct
mbed_official	532:fe11edbda85c	96	{
mbed_official	532:fe11edbda85c	97	uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock.
mbed_official	532:fe11edbda85c	98	This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
mbed_official	532:fe11edbda85c	99
mbed_official	532:fe11edbda85c	100	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
mbed_official	532:fe11edbda85c	101	This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
mbed_official	532:fe11edbda85c	102
mbed_official	532:fe11edbda85c	103	uint32_t PLLI2SP; /*!< Specifies division factor for SPDIFRX Clock.
mbed_official	532:fe11edbda85c	104	This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider */
mbed_official	532:fe11edbda85c	105
mbed_official	532:fe11edbda85c	106	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock.
mbed_official	532:fe11edbda85c	107	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
mbed_official	532:fe11edbda85c	108	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
mbed_official	532:fe11edbda85c	109
mbed_official	532:fe11edbda85c	110	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
mbed_official	532:fe11edbda85c	111	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
mbed_official	532:fe11edbda85c	112	This parameter will be used only when PLLI2S is selected as Clock Source I2S */
mbed_official	532:fe11edbda85c	113	}RCC_PLLI2SInitTypeDef;
mbed_official	532:fe11edbda85c	114
mbed_official	532:fe11edbda85c	115	/**
mbed_official	532:fe11edbda85c	116	* @brief PLLSAI Clock structure definition
mbed_official	532:fe11edbda85c	117	*/
mbed_official	532:fe11edbda85c	118	typedef struct
mbed_official	532:fe11edbda85c	119	{
mbed_official	532:fe11edbda85c	120	uint32_t PLLSAIM; /*!< Spcifies division factor for PLL VCO input clock.
mbed_official	532:fe11edbda85c	121	This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
mbed_official	532:fe11edbda85c	122
mbed_official	532:fe11edbda85c	123	uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
mbed_official	532:fe11edbda85c	124	This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
mbed_official	532:fe11edbda85c	125
mbed_official	532:fe11edbda85c	126	uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS, SDIO and RNG clocks.
mbed_official	532:fe11edbda85c	127	This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */
mbed_official	532:fe11edbda85c	128
mbed_official	532:fe11edbda85c	129	uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI clock.
mbed_official	532:fe11edbda85c	130	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
mbed_official	532:fe11edbda85c	131	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
mbed_official	532:fe11edbda85c	132	}RCC_PLLSAIInitTypeDef;
mbed_official	532:fe11edbda85c	133	/**
mbed_official	532:fe11edbda85c	134	* @brief RCC extended clocks structure definition
mbed_official	532:fe11edbda85c	135	*/
mbed_official	532:fe11edbda85c	136	typedef struct
mbed_official	532:fe11edbda85c	137	{
mbed_official	532:fe11edbda85c	138	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	532:fe11edbda85c	139	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	532:fe11edbda85c	140
mbed_official	532:fe11edbda85c	141	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
mbed_official	532:fe11edbda85c	142	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
mbed_official	532:fe11edbda85c	143
mbed_official	532:fe11edbda85c	144	RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
mbed_official	532:fe11edbda85c	145	This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
mbed_official	532:fe11edbda85c	146
mbed_official	532:fe11edbda85c	147	uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
mbed_official	532:fe11edbda85c	148	This parameter must be a number between Min_Data = 1 and Max_Data = 32
mbed_official	532:fe11edbda85c	149	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
mbed_official	532:fe11edbda85c	150
mbed_official	532:fe11edbda85c	151	uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
mbed_official	532:fe11edbda85c	152	This parameter must be a number between Min_Data = 1 and Max_Data = 32
mbed_official	532:fe11edbda85c	153	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
mbed_official	532:fe11edbda85c	154
mbed_official	532:fe11edbda85c	155	uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Source Selection.
mbed_official	532:fe11edbda85c	156	This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
mbed_official	532:fe11edbda85c	157
mbed_official	532:fe11edbda85c	158	uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Source Selection.
mbed_official	532:fe11edbda85c	159	This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
mbed_official	532:fe11edbda85c	160
mbed_official	532:fe11edbda85c	161	uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection.
mbed_official	532:fe11edbda85c	162	This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
mbed_official	532:fe11edbda85c	163
mbed_official	532:fe11edbda85c	164	uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection.
mbed_official	532:fe11edbda85c	165	This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
mbed_official	532:fe11edbda85c	166
mbed_official	532:fe11edbda85c	167	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
mbed_official	532:fe11edbda85c	168	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	532:fe11edbda85c	169
mbed_official	532:fe11edbda85c	170	uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
mbed_official	532:fe11edbda85c	171	This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
mbed_official	532:fe11edbda85c	172
mbed_official	532:fe11edbda85c	173	uint32_t CecClockSelection; /*!< Specifies CEC Clock Source Selection.
mbed_official	532:fe11edbda85c	174	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
mbed_official	532:fe11edbda85c	175
mbed_official	532:fe11edbda85c	176	uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
mbed_official	532:fe11edbda85c	177	This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
mbed_official	532:fe11edbda85c	178
mbed_official	532:fe11edbda85c	179	uint32_t SpdifClockSelection; /*!< Specifies SPDIFRX Clock Source Selection.
mbed_official	532:fe11edbda85c	180	This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */
mbed_official	532:fe11edbda85c	181
mbed_official	532:fe11edbda85c	182	uint32_t Clk48ClockSelection; /*!< Specifies CK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
mbed_official	532:fe11edbda85c	183	This parameter can be a value of @ref RCCEx_CK48_Clock_Source */
mbed_official	532:fe11edbda85c	184
mbed_official	532:fe11edbda85c	185	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
mbed_official	532:fe11edbda85c	186	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
mbed_official	532:fe11edbda85c	187	}RCC_PeriphCLKInitTypeDef;
mbed_official	532:fe11edbda85c	188	#endif /* STM32F446xx */
mbed_official	532:fe11edbda85c	189
mbed_official	532:fe11edbda85c	190	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
mbed_official	532:fe11edbda85c	191
mbed_official	235:685d5f11838f	192	/**
mbed_official	235:685d5f11838f	193	* @brief PLLI2S Clock structure definition
mbed_official	235:685d5f11838f	194	*/
mbed_official	235:685d5f11838f	195	typedef struct
mbed_official	235:685d5f11838f	196	{
mbed_official	235:685d5f11838f	197	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
mbed_official	235:685d5f11838f	198	This parameter must be a number between Min_Data = 192 and Max_Data = 432.
mbed_official	235:685d5f11838f	199	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
mbed_official	235:685d5f11838f	200
mbed_official	235:685d5f11838f	201	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
mbed_official	235:685d5f11838f	202	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
mbed_official	235:685d5f11838f	203	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
mbed_official	235:685d5f11838f	204
mbed_official	235:685d5f11838f	205	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
mbed_official	235:685d5f11838f	206	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
mbed_official	235:685d5f11838f	207	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
mbed_official	235:685d5f11838f	208	}RCC_PLLI2SInitTypeDef;
mbed_official	235:685d5f11838f	209
mbed_official	235:685d5f11838f	210	/**
mbed_official	235:685d5f11838f	211	* @brief PLLSAI Clock structure definition
mbed_official	235:685d5f11838f	212	*/
mbed_official	235:685d5f11838f	213	typedef struct
mbed_official	235:685d5f11838f	214	{
mbed_official	235:685d5f11838f	215	uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
mbed_official	235:685d5f11838f	216	This parameter must be a number between Min_Data = 192 and Max_Data = 432.
mbed_official	235:685d5f11838f	217	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
mbed_official	235:685d5f11838f	218
mbed_official	235:685d5f11838f	219	uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
mbed_official	235:685d5f11838f	220	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
mbed_official	235:685d5f11838f	221	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
mbed_official	235:685d5f11838f	222
mbed_official	235:685d5f11838f	223	uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
mbed_official	235:685d5f11838f	224	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
mbed_official	235:685d5f11838f	225	This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
mbed_official	235:685d5f11838f	226
mbed_official	235:685d5f11838f	227	}RCC_PLLSAIInitTypeDef;
mbed_official	235:685d5f11838f	228	/**
mbed_official	235:685d5f11838f	229	* @brief RCC extended clocks structure definition
mbed_official	235:685d5f11838f	230	*/
mbed_official	235:685d5f11838f	231	typedef struct
mbed_official	235:685d5f11838f	232	{
mbed_official	235:685d5f11838f	233	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	235:685d5f11838f	234	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	235:685d5f11838f	235
mbed_official	235:685d5f11838f	236	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
mbed_official	235:685d5f11838f	237	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
mbed_official	235:685d5f11838f	238
mbed_official	235:685d5f11838f	239	RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
mbed_official	235:685d5f11838f	240	This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
mbed_official	235:685d5f11838f	241
mbed_official	235:685d5f11838f	242	uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
mbed_official	235:685d5f11838f	243	This parameter must be a number between Min_Data = 1 and Max_Data = 32
mbed_official	235:685d5f11838f	244	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
mbed_official	235:685d5f11838f	245
mbed_official	235:685d5f11838f	246	uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
mbed_official	235:685d5f11838f	247	This parameter must be a number between Min_Data = 1 and Max_Data = 32
mbed_official	235:685d5f11838f	248	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
mbed_official	235:685d5f11838f	249
mbed_official	235:685d5f11838f	250	uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
mbed_official	235:685d5f11838f	251	This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
mbed_official	235:685d5f11838f	252
mbed_official	235:685d5f11838f	253	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
mbed_official	235:685d5f11838f	254	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	235:685d5f11838f	255
mbed_official	235:685d5f11838f	256	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
mbed_official	235:685d5f11838f	257	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
mbed_official	235:685d5f11838f	258
mbed_official	235:685d5f11838f	259	}RCC_PeriphCLKInitTypeDef;
mbed_official	235:685d5f11838f	260	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
mbed_official	235:685d5f11838f	261
mbed_official	235:685d5f11838f	262	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx) \|\|\
mbed_official	235:685d5f11838f	263	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
mbed_official	235:685d5f11838f	264	/**
mbed_official	235:685d5f11838f	265	* @brief PLLI2S Clock structure definition
mbed_official	235:685d5f11838f	266	*/
mbed_official	235:685d5f11838f	267	typedef struct
mbed_official	235:685d5f11838f	268	{
mbed_official	235:685d5f11838f	269	#if defined(STM32F411xE)
mbed_official	235:685d5f11838f	270	uint32_t PLLI2SM; /*!< PLLM: Division factor for PLLI2S VCO input clock.
mbed_official	235:685d5f11838f	271	This parameter must be a number between Min_Data = 2 and Max_Data = 62 */
mbed_official	235:685d5f11838f	272	#endif /* STM32F411xE */
mbed_official	235:685d5f11838f	273
mbed_official	235:685d5f11838f	274	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
mbed_official	235:685d5f11838f	275	This parameter must be a number between Min_Data = 192 and Max_Data = 432
mbed_official	235:685d5f11838f	276	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
mbed_official	235:685d5f11838f	277
mbed_official	235:685d5f11838f	278	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
mbed_official	235:685d5f11838f	279	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
mbed_official	235:685d5f11838f	280	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
mbed_official	235:685d5f11838f	281
mbed_official	235:685d5f11838f	282	}RCC_PLLI2SInitTypeDef;
mbed_official	235:685d5f11838f	283
mbed_official	235:685d5f11838f	284
mbed_official	235:685d5f11838f	285	/**
mbed_official	235:685d5f11838f	286	* @brief RCC extended clocks structure definition
mbed_official	235:685d5f11838f	287	*/
mbed_official	235:685d5f11838f	288	typedef struct
mbed_official	235:685d5f11838f	289	{
mbed_official	235:685d5f11838f	290	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	235:685d5f11838f	291	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	235:685d5f11838f	292
mbed_official	235:685d5f11838f	293	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
mbed_official	235:685d5f11838f	294	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
mbed_official	235:685d5f11838f	295
mbed_official	235:685d5f11838f	296	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
mbed_official	235:685d5f11838f	297	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	235:685d5f11838f	298
mbed_official	235:685d5f11838f	299	}RCC_PeriphCLKInitTypeDef;
mbed_official	235:685d5f11838f	300	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
mbed_official	532:fe11edbda85c	301	/**
mbed_official	532:fe11edbda85c	302	* @}
mbed_official	532:fe11edbda85c	303	*/
mbed_official	532:fe11edbda85c	304
mbed_official	235:685d5f11838f	305	/* Exported constants --------------------------------------------------------*/
mbed_official	532:fe11edbda85c	306	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
mbed_official	235:685d5f11838f	307	* @{
mbed_official	235:685d5f11838f	308	*/
mbed_official	235:685d5f11838f	309
mbed_official	532:fe11edbda85c	310	/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
mbed_official	235:685d5f11838f	311	* @{
mbed_official	235:685d5f11838f	312	*/
mbed_official	532:fe11edbda85c	313	/------------------------------- Peripheral Clock source for STM32F446xx -----------------------------/
mbed_official	532:fe11edbda85c	314	#if defined(STM32F446xx)
mbed_official	532:fe11edbda85c	315	#define RCC_PERIPHCLK_I2S_APB1 ((uint32_t)0x00000001)
mbed_official	532:fe11edbda85c	316	#define RCC_PERIPHCLK_I2S_APB2 ((uint32_t)0x00000002)
mbed_official	532:fe11edbda85c	317	#define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00000004)
mbed_official	532:fe11edbda85c	318	#define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00000008)
mbed_official	532:fe11edbda85c	319	#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
mbed_official	532:fe11edbda85c	320	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
mbed_official	532:fe11edbda85c	321	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000040)
mbed_official	532:fe11edbda85c	322	#define RCC_PERIPHCLK_FMPI2C1 ((uint32_t)0x00000080)
mbed_official	532:fe11edbda85c	323	#define RCC_PERIPHCLK_CK48 ((uint32_t)0x00000100)
mbed_official	532:fe11edbda85c	324	#define RCC_PERIPHCLK_SDIO ((uint32_t)0x00000200)
mbed_official	532:fe11edbda85c	325	#define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x00000400)
mbed_official	532:fe11edbda85c	326	#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000800)
mbed_official	532:fe11edbda85c	327	#endif /* STM32F446xx */
mbed_official	532:fe11edbda85c	328	/-----------------------------------------------------------------------------------------------------/
mbed_official	532:fe11edbda85c	329
mbed_official	532:fe11edbda85c	330	/--------------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------------/
mbed_official	532:fe11edbda85c	331	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
mbed_official	235:685d5f11838f	332	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
mbed_official	235:685d5f11838f	333	#define RCC_PERIPHCLK_SAI_PLLI2S ((uint32_t)0x00000002)
mbed_official	235:685d5f11838f	334	#define RCC_PERIPHCLK_SAI_PLLSAI ((uint32_t)0x00000004)
mbed_official	235:685d5f11838f	335	#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008)
mbed_official	235:685d5f11838f	336	#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
mbed_official	235:685d5f11838f	337	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
mbed_official	532:fe11edbda85c	338	#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000040)
mbed_official	235:685d5f11838f	339	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
mbed_official	532:fe11edbda85c	340	/-----------------------------------------------------------------------------------------------------/
mbed_official	235:685d5f11838f	341
mbed_official	532:fe11edbda85c	342	/------------------------ Peripheral Clock source for STM32F40xxx/STM32F41xxx ------------------------/
mbed_official	235:685d5f11838f	343	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx) \|\|\
mbed_official	235:685d5f11838f	344	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
mbed_official	235:685d5f11838f	345	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
mbed_official	235:685d5f11838f	346	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000002)
mbed_official	532:fe11edbda85c	347	#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000004)
mbed_official	235:685d5f11838f	348	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
mbed_official	532:fe11edbda85c	349	/-----------------------------------------------------------------------------------------------------/
mbed_official	235:685d5f11838f	350	/**
mbed_official	235:685d5f11838f	351	* @}
mbed_official	235:685d5f11838f	352	*/
mbed_official	235:685d5f11838f	353
mbed_official	532:fe11edbda85c	354	/** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR
mbed_official	235:685d5f11838f	355	* @{
mbed_official	532:fe11edbda85c	356	*/
mbed_official	532:fe11edbda85c	357	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx)
mbed_official	532:fe11edbda85c	358	#define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000)
mbed_official	532:fe11edbda85c	359	#define RCC_PLLSAIDIVR_4 ((uint32_t)0x00010000)
mbed_official	532:fe11edbda85c	360	#define RCC_PLLSAIDIVR_8 ((uint32_t)0x00020000)
mbed_official	532:fe11edbda85c	361	#define RCC_PLLSAIDIVR_16 ((uint32_t)0x00030000)
mbed_official	532:fe11edbda85c	362	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx */
mbed_official	235:685d5f11838f	363	/**
mbed_official	235:685d5f11838f	364	* @}
mbed_official	235:685d5f11838f	365	*/
mbed_official	235:685d5f11838f	366
mbed_official	532:fe11edbda85c	367	/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCC PLLI2SP Clock Divider
mbed_official	235:685d5f11838f	368	* @{
mbed_official	235:685d5f11838f	369	*/
mbed_official	532:fe11edbda85c	370	#if defined(STM32F446xx)
mbed_official	532:fe11edbda85c	371	#define RCC_PLLI2SP_DIV2 ((uint32_t)0x00000002)
mbed_official	532:fe11edbda85c	372	#define RCC_PLLI2SP_DIV4 ((uint32_t)0x00000004)
mbed_official	532:fe11edbda85c	373	#define RCC_PLLI2SP_DIV6 ((uint32_t)0x00000006)
mbed_official	532:fe11edbda85c	374	#define RCC_PLLI2SP_DIV8 ((uint32_t)0x00000008)
mbed_official	532:fe11edbda85c	375	#endif /* STM32F446xx */
mbed_official	235:685d5f11838f	376	/**
mbed_official	235:685d5f11838f	377	* @}
mbed_official	235:685d5f11838f	378	*/
mbed_official	235:685d5f11838f	379
mbed_official	532:fe11edbda85c	380	/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCC PLLSAIP Clock Divider
mbed_official	235:685d5f11838f	381	* @{
mbed_official	532:fe11edbda85c	382	*/
mbed_official	532:fe11edbda85c	383	#if defined(STM32F446xx)
mbed_official	532:fe11edbda85c	384	#define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000002)
mbed_official	532:fe11edbda85c	385	#define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000004)
mbed_official	532:fe11edbda85c	386	#define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000006)
mbed_official	532:fe11edbda85c	387	#define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000008)
mbed_official	532:fe11edbda85c	388	#endif /* STM32F446xx */
mbed_official	235:685d5f11838f	389	/**
mbed_official	235:685d5f11838f	390	* @}
mbed_official	235:685d5f11838f	391	*/
mbed_official	235:685d5f11838f	392
mbed_official	532:fe11edbda85c	393	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
mbed_official	532:fe11edbda85c	394	/** @defgroup RCCEx_SAI_BlockA_Clock_Source RCC SAI BlockA Clock Source
mbed_official	235:685d5f11838f	395	* @{
mbed_official	235:685d5f11838f	396	*/
mbed_official	235:685d5f11838f	397	#define RCC_SAIACLKSOURCE_PLLSAI ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	398	#define RCC_SAIACLKSOURCE_PLLI2S ((uint32_t)0x00100000)
mbed_official	235:685d5f11838f	399	#define RCC_SAIACLKSOURCE_EXT ((uint32_t)0x00200000)
mbed_official	235:685d5f11838f	400	/**
mbed_official	235:685d5f11838f	401	* @}
mbed_official	235:685d5f11838f	402	*/
mbed_official	235:685d5f11838f	403
mbed_official	532:fe11edbda85c	404	/** @defgroup RCCEx_SAI_BlockB_Clock_Source RCC SAI BlockB Clock Source
mbed_official	235:685d5f11838f	405	* @{
mbed_official	235:685d5f11838f	406	*/
mbed_official	235:685d5f11838f	407	#define RCC_SAIBCLKSOURCE_PLLSAI ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	408	#define RCC_SAIBCLKSOURCE_PLLI2S ((uint32_t)0x00400000)
mbed_official	235:685d5f11838f	409	#define RCC_SAIBCLKSOURCE_EXT ((uint32_t)0x00800000)
mbed_official	235:685d5f11838f	410	/**
mbed_official	235:685d5f11838f	411	* @}
mbed_official	235:685d5f11838f	412	*/
mbed_official	532:fe11edbda85c	413	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
mbed_official	235:685d5f11838f	414
mbed_official	532:fe11edbda85c	415	#if defined(STM32F446xx)
mbed_official	532:fe11edbda85c	416	/** @defgroup RCCEx_SAI1_Clock_Source RCC SAI1 Clock Source
mbed_official	532:fe11edbda85c	417	* @{
mbed_official	532:fe11edbda85c	418	*/
mbed_official	532:fe11edbda85c	419	#define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000)
mbed_official	532:fe11edbda85c	420	#define RCC_SAI1CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0)
mbed_official	532:fe11edbda85c	421	#define RCC_SAI1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1SRC_1)
mbed_official	532:fe11edbda85c	422	#define RCC_SAI1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1SRC)
mbed_official	532:fe11edbda85c	423	/**
mbed_official	532:fe11edbda85c	424	* @}
mbed_official	532:fe11edbda85c	425	*/
mbed_official	532:fe11edbda85c	426
mbed_official	532:fe11edbda85c	427	/** @defgroup RCCEx_SAI2_Clock_Source RCC SAI2 Clock Source
mbed_official	532:fe11edbda85c	428	* @{
mbed_official	532:fe11edbda85c	429	*/
mbed_official	532:fe11edbda85c	430	#define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000)
mbed_official	532:fe11edbda85c	431	#define RCC_SAI2CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI2SRC_0)
mbed_official	532:fe11edbda85c	432	#define RCC_SAI2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI2SRC_1)
mbed_official	532:fe11edbda85c	433	#define RCC_SAI2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI2SRC)
mbed_official	532:fe11edbda85c	434	/**
mbed_official	532:fe11edbda85c	435	* @}
mbed_official	532:fe11edbda85c	436	*/
mbed_official	532:fe11edbda85c	437
mbed_official	532:fe11edbda85c	438	/** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source
mbed_official	532:fe11edbda85c	439	* @{
mbed_official	532:fe11edbda85c	440	*/
mbed_official	532:fe11edbda85c	441	#define RCC_I2SAPB1CLKSOURCE_PLLI2S ((uint32_t)0x00000000)
mbed_official	532:fe11edbda85c	442	#define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
mbed_official	532:fe11edbda85c	443	#define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
mbed_official	532:fe11edbda85c	444	#define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC)
mbed_official	532:fe11edbda85c	445	/**
mbed_official	532:fe11edbda85c	446	* @}
mbed_official	532:fe11edbda85c	447	*/
mbed_official	532:fe11edbda85c	448
mbed_official	532:fe11edbda85c	449	/** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source
mbed_official	532:fe11edbda85c	450	* @{
mbed_official	532:fe11edbda85c	451	*/
mbed_official	532:fe11edbda85c	452	#define RCC_I2SAPB2CLKSOURCE_PLLI2S ((uint32_t)0x00000000)
mbed_official	532:fe11edbda85c	453	#define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
mbed_official	532:fe11edbda85c	454	#define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
mbed_official	532:fe11edbda85c	455	#define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC)
mbed_official	532:fe11edbda85c	456	/**
mbed_official	532:fe11edbda85c	457	* @}
mbed_official	532:fe11edbda85c	458	*/
mbed_official	532:fe11edbda85c	459
mbed_official	532:fe11edbda85c	460	/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
mbed_official	532:fe11edbda85c	461	* @{
mbed_official	532:fe11edbda85c	462	*/
mbed_official	532:fe11edbda85c	463	#define RCC_FMPI2C1CLKSOURCE_APB ((uint32_t)0x00000000)
mbed_official	532:fe11edbda85c	464	#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
mbed_official	532:fe11edbda85c	465	#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
mbed_official	532:fe11edbda85c	466	/**
mbed_official	532:fe11edbda85c	467	* @}
mbed_official	532:fe11edbda85c	468	*/
mbed_official	532:fe11edbda85c	469
mbed_official	532:fe11edbda85c	470	/** @defgroup RCCEx_CEC_Clock_Source RCC CEC Clock Source
mbed_official	532:fe11edbda85c	471	* @{
mbed_official	532:fe11edbda85c	472	*/
mbed_official	532:fe11edbda85c	473	#define RCC_CECCLKSOURCE_HSI ((uint32_t)0x00000000)
mbed_official	532:fe11edbda85c	474	#define RCC_CECCLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_CECSEL)
mbed_official	532:fe11edbda85c	475	/**
mbed_official	532:fe11edbda85c	476	* @}
mbed_official	532:fe11edbda85c	477	*/
mbed_official	532:fe11edbda85c	478
mbed_official	532:fe11edbda85c	479	/** @defgroup RCCEx_CK48_Clock_Source RCC CK48 Clock Source
mbed_official	532:fe11edbda85c	480	* @{
mbed_official	532:fe11edbda85c	481	*/
mbed_official	532:fe11edbda85c	482	#define RCC_CK48CLKSOURCE_PLLQ ((uint32_t)0x00000000)
mbed_official	532:fe11edbda85c	483	#define RCC_CK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
mbed_official	532:fe11edbda85c	484	/**
mbed_official	532:fe11edbda85c	485	* @}
mbed_official	532:fe11edbda85c	486	*/
mbed_official	532:fe11edbda85c	487
mbed_official	532:fe11edbda85c	488	/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
mbed_official	532:fe11edbda85c	489	* @{
mbed_official	532:fe11edbda85c	490	*/
mbed_official	532:fe11edbda85c	491	#define RCC_SDIOCLKSOURCE_CK48 ((uint32_t)0x00000000)
mbed_official	532:fe11edbda85c	492	#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
mbed_official	532:fe11edbda85c	493	/**
mbed_official	532:fe11edbda85c	494	* @}
mbed_official	532:fe11edbda85c	495	*/
mbed_official	532:fe11edbda85c	496
mbed_official	532:fe11edbda85c	497	/** @defgroup RCCEx_SPDIFRX_Clock_Source RCC SPDIFRX Clock Source
mbed_official	532:fe11edbda85c	498	* @{
mbed_official	532:fe11edbda85c	499	*/
mbed_official	532:fe11edbda85c	500	#define RCC_SPDIFRXCLKSOURCE_PLLR ((uint32_t)0x00000000)
mbed_official	532:fe11edbda85c	501	#define RCC_SPDIFRXCLKSOURCE_PLLI2SP ((uint32_t)RCC_DCKCFGR2_SPDIFRXSEL)
mbed_official	532:fe11edbda85c	502	/**
mbed_official	532:fe11edbda85c	503	* @}
mbed_official	532:fe11edbda85c	504	*/
mbed_official	532:fe11edbda85c	505
mbed_official	532:fe11edbda85c	506	#endif /* STM32F446xx */
mbed_official	532:fe11edbda85c	507
mbed_official	532:fe11edbda85c	508	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\|\
mbed_official	532:fe11edbda85c	509	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx)
mbed_official	532:fe11edbda85c	510	/** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection
mbed_official	235:685d5f11838f	511	* @{
mbed_official	235:685d5f11838f	512	*/
mbed_official	235:685d5f11838f	513	#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
mbed_official	235:685d5f11838f	514	#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
mbed_official	235:685d5f11838f	515	/**
mbed_official	235:685d5f11838f	516	* @}
mbed_official	235:685d5f11838f	517	*/
mbed_official	532:fe11edbda85c	518	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx) \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx */
mbed_official	235:685d5f11838f	519
mbed_official	532:fe11edbda85c	520	#if defined(STM32F411xE) \|\| defined(STM32F446xx)
mbed_official	532:fe11edbda85c	521	/** @defgroup RCCEx_LSE_Dual_Mode_Selection RCC LSE Dual Mode Selection
mbed_official	235:685d5f11838f	522	* @{
mbed_official	235:685d5f11838f	523	*/
mbed_official	235:685d5f11838f	524	#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
mbed_official	235:685d5f11838f	525	#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
mbed_official	235:685d5f11838f	526	/**
mbed_official	235:685d5f11838f	527	* @}
mbed_official	235:685d5f11838f	528	*/
mbed_official	532:fe11edbda85c	529	#endif /* STM32F411xE \|\| STM32F446xx */
mbed_official	532:fe11edbda85c	530
mbed_official	235:685d5f11838f	531	/**
mbed_official	235:685d5f11838f	532	* @}
mbed_official	235:685d5f11838f	533	*/
mbed_official	235:685d5f11838f	534
mbed_official	235:685d5f11838f	535	/* Exported macro ------------------------------------------------------------*/
mbed_official	532:fe11edbda85c	536	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
mbed_official	532:fe11edbda85c	537	* @{
mbed_official	532:fe11edbda85c	538	*/
mbed_official	532:fe11edbda85c	539	/------------------------------- STM32F42xxx/STM32F43xxx ----------------------------------/
mbed_official	235:685d5f11838f	540	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
mbed_official	235:685d5f11838f	541	/** @brief Enables or disables the AHB1 peripheral clock.
mbed_official	235:685d5f11838f	542	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	235:685d5f11838f	543	* is disabled and the application software has to enable this clock before
mbed_official	235:685d5f11838f	544	* using it.
mbed_official	235:685d5f11838f	545	*/
mbed_official	532:fe11edbda85c	546	#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	547	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	548	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
mbed_official	532:fe11edbda85c	549	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	550	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
mbed_official	532:fe11edbda85c	551	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	552	} while(0)
mbed_official	532:fe11edbda85c	553	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	554	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	555	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
mbed_official	532:fe11edbda85c	556	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	557	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
mbed_official	532:fe11edbda85c	558	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	559	} while(0)
mbed_official	532:fe11edbda85c	560	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	561	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	562	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
mbed_official	532:fe11edbda85c	563	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	564	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
mbed_official	532:fe11edbda85c	565	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	566	} while(0)
mbed_official	532:fe11edbda85c	567	#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	568	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	569	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
mbed_official	532:fe11edbda85c	570	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	571	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
mbed_official	532:fe11edbda85c	572	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	573	} while(0)
mbed_official	532:fe11edbda85c	574	#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	575	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	576	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
mbed_official	532:fe11edbda85c	577	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	578	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
mbed_official	532:fe11edbda85c	579	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	580	} while(0)
mbed_official	532:fe11edbda85c	581	#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	582	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	583	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
mbed_official	532:fe11edbda85c	584	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	585	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
mbed_official	532:fe11edbda85c	586	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	587	} while(0)
mbed_official	532:fe11edbda85c	588	#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	589	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	590	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
mbed_official	532:fe11edbda85c	591	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	592	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
mbed_official	532:fe11edbda85c	593	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	594	} while(0)
mbed_official	532:fe11edbda85c	595	#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	596	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	597	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
mbed_official	532:fe11edbda85c	598	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	599	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
mbed_official	532:fe11edbda85c	600	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	601	} while(0)
mbed_official	532:fe11edbda85c	602	#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	603	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	604	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
mbed_official	532:fe11edbda85c	605	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	606	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
mbed_official	532:fe11edbda85c	607	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	608	} while(0)
mbed_official	532:fe11edbda85c	609	#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	610	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	611	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
mbed_official	532:fe11edbda85c	612	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	613	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
mbed_official	532:fe11edbda85c	614	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	615	} while(0)
mbed_official	532:fe11edbda85c	616	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	617	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	618	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
mbed_official	532:fe11edbda85c	619	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	620	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
mbed_official	532:fe11edbda85c	621	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	622	} while(0)
mbed_official	532:fe11edbda85c	623	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	624	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	625	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
mbed_official	532:fe11edbda85c	626	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	627	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
mbed_official	532:fe11edbda85c	628	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	629	} while(0)
mbed_official	235:685d5f11838f	630
mbed_official	532:fe11edbda85c	631	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
mbed_official	532:fe11edbda85c	632	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
mbed_official	532:fe11edbda85c	633	#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
mbed_official	532:fe11edbda85c	634	#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
mbed_official	532:fe11edbda85c	635	#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
mbed_official	532:fe11edbda85c	636	#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
mbed_official	532:fe11edbda85c	637	#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
mbed_official	532:fe11edbda85c	638	#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
mbed_official	532:fe11edbda85c	639	#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
mbed_official	532:fe11edbda85c	640	#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
mbed_official	532:fe11edbda85c	641	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
mbed_official	532:fe11edbda85c	642	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
mbed_official	235:685d5f11838f	643
mbed_official	235:685d5f11838f	644	/**
mbed_official	235:685d5f11838f	645	* @brief Enable ETHERNET clock.
mbed_official	235:685d5f11838f	646	*/
mbed_official	532:fe11edbda85c	647	#define __HAL_RCC_ETH_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	648	__HAL_RCC_ETHMAC_CLK_ENABLE(); \
mbed_official	532:fe11edbda85c	649	__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
mbed_official	532:fe11edbda85c	650	__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
mbed_official	532:fe11edbda85c	651	} while(0)
mbed_official	235:685d5f11838f	652	/**
mbed_official	235:685d5f11838f	653	* @brief Disable ETHERNET clock.
mbed_official	235:685d5f11838f	654	*/
mbed_official	532:fe11edbda85c	655	#define __HAL_RCC_ETH_CLK_DISABLE() do { \
mbed_official	532:fe11edbda85c	656	__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
mbed_official	532:fe11edbda85c	657	__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
mbed_official	532:fe11edbda85c	658	__HAL_RCC_ETHMAC_CLK_DISABLE(); \
mbed_official	532:fe11edbda85c	659	} while(0)
mbed_official	235:685d5f11838f	660
mbed_official	235:685d5f11838f	661	/** @brief Enable or disable the AHB2 peripheral clock.
mbed_official	235:685d5f11838f	662	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	235:685d5f11838f	663	* is disabled and the application software has to enable this clock before
mbed_official	235:685d5f11838f	664	* using it.
mbed_official	235:685d5f11838f	665	*/
mbed_official	235:685d5f11838f	666
mbed_official	532:fe11edbda85c	667	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	668	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	669	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
mbed_official	532:fe11edbda85c	670	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	671	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
mbed_official	532:fe11edbda85c	672	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	673	} while(0)
mbed_official	532:fe11edbda85c	674	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
mbed_official	235:685d5f11838f	675
mbed_official	235:685d5f11838f	676	#if defined(STM32F437xx)\|\| defined(STM32F439xx)
mbed_official	532:fe11edbda85c	677	#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	678	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	679	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
mbed_official	532:fe11edbda85c	680	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	681	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
mbed_official	532:fe11edbda85c	682	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	683	} while(0)
mbed_official	532:fe11edbda85c	684	#define __HAL_RCC_HASH_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	685	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	686	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
mbed_official	532:fe11edbda85c	687	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	688	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
mbed_official	532:fe11edbda85c	689	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	690	} while(0)
mbed_official	235:685d5f11838f	691
mbed_official	532:fe11edbda85c	692	#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
mbed_official	532:fe11edbda85c	693	#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
mbed_official	235:685d5f11838f	694	#endif /* STM32F437xx \|\| STM32F439xx */
mbed_official	235:685d5f11838f	695
mbed_official	235:685d5f11838f	696	/** @brief Enables or disables the AHB3 peripheral clock.
mbed_official	235:685d5f11838f	697	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	235:685d5f11838f	698	* is disabled and the application software has to enable this clock before
mbed_official	235:685d5f11838f	699	* using it.
mbed_official	235:685d5f11838f	700	*/
mbed_official	532:fe11edbda85c	701	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	702	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	703	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
mbed_official	532:fe11edbda85c	704	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	705	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
mbed_official	532:fe11edbda85c	706	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	707	} while(0)
mbed_official	532:fe11edbda85c	708	#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
mbed_official	235:685d5f11838f	709
mbed_official	235:685d5f11838f	710	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
mbed_official	235:685d5f11838f	711	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	235:685d5f11838f	712	* is disabled and the application software has to enable this clock before
mbed_official	235:685d5f11838f	713	* using it.
mbed_official	235:685d5f11838f	714	*/
mbed_official	532:fe11edbda85c	715	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	716	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	717	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
mbed_official	532:fe11edbda85c	718	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	719	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
mbed_official	532:fe11edbda85c	720	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	721	} while(0)
mbed_official	532:fe11edbda85c	722	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	723	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	724	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
mbed_official	532:fe11edbda85c	725	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	726	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
mbed_official	532:fe11edbda85c	727	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	728	} while(0)
mbed_official	532:fe11edbda85c	729	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	730	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	731	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
mbed_official	532:fe11edbda85c	732	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	733	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
mbed_official	532:fe11edbda85c	734	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	735	} while(0)
mbed_official	532:fe11edbda85c	736	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	737	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	738	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
mbed_official	532:fe11edbda85c	739	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	740	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
mbed_official	532:fe11edbda85c	741	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	742	} while(0)
mbed_official	532:fe11edbda85c	743	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	744	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	745	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
mbed_official	532:fe11edbda85c	746	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	747	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
mbed_official	532:fe11edbda85c	748	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	749	} while(0)
mbed_official	532:fe11edbda85c	750	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	751	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	752	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
mbed_official	532:fe11edbda85c	753	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	754	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
mbed_official	532:fe11edbda85c	755	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	756	} while(0)
mbed_official	532:fe11edbda85c	757	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	758	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	759	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
mbed_official	532:fe11edbda85c	760	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	761	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
mbed_official	532:fe11edbda85c	762	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	763	} while(0)
mbed_official	532:fe11edbda85c	764	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	765	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	766	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
mbed_official	532:fe11edbda85c	767	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	768	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
mbed_official	532:fe11edbda85c	769	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	770	} while(0)
mbed_official	532:fe11edbda85c	771	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	772	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	773	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
mbed_official	532:fe11edbda85c	774	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	775	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
mbed_official	532:fe11edbda85c	776	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	777	} while(0)
mbed_official	532:fe11edbda85c	778	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	779	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	780	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
mbed_official	532:fe11edbda85c	781	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	782	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
mbed_official	532:fe11edbda85c	783	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	784	} while(0)
mbed_official	532:fe11edbda85c	785	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	786	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	787	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
mbed_official	532:fe11edbda85c	788	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	789	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
mbed_official	532:fe11edbda85c	790	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	791	} while(0)
mbed_official	532:fe11edbda85c	792	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	793	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	794	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
mbed_official	532:fe11edbda85c	795	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	796	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
mbed_official	532:fe11edbda85c	797	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	798	} while(0)
mbed_official	532:fe11edbda85c	799	#define __HAL_RCC_UART7_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	800	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	801	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
mbed_official	532:fe11edbda85c	802	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	803	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
mbed_official	532:fe11edbda85c	804	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	805	} while(0)
mbed_official	532:fe11edbda85c	806	#define __HAL_RCC_UART8_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	807	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	808	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
mbed_official	532:fe11edbda85c	809	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	810	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
mbed_official	532:fe11edbda85c	811	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	812	} while(0)
mbed_official	235:685d5f11838f	813
mbed_official	532:fe11edbda85c	814	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
mbed_official	532:fe11edbda85c	815	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
mbed_official	532:fe11edbda85c	816	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
mbed_official	532:fe11edbda85c	817	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
mbed_official	532:fe11edbda85c	818	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
mbed_official	532:fe11edbda85c	819	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
mbed_official	532:fe11edbda85c	820	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
mbed_official	532:fe11edbda85c	821	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
mbed_official	532:fe11edbda85c	822	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
mbed_official	532:fe11edbda85c	823	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
mbed_official	532:fe11edbda85c	824	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
mbed_official	532:fe11edbda85c	825	#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
mbed_official	532:fe11edbda85c	826	#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
mbed_official	235:685d5f11838f	827
mbed_official	235:685d5f11838f	828	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
mbed_official	235:685d5f11838f	829	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	235:685d5f11838f	830	* is disabled and the application software has to enable this clock before
mbed_official	235:685d5f11838f	831	* using it.
mbed_official	235:685d5f11838f	832	*/
mbed_official	532:fe11edbda85c	833	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	834	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	835	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
mbed_official	532:fe11edbda85c	836	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	837	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
mbed_official	532:fe11edbda85c	838	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	839	} while(0)
mbed_official	532:fe11edbda85c	840	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	841	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	842	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
mbed_official	532:fe11edbda85c	843	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	844	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
mbed_official	532:fe11edbda85c	845	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	846	} while(0)
mbed_official	532:fe11edbda85c	847	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	848	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	849	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
mbed_official	532:fe11edbda85c	850	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	851	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
mbed_official	532:fe11edbda85c	852	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	853	} while(0)
mbed_official	532:fe11edbda85c	854	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	855	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	856	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
mbed_official	532:fe11edbda85c	857	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	858	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
mbed_official	532:fe11edbda85c	859	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	860	} while(0)
mbed_official	532:fe11edbda85c	861	#define __HAL_RCC_SPI6_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	862	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	863	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
mbed_official	532:fe11edbda85c	864	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	865	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
mbed_official	532:fe11edbda85c	866	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	867	} while(0)
mbed_official	532:fe11edbda85c	868	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	869	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	870	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
mbed_official	532:fe11edbda85c	871	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	872	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
mbed_official	532:fe11edbda85c	873	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	874	} while(0)
mbed_official	235:685d5f11838f	875
mbed_official	532:fe11edbda85c	876	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
mbed_official	532:fe11edbda85c	877	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
mbed_official	532:fe11edbda85c	878	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
mbed_official	532:fe11edbda85c	879	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
mbed_official	532:fe11edbda85c	880	#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
mbed_official	532:fe11edbda85c	881	#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
mbed_official	235:685d5f11838f	882
mbed_official	235:685d5f11838f	883	#if defined(STM32F429xx)\|\| defined(STM32F439xx)
mbed_official	532:fe11edbda85c	884	#define __HAL_RCC_LTDC_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_LTDCEN))
mbed_official	235:685d5f11838f	885
mbed_official	532:fe11edbda85c	886	#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
mbed_official	235:685d5f11838f	887	#endif /* STM32F429xx \|\| STM32F439xx */
mbed_official	235:685d5f11838f	888
mbed_official	235:685d5f11838f	889	/** @brief Force or release AHB1 peripheral reset.
mbed_official	235:685d5f11838f	890	*/
mbed_official	532:fe11edbda85c	891	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
mbed_official	532:fe11edbda85c	892	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
mbed_official	532:fe11edbda85c	893	#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOIRST))
mbed_official	532:fe11edbda85c	894	#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_ETHMACRST))
mbed_official	532:fe11edbda85c	895	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
mbed_official	532:fe11edbda85c	896	#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOJRST))
mbed_official	532:fe11edbda85c	897	#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOKRST))
mbed_official	532:fe11edbda85c	898	#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2DRST))
mbed_official	235:685d5f11838f	899
mbed_official	532:fe11edbda85c	900	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
mbed_official	532:fe11edbda85c	901	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
mbed_official	532:fe11edbda85c	902	#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
mbed_official	532:fe11edbda85c	903	#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
mbed_official	532:fe11edbda85c	904	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
mbed_official	532:fe11edbda85c	905	#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
mbed_official	532:fe11edbda85c	906	#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
mbed_official	532:fe11edbda85c	907	#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
mbed_official	235:685d5f11838f	908
mbed_official	235:685d5f11838f	909	/** @brief Force or release AHB2 peripheral reset.
mbed_official	235:685d5f11838f	910	*/
mbed_official	532:fe11edbda85c	911	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
mbed_official	532:fe11edbda85c	912	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
mbed_official	235:685d5f11838f	913
mbed_official	532:fe11edbda85c	914	#if defined(STM32F437xx)\|\| defined(STM32F439xx)
mbed_official	532:fe11edbda85c	915	#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_CRYPRST))
mbed_official	532:fe11edbda85c	916	#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_HASHRST))
mbed_official	235:685d5f11838f	917
mbed_official	532:fe11edbda85c	918	#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
mbed_official	532:fe11edbda85c	919	#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
mbed_official	235:685d5f11838f	920	#endif /* STM32F437xx \|\| STM32F439xx */
mbed_official	235:685d5f11838f	921
mbed_official	235:685d5f11838f	922	/** @brief Force or release AHB3 peripheral reset
mbed_official	235:685d5f11838f	923	*/
mbed_official	532:fe11edbda85c	924	#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FMCRST))
mbed_official	532:fe11edbda85c	925	#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
mbed_official	235:685d5f11838f	926
mbed_official	235:685d5f11838f	927	/** @brief Force or release APB1 peripheral reset.
mbed_official	235:685d5f11838f	928	*/
mbed_official	532:fe11edbda85c	929	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
mbed_official	532:fe11edbda85c	930	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
mbed_official	532:fe11edbda85c	931	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
mbed_official	532:fe11edbda85c	932	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
mbed_official	532:fe11edbda85c	933	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
mbed_official	532:fe11edbda85c	934	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
mbed_official	532:fe11edbda85c	935	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
mbed_official	532:fe11edbda85c	936	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
mbed_official	532:fe11edbda85c	937	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
mbed_official	532:fe11edbda85c	938	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
mbed_official	532:fe11edbda85c	939	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
mbed_official	532:fe11edbda85c	940	#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART7RST))
mbed_official	532:fe11edbda85c	941	#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART8RST))
mbed_official	235:685d5f11838f	942
mbed_official	532:fe11edbda85c	943	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
mbed_official	532:fe11edbda85c	944	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
mbed_official	532:fe11edbda85c	945	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
mbed_official	532:fe11edbda85c	946	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
mbed_official	532:fe11edbda85c	947	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
mbed_official	532:fe11edbda85c	948	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
mbed_official	532:fe11edbda85c	949	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
mbed_official	532:fe11edbda85c	950	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
mbed_official	532:fe11edbda85c	951	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
mbed_official	532:fe11edbda85c	952	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
mbed_official	532:fe11edbda85c	953	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
mbed_official	532:fe11edbda85c	954	#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
mbed_official	532:fe11edbda85c	955	#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
mbed_official	235:685d5f11838f	956
mbed_official	235:685d5f11838f	957	/** @brief Force or release APB2 peripheral reset.
mbed_official	235:685d5f11838f	958	*/
mbed_official	532:fe11edbda85c	959	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
mbed_official	532:fe11edbda85c	960	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
mbed_official	532:fe11edbda85c	961	#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI6RST))
mbed_official	532:fe11edbda85c	962	#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
mbed_official	235:685d5f11838f	963
mbed_official	532:fe11edbda85c	964	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
mbed_official	532:fe11edbda85c	965	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
mbed_official	532:fe11edbda85c	966	#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
mbed_official	532:fe11edbda85c	967	#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
mbed_official	235:685d5f11838f	968
mbed_official	235:685d5f11838f	969	#if defined(STM32F429xx)\|\| defined(STM32F439xx)
mbed_official	532:fe11edbda85c	970	#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_LTDCRST))
mbed_official	532:fe11edbda85c	971	#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
mbed_official	235:685d5f11838f	972	#endif /* STM32F429xx\|\| STM32F439xx */
mbed_official	235:685d5f11838f	973
mbed_official	235:685d5f11838f	974	/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
mbed_official	235:685d5f11838f	975	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	235:685d5f11838f	976	* power consumption.
mbed_official	235:685d5f11838f	977	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	235:685d5f11838f	978	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	235:685d5f11838f	979	*/
mbed_official	532:fe11edbda85c	980	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
mbed_official	532:fe11edbda85c	981	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
mbed_official	532:fe11edbda85c	982	#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOILPEN))
mbed_official	532:fe11edbda85c	983	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
mbed_official	532:fe11edbda85c	984	#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACLPEN))
mbed_official	532:fe11edbda85c	985	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACTXLPEN))
mbed_official	532:fe11edbda85c	986	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACRXLPEN))
mbed_official	532:fe11edbda85c	987	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACPTPLPEN))
mbed_official	532:fe11edbda85c	988	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
mbed_official	532:fe11edbda85c	989	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
mbed_official	532:fe11edbda85c	990	#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOJLPEN))
mbed_official	532:fe11edbda85c	991	#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOKLPEN))
mbed_official	532:fe11edbda85c	992	#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM3LPEN))
mbed_official	532:fe11edbda85c	993	#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2DLPEN))
mbed_official	235:685d5f11838f	994
mbed_official	532:fe11edbda85c	995	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
mbed_official	532:fe11edbda85c	996	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
mbed_official	532:fe11edbda85c	997	#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
mbed_official	532:fe11edbda85c	998	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
mbed_official	532:fe11edbda85c	999	#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
mbed_official	532:fe11edbda85c	1000	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
mbed_official	532:fe11edbda85c	1001	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
mbed_official	532:fe11edbda85c	1002	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
mbed_official	532:fe11edbda85c	1003	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
mbed_official	532:fe11edbda85c	1004	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
mbed_official	532:fe11edbda85c	1005	#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
mbed_official	532:fe11edbda85c	1006	#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
mbed_official	532:fe11edbda85c	1007	#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
mbed_official	235:685d5f11838f	1008
mbed_official	235:685d5f11838f	1009	/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
mbed_official	235:685d5f11838f	1010	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	235:685d5f11838f	1011	* power consumption.
mbed_official	235:685d5f11838f	1012	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	235:685d5f11838f	1013	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	235:685d5f11838f	1014	*/
mbed_official	532:fe11edbda85c	1015	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
mbed_official	532:fe11edbda85c	1016	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
mbed_official	235:685d5f11838f	1017
mbed_official	532:fe11edbda85c	1018	#if defined(STM32F437xx)\|\| defined(STM32F439xx)
mbed_official	532:fe11edbda85c	1019	#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_CRYPLPEN))
mbed_official	532:fe11edbda85c	1020	#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_HASHLPEN))
mbed_official	235:685d5f11838f	1021
mbed_official	532:fe11edbda85c	1022	#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
mbed_official	532:fe11edbda85c	1023	#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
mbed_official	235:685d5f11838f	1024	#endif /* STM32F437xx \|\| STM32F439xx */
mbed_official	235:685d5f11838f	1025
mbed_official	235:685d5f11838f	1026	/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
mbed_official	235:685d5f11838f	1027	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	235:685d5f11838f	1028	* power consumption.
mbed_official	235:685d5f11838f	1029	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	235:685d5f11838f	1030	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	235:685d5f11838f	1031	*/
mbed_official	532:fe11edbda85c	1032	#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FMCLPEN))
mbed_official	532:fe11edbda85c	1033	#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
mbed_official	235:685d5f11838f	1034
mbed_official	235:685d5f11838f	1035	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
mbed_official	235:685d5f11838f	1036	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	235:685d5f11838f	1037	* power consumption.
mbed_official	235:685d5f11838f	1038	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	235:685d5f11838f	1039	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	235:685d5f11838f	1040	*/
mbed_official	532:fe11edbda85c	1041	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
mbed_official	532:fe11edbda85c	1042	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
mbed_official	532:fe11edbda85c	1043	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
mbed_official	532:fe11edbda85c	1044	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
mbed_official	532:fe11edbda85c	1045	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
mbed_official	532:fe11edbda85c	1046	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
mbed_official	532:fe11edbda85c	1047	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
mbed_official	532:fe11edbda85c	1048	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
mbed_official	532:fe11edbda85c	1049	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
mbed_official	532:fe11edbda85c	1050	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
mbed_official	532:fe11edbda85c	1051	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
mbed_official	532:fe11edbda85c	1052	#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART7LPEN))
mbed_official	532:fe11edbda85c	1053	#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART8LPEN))
mbed_official	235:685d5f11838f	1054
mbed_official	532:fe11edbda85c	1055	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
mbed_official	532:fe11edbda85c	1056	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
mbed_official	532:fe11edbda85c	1057	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
mbed_official	532:fe11edbda85c	1058	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
mbed_official	532:fe11edbda85c	1059	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
mbed_official	532:fe11edbda85c	1060	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
mbed_official	532:fe11edbda85c	1061	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
mbed_official	532:fe11edbda85c	1062	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
mbed_official	532:fe11edbda85c	1063	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
mbed_official	532:fe11edbda85c	1064	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
mbed_official	532:fe11edbda85c	1065	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
mbed_official	532:fe11edbda85c	1066	#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
mbed_official	532:fe11edbda85c	1067	#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
mbed_official	235:685d5f11838f	1068
mbed_official	235:685d5f11838f	1069	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
mbed_official	235:685d5f11838f	1070	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	235:685d5f11838f	1071	* power consumption.
mbed_official	235:685d5f11838f	1072	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	235:685d5f11838f	1073	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	235:685d5f11838f	1074	*/
mbed_official	532:fe11edbda85c	1075	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
mbed_official	532:fe11edbda85c	1076	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
mbed_official	532:fe11edbda85c	1077	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
mbed_official	532:fe11edbda85c	1078	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
mbed_official	532:fe11edbda85c	1079	#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI6LPEN))
mbed_official	532:fe11edbda85c	1080	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
mbed_official	235:685d5f11838f	1081
mbed_official	532:fe11edbda85c	1082	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
mbed_official	532:fe11edbda85c	1083	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
mbed_official	532:fe11edbda85c	1084	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
mbed_official	532:fe11edbda85c	1085	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
mbed_official	532:fe11edbda85c	1086	#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
mbed_official	532:fe11edbda85c	1087	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
mbed_official	235:685d5f11838f	1088
mbed_official	235:685d5f11838f	1089	#if defined(STM32F429xx)\|\| defined(STM32F439xx)
mbed_official	532:fe11edbda85c	1090	#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_LTDCLPEN))
mbed_official	235:685d5f11838f	1091
mbed_official	532:fe11edbda85c	1092	#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
mbed_official	235:685d5f11838f	1093	#endif /* STM32F429xx \|\| STM32F439xx */
mbed_official	532:fe11edbda85c	1094
mbed_official	235:685d5f11838f	1095	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx\|\| STM32F439xx */
mbed_official	235:685d5f11838f	1096	/---------------------------------------------------------------------------------------------/
mbed_official	235:685d5f11838f	1097
mbed_official	235:685d5f11838f	1098	/----------------------------------- STM32F40xxx/STM32F41xxx----------------------------------/
mbed_official	235:685d5f11838f	1099	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx)
mbed_official	235:685d5f11838f	1100	/** @brief Enables or disables the AHB1 peripheral clock.
mbed_official	235:685d5f11838f	1101	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	235:685d5f11838f	1102	* is disabled and the application software has to enable this clock before
mbed_official	235:685d5f11838f	1103	* using it.
mbed_official	235:685d5f11838f	1104	*/
mbed_official	532:fe11edbda85c	1105	#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1106	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1107	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
mbed_official	532:fe11edbda85c	1108	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1109	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
mbed_official	532:fe11edbda85c	1110	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1111	} while(0)
mbed_official	532:fe11edbda85c	1112	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1113	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1114	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
mbed_official	532:fe11edbda85c	1115	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1116	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
mbed_official	532:fe11edbda85c	1117	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1118	} while(0)
mbed_official	532:fe11edbda85c	1119	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1120	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1121	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
mbed_official	532:fe11edbda85c	1122	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1123	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
mbed_official	532:fe11edbda85c	1124	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1125	} while(0)
mbed_official	532:fe11edbda85c	1126	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1127	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1128	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
mbed_official	532:fe11edbda85c	1129	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1130	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
mbed_official	532:fe11edbda85c	1131	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1132	} while(0)
mbed_official	532:fe11edbda85c	1133	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1134	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1135	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
mbed_official	532:fe11edbda85c	1136	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1137	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
mbed_official	532:fe11edbda85c	1138	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1139	} while(0)
mbed_official	235:685d5f11838f	1140
mbed_official	532:fe11edbda85c	1141	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
mbed_official	532:fe11edbda85c	1142	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
mbed_official	532:fe11edbda85c	1143	#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
mbed_official	532:fe11edbda85c	1144	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
mbed_official	532:fe11edbda85c	1145	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
mbed_official	235:685d5f11838f	1146
mbed_official	235:685d5f11838f	1147	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
mbed_official	235:685d5f11838f	1148	/**
mbed_official	235:685d5f11838f	1149	* @brief Enable ETHERNET clock.
mbed_official	235:685d5f11838f	1150	*/
mbed_official	532:fe11edbda85c	1151	#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1152	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1153	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
mbed_official	532:fe11edbda85c	1154	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1155	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
mbed_official	532:fe11edbda85c	1156	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1157	} while(0)
mbed_official	532:fe11edbda85c	1158	#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1159	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1160	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
mbed_official	532:fe11edbda85c	1161	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1162	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
mbed_official	532:fe11edbda85c	1163	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1164	} while(0)
mbed_official	532:fe11edbda85c	1165	#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1166	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1167	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
mbed_official	532:fe11edbda85c	1168	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1169	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
mbed_official	532:fe11edbda85c	1170	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1171	} while(0)
mbed_official	532:fe11edbda85c	1172	#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1173	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1174	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
mbed_official	532:fe11edbda85c	1175	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1176	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
mbed_official	532:fe11edbda85c	1177	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1178	} while(0)
mbed_official	532:fe11edbda85c	1179	#define __HAL_RCC_ETH_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1180	__HAL_RCC_ETHMAC_CLK_ENABLE(); \
mbed_official	532:fe11edbda85c	1181	__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
mbed_official	532:fe11edbda85c	1182	__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
mbed_official	532:fe11edbda85c	1183	} while(0)
mbed_official	235:685d5f11838f	1184
mbed_official	235:685d5f11838f	1185	/**
mbed_official	235:685d5f11838f	1186	* @brief Disable ETHERNET clock.
mbed_official	235:685d5f11838f	1187	*/
mbed_official	532:fe11edbda85c	1188	#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
mbed_official	532:fe11edbda85c	1189	#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
mbed_official	532:fe11edbda85c	1190	#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
mbed_official	532:fe11edbda85c	1191	#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
mbed_official	532:fe11edbda85c	1192	#define __HAL_RCC_ETH_CLK_DISABLE() do { \
mbed_official	532:fe11edbda85c	1193	__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
mbed_official	532:fe11edbda85c	1194	__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
mbed_official	532:fe11edbda85c	1195	__HAL_RCC_ETHMAC_CLK_DISABLE(); \
mbed_official	235:685d5f11838f	1196	} while(0)
mbed_official	235:685d5f11838f	1197	#endif /* STM32F407xx \|\| STM32F417xx */
mbed_official	235:685d5f11838f	1198
mbed_official	235:685d5f11838f	1199	/** @brief Enable or disable the AHB2 peripheral clock.
mbed_official	235:685d5f11838f	1200	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	235:685d5f11838f	1201	* is disabled and the application software has to enable this clock before
mbed_official	235:685d5f11838f	1202	* using it.
mbed_official	235:685d5f11838f	1203	*/
mbed_official	235:685d5f11838f	1204	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
mbed_official	532:fe11edbda85c	1205	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1206	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1207	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
mbed_official	532:fe11edbda85c	1208	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1209	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
mbed_official	532:fe11edbda85c	1210	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1211	} while(0)
mbed_official	532:fe11edbda85c	1212	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
mbed_official	235:685d5f11838f	1213	#endif /* STM32F407xx \|\| STM32F417xx */
mbed_official	235:685d5f11838f	1214
mbed_official	235:685d5f11838f	1215	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
mbed_official	532:fe11edbda85c	1216	#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1217	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1218	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
mbed_official	532:fe11edbda85c	1219	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1220	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
mbed_official	532:fe11edbda85c	1221	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1222	} while(0)
mbed_official	532:fe11edbda85c	1223	#define __HAL_RCC_HASH_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1224	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1225	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
mbed_official	532:fe11edbda85c	1226	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1227	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
mbed_official	532:fe11edbda85c	1228	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1229	} while(0)
mbed_official	532:fe11edbda85c	1230	#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
mbed_official	532:fe11edbda85c	1231	#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
mbed_official	235:685d5f11838f	1232	#endif /* STM32F415xx \|\| STM32F417xx */
mbed_official	235:685d5f11838f	1233
mbed_official	235:685d5f11838f	1234	/** @brief Enables or disables the AHB3 peripheral clock.
mbed_official	235:685d5f11838f	1235	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	235:685d5f11838f	1236	* is disabled and the application software has to enable this clock before
mbed_official	235:685d5f11838f	1237	* using it.
mbed_official	235:685d5f11838f	1238	*/
mbed_official	532:fe11edbda85c	1239	#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1240	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1241	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
mbed_official	532:fe11edbda85c	1242	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1243	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
mbed_official	532:fe11edbda85c	1244	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1245	} while(0)
mbed_official	532:fe11edbda85c	1246	#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
mbed_official	235:685d5f11838f	1247
mbed_official	235:685d5f11838f	1248	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
mbed_official	235:685d5f11838f	1249	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	235:685d5f11838f	1250	* is disabled and the application software has to enable this clock before
mbed_official	235:685d5f11838f	1251	* using it.
mbed_official	235:685d5f11838f	1252	*/
mbed_official	532:fe11edbda85c	1253	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1254	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1255	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
mbed_official	532:fe11edbda85c	1256	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1257	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
mbed_official	532:fe11edbda85c	1258	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1259	} while(0)
mbed_official	532:fe11edbda85c	1260	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1261	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1262	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
mbed_official	532:fe11edbda85c	1263	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1264	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
mbed_official	532:fe11edbda85c	1265	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1266	} while(0)
mbed_official	532:fe11edbda85c	1267	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1268	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1269	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
mbed_official	532:fe11edbda85c	1270	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1271	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
mbed_official	532:fe11edbda85c	1272	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1273	} while(0)
mbed_official	532:fe11edbda85c	1274	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1275	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1276	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
mbed_official	532:fe11edbda85c	1277	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1278	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
mbed_official	532:fe11edbda85c	1279	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1280	} while(0)
mbed_official	532:fe11edbda85c	1281	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1282	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1283	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
mbed_official	532:fe11edbda85c	1284	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1285	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
mbed_official	532:fe11edbda85c	1286	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1287	} while(0)
mbed_official	532:fe11edbda85c	1288	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1289	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1290	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
mbed_official	532:fe11edbda85c	1291	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1292	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
mbed_official	532:fe11edbda85c	1293	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1294	} while(0)
mbed_official	532:fe11edbda85c	1295	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1296	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1297	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
mbed_official	532:fe11edbda85c	1298	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1299	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
mbed_official	532:fe11edbda85c	1300	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1301	} while(0)
mbed_official	532:fe11edbda85c	1302	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1303	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1304	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
mbed_official	532:fe11edbda85c	1305	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1306	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
mbed_official	532:fe11edbda85c	1307	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1308	} while(0)
mbed_official	532:fe11edbda85c	1309	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1310	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1311	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
mbed_official	532:fe11edbda85c	1312	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1313	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
mbed_official	532:fe11edbda85c	1314	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1315	} while(0)
mbed_official	532:fe11edbda85c	1316	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1317	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1318	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
mbed_official	532:fe11edbda85c	1319	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1320	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
mbed_official	532:fe11edbda85c	1321	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1322	} while(0)
mbed_official	532:fe11edbda85c	1323	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1324	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1325	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
mbed_official	532:fe11edbda85c	1326	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1327	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
mbed_official	532:fe11edbda85c	1328	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1329	} while(0)
mbed_official	532:fe11edbda85c	1330
mbed_official	532:fe11edbda85c	1331	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
mbed_official	532:fe11edbda85c	1332	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
mbed_official	532:fe11edbda85c	1333	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
mbed_official	532:fe11edbda85c	1334	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
mbed_official	532:fe11edbda85c	1335	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
mbed_official	532:fe11edbda85c	1336	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
mbed_official	532:fe11edbda85c	1337	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
mbed_official	532:fe11edbda85c	1338	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
mbed_official	532:fe11edbda85c	1339	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
mbed_official	532:fe11edbda85c	1340	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
mbed_official	532:fe11edbda85c	1341	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
mbed_official	235:685d5f11838f	1342
mbed_official	235:685d5f11838f	1343	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
mbed_official	235:685d5f11838f	1344	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	235:685d5f11838f	1345	* is disabled and the application software has to enable this clock before
mbed_official	235:685d5f11838f	1346	* using it.
mbed_official	235:685d5f11838f	1347	*/
mbed_official	532:fe11edbda85c	1348	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1349	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1350	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
mbed_official	532:fe11edbda85c	1351	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1352	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
mbed_official	532:fe11edbda85c	1353	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1354	} while(0)
mbed_official	532:fe11edbda85c	1355	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1356	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1357	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
mbed_official	532:fe11edbda85c	1358	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1359	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
mbed_official	532:fe11edbda85c	1360	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1361	} while(0)
mbed_official	532:fe11edbda85c	1362	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1363	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1364	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
mbed_official	532:fe11edbda85c	1365	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1366	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
mbed_official	532:fe11edbda85c	1367	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1368	} while(0)
mbed_official	235:685d5f11838f	1369
mbed_official	532:fe11edbda85c	1370	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
mbed_official	532:fe11edbda85c	1371	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
mbed_official	532:fe11edbda85c	1372	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
mbed_official	235:685d5f11838f	1373
mbed_official	235:685d5f11838f	1374	/** @brief Force or release AHB1 peripheral reset.
mbed_official	235:685d5f11838f	1375	*/
mbed_official	532:fe11edbda85c	1376	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
mbed_official	532:fe11edbda85c	1377	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
mbed_official	532:fe11edbda85c	1378	#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOIRST))
mbed_official	532:fe11edbda85c	1379	#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_ETHMACRST))
mbed_official	532:fe11edbda85c	1380	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
mbed_official	235:685d5f11838f	1381
mbed_official	532:fe11edbda85c	1382	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
mbed_official	532:fe11edbda85c	1383	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
mbed_official	532:fe11edbda85c	1384	#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
mbed_official	532:fe11edbda85c	1385	#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
mbed_official	532:fe11edbda85c	1386	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
mbed_official	235:685d5f11838f	1387
mbed_official	235:685d5f11838f	1388	/** @brief Force or release AHB2 peripheral reset.
mbed_official	235:685d5f11838f	1389	*/
mbed_official	235:685d5f11838f	1390	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
mbed_official	532:fe11edbda85c	1391	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
mbed_official	532:fe11edbda85c	1392	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
mbed_official	235:685d5f11838f	1393	#endif /* STM32F407xx \|\| STM32F417xx */
mbed_official	235:685d5f11838f	1394
mbed_official	235:685d5f11838f	1395	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
mbed_official	532:fe11edbda85c	1396	#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_CRYPRST))
mbed_official	532:fe11edbda85c	1397	#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_HASHRST))
mbed_official	235:685d5f11838f	1398
mbed_official	532:fe11edbda85c	1399	#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
mbed_official	532:fe11edbda85c	1400	#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
mbed_official	235:685d5f11838f	1401
mbed_official	235:685d5f11838f	1402	#endif /* STM32F415xx \|\| STM32F417xx */
mbed_official	235:685d5f11838f	1403
mbed_official	235:685d5f11838f	1404	/** @brief Force or release AHB3 peripheral reset
mbed_official	235:685d5f11838f	1405	*/
mbed_official	532:fe11edbda85c	1406	#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FSMCRST))
mbed_official	532:fe11edbda85c	1407	#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
mbed_official	235:685d5f11838f	1408
mbed_official	235:685d5f11838f	1409	/** @brief Force or release APB1 peripheral reset.
mbed_official	235:685d5f11838f	1410	*/
mbed_official	532:fe11edbda85c	1411	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
mbed_official	532:fe11edbda85c	1412	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
mbed_official	532:fe11edbda85c	1413	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
mbed_official	532:fe11edbda85c	1414	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
mbed_official	532:fe11edbda85c	1415	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
mbed_official	532:fe11edbda85c	1416	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
mbed_official	532:fe11edbda85c	1417	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
mbed_official	532:fe11edbda85c	1418	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
mbed_official	532:fe11edbda85c	1419	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
mbed_official	532:fe11edbda85c	1420	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
mbed_official	532:fe11edbda85c	1421	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
mbed_official	235:685d5f11838f	1422
mbed_official	532:fe11edbda85c	1423	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
mbed_official	532:fe11edbda85c	1424	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
mbed_official	532:fe11edbda85c	1425	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
mbed_official	532:fe11edbda85c	1426	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
mbed_official	532:fe11edbda85c	1427	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
mbed_official	532:fe11edbda85c	1428	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
mbed_official	532:fe11edbda85c	1429	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
mbed_official	532:fe11edbda85c	1430	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
mbed_official	532:fe11edbda85c	1431	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
mbed_official	532:fe11edbda85c	1432	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
mbed_official	532:fe11edbda85c	1433	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
mbed_official	235:685d5f11838f	1434
mbed_official	235:685d5f11838f	1435	/** @brief Force or release APB2 peripheral reset.
mbed_official	235:685d5f11838f	1436	*/
mbed_official	532:fe11edbda85c	1437	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
mbed_official	532:fe11edbda85c	1438	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
mbed_official	235:685d5f11838f	1439
mbed_official	235:685d5f11838f	1440	/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
mbed_official	235:685d5f11838f	1441	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	235:685d5f11838f	1442	* power consumption.
mbed_official	235:685d5f11838f	1443	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	235:685d5f11838f	1444	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	235:685d5f11838f	1445	*/
mbed_official	532:fe11edbda85c	1446	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
mbed_official	532:fe11edbda85c	1447	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
mbed_official	532:fe11edbda85c	1448	#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOILPEN))
mbed_official	532:fe11edbda85c	1449	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
mbed_official	532:fe11edbda85c	1450	#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACLPEN))
mbed_official	532:fe11edbda85c	1451	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACTXLPEN))
mbed_official	532:fe11edbda85c	1452	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACRXLPEN))
mbed_official	532:fe11edbda85c	1453	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACPTPLPEN))
mbed_official	532:fe11edbda85c	1454	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
mbed_official	532:fe11edbda85c	1455	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
mbed_official	235:685d5f11838f	1456
mbed_official	532:fe11edbda85c	1457	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
mbed_official	532:fe11edbda85c	1458	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
mbed_official	532:fe11edbda85c	1459	#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
mbed_official	532:fe11edbda85c	1460	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
mbed_official	532:fe11edbda85c	1461	#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
mbed_official	532:fe11edbda85c	1462	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
mbed_official	532:fe11edbda85c	1463	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
mbed_official	532:fe11edbda85c	1464	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
mbed_official	532:fe11edbda85c	1465	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
mbed_official	532:fe11edbda85c	1466	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
mbed_official	235:685d5f11838f	1467
mbed_official	235:685d5f11838f	1468	/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
mbed_official	235:685d5f11838f	1469	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	235:685d5f11838f	1470	* power consumption.
mbed_official	235:685d5f11838f	1471	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	235:685d5f11838f	1472	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	235:685d5f11838f	1473	*/
mbed_official	235:685d5f11838f	1474	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
mbed_official	532:fe11edbda85c	1475	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
mbed_official	532:fe11edbda85c	1476	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
mbed_official	235:685d5f11838f	1477	#endif /* STM32F407xx \|\| STM32F417xx */
mbed_official	235:685d5f11838f	1478
mbed_official	235:685d5f11838f	1479	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
mbed_official	532:fe11edbda85c	1480	#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_CRYPLPEN))
mbed_official	532:fe11edbda85c	1481	#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_HASHLPEN))
mbed_official	235:685d5f11838f	1482
mbed_official	532:fe11edbda85c	1483	#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
mbed_official	532:fe11edbda85c	1484	#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
mbed_official	235:685d5f11838f	1485	#endif /* STM32F415xx \|\| STM32F417xx */
mbed_official	235:685d5f11838f	1486
mbed_official	235:685d5f11838f	1487	/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
mbed_official	235:685d5f11838f	1488	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	235:685d5f11838f	1489	* power consumption.
mbed_official	235:685d5f11838f	1490	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	235:685d5f11838f	1491	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	235:685d5f11838f	1492	*/
mbed_official	532:fe11edbda85c	1493	#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FSMCLPEN))
mbed_official	532:fe11edbda85c	1494	#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
mbed_official	235:685d5f11838f	1495
mbed_official	235:685d5f11838f	1496	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
mbed_official	235:685d5f11838f	1497	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	235:685d5f11838f	1498	* power consumption.
mbed_official	235:685d5f11838f	1499	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	235:685d5f11838f	1500	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	235:685d5f11838f	1501	*/
mbed_official	532:fe11edbda85c	1502	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
mbed_official	532:fe11edbda85c	1503	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
mbed_official	532:fe11edbda85c	1504	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
mbed_official	532:fe11edbda85c	1505	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
mbed_official	532:fe11edbda85c	1506	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
mbed_official	532:fe11edbda85c	1507	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
mbed_official	532:fe11edbda85c	1508	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
mbed_official	532:fe11edbda85c	1509	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
mbed_official	532:fe11edbda85c	1510	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
mbed_official	532:fe11edbda85c	1511	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
mbed_official	532:fe11edbda85c	1512	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
mbed_official	532:fe11edbda85c	1513
mbed_official	532:fe11edbda85c	1514	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
mbed_official	532:fe11edbda85c	1515	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
mbed_official	532:fe11edbda85c	1516	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
mbed_official	532:fe11edbda85c	1517	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
mbed_official	532:fe11edbda85c	1518	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
mbed_official	532:fe11edbda85c	1519	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
mbed_official	532:fe11edbda85c	1520	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
mbed_official	532:fe11edbda85c	1521	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
mbed_official	532:fe11edbda85c	1522	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
mbed_official	532:fe11edbda85c	1523	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
mbed_official	532:fe11edbda85c	1524	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
mbed_official	532:fe11edbda85c	1525
mbed_official	532:fe11edbda85c	1526	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
mbed_official	532:fe11edbda85c	1527	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	532:fe11edbda85c	1528	* power consumption.
mbed_official	532:fe11edbda85c	1529	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	532:fe11edbda85c	1530	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	532:fe11edbda85c	1531	*/
mbed_official	532:fe11edbda85c	1532	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
mbed_official	532:fe11edbda85c	1533	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
mbed_official	532:fe11edbda85c	1534	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
mbed_official	532:fe11edbda85c	1535
mbed_official	532:fe11edbda85c	1536	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
mbed_official	532:fe11edbda85c	1537	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
mbed_official	532:fe11edbda85c	1538	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
mbed_official	532:fe11edbda85c	1539	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
mbed_official	532:fe11edbda85c	1540	/---------------------------------------------------------------------------------------------/
mbed_official	532:fe11edbda85c	1541
mbed_official	532:fe11edbda85c	1542	/------------------------------------------ STM32F411xx --------------------------------------/
mbed_official	532:fe11edbda85c	1543	#if defined(STM32F411xE)
mbed_official	532:fe11edbda85c	1544	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
mbed_official	532:fe11edbda85c	1545	*/
mbed_official	532:fe11edbda85c	1546	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1547	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1548	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
mbed_official	532:fe11edbda85c	1549	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1550	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
mbed_official	532:fe11edbda85c	1551	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1552	} while(0)
mbed_official	532:fe11edbda85c	1553	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
mbed_official	532:fe11edbda85c	1554
mbed_official	532:fe11edbda85c	1555	/** @brief Force or release APB2 peripheral reset.
mbed_official	532:fe11edbda85c	1556	*/
mbed_official	532:fe11edbda85c	1557	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
mbed_official	532:fe11edbda85c	1558	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
mbed_official	532:fe11edbda85c	1559
mbed_official	532:fe11edbda85c	1560	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
mbed_official	532:fe11edbda85c	1561	*/
mbed_official	532:fe11edbda85c	1562	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
mbed_official	532:fe11edbda85c	1563	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
mbed_official	532:fe11edbda85c	1564
mbed_official	532:fe11edbda85c	1565	#endif /* STM32F411xE */
mbed_official	532:fe11edbda85c	1566	/---------------------------------------------------------------------------------------------/
mbed_official	532:fe11edbda85c	1567
mbed_official	532:fe11edbda85c	1568	/----------------------------------------- STM32F446xx ---------------------------------------/
mbed_official	532:fe11edbda85c	1569	#if defined(STM32F446xx)
mbed_official	532:fe11edbda85c	1570	/** @brief Enables or disables the AHB1 peripheral clock.
mbed_official	532:fe11edbda85c	1571	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	532:fe11edbda85c	1572	* is disabled and the application software has to enable this clock before
mbed_official	532:fe11edbda85c	1573	* using it.
mbed_official	532:fe11edbda85c	1574	*/
mbed_official	532:fe11edbda85c	1575	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1576	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1577	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
mbed_official	532:fe11edbda85c	1578	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1579	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
mbed_official	532:fe11edbda85c	1580	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1581	} while(0)
mbed_official	532:fe11edbda85c	1582	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1583	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1584	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
mbed_official	532:fe11edbda85c	1585	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1586	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
mbed_official	532:fe11edbda85c	1587	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1588	} while(0)
mbed_official	532:fe11edbda85c	1589	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1590	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1591	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
mbed_official	532:fe11edbda85c	1592	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1593	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
mbed_official	532:fe11edbda85c	1594	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1595	} while(0)
mbed_official	532:fe11edbda85c	1596	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1597	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1598	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
mbed_official	532:fe11edbda85c	1599	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1600	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
mbed_official	532:fe11edbda85c	1601	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1602	} while(0)
mbed_official	532:fe11edbda85c	1603
mbed_official	532:fe11edbda85c	1604	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
mbed_official	532:fe11edbda85c	1605	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
mbed_official	532:fe11edbda85c	1606	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
mbed_official	532:fe11edbda85c	1607	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
mbed_official	532:fe11edbda85c	1608
mbed_official	532:fe11edbda85c	1609	/** @brief Enable or disable the AHB2 peripheral clock.
mbed_official	532:fe11edbda85c	1610	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	532:fe11edbda85c	1611	* is disabled and the application software has to enable this clock before
mbed_official	532:fe11edbda85c	1612	* using it.
mbed_official	532:fe11edbda85c	1613	*/
mbed_official	532:fe11edbda85c	1614	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1615	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1616	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
mbed_official	532:fe11edbda85c	1617	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1618	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
mbed_official	532:fe11edbda85c	1619	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1620	} while(0)
mbed_official	532:fe11edbda85c	1621	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
mbed_official	532:fe11edbda85c	1622
mbed_official	532:fe11edbda85c	1623	/** @brief Enables or disables the AHB3 peripheral clock.
mbed_official	532:fe11edbda85c	1624	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	532:fe11edbda85c	1625	* is disabled and the application software has to enable this clock before
mbed_official	532:fe11edbda85c	1626	* using it.
mbed_official	532:fe11edbda85c	1627	*/
mbed_official	532:fe11edbda85c	1628	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1629	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1630	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
mbed_official	532:fe11edbda85c	1631	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1632	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
mbed_official	532:fe11edbda85c	1633	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1634	} while(0)
mbed_official	532:fe11edbda85c	1635	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1636	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1637	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
mbed_official	532:fe11edbda85c	1638	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1639	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
mbed_official	532:fe11edbda85c	1640	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1641	} while(0)
mbed_official	532:fe11edbda85c	1642
mbed_official	532:fe11edbda85c	1643	#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
mbed_official	532:fe11edbda85c	1644	#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
mbed_official	235:685d5f11838f	1645
mbed_official	532:fe11edbda85c	1646	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
mbed_official	532:fe11edbda85c	1647	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	532:fe11edbda85c	1648	* is disabled and the application software has to enable this clock before
mbed_official	532:fe11edbda85c	1649	* using it.
mbed_official	532:fe11edbda85c	1650	*/
mbed_official	532:fe11edbda85c	1651	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1652	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1653	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
mbed_official	532:fe11edbda85c	1654	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1655	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
mbed_official	532:fe11edbda85c	1656	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1657	} while(0)
mbed_official	532:fe11edbda85c	1658	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1659	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1660	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
mbed_official	532:fe11edbda85c	1661	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1662	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
mbed_official	532:fe11edbda85c	1663	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1664	} while(0)
mbed_official	532:fe11edbda85c	1665	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1666	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1667	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
mbed_official	532:fe11edbda85c	1668	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1669	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
mbed_official	532:fe11edbda85c	1670	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1671	} while(0)
mbed_official	532:fe11edbda85c	1672	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1673	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1674	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
mbed_official	532:fe11edbda85c	1675	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1676	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
mbed_official	532:fe11edbda85c	1677	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1678	} while(0)
mbed_official	532:fe11edbda85c	1679	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1680	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1681	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
mbed_official	532:fe11edbda85c	1682	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1683	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
mbed_official	532:fe11edbda85c	1684	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1685	} while(0)
mbed_official	532:fe11edbda85c	1686	#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1687	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1688	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
mbed_official	532:fe11edbda85c	1689	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1690	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
mbed_official	532:fe11edbda85c	1691	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1692	} while(0)
mbed_official	532:fe11edbda85c	1693	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1694	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1695	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
mbed_official	532:fe11edbda85c	1696	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1697	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
mbed_official	532:fe11edbda85c	1698	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1699	} while(0)
mbed_official	532:fe11edbda85c	1700	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1701	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1702	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
mbed_official	532:fe11edbda85c	1703	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1704	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
mbed_official	532:fe11edbda85c	1705	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1706	} while(0)
mbed_official	532:fe11edbda85c	1707	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1708	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1709	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
mbed_official	532:fe11edbda85c	1710	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1711	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
mbed_official	532:fe11edbda85c	1712	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1713	} while(0)
mbed_official	532:fe11edbda85c	1714	#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1715	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1716	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
mbed_official	532:fe11edbda85c	1717	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1718	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
mbed_official	532:fe11edbda85c	1719	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1720	} while(0)
mbed_official	532:fe11edbda85c	1721	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1722	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1723	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
mbed_official	532:fe11edbda85c	1724	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1725	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
mbed_official	532:fe11edbda85c	1726	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1727	} while(0)
mbed_official	532:fe11edbda85c	1728	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1729	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1730	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
mbed_official	532:fe11edbda85c	1731	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1732	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
mbed_official	532:fe11edbda85c	1733	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1734	} while(0)
mbed_official	532:fe11edbda85c	1735	#define __HAL_RCC_CEC_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1736	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1737	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
mbed_official	532:fe11edbda85c	1738	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1739	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
mbed_official	532:fe11edbda85c	1740	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1741	} while(0)
mbed_official	532:fe11edbda85c	1742	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1743	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1744	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
mbed_official	532:fe11edbda85c	1745	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1746	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
mbed_official	532:fe11edbda85c	1747	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1748	} while(0)
mbed_official	532:fe11edbda85c	1749
mbed_official	532:fe11edbda85c	1750	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
mbed_official	532:fe11edbda85c	1751	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
mbed_official	532:fe11edbda85c	1752	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
mbed_official	532:fe11edbda85c	1753	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
mbed_official	532:fe11edbda85c	1754	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
mbed_official	532:fe11edbda85c	1755	#define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
mbed_official	532:fe11edbda85c	1756	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
mbed_official	532:fe11edbda85c	1757	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
mbed_official	532:fe11edbda85c	1758	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
mbed_official	532:fe11edbda85c	1759	#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
mbed_official	532:fe11edbda85c	1760	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
mbed_official	532:fe11edbda85c	1761	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
mbed_official	532:fe11edbda85c	1762	#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
mbed_official	532:fe11edbda85c	1763	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
mbed_official	532:fe11edbda85c	1764
mbed_official	532:fe11edbda85c	1765	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
mbed_official	532:fe11edbda85c	1766	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	532:fe11edbda85c	1767	* is disabled and the application software has to enable this clock before
mbed_official	532:fe11edbda85c	1768	* using it.
mbed_official	532:fe11edbda85c	1769	*/
mbed_official	532:fe11edbda85c	1770	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1771	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1772	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
mbed_official	532:fe11edbda85c	1773	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1774	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
mbed_official	532:fe11edbda85c	1775	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1776	} while(0)
mbed_official	532:fe11edbda85c	1777	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1778	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1779	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
mbed_official	532:fe11edbda85c	1780	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1781	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
mbed_official	532:fe11edbda85c	1782	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1783	} while(0)
mbed_official	532:fe11edbda85c	1784	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1785	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1786	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
mbed_official	532:fe11edbda85c	1787	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1788	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
mbed_official	532:fe11edbda85c	1789	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1790	} while(0)
mbed_official	532:fe11edbda85c	1791	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1792	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1793	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
mbed_official	532:fe11edbda85c	1794	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1795	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
mbed_official	532:fe11edbda85c	1796	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1797	} while(0)
mbed_official	532:fe11edbda85c	1798	#define __HAL_RCC_SAI2_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	1799	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	1800	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
mbed_official	532:fe11edbda85c	1801	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	1802	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
mbed_official	532:fe11edbda85c	1803	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	1804	} while(0)
mbed_official	532:fe11edbda85c	1805
mbed_official	532:fe11edbda85c	1806	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
mbed_official	532:fe11edbda85c	1807	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
mbed_official	532:fe11edbda85c	1808	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
mbed_official	532:fe11edbda85c	1809	#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
mbed_official	532:fe11edbda85c	1810	#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
mbed_official	532:fe11edbda85c	1811
mbed_official	532:fe11edbda85c	1812	/** @brief Force or release AHB1 peripheral reset.
mbed_official	532:fe11edbda85c	1813	*/
mbed_official	532:fe11edbda85c	1814	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
mbed_official	532:fe11edbda85c	1815	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
mbed_official	532:fe11edbda85c	1816	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
mbed_official	532:fe11edbda85c	1817
mbed_official	532:fe11edbda85c	1818	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
mbed_official	532:fe11edbda85c	1819	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
mbed_official	532:fe11edbda85c	1820	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
mbed_official	532:fe11edbda85c	1821
mbed_official	532:fe11edbda85c	1822	/** @brief Force or release AHB2 peripheral reset.
mbed_official	532:fe11edbda85c	1823	*/
mbed_official	532:fe11edbda85c	1824	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
mbed_official	532:fe11edbda85c	1825	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
mbed_official	532:fe11edbda85c	1826
mbed_official	532:fe11edbda85c	1827	/** @brief Force or release AHB3 peripheral reset
mbed_official	532:fe11edbda85c	1828	*/
mbed_official	532:fe11edbda85c	1829	#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FMCRST))
mbed_official	532:fe11edbda85c	1830	#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_QSPIRST))
mbed_official	532:fe11edbda85c	1831
mbed_official	532:fe11edbda85c	1832	#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
mbed_official	532:fe11edbda85c	1833	#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
mbed_official	532:fe11edbda85c	1834
mbed_official	532:fe11edbda85c	1835	/** @brief Force or release APB1 peripheral reset.
mbed_official	532:fe11edbda85c	1836	*/
mbed_official	532:fe11edbda85c	1837	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
mbed_official	532:fe11edbda85c	1838	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
mbed_official	532:fe11edbda85c	1839	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
mbed_official	532:fe11edbda85c	1840	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
mbed_official	532:fe11edbda85c	1841	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
mbed_official	532:fe11edbda85c	1842	#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPDIFRXRST))
mbed_official	532:fe11edbda85c	1843	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
mbed_official	532:fe11edbda85c	1844	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
mbed_official	532:fe11edbda85c	1845	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
mbed_official	532:fe11edbda85c	1846	#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_FMPI2C1RST))
mbed_official	532:fe11edbda85c	1847	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
mbed_official	532:fe11edbda85c	1848	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
mbed_official	532:fe11edbda85c	1849	#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
mbed_official	532:fe11edbda85c	1850	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
mbed_official	532:fe11edbda85c	1851
mbed_official	532:fe11edbda85c	1852	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
mbed_official	532:fe11edbda85c	1853	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
mbed_official	532:fe11edbda85c	1854	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
mbed_official	532:fe11edbda85c	1855	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
mbed_official	532:fe11edbda85c	1856	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
mbed_official	532:fe11edbda85c	1857	#define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
mbed_official	532:fe11edbda85c	1858	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
mbed_official	532:fe11edbda85c	1859	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
mbed_official	532:fe11edbda85c	1860	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
mbed_official	532:fe11edbda85c	1861	#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
mbed_official	532:fe11edbda85c	1862	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
mbed_official	532:fe11edbda85c	1863	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
mbed_official	532:fe11edbda85c	1864	#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
mbed_official	532:fe11edbda85c	1865	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
mbed_official	532:fe11edbda85c	1866
mbed_official	532:fe11edbda85c	1867	/** @brief Force or release APB2 peripheral reset.
mbed_official	532:fe11edbda85c	1868	*/
mbed_official	532:fe11edbda85c	1869	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
mbed_official	532:fe11edbda85c	1870	#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
mbed_official	532:fe11edbda85c	1871	#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI2RST))
mbed_official	532:fe11edbda85c	1872
mbed_official	532:fe11edbda85c	1873	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
mbed_official	532:fe11edbda85c	1874	#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
mbed_official	532:fe11edbda85c	1875	#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
mbed_official	532:fe11edbda85c	1876
mbed_official	532:fe11edbda85c	1877	/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
mbed_official	532:fe11edbda85c	1878	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	532:fe11edbda85c	1879	* power consumption.
mbed_official	532:fe11edbda85c	1880	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	532:fe11edbda85c	1881	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	532:fe11edbda85c	1882	*/
mbed_official	532:fe11edbda85c	1883	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
mbed_official	532:fe11edbda85c	1884	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
mbed_official	532:fe11edbda85c	1885	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
mbed_official	532:fe11edbda85c	1886	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
mbed_official	532:fe11edbda85c	1887	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
mbed_official	532:fe11edbda85c	1888
mbed_official	532:fe11edbda85c	1889	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
mbed_official	532:fe11edbda85c	1890	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
mbed_official	532:fe11edbda85c	1891	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
mbed_official	532:fe11edbda85c	1892	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
mbed_official	532:fe11edbda85c	1893	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
mbed_official	532:fe11edbda85c	1894	/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
mbed_official	532:fe11edbda85c	1895	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	532:fe11edbda85c	1896	* power consumption.
mbed_official	532:fe11edbda85c	1897	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	532:fe11edbda85c	1898	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	532:fe11edbda85c	1899	*/
mbed_official	532:fe11edbda85c	1900	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
mbed_official	532:fe11edbda85c	1901	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
mbed_official	532:fe11edbda85c	1902
mbed_official	532:fe11edbda85c	1903	/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
mbed_official	532:fe11edbda85c	1904	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	532:fe11edbda85c	1905	* power consumption.
mbed_official	532:fe11edbda85c	1906	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	532:fe11edbda85c	1907	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	532:fe11edbda85c	1908	*/
mbed_official	532:fe11edbda85c	1909	#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FMCLPEN))
mbed_official	532:fe11edbda85c	1910	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_QSPILPEN))
mbed_official	532:fe11edbda85c	1911
mbed_official	532:fe11edbda85c	1912	#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
mbed_official	532:fe11edbda85c	1913	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
mbed_official	532:fe11edbda85c	1914
mbed_official	532:fe11edbda85c	1915	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
mbed_official	532:fe11edbda85c	1916	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	532:fe11edbda85c	1917	* power consumption.
mbed_official	532:fe11edbda85c	1918	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	532:fe11edbda85c	1919	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	532:fe11edbda85c	1920	*/
mbed_official	532:fe11edbda85c	1921	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
mbed_official	532:fe11edbda85c	1922	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
mbed_official	532:fe11edbda85c	1923	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
mbed_official	532:fe11edbda85c	1924	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
mbed_official	532:fe11edbda85c	1925	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
mbed_official	532:fe11edbda85c	1926	#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPDIFRXLPEN))
mbed_official	532:fe11edbda85c	1927	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
mbed_official	532:fe11edbda85c	1928	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
mbed_official	532:fe11edbda85c	1929	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
mbed_official	532:fe11edbda85c	1930	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_FMPI2C1LPEN))
mbed_official	532:fe11edbda85c	1931	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
mbed_official	532:fe11edbda85c	1932	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
mbed_official	532:fe11edbda85c	1933	#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CECLPEN))
mbed_official	532:fe11edbda85c	1934	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
mbed_official	532:fe11edbda85c	1935
mbed_official	532:fe11edbda85c	1936	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
mbed_official	532:fe11edbda85c	1937	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
mbed_official	532:fe11edbda85c	1938	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
mbed_official	532:fe11edbda85c	1939	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
mbed_official	532:fe11edbda85c	1940	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
mbed_official	532:fe11edbda85c	1941	#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
mbed_official	532:fe11edbda85c	1942	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
mbed_official	532:fe11edbda85c	1943	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
mbed_official	532:fe11edbda85c	1944	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
mbed_official	532:fe11edbda85c	1945	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
mbed_official	532:fe11edbda85c	1946	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
mbed_official	532:fe11edbda85c	1947	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
mbed_official	532:fe11edbda85c	1948	#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
mbed_official	532:fe11edbda85c	1949	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
mbed_official	235:685d5f11838f	1950
mbed_official	235:685d5f11838f	1951	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
mbed_official	235:685d5f11838f	1952	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	235:685d5f11838f	1953	* power consumption.
mbed_official	235:685d5f11838f	1954	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	235:685d5f11838f	1955	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	235:685d5f11838f	1956	*/
mbed_official	532:fe11edbda85c	1957	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
mbed_official	532:fe11edbda85c	1958	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
mbed_official	532:fe11edbda85c	1959	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
mbed_official	532:fe11edbda85c	1960	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
mbed_official	532:fe11edbda85c	1961	#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI2LPEN))
mbed_official	532:fe11edbda85c	1962
mbed_official	532:fe11edbda85c	1963	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
mbed_official	532:fe11edbda85c	1964	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
mbed_official	532:fe11edbda85c	1965	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
mbed_official	532:fe11edbda85c	1966	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
mbed_official	532:fe11edbda85c	1967	#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
mbed_official	532:fe11edbda85c	1968
mbed_official	532:fe11edbda85c	1969	#endif /* STM32F446xx */
mbed_official	532:fe11edbda85c	1970	/------------------------------------------------------------------------------------------------------------/
mbed_official	532:fe11edbda85c	1971
mbed_official	532:fe11edbda85c	1972	/------------------------------------------------- PLL Configuration ----------------------------------------/
mbed_official	532:fe11edbda85c	1973	#if defined(STM32F446xx)
mbed_official	532:fe11edbda85c	1974	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
mbed_official	532:fe11edbda85c	1975	* @note This function must be used only when the main PLL is disabled.
mbed_official	532:fe11edbda85c	1976	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
mbed_official	532:fe11edbda85c	1977	* This parameter can be one of the following values:
mbed_official	532:fe11edbda85c	1978	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
mbed_official	532:fe11edbda85c	1979	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
mbed_official	532:fe11edbda85c	1980	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
mbed_official	532:fe11edbda85c	1981	* @param __PLLM__: specifies the division factor for PLL VCO input clock
mbed_official	532:fe11edbda85c	1982	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
mbed_official	532:fe11edbda85c	1983	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
mbed_official	532:fe11edbda85c	1984	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
mbed_official	532:fe11edbda85c	1985	* of 2 MHz to limit PLL jitter.
mbed_official	532:fe11edbda85c	1986	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
mbed_official	532:fe11edbda85c	1987	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
mbed_official	532:fe11edbda85c	1988	* @note You have to set the PLLN parameter correctly to ensure that the VCO
mbed_official	532:fe11edbda85c	1989	* output frequency is between 192 and 432 MHz.
mbed_official	532:fe11edbda85c	1990	*
mbed_official	532:fe11edbda85c	1991	* @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
mbed_official	532:fe11edbda85c	1992	* This parameter must be a number in the range {2, 4, 6, or 8}.
mbed_official	532:fe11edbda85c	1993	*
mbed_official	532:fe11edbda85c	1994	* @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
mbed_official	532:fe11edbda85c	1995	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
mbed_official	532:fe11edbda85c	1996	* @note If the USB OTG FS is used in your application, you have to set the
mbed_official	532:fe11edbda85c	1997	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
mbed_official	532:fe11edbda85c	1998	* the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
mbed_official	532:fe11edbda85c	1999	* correctly.
mbed_official	532:fe11edbda85c	2000	*
mbed_official	532:fe11edbda85c	2001	* @param __PLLR__: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
mbed_official	532:fe11edbda85c	2002	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
mbed_official	532:fe11edbda85c	2003	* @note This parameter is only available in STM32F446xx devices.
mbed_official	532:fe11edbda85c	2004	*
mbed_official	532:fe11edbda85c	2005	*/
mbed_official	532:fe11edbda85c	2006	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \
mbed_official	532:fe11edbda85c	2007	(RCC->PLLCFGR = ((__RCC_PLLSource__) \| (__PLLM__) \| \
mbed_official	532:fe11edbda85c	2008	((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) \| \
mbed_official	532:fe11edbda85c	2009	((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) \| \
mbed_official	532:fe11edbda85c	2010	((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)) \| \
mbed_official	532:fe11edbda85c	2011	((__PLLR__) << POSITION_VAL(RCC_PLLCFGR_PLLR))))
mbed_official	532:fe11edbda85c	2012	#else
mbed_official	532:fe11edbda85c	2013	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
mbed_official	532:fe11edbda85c	2014	* @note This function must be used only when the main PLL is disabled.
mbed_official	532:fe11edbda85c	2015	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
mbed_official	532:fe11edbda85c	2016	* This parameter can be one of the following values:
mbed_official	532:fe11edbda85c	2017	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
mbed_official	532:fe11edbda85c	2018	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
mbed_official	532:fe11edbda85c	2019	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
mbed_official	532:fe11edbda85c	2020	* @param __PLLM__: specifies the division factor for PLL VCO input clock
mbed_official	532:fe11edbda85c	2021	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
mbed_official	532:fe11edbda85c	2022	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
mbed_official	532:fe11edbda85c	2023	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
mbed_official	532:fe11edbda85c	2024	* of 2 MHz to limit PLL jitter.
mbed_official	532:fe11edbda85c	2025	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
mbed_official	532:fe11edbda85c	2026	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
mbed_official	532:fe11edbda85c	2027	* @note You have to set the PLLN parameter correctly to ensure that the VCO
mbed_official	532:fe11edbda85c	2028	* output frequency is between 192 and 432 MHz.
mbed_official	532:fe11edbda85c	2029	*
mbed_official	532:fe11edbda85c	2030	* @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
mbed_official	532:fe11edbda85c	2031	* This parameter must be a number in the range {2, 4, 6, or 8}.
mbed_official	532:fe11edbda85c	2032	*
mbed_official	532:fe11edbda85c	2033	* @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
mbed_official	532:fe11edbda85c	2034	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
mbed_official	532:fe11edbda85c	2035	* @note If the USB OTG FS is used in your application, you have to set the
mbed_official	532:fe11edbda85c	2036	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
mbed_official	532:fe11edbda85c	2037	* the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
mbed_official	532:fe11edbda85c	2038	* correctly.
mbed_official	532:fe11edbda85c	2039	*
mbed_official	532:fe11edbda85c	2040	*/
mbed_official	532:fe11edbda85c	2041	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \
mbed_official	532:fe11edbda85c	2042	(RCC->PLLCFGR = (0x20000000 \| (__RCC_PLLSource__) \| (__PLLM__)\| \
mbed_official	532:fe11edbda85c	2043	((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) \| \
mbed_official	532:fe11edbda85c	2044	((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) \| \
mbed_official	532:fe11edbda85c	2045	((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
mbed_official	532:fe11edbda85c	2046	#endif /* STM32F446xx */
mbed_official	532:fe11edbda85c	2047	/-------------------------------------------------------------------------------------------------------/
mbed_official	235:685d5f11838f	2048
mbed_official	532:fe11edbda85c	2049	/------------------------------------------- PLLI2S Configuration --------------------------------------/
mbed_official	532:fe11edbda85c	2050	#if defined(STM32F446xx)
mbed_official	532:fe11edbda85c	2051	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
mbed_official	532:fe11edbda85c	2052	* @note This macro must be used only when the PLLI2S is disabled.
mbed_official	532:fe11edbda85c	2053	* @note PLLI2S clock source is common with the main PLL (configured in
mbed_official	532:fe11edbda85c	2054	* HAL_RCC_ClockConfig() API).
mbed_official	532:fe11edbda85c	2055	* @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
mbed_official	532:fe11edbda85c	2056	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
mbed_official	532:fe11edbda85c	2057	* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
mbed_official	532:fe11edbda85c	2058	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
mbed_official	532:fe11edbda85c	2059	* of 1 MHz to limit PLLI2S jitter.
mbed_official	532:fe11edbda85c	2060	* @note The PLLI2SM parameter is only used with STM32F411xE and STM32F446xx Devices
mbed_official	532:fe11edbda85c	2061	*
mbed_official	532:fe11edbda85c	2062	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
mbed_official	532:fe11edbda85c	2063	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
mbed_official	532:fe11edbda85c	2064	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
mbed_official	532:fe11edbda85c	2065	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
mbed_official	532:fe11edbda85c	2066	*
mbed_official	532:fe11edbda85c	2067	* @param __PLLI2SP__: specifies division factor for SPDIFRX Clock.
mbed_official	532:fe11edbda85c	2068	* This parameter must be a number in the range {2, 4, 6, or 8}.
mbed_official	532:fe11edbda85c	2069	* @note the PLLI2SP parameter is only available with STM32F446xx Devices
mbed_official	532:fe11edbda85c	2070	*
mbed_official	532:fe11edbda85c	2071	* @param __PLLI2SR__: specifies the division factor for I2S clock
mbed_official	532:fe11edbda85c	2072	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
mbed_official	532:fe11edbda85c	2073	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
mbed_official	532:fe11edbda85c	2074	* on the I2S clock frequency.
mbed_official	532:fe11edbda85c	2075	*
mbed_official	532:fe11edbda85c	2076	* @param __PLLI2SQ__: specifies the division factor for SAI clock
mbed_official	532:fe11edbda85c	2077	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
mbed_official	532:fe11edbda85c	2078	* @note the PLLI2SQ parameter is only available with STM32F427/437/429x/439xx Devices
mbed_official	532:fe11edbda85c	2079	*
mbed_official	532:fe11edbda85c	2080	*/
mbed_official	532:fe11edbda85c	2081	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \
mbed_official	532:fe11edbda85c	2082	(RCC->PLLI2SCFGR = ((__PLLI2SM__) \|\
mbed_official	532:fe11edbda85c	2083	((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
mbed_official	532:fe11edbda85c	2084	((((__PLLI2SP__) >> 1) -1) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) \|\
mbed_official	532:fe11edbda85c	2085	((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) \|\
mbed_official	532:fe11edbda85c	2086	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
mbed_official	532:fe11edbda85c	2087	#else
mbed_official	532:fe11edbda85c	2088	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
mbed_official	532:fe11edbda85c	2089	* @note This macro must be used only when the PLLI2S is disabled.
mbed_official	532:fe11edbda85c	2090	* @note PLLI2S clock source is common with the main PLL (configured in
mbed_official	532:fe11edbda85c	2091	* HAL_RCC_ClockConfig() API).
mbed_official	532:fe11edbda85c	2092	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
mbed_official	532:fe11edbda85c	2093	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
mbed_official	532:fe11edbda85c	2094	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
mbed_official	532:fe11edbda85c	2095	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
mbed_official	532:fe11edbda85c	2096	* @param __PLLI2SR__: specifies the division factor for I2S clock
mbed_official	532:fe11edbda85c	2097	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
mbed_official	532:fe11edbda85c	2098	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
mbed_official	532:fe11edbda85c	2099	* on the I2S clock frequency.
mbed_official	532:fe11edbda85c	2100	*
mbed_official	532:fe11edbda85c	2101	*/
mbed_official	532:fe11edbda85c	2102	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) \
mbed_official	532:fe11edbda85c	2103	(RCC->PLLI2SCFGR = (((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \| \
mbed_official	532:fe11edbda85c	2104	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
mbed_official	532:fe11edbda85c	2105	#endif /* STM32F446xx */
mbed_official	235:685d5f11838f	2106
mbed_official	235:685d5f11838f	2107	#if defined(STM32F411xE)
mbed_official	532:fe11edbda85c	2108
mbed_official	532:fe11edbda85c	2109	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
mbed_official	532:fe11edbda85c	2110	* @note This macro must be used only when the PLLI2S is disabled.
mbed_official	532:fe11edbda85c	2111	* @note This macro must be used only when the PLLI2S is disabled.
mbed_official	532:fe11edbda85c	2112	* @note PLLI2S clock source is common with the main PLL (configured in
mbed_official	532:fe11edbda85c	2113	* HAL_RCC_ClockConfig() API).
mbed_official	532:fe11edbda85c	2114	* @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
mbed_official	532:fe11edbda85c	2115	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
mbed_official	532:fe11edbda85c	2116	* @note The PLLI2SM parameter is only used with STM32F411xE Devices
mbed_official	532:fe11edbda85c	2117	* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
mbed_official	532:fe11edbda85c	2118	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
mbed_official	532:fe11edbda85c	2119	* of 2 MHz to limit PLLI2S jitter.
mbed_official	532:fe11edbda85c	2120	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
mbed_official	532:fe11edbda85c	2121	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
mbed_official	532:fe11edbda85c	2122	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
mbed_official	532:fe11edbda85c	2123	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
mbed_official	532:fe11edbda85c	2124	* @param __PLLI2SR__: specifies the division factor for I2S clock
mbed_official	532:fe11edbda85c	2125	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
mbed_official	532:fe11edbda85c	2126	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
mbed_official	532:fe11edbda85c	2127	* on the I2S clock frequency.
mbed_official	532:fe11edbda85c	2128	*/
mbed_official	532:fe11edbda85c	2129	#define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SM__) \|\
mbed_official	532:fe11edbda85c	2130	((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
mbed_official	532:fe11edbda85c	2131	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
mbed_official	532:fe11edbda85c	2132	#endif /* STM32F411xE */
mbed_official	532:fe11edbda85c	2133
mbed_official	532:fe11edbda85c	2134	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
mbed_official	532:fe11edbda85c	2135	/** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
mbed_official	532:fe11edbda85c	2136	* @note This macro must be used only when the PLLI2S is disabled.
mbed_official	532:fe11edbda85c	2137	* @note PLLI2S clock source is common with the main PLL (configured in
mbed_official	532:fe11edbda85c	2138	* HAL_RCC_ClockConfig() API)
mbed_official	532:fe11edbda85c	2139	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
mbed_official	532:fe11edbda85c	2140	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
mbed_official	532:fe11edbda85c	2141	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
mbed_official	532:fe11edbda85c	2142	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
mbed_official	532:fe11edbda85c	2143	* @param __PLLI2SQ__: specifies the division factor for SAI1 clock.
mbed_official	532:fe11edbda85c	2144	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
mbed_official	532:fe11edbda85c	2145	* @note the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx Devices
mbed_official	532:fe11edbda85c	2146	* and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
mbed_official	532:fe11edbda85c	2147	* @param __PLLI2SR__: specifies the division factor for I2S clock
mbed_official	532:fe11edbda85c	2148	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
mbed_official	532:fe11edbda85c	2149	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
mbed_official	532:fe11edbda85c	2150	* on the I2S clock frequency.
mbed_official	532:fe11edbda85c	2151	*/
mbed_official	532:fe11edbda85c	2152	#define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) \|\
mbed_official	532:fe11edbda85c	2153	((__PLLI2SQ__) << 24) \|\
mbed_official	532:fe11edbda85c	2154	((__PLLI2SR__) << 28))
mbed_official	532:fe11edbda85c	2155	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
mbed_official	532:fe11edbda85c	2156	/----------------------------------------------------------------------------------------------------------------/
mbed_official	532:fe11edbda85c	2157
mbed_official	532:fe11edbda85c	2158	/--------------------------------------------------- PLLSAI Configuration ---------------------------------------/
mbed_official	532:fe11edbda85c	2159	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx)
mbed_official	532:fe11edbda85c	2160	/** @brief Macros to Enable or Disable the PLLISAI.
mbed_official	532:fe11edbda85c	2161	* @note The PLLSAI is only available with STM32F429x/439x Devices.
mbed_official	532:fe11edbda85c	2162	* @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
mbed_official	532:fe11edbda85c	2163	*/
mbed_official	532:fe11edbda85c	2164	#define __HAL_RCC_PLLSAI_ENABLE() ((__IO uint32_t ) RCC_CR_PLLSAION_BB = ENABLE)
mbed_official	532:fe11edbda85c	2165	#define __HAL_RCC_PLLSAI_DISABLE() ((__IO uint32_t ) RCC_CR_PLLSAION_BB = DISABLE)
mbed_official	532:fe11edbda85c	2166
mbed_official	532:fe11edbda85c	2167	#if defined(STM32F446xx)
mbed_official	532:fe11edbda85c	2168	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
mbed_official	532:fe11edbda85c	2169	*
mbed_official	532:fe11edbda85c	2170	* @param __PLLSAIM__: specifies the division factor for PLLSAI VCO input clock
mbed_official	532:fe11edbda85c	2171	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
mbed_official	532:fe11edbda85c	2172	* @note You have to set the PLLSAIM parameter correctly to ensure that the VCO input
mbed_official	532:fe11edbda85c	2173	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
mbed_official	532:fe11edbda85c	2174	* of 1 MHz to limit PLLI2S jitter.
mbed_official	532:fe11edbda85c	2175	* @note The PLLSAIM parameter is only used with STM32F446xx Devices
mbed_official	532:fe11edbda85c	2176	*
mbed_official	532:fe11edbda85c	2177	* @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
mbed_official	532:fe11edbda85c	2178	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
mbed_official	532:fe11edbda85c	2179	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
mbed_official	532:fe11edbda85c	2180	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
mbed_official	532:fe11edbda85c	2181	*
mbed_official	532:fe11edbda85c	2182	* @param __PLLSAIP__: specifies division factor for OTG FS, SDIO and RNG clocks.
mbed_official	532:fe11edbda85c	2183	* This parameter must be a number in the range {2, 4, 6, or 8}.
mbed_official	532:fe11edbda85c	2184	* @note the PLLSAIP parameter is only available with STM32F446xx Devices
mbed_official	532:fe11edbda85c	2185	*
mbed_official	532:fe11edbda85c	2186	* @param __PLLSAIQ__: specifies the division factor for SAI clock
mbed_official	532:fe11edbda85c	2187	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
mbed_official	532:fe11edbda85c	2188	*
mbed_official	532:fe11edbda85c	2189	* @param __PLLSAIR__: specifies the division factor for LTDC clock
mbed_official	532:fe11edbda85c	2190	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
mbed_official	532:fe11edbda85c	2191	* @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
mbed_official	532:fe11edbda85c	2192	*/
mbed_official	532:fe11edbda85c	2193	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
mbed_official	532:fe11edbda85c	2194	(RCC->PLLSAICFGR = ((__PLLSAIM__) \| \
mbed_official	532:fe11edbda85c	2195	((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) \| \
mbed_official	532:fe11edbda85c	2196	((((__PLLSAIP__) >> 1) -1) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) \| \
mbed_official	532:fe11edbda85c	2197	((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ))))
mbed_official	532:fe11edbda85c	2198	#endif /* STM32F446xx */
mbed_official	532:fe11edbda85c	2199
mbed_official	532:fe11edbda85c	2200	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
mbed_official	532:fe11edbda85c	2201	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
mbed_official	532:fe11edbda85c	2202	*
mbed_official	532:fe11edbda85c	2203	* @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
mbed_official	532:fe11edbda85c	2204	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
mbed_official	532:fe11edbda85c	2205	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
mbed_official	532:fe11edbda85c	2206	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
mbed_official	532:fe11edbda85c	2207	*
mbed_official	532:fe11edbda85c	2208	* @param __PLLSAIQ__: specifies the division factor for SAI clock
mbed_official	532:fe11edbda85c	2209	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
mbed_official	532:fe11edbda85c	2210	*
mbed_official	532:fe11edbda85c	2211	* @param __PLLSAIR__: specifies the division factor for LTDC clock
mbed_official	532:fe11edbda85c	2212	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
mbed_official	532:fe11edbda85c	2213	* @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
mbed_official	235:685d5f11838f	2214	*/
mbed_official	532:fe11edbda85c	2215	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) \
mbed_official	532:fe11edbda85c	2216	(RCC->PLLSAICFGR = (((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) \| \
mbed_official	532:fe11edbda85c	2217	((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) \| \
mbed_official	532:fe11edbda85c	2218	((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR))))
mbed_official	532:fe11edbda85c	2219	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
mbed_official	532:fe11edbda85c	2220
mbed_official	532:fe11edbda85c	2221	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx */
mbed_official	532:fe11edbda85c	2222	/----------------------------------------------------------------------------------------------------------------------/
mbed_official	532:fe11edbda85c	2223
mbed_official	532:fe11edbda85c	2224	/----------------------------------------- PLLSAI/PLLI2S Dividers Configuration ---------------------------------------/
mbed_official	532:fe11edbda85c	2225	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx)
mbed_official	532:fe11edbda85c	2226	/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
mbed_official	532:fe11edbda85c	2227	* @note This function must be called before enabling the PLLI2S.
mbed_official	532:fe11edbda85c	2228	* @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .
mbed_official	532:fe11edbda85c	2229	* This parameter must be a number between 1 and 32.
mbed_official	532:fe11edbda85c	2230	* SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
mbed_official	532:fe11edbda85c	2231	*/
mbed_official	532:fe11edbda85c	2232	#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
mbed_official	532:fe11edbda85c	2233
mbed_official	532:fe11edbda85c	2234	/** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
mbed_official	532:fe11edbda85c	2235	* @note This function must be called before enabling the PLLSAI.
mbed_official	532:fe11edbda85c	2236	* @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
mbed_official	532:fe11edbda85c	2237	* This parameter must be a number between Min_Data = 1 and Max_Data = 32.
mbed_official	532:fe11edbda85c	2238	* SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
mbed_official	532:fe11edbda85c	2239	*/
mbed_official	532:fe11edbda85c	2240	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
mbed_official	532:fe11edbda85c	2241	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx */
mbed_official	532:fe11edbda85c	2242
mbed_official	532:fe11edbda85c	2243	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
mbed_official	532:fe11edbda85c	2244	/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
mbed_official	532:fe11edbda85c	2245	*
mbed_official	532:fe11edbda85c	2246	* @note The LTDC peripheral is only available with STM32F427/437/429/439xx Devices.
mbed_official	532:fe11edbda85c	2247	* @note This function must be called before enabling the PLLSAI.
mbed_official	532:fe11edbda85c	2248	* @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
mbed_official	532:fe11edbda85c	2249	* This parameter must be a number between Min_Data = 2 and Max_Data = 16.
mbed_official	532:fe11edbda85c	2250	* LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
mbed_official	532:fe11edbda85c	2251	*/
mbed_official	532:fe11edbda85c	2252	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
mbed_official	532:fe11edbda85c	2253	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
mbed_official	532:fe11edbda85c	2254	/-----------------------------------------------------------------------------------------------------------------------------------/
mbed_official	532:fe11edbda85c	2255
mbed_official	532:fe11edbda85c	2256	/-------------------------------------------------- Peripheral Clock selection -----------------------------------------------------/
mbed_official	532:fe11edbda85c	2257	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\|\
mbed_official	532:fe11edbda85c	2258	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
mbed_official	532:fe11edbda85c	2259	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
mbed_official	532:fe11edbda85c	2260	/** @brief Macro to configure the I2S clock source (I2SCLK).
mbed_official	532:fe11edbda85c	2261	* @note This function must be called before enabling the I2S APB clock.
mbed_official	532:fe11edbda85c	2262	* @param __SOURCE__: specifies the I2S clock source.
mbed_official	532:fe11edbda85c	2263	* This parameter can be one of the following values:
mbed_official	532:fe11edbda85c	2264	* @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
mbed_official	532:fe11edbda85c	2265	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
mbed_official	532:fe11edbda85c	2266	* used as I2S clock source.
mbed_official	235:685d5f11838f	2267	*/
mbed_official	532:fe11edbda85c	2268	#define __HAL_RCC_I2S_CONFIG(__SOURCE__) ((__IO uint32_t ) RCC_CFGR_I2SSRC_BB = (__SOURCE__))
mbed_official	532:fe11edbda85c	2269	#endif /* STM32F40xxx \|\| STM32F41xxx \|\| STM32F42xxx \|\| STM32F43xxx */
mbed_official	532:fe11edbda85c	2270
mbed_official	532:fe11edbda85c	2271	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
mbed_official	532:fe11edbda85c	2272
mbed_official	532:fe11edbda85c	2273	/** @brief Macro to configure SAI1BlockA clock source selection.
mbed_official	532:fe11edbda85c	2274	* @note The SAI peripheral is only available with STM32F427/437/429/439xx Devices.
mbed_official	532:fe11edbda85c	2275	* @note This function must be called before enabling PLLSAI, PLLI2S and
mbed_official	532:fe11edbda85c	2276	* the SAI clock.
mbed_official	532:fe11edbda85c	2277	* @param __SOURCE__: specifies the SAI Block A clock source.
mbed_official	532:fe11edbda85c	2278	* This parameter can be one of the following values:
mbed_official	532:fe11edbda85c	2279	* @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
mbed_official	532:fe11edbda85c	2280	* as SAI1 Block A clock.
mbed_official	532:fe11edbda85c	2281	* @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
mbed_official	532:fe11edbda85c	2282	* as SAI1 Block A clock.
mbed_official	532:fe11edbda85c	2283	* @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
mbed_official	532:fe11edbda85c	2284	* used as SAI1 Block A clock.
mbed_official	532:fe11edbda85c	2285	*/
mbed_official	532:fe11edbda85c	2286	#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
mbed_official	532:fe11edbda85c	2287
mbed_official	532:fe11edbda85c	2288	/** @brief Macro to configure SAI1BlockB clock source selection.
mbed_official	532:fe11edbda85c	2289	* @note The SAI peripheral is only available with STM32F427/437/429/439xx Devices.
mbed_official	532:fe11edbda85c	2290	* @note This function must be called before enabling PLLSAI, PLLI2S and
mbed_official	532:fe11edbda85c	2291	* the SAI clock.
mbed_official	532:fe11edbda85c	2292	* @param __SOURCE__: specifies the SAI Block B clock source.
mbed_official	532:fe11edbda85c	2293	* This parameter can be one of the following values:
mbed_official	532:fe11edbda85c	2294	* @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
mbed_official	532:fe11edbda85c	2295	* as SAI1 Block B clock.
mbed_official	532:fe11edbda85c	2296	* @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
mbed_official	532:fe11edbda85c	2297	* as SAI1 Block B clock.
mbed_official	532:fe11edbda85c	2298	* @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
mbed_official	532:fe11edbda85c	2299	* used as SAI1 Block B clock.
mbed_official	532:fe11edbda85c	2300	*/
mbed_official	532:fe11edbda85c	2301	#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
mbed_official	532:fe11edbda85c	2302	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
mbed_official	532:fe11edbda85c	2303
mbed_official	532:fe11edbda85c	2304	#if defined(STM32F446xx)
mbed_official	532:fe11edbda85c	2305	/** @brief Macro to configure SAI1 clock source selection.
mbed_official	532:fe11edbda85c	2306	* @note This configuration is only available with STM32F446xx Devices.
mbed_official	532:fe11edbda85c	2307	* @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
mbed_official	532:fe11edbda85c	2308	* the SAI clock.
mbed_official	532:fe11edbda85c	2309	* @param __SOURCE__: specifies the SAI1 clock source.
mbed_official	532:fe11edbda85c	2310	* This parameter can be one of the following values:
mbed_official	532:fe11edbda85c	2311	* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
mbed_official	532:fe11edbda85c	2312	* @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
mbed_official	532:fe11edbda85c	2313	* @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
mbed_official	532:fe11edbda85c	2314	* @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
mbed_official	532:fe11edbda85c	2315	*/
mbed_official	532:fe11edbda85c	2316	#define __HAL_RCC_SAI1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC, (__SOURCE__)))
mbed_official	532:fe11edbda85c	2317
mbed_official	532:fe11edbda85c	2318	/** @brief Macro to Get SAI1 clock source selection.
mbed_official	532:fe11edbda85c	2319	* @note This configuration is only available with STM32F446xx Devices.
mbed_official	532:fe11edbda85c	2320	* @retval The clock source can be one of the following values:
mbed_official	532:fe11edbda85c	2321	* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
mbed_official	532:fe11edbda85c	2322	* @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
mbed_official	532:fe11edbda85c	2323	* @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
mbed_official	532:fe11edbda85c	2324	* @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
mbed_official	532:fe11edbda85c	2325	*/
mbed_official	532:fe11edbda85c	2326	#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC))
mbed_official	532:fe11edbda85c	2327
mbed_official	532:fe11edbda85c	2328	/** @brief Macro to configure SAI2 clock source selection.
mbed_official	532:fe11edbda85c	2329	* @note This configuration is only available with STM32F446xx Devices.
mbed_official	532:fe11edbda85c	2330	* @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
mbed_official	532:fe11edbda85c	2331	* the SAI clock.
mbed_official	532:fe11edbda85c	2332	* @param __SOURCE__: specifies the SAI2 clock source.
mbed_official	532:fe11edbda85c	2333	* This parameter can be one of the following values:
mbed_official	532:fe11edbda85c	2334	* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
mbed_official	532:fe11edbda85c	2335	* @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
mbed_official	532:fe11edbda85c	2336	* @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
mbed_official	532:fe11edbda85c	2337	* @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
mbed_official	532:fe11edbda85c	2338	*/
mbed_official	532:fe11edbda85c	2339	#define __HAL_RCC_SAI2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC, (__SOURCE__)))
mbed_official	235:685d5f11838f	2340
mbed_official	532:fe11edbda85c	2341	/** @brief Macro to Get SAI2 clock source selection.
mbed_official	532:fe11edbda85c	2342	* @note This configuration is only available with STM32F446xx Devices.
mbed_official	532:fe11edbda85c	2343	* @retval The clock source can be one of the following values:
mbed_official	532:fe11edbda85c	2344	* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
mbed_official	532:fe11edbda85c	2345	* @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
mbed_official	532:fe11edbda85c	2346	* @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
mbed_official	532:fe11edbda85c	2347	* @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
mbed_official	532:fe11edbda85c	2348	*/
mbed_official	532:fe11edbda85c	2349	#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC))
mbed_official	532:fe11edbda85c	2350
mbed_official	532:fe11edbda85c	2351	/** @brief Macro to configure I2S APB1 clock source selection.
mbed_official	532:fe11edbda85c	2352	* @note This configuration is only available with STM32F446xx Devices.
mbed_official	532:fe11edbda85c	2353	* @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
mbed_official	532:fe11edbda85c	2354	* @param __SOURCE__: specifies the I2S APB1 clock source.
mbed_official	532:fe11edbda85c	2355	* This parameter can be one of the following values:
mbed_official	532:fe11edbda85c	2356	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
mbed_official	532:fe11edbda85c	2357	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
mbed_official	532:fe11edbda85c	2358	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
mbed_official	532:fe11edbda85c	2359	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
mbed_official	532:fe11edbda85c	2360	*/
mbed_official	532:fe11edbda85c	2361	#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
mbed_official	532:fe11edbda85c	2362
mbed_official	532:fe11edbda85c	2363	/** @brief Macro to Get I2S APB1 clock source selection.
mbed_official	532:fe11edbda85c	2364	* @note This configuration is only available with STM32F446xx Devices.
mbed_official	532:fe11edbda85c	2365	* @retval The clock source can be one of the following values:
mbed_official	532:fe11edbda85c	2366	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
mbed_official	532:fe11edbda85c	2367	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
mbed_official	532:fe11edbda85c	2368	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
mbed_official	532:fe11edbda85c	2369	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
mbed_official	532:fe11edbda85c	2370	*/
mbed_official	532:fe11edbda85c	2371	#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
mbed_official	532:fe11edbda85c	2372
mbed_official	532:fe11edbda85c	2373	/** @brief Macro to configure I2S APB2 clock source selection.
mbed_official	532:fe11edbda85c	2374	* @note This configuration is only available with STM32F446xx Devices.
mbed_official	532:fe11edbda85c	2375	* @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
mbed_official	532:fe11edbda85c	2376	* @param __SOURCE__: specifies the SAI Block A clock source.
mbed_official	532:fe11edbda85c	2377	* This parameter can be one of the following values:
mbed_official	532:fe11edbda85c	2378	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
mbed_official	532:fe11edbda85c	2379	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
mbed_official	532:fe11edbda85c	2380	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
mbed_official	532:fe11edbda85c	2381	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
mbed_official	532:fe11edbda85c	2382	*/
mbed_official	532:fe11edbda85c	2383	#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
mbed_official	532:fe11edbda85c	2384
mbed_official	532:fe11edbda85c	2385	/** @brief Macro to Get I2S APB2 clock source selection.
mbed_official	532:fe11edbda85c	2386	* @note This configuration is only available with STM32F446xx Devices.
mbed_official	532:fe11edbda85c	2387	* @retval The clock source can be one of the following values:
mbed_official	532:fe11edbda85c	2388	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
mbed_official	532:fe11edbda85c	2389	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
mbed_official	532:fe11edbda85c	2390	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
mbed_official	532:fe11edbda85c	2391	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
mbed_official	532:fe11edbda85c	2392	*/
mbed_official	532:fe11edbda85c	2393	#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
mbed_official	532:fe11edbda85c	2394
mbed_official	532:fe11edbda85c	2395	/** @brief Macro to configure the CEC clock.
mbed_official	532:fe11edbda85c	2396	* @param __SOURCE__: specifies the CEC clock source.
mbed_official	532:fe11edbda85c	2397	* This parameter can be one of the following values:
mbed_official	532:fe11edbda85c	2398	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
mbed_official	532:fe11edbda85c	2399	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
mbed_official	532:fe11edbda85c	2400	*/
mbed_official	532:fe11edbda85c	2401	#define __HAL_RCC_CEC_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__SOURCE__)))
mbed_official	235:685d5f11838f	2402
mbed_official	532:fe11edbda85c	2403	/** @brief Macro to Get the CEC clock.
mbed_official	532:fe11edbda85c	2404	* @retval The clock source can be one of the following values:
mbed_official	532:fe11edbda85c	2405	* @arg RCC_CECCLKSOURCE_HSI488: HSI selected as CEC clock
mbed_official	532:fe11edbda85c	2406	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
mbed_official	532:fe11edbda85c	2407	*/
mbed_official	532:fe11edbda85c	2408	#define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))
mbed_official	532:fe11edbda85c	2409
mbed_official	532:fe11edbda85c	2410	/** @brief Macro to configure the FMPI2C1 clock.
mbed_official	532:fe11edbda85c	2411	* @param __SOURCE__: specifies the FMPI2C1 clock source.
mbed_official	532:fe11edbda85c	2412	* This parameter can be one of the following values:
mbed_official	532:fe11edbda85c	2413	* @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as CEC clock
mbed_official	532:fe11edbda85c	2414	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as CEC clock
mbed_official	532:fe11edbda85c	2415	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as CEC clock
mbed_official	532:fe11edbda85c	2416	*/
mbed_official	532:fe11edbda85c	2417	#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
mbed_official	532:fe11edbda85c	2418
mbed_official	532:fe11edbda85c	2419	/** @brief Macro to Get the FMPI2C1 clock.
mbed_official	532:fe11edbda85c	2420	* @retval The clock source can be one of the following values:
mbed_official	532:fe11edbda85c	2421	* @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as CEC clock
mbed_official	532:fe11edbda85c	2422	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as CEC clock
mbed_official	532:fe11edbda85c	2423	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as CEC clock
mbed_official	532:fe11edbda85c	2424	*/
mbed_official	532:fe11edbda85c	2425	#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
mbed_official	532:fe11edbda85c	2426
mbed_official	532:fe11edbda85c	2427	/** @brief Macro to configure the CLK48 clock.
mbed_official	532:fe11edbda85c	2428	* @param __SOURCE__: specifies the CK48 clock source.
mbed_official	532:fe11edbda85c	2429	* This parameter can be one of the following values:
mbed_official	532:fe11edbda85c	2430	* @arg RCC_CK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CK48 clock.
mbed_official	532:fe11edbda85c	2431	* @arg RCC_CK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CK48 clock.
mbed_official	532:fe11edbda85c	2432	*/
mbed_official	532:fe11edbda85c	2433	#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
mbed_official	532:fe11edbda85c	2434
mbed_official	532:fe11edbda85c	2435	/** @brief Macro to Get the CLK48 clock.
mbed_official	532:fe11edbda85c	2436	* @retval The clock source can be one of the following values:
mbed_official	532:fe11edbda85c	2437	* @arg RCC_CK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CK48 clock.
mbed_official	532:fe11edbda85c	2438	* @arg RCC_CK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CK48 clock.
mbed_official	532:fe11edbda85c	2439	*/
mbed_official	532:fe11edbda85c	2440	#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
mbed_official	532:fe11edbda85c	2441
mbed_official	532:fe11edbda85c	2442	/** @brief Macro to configure the SDIO clock.
mbed_official	532:fe11edbda85c	2443	* @param __SOURCE__: specifies the SDIO clock source.
mbed_official	532:fe11edbda85c	2444	* This parameter can be one of the following values:
mbed_official	532:fe11edbda85c	2445	* @arg RCC_SDIOCLKSOURCE_CK48: CK48 output used as SDIO clock.
mbed_official	532:fe11edbda85c	2446	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
mbed_official	532:fe11edbda85c	2447	*/
mbed_official	532:fe11edbda85c	2448	#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
mbed_official	532:fe11edbda85c	2449
mbed_official	532:fe11edbda85c	2450	/** @brief Macro to Get the SDIO clock.
mbed_official	532:fe11edbda85c	2451	* @retval The clock source can be one of the following values:
mbed_official	532:fe11edbda85c	2452	* @arg RCC_SDIOCLKSOURCE_CK48: CK48 output used as SDIO clock.
mbed_official	532:fe11edbda85c	2453	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
mbed_official	532:fe11edbda85c	2454	*/
mbed_official	532:fe11edbda85c	2455	#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
mbed_official	532:fe11edbda85c	2456
mbed_official	532:fe11edbda85c	2457	/** @brief Macro to configure the SPDIFRX clock.
mbed_official	532:fe11edbda85c	2458	* @param __SOURCE__: specifies the SPDIFRX clock source.
mbed_official	532:fe11edbda85c	2459	* This parameter can be one of the following values:
mbed_official	532:fe11edbda85c	2460	* @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
mbed_official	532:fe11edbda85c	2461	* @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
mbed_official	532:fe11edbda85c	2462	*/
mbed_official	532:fe11edbda85c	2463	#define __HAL_RCC_SPDIFRX_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, (uint32_t)(__SOURCE__)))
mbed_official	532:fe11edbda85c	2464
mbed_official	532:fe11edbda85c	2465	/** @brief Macro to Get the SPDIFRX clock.
mbed_official	532:fe11edbda85c	2466	* @retval The clock source can be one of the following values:
mbed_official	532:fe11edbda85c	2467	* @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
mbed_official	532:fe11edbda85c	2468	* @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
mbed_official	532:fe11edbda85c	2469	*/
mbed_official	532:fe11edbda85c	2470	#define __HAL_RCC_GET_SPDIFRX_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL))
mbed_official	532:fe11edbda85c	2471	#endif /* STM32F446xx */
mbed_official	235:685d5f11838f	2472
mbed_official	235:685d5f11838f	2473	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\|\
mbed_official	532:fe11edbda85c	2474	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx)
mbed_official	235:685d5f11838f	2475
mbed_official	235:685d5f11838f	2476	/** @brief Macro to configure the Timers clocks prescalers
mbed_official	235:685d5f11838f	2477	* @note This feature is only available with STM32F429x/439x Devices.
mbed_official	235:685d5f11838f	2478	* @param __PRESC__ : specifies the Timers clocks prescalers selection
mbed_official	235:685d5f11838f	2479	* This parameter can be one of the following values:
mbed_official	235:685d5f11838f	2480	* @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
mbed_official	235:685d5f11838f	2481	* equal to HPRE if PPREx is corresponding to division by 1 or 2,
mbed_official	235:685d5f11838f	2482	* else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
mbed_official	235:685d5f11838f	2483	* division by 4 or more.
mbed_official	235:685d5f11838f	2484	* @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
mbed_official	235:685d5f11838f	2485	* equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
mbed_official	235:685d5f11838f	2486	* else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
mbed_official	235:685d5f11838f	2487	* to division by 8 or more.
mbed_official	235:685d5f11838f	2488	*/
mbed_official	532:fe11edbda85c	2489	#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) ((__IO uint32_t ) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__))
mbed_official	235:685d5f11838f	2490
mbed_official	532:fe11edbda85c	2491	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx) \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx */
mbed_official	235:685d5f11838f	2492
mbed_official	532:fe11edbda85c	2493	/-------------------------------------------------------------------------------------------------------------------/
mbed_official	235:685d5f11838f	2494
mbed_official	532:fe11edbda85c	2495	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx)
mbed_official	235:685d5f11838f	2496	/** @brief Enable PLLSAI_RDY interrupt.
mbed_official	235:685d5f11838f	2497	*/
mbed_official	235:685d5f11838f	2498	#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYIE))
mbed_official	235:685d5f11838f	2499
mbed_official	235:685d5f11838f	2500	/** @brief Disable PLLSAI_RDY interrupt.
mbed_official	235:685d5f11838f	2501	*/
mbed_official	235:685d5f11838f	2502	#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
mbed_official	235:685d5f11838f	2503
mbed_official	235:685d5f11838f	2504	/** @brief Clear the PLLSAI RDY interrupt pending bits.
mbed_official	235:685d5f11838f	2505	*/
mbed_official	235:685d5f11838f	2506	#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYF))
mbed_official	235:685d5f11838f	2507
mbed_official	235:685d5f11838f	2508	/** @brief Check the PLLSAI RDY interrupt has occurred or not.
mbed_official	235:685d5f11838f	2509	* @retval The new state (TRUE or FALSE).
mbed_official	235:685d5f11838f	2510	*/
mbed_official	235:685d5f11838f	2511	#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
mbed_official	235:685d5f11838f	2512
mbed_official	235:685d5f11838f	2513	/** @brief Check PLLSAI RDY flag is set or not.
mbed_official	235:685d5f11838f	2514	* @retval The new state (TRUE or FALSE).
mbed_official	235:685d5f11838f	2515	*/
mbed_official	235:685d5f11838f	2516	#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
mbed_official	235:685d5f11838f	2517
mbed_official	532:fe11edbda85c	2518	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx */
mbed_official	532:fe11edbda85c	2519
mbed_official	532:fe11edbda85c	2520	/**
mbed_official	532:fe11edbda85c	2521	* @}
mbed_official	532:fe11edbda85c	2522	*/
mbed_official	235:685d5f11838f	2523
mbed_official	235:685d5f11838f	2524	/* Exported functions --------------------------------------------------------*/
mbed_official	532:fe11edbda85c	2525	/** @addtogroup RCCEx_Exported_Functions
mbed_official	532:fe11edbda85c	2526	* @{
mbed_official	532:fe11edbda85c	2527	*/
mbed_official	532:fe11edbda85c	2528
mbed_official	532:fe11edbda85c	2529	/** @addtogroup RCCEx_Exported_Functions_Group1
mbed_official	532:fe11edbda85c	2530	* @{
mbed_official	532:fe11edbda85c	2531	*/
mbed_official	235:685d5f11838f	2532	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
mbed_official	235:685d5f11838f	2533	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
mbed_official	235:685d5f11838f	2534
mbed_official	532:fe11edbda85c	2535	#if defined(STM32F446xx)
mbed_official	532:fe11edbda85c	2536	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
mbed_official	532:fe11edbda85c	2537	#endif /* STM32F446xx */
mbed_official	532:fe11edbda85c	2538
mbed_official	532:fe11edbda85c	2539	#if defined(STM32F411xE) \|\| defined(STM32F446xx)
mbed_official	235:685d5f11838f	2540	void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
mbed_official	532:fe11edbda85c	2541	#endif /* STM32F411xE \|\| STM32F446xx */
mbed_official	235:685d5f11838f	2542	/**
mbed_official	235:685d5f11838f	2543	* @}
mbed_official	235:685d5f11838f	2544	*/
mbed_official	235:685d5f11838f	2545
mbed_official	235:685d5f11838f	2546	/**
mbed_official	235:685d5f11838f	2547	* @}
mbed_official	235:685d5f11838f	2548	*/
mbed_official	532:fe11edbda85c	2549	/* Private types -------------------------------------------------------------*/
mbed_official	532:fe11edbda85c	2550	/* Private variables ---------------------------------------------------------*/
mbed_official	532:fe11edbda85c	2551	/* Private constants ---------------------------------------------------------*/
mbed_official	532:fe11edbda85c	2552	/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
mbed_official	532:fe11edbda85c	2553	* @{
mbed_official	532:fe11edbda85c	2554	*/
mbed_official	532:fe11edbda85c	2555
mbed_official	532:fe11edbda85c	2556	/** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion
mbed_official	532:fe11edbda85c	2557	* @brief RCC registers bit address in the alias region
mbed_official	532:fe11edbda85c	2558	* @{
mbed_official	532:fe11edbda85c	2559	*/
mbed_official	532:fe11edbda85c	2560	/* --- CR Register ---*/
mbed_official	532:fe11edbda85c	2561	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx)
mbed_official	532:fe11edbda85c	2562	/* Alias word address of PLLSAION bit */
mbed_official	532:fe11edbda85c	2563	#define RCC_PLLSAION_BIT_NUMBER 0x1C
mbed_official	532:fe11edbda85c	2564	#define RCC_CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLSAION_BIT_NUMBER * 4))
mbed_official	532:fe11edbda85c	2565
mbed_official	532:fe11edbda85c	2566	/* --- DCKCFGR Register ---*/
mbed_official	532:fe11edbda85c	2567	/* Alias word address of TIMPRE bit */
mbed_official	532:fe11edbda85c	2568	#define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
mbed_official	532:fe11edbda85c	2569	#define RCC_TIMPRE_BIT_NUMBER 0x18
mbed_official	532:fe11edbda85c	2570	#define RCC_DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32) + (RCC_TIMPRE_BIT_NUMBER * 4))
mbed_official	532:fe11edbda85c	2571	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx */
mbed_official	532:fe11edbda85c	2572
mbed_official	532:fe11edbda85c	2573	#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official	532:fe11edbda85c	2574
mbed_official	532:fe11edbda85c	2575	/**
mbed_official	532:fe11edbda85c	2576	* @}
mbed_official	532:fe11edbda85c	2577	*/
mbed_official	532:fe11edbda85c	2578
mbed_official	532:fe11edbda85c	2579	/**
mbed_official	532:fe11edbda85c	2580	* @}
mbed_official	532:fe11edbda85c	2581	*/
mbed_official	532:fe11edbda85c	2582
mbed_official	532:fe11edbda85c	2583	/* Private macros ------------------------------------------------------------*/
mbed_official	532:fe11edbda85c	2584	/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros
mbed_official	532:fe11edbda85c	2585	* @{
mbed_official	532:fe11edbda85c	2586	*/
mbed_official	532:fe11edbda85c	2587	/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
mbed_official	532:fe11edbda85c	2588	* @{
mbed_official	532:fe11edbda85c	2589	*/
mbed_official	532:fe11edbda85c	2590
mbed_official	532:fe11edbda85c	2591	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
mbed_official	532:fe11edbda85c	2592	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000002F))
mbed_official	532:fe11edbda85c	2593	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
mbed_official	532:fe11edbda85c	2594
mbed_official	532:fe11edbda85c	2595	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx) \|\|\
mbed_official	532:fe11edbda85c	2596	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
mbed_official	532:fe11edbda85c	2597	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000003))
mbed_official	532:fe11edbda85c	2598	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
mbed_official	532:fe11edbda85c	2599
mbed_official	532:fe11edbda85c	2600	#if defined(STM32F446xx)
mbed_official	532:fe11edbda85c	2601	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x000007FF))
mbed_official	532:fe11edbda85c	2602	#endif /* STM32F446xx */
mbed_official	532:fe11edbda85c	2603
mbed_official	532:fe11edbda85c	2604	#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
mbed_official	532:fe11edbda85c	2605	#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
mbed_official	532:fe11edbda85c	2606
mbed_official	532:fe11edbda85c	2607
mbed_official	532:fe11edbda85c	2608	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F446xx)
mbed_official	532:fe11edbda85c	2609	#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
mbed_official	532:fe11edbda85c	2610
mbed_official	532:fe11edbda85c	2611	#define IS_RCC_PLLSAIN_VALUE(VALUE) ((49 <= (VALUE)) && ((VALUE) <= 432))
mbed_official	532:fe11edbda85c	2612
mbed_official	532:fe11edbda85c	2613	#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
mbed_official	532:fe11edbda85c	2614
mbed_official	532:fe11edbda85c	2615	#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
mbed_official	532:fe11edbda85c	2616
mbed_official	532:fe11edbda85c	2617	#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
mbed_official	532:fe11edbda85c	2618
mbed_official	532:fe11edbda85c	2619	#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
mbed_official	532:fe11edbda85c	2620
mbed_official	532:fe11edbda85c	2621	#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) \|\|\
mbed_official	532:fe11edbda85c	2622	((VALUE) == RCC_PLLSAIDIVR_4) \|\|\
mbed_official	532:fe11edbda85c	2623	((VALUE) == RCC_PLLSAIDIVR_8) \|\|\
mbed_official	532:fe11edbda85c	2624	((VALUE) == RCC_PLLSAIDIVR_16))
mbed_official	532:fe11edbda85c	2625	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
mbed_official	532:fe11edbda85c	2626
mbed_official	532:fe11edbda85c	2627	#if defined(STM32F446xx) \|\| defined(STM32F411xE)
mbed_official	532:fe11edbda85c	2628	#define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63)
mbed_official	532:fe11edbda85c	2629
mbed_official	532:fe11edbda85c	2630	#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) \|\|\
mbed_official	532:fe11edbda85c	2631	((MODE) == RCC_LSE_HIGHDRIVE_MODE))
mbed_official	532:fe11edbda85c	2632	#endif /* STM32F446xx \|\| STM32F411xE */
mbed_official	532:fe11edbda85c	2633
mbed_official	532:fe11edbda85c	2634	#if defined(STM32F446xx)
mbed_official	532:fe11edbda85c	2635	#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
mbed_official	235:685d5f11838f	2636
mbed_official	532:fe11edbda85c	2637	#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) \|\|\
mbed_official	532:fe11edbda85c	2638	((VALUE) == RCC_PLLI2SP_DIV4) \|\|\
mbed_official	532:fe11edbda85c	2639	((VALUE) == RCC_PLLI2SP_DIV6) \|\|\
mbed_official	532:fe11edbda85c	2640	((VALUE) == RCC_PLLI2SP_DIV8))
mbed_official	532:fe11edbda85c	2641
mbed_official	532:fe11edbda85c	2642	#define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63)
mbed_official	532:fe11edbda85c	2643
mbed_official	532:fe11edbda85c	2644	#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) \|\|\
mbed_official	532:fe11edbda85c	2645	((VALUE) == RCC_PLLSAIP_DIV4) \|\|\
mbed_official	532:fe11edbda85c	2646	((VALUE) == RCC_PLLSAIP_DIV6) \|\|\
mbed_official	532:fe11edbda85c	2647	((VALUE) == RCC_PLLSAIP_DIV8))
mbed_official	532:fe11edbda85c	2648
mbed_official	532:fe11edbda85c	2649	#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) \|\|\
mbed_official	532:fe11edbda85c	2650	((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) \|\|\
mbed_official	532:fe11edbda85c	2651	((SOURCE) == RCC_SAI1CLKSOURCE_PLLR) \|\|\
mbed_official	532:fe11edbda85c	2652	((SOURCE) == RCC_SAI1CLKSOURCE_EXT))
mbed_official	532:fe11edbda85c	2653
mbed_official	532:fe11edbda85c	2654	#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) \|\|\
mbed_official	532:fe11edbda85c	2655	((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) \|\|\
mbed_official	532:fe11edbda85c	2656	((SOURCE) == RCC_SAI2CLKSOURCE_PLLR) \|\|\
mbed_official	532:fe11edbda85c	2657	((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))
mbed_official	532:fe11edbda85c	2658
mbed_official	532:fe11edbda85c	2659	#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) \|\|\
mbed_official	532:fe11edbda85c	2660	((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) \|\|\
mbed_official	532:fe11edbda85c	2661	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) \|\|\
mbed_official	532:fe11edbda85c	2662	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
mbed_official	532:fe11edbda85c	2663
mbed_official	532:fe11edbda85c	2664	#define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) \|\|\
mbed_official	532:fe11edbda85c	2665	((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) \|\|\
mbed_official	532:fe11edbda85c	2666	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) \|\|\
mbed_official	532:fe11edbda85c	2667	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
mbed_official	532:fe11edbda85c	2668
mbed_official	532:fe11edbda85c	2669	#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_APB) \|\|\
mbed_official	532:fe11edbda85c	2670	((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) \|\|\
mbed_official	532:fe11edbda85c	2671	((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
mbed_official	532:fe11edbda85c	2672
mbed_official	532:fe11edbda85c	2673	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) \|\|\
mbed_official	532:fe11edbda85c	2674	((SOURCE) == RCC_CECCLKSOURCE_LSE))
mbed_official	532:fe11edbda85c	2675
mbed_official	532:fe11edbda85c	2676	#define IS_RCC_CK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CK48CLKSOURCE_PLLQ) \|\|\
mbed_official	532:fe11edbda85c	2677	((SOURCE) == RCC_CK48CLKSOURCE_PLLSAIP))
mbed_official	532:fe11edbda85c	2678
mbed_official	532:fe11edbda85c	2679	#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CK48) \|\|\
mbed_official	532:fe11edbda85c	2680	((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
mbed_official	532:fe11edbda85c	2681
mbed_official	532:fe11edbda85c	2682	#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE) (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLR) \|\|\
mbed_official	532:fe11edbda85c	2683	((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
mbed_official	532:fe11edbda85c	2684	#endif /* STM32F446xx */
mbed_official	532:fe11edbda85c	2685
mbed_official	532:fe11edbda85c	2686	/**
mbed_official	532:fe11edbda85c	2687	* @}
mbed_official	532:fe11edbda85c	2688	*/
mbed_official	532:fe11edbda85c	2689
mbed_official	532:fe11edbda85c	2690	/**
mbed_official	532:fe11edbda85c	2691	* @}
mbed_official	532:fe11edbda85c	2692	*/
mbed_official	532:fe11edbda85c	2693
mbed_official	532:fe11edbda85c	2694	/**
mbed_official	532:fe11edbda85c	2695	* @}
mbed_official	532:fe11edbda85c	2696	*/
mbed_official	532:fe11edbda85c	2697
mbed_official	532:fe11edbda85c	2698	/**
mbed_official	532:fe11edbda85c	2699	* @}
mbed_official	532:fe11edbda85c	2700	*/
mbed_official	235:685d5f11838f	2701	#ifdef __cplusplus
mbed_official	235:685d5f11838f	2702	}
mbed_official	235:685d5f11838f	2703	#endif
mbed_official	235:685d5f11838f	2704
mbed_official	235:685d5f11838f	2705	#endif /* __STM32F4xx_HAL_RCC_EX_H */
mbed_official	235:685d5f11838f	2706
mbed_official	235:685d5f11838f	2707	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	27 Oct 2015
Imports:	0
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Commits:	637
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targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc_ex.h@532:fe11edbda85c, 2015-04-30 (annotated)

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