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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F411RE/stm32f4xx_hal_rcc_ex.h@235:685d5f11838f, 2014-06-23 (annotated)
- Committer:
- mbed_official
- Date:
- Mon Jun 23 14:00:09 2014 +0100
- Revision:
- 235:685d5f11838f
Synchronized with git revision 9728c76667962b289ee9c4c687ef9f115db48cd3
Full URL: https://github.com/mbedmicro/mbed/commit/9728c76667962b289ee9c4c687ef9f115db48cd3/
[NUCLEO_F411RE] Add all target files
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 235:685d5f11838f | 1 | /** |
| mbed_official | 235:685d5f11838f | 2 | ****************************************************************************** |
| mbed_official | 235:685d5f11838f | 3 | * @file stm32f4xx_hal_rcc_ex.h |
| mbed_official | 235:685d5f11838f | 4 | * @author MCD Application Team |
| mbed_official | 235:685d5f11838f | 5 | * @version V1.1.0 |
| mbed_official | 235:685d5f11838f | 6 | * @date 19-June-2014 |
| mbed_official | 235:685d5f11838f | 7 | * @brief Header file of RCC HAL Extension module. |
| mbed_official | 235:685d5f11838f | 8 | ****************************************************************************** |
| mbed_official | 235:685d5f11838f | 9 | * @attention |
| mbed_official | 235:685d5f11838f | 10 | * |
| mbed_official | 235:685d5f11838f | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| mbed_official | 235:685d5f11838f | 12 | * |
| mbed_official | 235:685d5f11838f | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 235:685d5f11838f | 14 | * are permitted provided that the following conditions are met: |
| mbed_official | 235:685d5f11838f | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 235:685d5f11838f | 16 | * this list of conditions and the following disclaimer. |
| mbed_official | 235:685d5f11838f | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 235:685d5f11838f | 18 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 235:685d5f11838f | 19 | * and/or other materials provided with the distribution. |
| mbed_official | 235:685d5f11838f | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 235:685d5f11838f | 21 | * may be used to endorse or promote products derived from this software |
| mbed_official | 235:685d5f11838f | 22 | * without specific prior written permission. |
| mbed_official | 235:685d5f11838f | 23 | * |
| mbed_official | 235:685d5f11838f | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 235:685d5f11838f | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 235:685d5f11838f | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 235:685d5f11838f | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 235:685d5f11838f | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 235:685d5f11838f | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 235:685d5f11838f | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 235:685d5f11838f | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 235:685d5f11838f | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 235:685d5f11838f | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 235:685d5f11838f | 34 | * |
| mbed_official | 235:685d5f11838f | 35 | ****************************************************************************** |
| mbed_official | 235:685d5f11838f | 36 | */ |
| mbed_official | 235:685d5f11838f | 37 | |
| mbed_official | 235:685d5f11838f | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 39 | #ifndef __STM32F4xx_HAL_RCC_EX_H |
| mbed_official | 235:685d5f11838f | 40 | #define __STM32F4xx_HAL_RCC_EX_H |
| mbed_official | 235:685d5f11838f | 41 | |
| mbed_official | 235:685d5f11838f | 42 | #ifdef __cplusplus |
| mbed_official | 235:685d5f11838f | 43 | extern "C" { |
| mbed_official | 235:685d5f11838f | 44 | #endif |
| mbed_official | 235:685d5f11838f | 45 | |
| mbed_official | 235:685d5f11838f | 46 | /* Includes ------------------------------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 47 | #include "stm32f4xx_hal_def.h" |
| mbed_official | 235:685d5f11838f | 48 | |
| mbed_official | 235:685d5f11838f | 49 | /** @addtogroup STM32F4xx_HAL_Driver |
| mbed_official | 235:685d5f11838f | 50 | * @{ |
| mbed_official | 235:685d5f11838f | 51 | */ |
| mbed_official | 235:685d5f11838f | 52 | |
| mbed_official | 235:685d5f11838f | 53 | /** @addtogroup RCCEx |
| mbed_official | 235:685d5f11838f | 54 | * @{ |
| mbed_official | 235:685d5f11838f | 55 | */ |
| mbed_official | 235:685d5f11838f | 56 | |
| mbed_official | 235:685d5f11838f | 57 | /* Exported types ------------------------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 58 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) |
| mbed_official | 235:685d5f11838f | 59 | /** |
| mbed_official | 235:685d5f11838f | 60 | * @brief PLLI2S Clock structure definition |
| mbed_official | 235:685d5f11838f | 61 | */ |
| mbed_official | 235:685d5f11838f | 62 | typedef struct |
| mbed_official | 235:685d5f11838f | 63 | { |
| mbed_official | 235:685d5f11838f | 64 | uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. |
| mbed_official | 235:685d5f11838f | 65 | This parameter must be a number between Min_Data = 192 and Max_Data = 432. |
| mbed_official | 235:685d5f11838f | 66 | This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ |
| mbed_official | 235:685d5f11838f | 67 | |
| mbed_official | 235:685d5f11838f | 68 | uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. |
| mbed_official | 235:685d5f11838f | 69 | This parameter must be a number between Min_Data = 2 and Max_Data = 7. |
| mbed_official | 235:685d5f11838f | 70 | This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ |
| mbed_official | 235:685d5f11838f | 71 | |
| mbed_official | 235:685d5f11838f | 72 | uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock. |
| mbed_official | 235:685d5f11838f | 73 | This parameter must be a number between Min_Data = 2 and Max_Data = 15. |
| mbed_official | 235:685d5f11838f | 74 | This parameter will be used only when PLLI2S is selected as Clock Source SAI */ |
| mbed_official | 235:685d5f11838f | 75 | }RCC_PLLI2SInitTypeDef; |
| mbed_official | 235:685d5f11838f | 76 | |
| mbed_official | 235:685d5f11838f | 77 | /** |
| mbed_official | 235:685d5f11838f | 78 | * @brief PLLSAI Clock structure definition |
| mbed_official | 235:685d5f11838f | 79 | */ |
| mbed_official | 235:685d5f11838f | 80 | typedef struct |
| mbed_official | 235:685d5f11838f | 81 | { |
| mbed_official | 235:685d5f11838f | 82 | uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. |
| mbed_official | 235:685d5f11838f | 83 | This parameter must be a number between Min_Data = 192 and Max_Data = 432. |
| mbed_official | 235:685d5f11838f | 84 | This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ |
| mbed_official | 235:685d5f11838f | 85 | |
| mbed_official | 235:685d5f11838f | 86 | uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock. |
| mbed_official | 235:685d5f11838f | 87 | This parameter must be a number between Min_Data = 2 and Max_Data = 15. |
| mbed_official | 235:685d5f11838f | 88 | This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ |
| mbed_official | 235:685d5f11838f | 89 | |
| mbed_official | 235:685d5f11838f | 90 | uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock |
| mbed_official | 235:685d5f11838f | 91 | This parameter must be a number between Min_Data = 2 and Max_Data = 7. |
| mbed_official | 235:685d5f11838f | 92 | This parameter will be used only when PLLSAI is selected as Clock Source LTDC */ |
| mbed_official | 235:685d5f11838f | 93 | |
| mbed_official | 235:685d5f11838f | 94 | }RCC_PLLSAIInitTypeDef; |
| mbed_official | 235:685d5f11838f | 95 | /** |
| mbed_official | 235:685d5f11838f | 96 | * @brief RCC extended clocks structure definition |
| mbed_official | 235:685d5f11838f | 97 | */ |
| mbed_official | 235:685d5f11838f | 98 | typedef struct |
| mbed_official | 235:685d5f11838f | 99 | { |
| mbed_official | 235:685d5f11838f | 100 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
| mbed_official | 235:685d5f11838f | 101 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
| mbed_official | 235:685d5f11838f | 102 | |
| mbed_official | 235:685d5f11838f | 103 | RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. |
| mbed_official | 235:685d5f11838f | 104 | This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ |
| mbed_official | 235:685d5f11838f | 105 | |
| mbed_official | 235:685d5f11838f | 106 | RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters. |
| mbed_official | 235:685d5f11838f | 107 | This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */ |
| mbed_official | 235:685d5f11838f | 108 | |
| mbed_official | 235:685d5f11838f | 109 | uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. |
| mbed_official | 235:685d5f11838f | 110 | This parameter must be a number between Min_Data = 1 and Max_Data = 32 |
| mbed_official | 235:685d5f11838f | 111 | This parameter will be used only when PLLI2S is selected as Clock Source SAI */ |
| mbed_official | 235:685d5f11838f | 112 | |
| mbed_official | 235:685d5f11838f | 113 | uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. |
| mbed_official | 235:685d5f11838f | 114 | This parameter must be a number between Min_Data = 1 and Max_Data = 32 |
| mbed_official | 235:685d5f11838f | 115 | This parameter will be used only when PLLSAI is selected as Clock Source SAI */ |
| mbed_official | 235:685d5f11838f | 116 | |
| mbed_official | 235:685d5f11838f | 117 | uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock. |
| mbed_official | 235:685d5f11838f | 118 | This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */ |
| mbed_official | 235:685d5f11838f | 119 | |
| mbed_official | 235:685d5f11838f | 120 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection. |
| mbed_official | 235:685d5f11838f | 121 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
| mbed_official | 235:685d5f11838f | 122 | |
| mbed_official | 235:685d5f11838f | 123 | uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection. |
| mbed_official | 235:685d5f11838f | 124 | This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ |
| mbed_official | 235:685d5f11838f | 125 | |
| mbed_official | 235:685d5f11838f | 126 | }RCC_PeriphCLKInitTypeDef; |
| mbed_official | 235:685d5f11838f | 127 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
| mbed_official | 235:685d5f11838f | 128 | |
| mbed_official | 235:685d5f11838f | 129 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\ |
| mbed_official | 235:685d5f11838f | 130 | defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) |
| mbed_official | 235:685d5f11838f | 131 | /** |
| mbed_official | 235:685d5f11838f | 132 | * @brief PLLI2S Clock structure definition |
| mbed_official | 235:685d5f11838f | 133 | */ |
| mbed_official | 235:685d5f11838f | 134 | typedef struct |
| mbed_official | 235:685d5f11838f | 135 | { |
| mbed_official | 235:685d5f11838f | 136 | #if defined(STM32F411xE) |
| mbed_official | 235:685d5f11838f | 137 | uint32_t PLLI2SM; /*!< PLLM: Division factor for PLLI2S VCO input clock. |
| mbed_official | 235:685d5f11838f | 138 | This parameter must be a number between Min_Data = 2 and Max_Data = 62 */ |
| mbed_official | 235:685d5f11838f | 139 | #endif /* STM32F411xE */ |
| mbed_official | 235:685d5f11838f | 140 | |
| mbed_official | 235:685d5f11838f | 141 | uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. |
| mbed_official | 235:685d5f11838f | 142 | This parameter must be a number between Min_Data = 192 and Max_Data = 432 |
| mbed_official | 235:685d5f11838f | 143 | This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ |
| mbed_official | 235:685d5f11838f | 144 | |
| mbed_official | 235:685d5f11838f | 145 | uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. |
| mbed_official | 235:685d5f11838f | 146 | This parameter must be a number between Min_Data = 2 and Max_Data = 7. |
| mbed_official | 235:685d5f11838f | 147 | This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ |
| mbed_official | 235:685d5f11838f | 148 | |
| mbed_official | 235:685d5f11838f | 149 | }RCC_PLLI2SInitTypeDef; |
| mbed_official | 235:685d5f11838f | 150 | |
| mbed_official | 235:685d5f11838f | 151 | |
| mbed_official | 235:685d5f11838f | 152 | /** |
| mbed_official | 235:685d5f11838f | 153 | * @brief RCC extended clocks structure definition |
| mbed_official | 235:685d5f11838f | 154 | */ |
| mbed_official | 235:685d5f11838f | 155 | typedef struct |
| mbed_official | 235:685d5f11838f | 156 | { |
| mbed_official | 235:685d5f11838f | 157 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
| mbed_official | 235:685d5f11838f | 158 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
| mbed_official | 235:685d5f11838f | 159 | |
| mbed_official | 235:685d5f11838f | 160 | RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. |
| mbed_official | 235:685d5f11838f | 161 | This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ |
| mbed_official | 235:685d5f11838f | 162 | |
| mbed_official | 235:685d5f11838f | 163 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection. |
| mbed_official | 235:685d5f11838f | 164 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
| mbed_official | 235:685d5f11838f | 165 | |
| mbed_official | 235:685d5f11838f | 166 | }RCC_PeriphCLKInitTypeDef; |
| mbed_official | 235:685d5f11838f | 167 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ |
| mbed_official | 235:685d5f11838f | 168 | /* Exported constants --------------------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 169 | /** @defgroup RCCEx_Exported_Constants |
| mbed_official | 235:685d5f11838f | 170 | * @{ |
| mbed_official | 235:685d5f11838f | 171 | */ |
| mbed_official | 235:685d5f11838f | 172 | |
| mbed_official | 235:685d5f11838f | 173 | /** @defgroup RCCEx_Periph_Clock_Selection |
| mbed_official | 235:685d5f11838f | 174 | * @{ |
| mbed_official | 235:685d5f11838f | 175 | */ |
| mbed_official | 235:685d5f11838f | 176 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) |
| mbed_official | 235:685d5f11838f | 177 | #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001) |
| mbed_official | 235:685d5f11838f | 178 | #define RCC_PERIPHCLK_SAI_PLLI2S ((uint32_t)0x00000002) |
| mbed_official | 235:685d5f11838f | 179 | #define RCC_PERIPHCLK_SAI_PLLSAI ((uint32_t)0x00000004) |
| mbed_official | 235:685d5f11838f | 180 | #define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008) |
| mbed_official | 235:685d5f11838f | 181 | #define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010) |
| mbed_official | 235:685d5f11838f | 182 | #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020) |
| mbed_official | 235:685d5f11838f | 183 | #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000002F)) |
| mbed_official | 235:685d5f11838f | 184 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
| mbed_official | 235:685d5f11838f | 185 | |
| mbed_official | 235:685d5f11838f | 186 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\ |
| mbed_official | 235:685d5f11838f | 187 | defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) |
| mbed_official | 235:685d5f11838f | 188 | #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001) |
| mbed_official | 235:685d5f11838f | 189 | #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000002) |
| mbed_official | 235:685d5f11838f | 190 | #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000003)) |
| mbed_official | 235:685d5f11838f | 191 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ |
| mbed_official | 235:685d5f11838f | 192 | |
| mbed_official | 235:685d5f11838f | 193 | /** |
| mbed_official | 235:685d5f11838f | 194 | * @} |
| mbed_official | 235:685d5f11838f | 195 | */ |
| mbed_official | 235:685d5f11838f | 196 | |
| mbed_official | 235:685d5f11838f | 197 | /** @defgroup RCCEx_BitAddress_AliasRegion |
| mbed_official | 235:685d5f11838f | 198 | * @brief RCC registers bit address in the alias region |
| mbed_official | 235:685d5f11838f | 199 | * @{ |
| mbed_official | 235:685d5f11838f | 200 | */ |
| mbed_official | 235:685d5f11838f | 201 | /* --- CR Register ---*/ |
| mbed_official | 235:685d5f11838f | 202 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) |
| mbed_official | 235:685d5f11838f | 203 | /* Alias word address of PLLSAION bit */ |
| mbed_official | 235:685d5f11838f | 204 | #define PLLSAION_BitNumber 0x1C |
| mbed_official | 235:685d5f11838f | 205 | #define CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLSAION_BitNumber * 4)) |
| mbed_official | 235:685d5f11838f | 206 | |
| mbed_official | 235:685d5f11838f | 207 | /* --- DCKCFGR Register ---*/ |
| mbed_official | 235:685d5f11838f | 208 | /* Alias word address of TIMPRE bit */ |
| mbed_official | 235:685d5f11838f | 209 | #define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8C) |
| mbed_official | 235:685d5f11838f | 210 | #define TIMPRE_BitNumber 0x18 |
| mbed_official | 235:685d5f11838f | 211 | #define DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4)) |
| mbed_official | 235:685d5f11838f | 212 | /** |
| mbed_official | 235:685d5f11838f | 213 | * @} |
| mbed_official | 235:685d5f11838f | 214 | */ |
| mbed_official | 235:685d5f11838f | 215 | |
| mbed_official | 235:685d5f11838f | 216 | /** @defgroup RCCEx_PLLI2S_Clock_Source |
| mbed_official | 235:685d5f11838f | 217 | * @{ |
| mbed_official | 235:685d5f11838f | 218 | */ |
| mbed_official | 235:685d5f11838f | 219 | #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) |
| mbed_official | 235:685d5f11838f | 220 | /** |
| mbed_official | 235:685d5f11838f | 221 | * @} |
| mbed_official | 235:685d5f11838f | 222 | */ |
| mbed_official | 235:685d5f11838f | 223 | |
| mbed_official | 235:685d5f11838f | 224 | /** @defgroup RCCEx_PLLSAI_Clock_Source |
| mbed_official | 235:685d5f11838f | 225 | * @{ |
| mbed_official | 235:685d5f11838f | 226 | */ |
| mbed_official | 235:685d5f11838f | 227 | #define IS_RCC_PLLSAIN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) |
| mbed_official | 235:685d5f11838f | 228 | #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) |
| mbed_official | 235:685d5f11838f | 229 | #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) |
| mbed_official | 235:685d5f11838f | 230 | /** |
| mbed_official | 235:685d5f11838f | 231 | * @} |
| mbed_official | 235:685d5f11838f | 232 | */ |
| mbed_official | 235:685d5f11838f | 233 | |
| mbed_official | 235:685d5f11838f | 234 | /** @defgroup RCCEx_PLLSAI_DIVQ |
| mbed_official | 235:685d5f11838f | 235 | * @{ |
| mbed_official | 235:685d5f11838f | 236 | */ |
| mbed_official | 235:685d5f11838f | 237 | #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) |
| mbed_official | 235:685d5f11838f | 238 | /** |
| mbed_official | 235:685d5f11838f | 239 | * @} |
| mbed_official | 235:685d5f11838f | 240 | */ |
| mbed_official | 235:685d5f11838f | 241 | |
| mbed_official | 235:685d5f11838f | 242 | /** @defgroup RCCEx_PLLI2S_DIVQ |
| mbed_official | 235:685d5f11838f | 243 | * @{ |
| mbed_official | 235:685d5f11838f | 244 | */ |
| mbed_official | 235:685d5f11838f | 245 | #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) |
| mbed_official | 235:685d5f11838f | 246 | |
| mbed_official | 235:685d5f11838f | 247 | /** |
| mbed_official | 235:685d5f11838f | 248 | * @} |
| mbed_official | 235:685d5f11838f | 249 | */ |
| mbed_official | 235:685d5f11838f | 250 | |
| mbed_official | 235:685d5f11838f | 251 | /** @defgroup RCCEx_PLLSAI_DIVR |
| mbed_official | 235:685d5f11838f | 252 | * @{ |
| mbed_official | 235:685d5f11838f | 253 | */ |
| mbed_official | 235:685d5f11838f | 254 | #define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000) |
| mbed_official | 235:685d5f11838f | 255 | #define RCC_PLLSAIDIVR_4 ((uint32_t)0x00010000) |
| mbed_official | 235:685d5f11838f | 256 | #define RCC_PLLSAIDIVR_8 ((uint32_t)0x00020000) |
| mbed_official | 235:685d5f11838f | 257 | #define RCC_PLLSAIDIVR_16 ((uint32_t)0x00030000) |
| mbed_official | 235:685d5f11838f | 258 | #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\ |
| mbed_official | 235:685d5f11838f | 259 | ((VALUE) == RCC_PLLSAIDIVR_4) ||\ |
| mbed_official | 235:685d5f11838f | 260 | ((VALUE) == RCC_PLLSAIDIVR_8) ||\ |
| mbed_official | 235:685d5f11838f | 261 | ((VALUE) == RCC_PLLSAIDIVR_16)) |
| mbed_official | 235:685d5f11838f | 262 | |
| mbed_official | 235:685d5f11838f | 263 | /** |
| mbed_official | 235:685d5f11838f | 264 | * @} |
| mbed_official | 235:685d5f11838f | 265 | */ |
| mbed_official | 235:685d5f11838f | 266 | |
| mbed_official | 235:685d5f11838f | 267 | /** @defgroup RCCEx_SAI_BlockA_Clock_Source |
| mbed_official | 235:685d5f11838f | 268 | * @{ |
| mbed_official | 235:685d5f11838f | 269 | */ |
| mbed_official | 235:685d5f11838f | 270 | #define RCC_SAIACLKSOURCE_PLLSAI ((uint32_t)0x00000000) |
| mbed_official | 235:685d5f11838f | 271 | #define RCC_SAIACLKSOURCE_PLLI2S ((uint32_t)0x00100000) |
| mbed_official | 235:685d5f11838f | 272 | #define RCC_SAIACLKSOURCE_EXT ((uint32_t)0x00200000) |
| mbed_official | 235:685d5f11838f | 273 | /** |
| mbed_official | 235:685d5f11838f | 274 | * @} |
| mbed_official | 235:685d5f11838f | 275 | */ |
| mbed_official | 235:685d5f11838f | 276 | |
| mbed_official | 235:685d5f11838f | 277 | /** @defgroup RCCEx_SAI_BlockB_Clock_Source |
| mbed_official | 235:685d5f11838f | 278 | * @{ |
| mbed_official | 235:685d5f11838f | 279 | */ |
| mbed_official | 235:685d5f11838f | 280 | #define RCC_SAIBCLKSOURCE_PLLSAI ((uint32_t)0x00000000) |
| mbed_official | 235:685d5f11838f | 281 | #define RCC_SAIBCLKSOURCE_PLLI2S ((uint32_t)0x00400000) |
| mbed_official | 235:685d5f11838f | 282 | #define RCC_SAIBCLKSOURCE_EXT ((uint32_t)0x00800000) |
| mbed_official | 235:685d5f11838f | 283 | /** |
| mbed_official | 235:685d5f11838f | 284 | * @} |
| mbed_official | 235:685d5f11838f | 285 | */ |
| mbed_official | 235:685d5f11838f | 286 | |
| mbed_official | 235:685d5f11838f | 287 | /** @defgroup RCCEx_TIM_PRescaler_Selection |
| mbed_official | 235:685d5f11838f | 288 | * @{ |
| mbed_official | 235:685d5f11838f | 289 | */ |
| mbed_official | 235:685d5f11838f | 290 | #define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00) |
| mbed_official | 235:685d5f11838f | 291 | #define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01) |
| mbed_official | 235:685d5f11838f | 292 | /** |
| mbed_official | 235:685d5f11838f | 293 | * @} |
| mbed_official | 235:685d5f11838f | 294 | */ |
| mbed_official | 235:685d5f11838f | 295 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
| mbed_official | 235:685d5f11838f | 296 | |
| mbed_official | 235:685d5f11838f | 297 | #if defined(STM32F411xE) |
| mbed_official | 235:685d5f11838f | 298 | /** @defgroup RCCEx_PLLI2S_PLLI2SM |
| mbed_official | 235:685d5f11838f | 299 | * @{ |
| mbed_official | 235:685d5f11838f | 300 | */ |
| mbed_official | 235:685d5f11838f | 301 | #define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63) |
| mbed_official | 235:685d5f11838f | 302 | /** |
| mbed_official | 235:685d5f11838f | 303 | * @} |
| mbed_official | 235:685d5f11838f | 304 | */ |
| mbed_official | 235:685d5f11838f | 305 | |
| mbed_official | 235:685d5f11838f | 306 | /** @defgroup RCCEx_LSE_Dual_Mode_Selection |
| mbed_official | 235:685d5f11838f | 307 | * @{ |
| mbed_official | 235:685d5f11838f | 308 | */ |
| mbed_official | 235:685d5f11838f | 309 | #define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00) |
| mbed_official | 235:685d5f11838f | 310 | #define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01) |
| mbed_official | 235:685d5f11838f | 311 | #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\ |
| mbed_official | 235:685d5f11838f | 312 | ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) |
| mbed_official | 235:685d5f11838f | 313 | /** |
| mbed_official | 235:685d5f11838f | 314 | * @} |
| mbed_official | 235:685d5f11838f | 315 | */ |
| mbed_official | 235:685d5f11838f | 316 | |
| mbed_official | 235:685d5f11838f | 317 | #endif /* STM32F411xE */ |
| mbed_official | 235:685d5f11838f | 318 | /** |
| mbed_official | 235:685d5f11838f | 319 | * @} |
| mbed_official | 235:685d5f11838f | 320 | */ |
| mbed_official | 235:685d5f11838f | 321 | |
| mbed_official | 235:685d5f11838f | 322 | /* Exported macro ------------------------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 323 | |
| mbed_official | 235:685d5f11838f | 324 | /*----------------------------------- STM32F42xxx/STM32F43xxx----------------------------------*/ |
| mbed_official | 235:685d5f11838f | 325 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) |
| mbed_official | 235:685d5f11838f | 326 | /** @brief Enables or disables the AHB1 peripheral clock. |
| mbed_official | 235:685d5f11838f | 327 | * @note After reset, the peripheral clock (used for registers read/write access) |
| mbed_official | 235:685d5f11838f | 328 | * is disabled and the application software has to enable this clock before |
| mbed_official | 235:685d5f11838f | 329 | * using it. |
| mbed_official | 235:685d5f11838f | 330 | */ |
| mbed_official | 235:685d5f11838f | 331 | #define __GPIOI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOIEN)) |
| mbed_official | 235:685d5f11838f | 332 | #define __GPIOF_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOFEN)) |
| mbed_official | 235:685d5f11838f | 333 | #define __GPIOG_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOGEN)) |
| mbed_official | 235:685d5f11838f | 334 | #define __GPIOJ_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOJEN)) |
| mbed_official | 235:685d5f11838f | 335 | #define __GPIOK_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOKEN)) |
| mbed_official | 235:685d5f11838f | 336 | #define __DMA2D_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_DMA2DEN)) |
| mbed_official | 235:685d5f11838f | 337 | #define __ETHMAC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACEN)) |
| mbed_official | 235:685d5f11838f | 338 | #define __ETHMACTX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACTXEN)) |
| mbed_official | 235:685d5f11838f | 339 | #define __ETHMACRX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACRXEN)) |
| mbed_official | 235:685d5f11838f | 340 | #define __ETHMACPTP_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACPTPEN)) |
| mbed_official | 235:685d5f11838f | 341 | #define __USB_OTG_HS_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSEN)) |
| mbed_official | 235:685d5f11838f | 342 | #define __USB_OTG_HS_ULPI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSULPIEN)) |
| mbed_official | 235:685d5f11838f | 343 | |
| mbed_official | 235:685d5f11838f | 344 | #define __GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) |
| mbed_official | 235:685d5f11838f | 345 | #define __GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) |
| mbed_official | 235:685d5f11838f | 346 | #define __GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) |
| mbed_official | 235:685d5f11838f | 347 | #define __GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN)) |
| mbed_official | 235:685d5f11838f | 348 | #define __GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN)) |
| mbed_official | 235:685d5f11838f | 349 | #define __DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN)) |
| mbed_official | 235:685d5f11838f | 350 | #define __ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN)) |
| mbed_official | 235:685d5f11838f | 351 | #define __ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN)) |
| mbed_official | 235:685d5f11838f | 352 | #define __ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN)) |
| mbed_official | 235:685d5f11838f | 353 | #define __ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN)) |
| mbed_official | 235:685d5f11838f | 354 | #define __USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) |
| mbed_official | 235:685d5f11838f | 355 | #define __USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) |
| mbed_official | 235:685d5f11838f | 356 | |
| mbed_official | 235:685d5f11838f | 357 | /** |
| mbed_official | 235:685d5f11838f | 358 | * @brief Enable ETHERNET clock. |
| mbed_official | 235:685d5f11838f | 359 | */ |
| mbed_official | 235:685d5f11838f | 360 | #define __ETH_CLK_ENABLE() do { \ |
| mbed_official | 235:685d5f11838f | 361 | __ETHMAC_CLK_ENABLE(); \ |
| mbed_official | 235:685d5f11838f | 362 | __ETHMACTX_CLK_ENABLE(); \ |
| mbed_official | 235:685d5f11838f | 363 | __ETHMACRX_CLK_ENABLE(); \ |
| mbed_official | 235:685d5f11838f | 364 | } while(0) |
| mbed_official | 235:685d5f11838f | 365 | /** |
| mbed_official | 235:685d5f11838f | 366 | * @brief Disable ETHERNET clock. |
| mbed_official | 235:685d5f11838f | 367 | */ |
| mbed_official | 235:685d5f11838f | 368 | #define __ETH_CLK_DISABLE() do { \ |
| mbed_official | 235:685d5f11838f | 369 | __ETHMACTX_CLK_DISABLE(); \ |
| mbed_official | 235:685d5f11838f | 370 | __ETHMACRX_CLK_DISABLE(); \ |
| mbed_official | 235:685d5f11838f | 371 | __ETHMAC_CLK_DISABLE(); \ |
| mbed_official | 235:685d5f11838f | 372 | } while(0) |
| mbed_official | 235:685d5f11838f | 373 | |
| mbed_official | 235:685d5f11838f | 374 | /** @brief Enable or disable the AHB2 peripheral clock. |
| mbed_official | 235:685d5f11838f | 375 | * @note After reset, the peripheral clock (used for registers read/write access) |
| mbed_official | 235:685d5f11838f | 376 | * is disabled and the application software has to enable this clock before |
| mbed_official | 235:685d5f11838f | 377 | * using it. |
| mbed_official | 235:685d5f11838f | 378 | */ |
| mbed_official | 235:685d5f11838f | 379 | |
| mbed_official | 235:685d5f11838f | 380 | #define __DCMI_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_DCMIEN)) |
| mbed_official | 235:685d5f11838f | 381 | #define __DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) |
| mbed_official | 235:685d5f11838f | 382 | |
| mbed_official | 235:685d5f11838f | 383 | #if defined(STM32F437xx)|| defined(STM32F439xx) |
| mbed_official | 235:685d5f11838f | 384 | #define __CRYP_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_CRYPEN)) |
| mbed_official | 235:685d5f11838f | 385 | #define __HASH_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_HASHEN)) |
| mbed_official | 235:685d5f11838f | 386 | |
| mbed_official | 235:685d5f11838f | 387 | #define __CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) |
| mbed_official | 235:685d5f11838f | 388 | #define __HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) |
| mbed_official | 235:685d5f11838f | 389 | #endif /* STM32F437xx || STM32F439xx */ |
| mbed_official | 235:685d5f11838f | 390 | |
| mbed_official | 235:685d5f11838f | 391 | /** @brief Enables or disables the AHB3 peripheral clock. |
| mbed_official | 235:685d5f11838f | 392 | * @note After reset, the peripheral clock (used for registers read/write access) |
| mbed_official | 235:685d5f11838f | 393 | * is disabled and the application software has to enable this clock before |
| mbed_official | 235:685d5f11838f | 394 | * using it. |
| mbed_official | 235:685d5f11838f | 395 | */ |
| mbed_official | 235:685d5f11838f | 396 | #define __FMC_CLK_ENABLE() (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN)) |
| mbed_official | 235:685d5f11838f | 397 | #define __FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN)) |
| mbed_official | 235:685d5f11838f | 398 | |
| mbed_official | 235:685d5f11838f | 399 | /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock. |
| mbed_official | 235:685d5f11838f | 400 | * @note After reset, the peripheral clock (used for registers read/write access) |
| mbed_official | 235:685d5f11838f | 401 | * is disabled and the application software has to enable this clock before |
| mbed_official | 235:685d5f11838f | 402 | * using it. |
| mbed_official | 235:685d5f11838f | 403 | */ |
| mbed_official | 235:685d5f11838f | 404 | #define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN)) |
| mbed_official | 235:685d5f11838f | 405 | #define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN)) |
| mbed_official | 235:685d5f11838f | 406 | #define __TIM12_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM12EN)) |
| mbed_official | 235:685d5f11838f | 407 | #define __TIM13_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM13EN)) |
| mbed_official | 235:685d5f11838f | 408 | #define __TIM14_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN)) |
| mbed_official | 235:685d5f11838f | 409 | #define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN)) |
| mbed_official | 235:685d5f11838f | 410 | #define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN)) |
| mbed_official | 235:685d5f11838f | 411 | #define __UART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART4EN)) |
| mbed_official | 235:685d5f11838f | 412 | #define __UART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART5EN)) |
| mbed_official | 235:685d5f11838f | 413 | #define __CAN1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN1EN)) |
| mbed_official | 235:685d5f11838f | 414 | #define __CAN2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN2EN)) |
| mbed_official | 235:685d5f11838f | 415 | #define __DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN)) |
| mbed_official | 235:685d5f11838f | 416 | #define __UART7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART7EN)) |
| mbed_official | 235:685d5f11838f | 417 | #define __UART8_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART8EN)) |
| mbed_official | 235:685d5f11838f | 418 | |
| mbed_official | 235:685d5f11838f | 419 | #define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) |
| mbed_official | 235:685d5f11838f | 420 | #define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) |
| mbed_official | 235:685d5f11838f | 421 | #define __TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) |
| mbed_official | 235:685d5f11838f | 422 | #define __TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) |
| mbed_official | 235:685d5f11838f | 423 | #define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) |
| mbed_official | 235:685d5f11838f | 424 | #define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) |
| mbed_official | 235:685d5f11838f | 425 | #define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) |
| mbed_official | 235:685d5f11838f | 426 | #define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) |
| mbed_official | 235:685d5f11838f | 427 | #define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) |
| mbed_official | 235:685d5f11838f | 428 | #define __CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) |
| mbed_official | 235:685d5f11838f | 429 | #define __CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) |
| mbed_official | 235:685d5f11838f | 430 | #define __DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) |
| mbed_official | 235:685d5f11838f | 431 | #define __UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) |
| mbed_official | 235:685d5f11838f | 432 | #define __UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) |
| mbed_official | 235:685d5f11838f | 433 | |
| mbed_official | 235:685d5f11838f | 434 | /** @brief Enable or disable the High Speed APB (APB2) peripheral clock. |
| mbed_official | 235:685d5f11838f | 435 | * @note After reset, the peripheral clock (used for registers read/write access) |
| mbed_official | 235:685d5f11838f | 436 | * is disabled and the application software has to enable this clock before |
| mbed_official | 235:685d5f11838f | 437 | * using it. |
| mbed_official | 235:685d5f11838f | 438 | */ |
| mbed_official | 235:685d5f11838f | 439 | #define __TIM8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM8EN)) |
| mbed_official | 235:685d5f11838f | 440 | #define __ADC2_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC2EN)) |
| mbed_official | 235:685d5f11838f | 441 | #define __ADC3_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC3EN)) |
| mbed_official | 235:685d5f11838f | 442 | #define __SPI5_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI5EN)) |
| mbed_official | 235:685d5f11838f | 443 | #define __SPI6_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI6EN)) |
| mbed_official | 235:685d5f11838f | 444 | #define __SAI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SAI1EN)) |
| mbed_official | 235:685d5f11838f | 445 | |
| mbed_official | 235:685d5f11838f | 446 | #define __TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) |
| mbed_official | 235:685d5f11838f | 447 | #define __ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) |
| mbed_official | 235:685d5f11838f | 448 | #define __ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) |
| mbed_official | 235:685d5f11838f | 449 | #define __SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) |
| mbed_official | 235:685d5f11838f | 450 | #define __SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN)) |
| mbed_official | 235:685d5f11838f | 451 | #define __SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) |
| mbed_official | 235:685d5f11838f | 452 | |
| mbed_official | 235:685d5f11838f | 453 | #if defined(STM32F429xx)|| defined(STM32F439xx) |
| mbed_official | 235:685d5f11838f | 454 | #define __LTDC_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_LTDCEN)) |
| mbed_official | 235:685d5f11838f | 455 | |
| mbed_official | 235:685d5f11838f | 456 | #define __LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN)) |
| mbed_official | 235:685d5f11838f | 457 | #endif /* STM32F429xx || STM32F439xx */ |
| mbed_official | 235:685d5f11838f | 458 | |
| mbed_official | 235:685d5f11838f | 459 | /** @brief Force or release AHB1 peripheral reset. |
| mbed_official | 235:685d5f11838f | 460 | */ |
| mbed_official | 235:685d5f11838f | 461 | #define __GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) |
| mbed_official | 235:685d5f11838f | 462 | #define __GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) |
| mbed_official | 235:685d5f11838f | 463 | #define __GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST)) |
| mbed_official | 235:685d5f11838f | 464 | #define __ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) |
| mbed_official | 235:685d5f11838f | 465 | #define __OTGHS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) |
| mbed_official | 235:685d5f11838f | 466 | #define __GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST)) |
| mbed_official | 235:685d5f11838f | 467 | #define __GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST)) |
| mbed_official | 235:685d5f11838f | 468 | #define __DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST)) |
| mbed_official | 235:685d5f11838f | 469 | |
| mbed_official | 235:685d5f11838f | 470 | #define __GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) |
| mbed_official | 235:685d5f11838f | 471 | #define __GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) |
| mbed_official | 235:685d5f11838f | 472 | #define __GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) |
| mbed_official | 235:685d5f11838f | 473 | #define __ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) |
| mbed_official | 235:685d5f11838f | 474 | #define __OTGHS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) |
| mbed_official | 235:685d5f11838f | 475 | #define __GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST)) |
| mbed_official | 235:685d5f11838f | 476 | #define __GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST)) |
| mbed_official | 235:685d5f11838f | 477 | #define __DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST)) |
| mbed_official | 235:685d5f11838f | 478 | |
| mbed_official | 235:685d5f11838f | 479 | /** @brief Force or release AHB2 peripheral reset. |
| mbed_official | 235:685d5f11838f | 480 | */ |
| mbed_official | 235:685d5f11838f | 481 | #define __DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) |
| mbed_official | 235:685d5f11838f | 482 | #define __DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) |
| mbed_official | 235:685d5f11838f | 483 | |
| mbed_official | 235:685d5f11838f | 484 | #if defined(STM32F437xx)|| defined(STM32F439xx) |
| mbed_official | 235:685d5f11838f | 485 | #define __CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) |
| mbed_official | 235:685d5f11838f | 486 | #define __HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) |
| mbed_official | 235:685d5f11838f | 487 | |
| mbed_official | 235:685d5f11838f | 488 | #define __CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) |
| mbed_official | 235:685d5f11838f | 489 | #define __HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) |
| mbed_official | 235:685d5f11838f | 490 | #endif /* STM32F437xx || STM32F439xx */ |
| mbed_official | 235:685d5f11838f | 491 | |
| mbed_official | 235:685d5f11838f | 492 | /** @brief Force or release AHB3 peripheral reset |
| mbed_official | 235:685d5f11838f | 493 | */ |
| mbed_official | 235:685d5f11838f | 494 | #define __FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) |
| mbed_official | 235:685d5f11838f | 495 | #define __FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) |
| mbed_official | 235:685d5f11838f | 496 | |
| mbed_official | 235:685d5f11838f | 497 | /** @brief Force or release APB1 peripheral reset. |
| mbed_official | 235:685d5f11838f | 498 | */ |
| mbed_official | 235:685d5f11838f | 499 | #define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) |
| mbed_official | 235:685d5f11838f | 500 | #define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) |
| mbed_official | 235:685d5f11838f | 501 | #define __TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) |
| mbed_official | 235:685d5f11838f | 502 | #define __TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) |
| mbed_official | 235:685d5f11838f | 503 | #define __TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) |
| mbed_official | 235:685d5f11838f | 504 | #define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) |
| mbed_official | 235:685d5f11838f | 505 | #define __UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) |
| mbed_official | 235:685d5f11838f | 506 | #define __UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) |
| mbed_official | 235:685d5f11838f | 507 | #define __CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) |
| mbed_official | 235:685d5f11838f | 508 | #define __CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) |
| mbed_official | 235:685d5f11838f | 509 | #define __DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) |
| mbed_official | 235:685d5f11838f | 510 | #define __UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST)) |
| mbed_official | 235:685d5f11838f | 511 | #define __UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST)) |
| mbed_official | 235:685d5f11838f | 512 | |
| mbed_official | 235:685d5f11838f | 513 | #define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) |
| mbed_official | 235:685d5f11838f | 514 | #define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) |
| mbed_official | 235:685d5f11838f | 515 | #define __TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) |
| mbed_official | 235:685d5f11838f | 516 | #define __TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) |
| mbed_official | 235:685d5f11838f | 517 | #define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) |
| mbed_official | 235:685d5f11838f | 518 | #define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) |
| mbed_official | 235:685d5f11838f | 519 | #define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) |
| mbed_official | 235:685d5f11838f | 520 | #define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) |
| mbed_official | 235:685d5f11838f | 521 | #define __CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) |
| mbed_official | 235:685d5f11838f | 522 | #define __CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) |
| mbed_official | 235:685d5f11838f | 523 | #define __DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) |
| mbed_official | 235:685d5f11838f | 524 | #define __UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST)) |
| mbed_official | 235:685d5f11838f | 525 | #define __UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST)) |
| mbed_official | 235:685d5f11838f | 526 | |
| mbed_official | 235:685d5f11838f | 527 | /** @brief Force or release APB2 peripheral reset. |
| mbed_official | 235:685d5f11838f | 528 | */ |
| mbed_official | 235:685d5f11838f | 529 | #define __TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) |
| mbed_official | 235:685d5f11838f | 530 | #define __SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) |
| mbed_official | 235:685d5f11838f | 531 | #define __SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST)) |
| mbed_official | 235:685d5f11838f | 532 | #define __SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) |
| mbed_official | 235:685d5f11838f | 533 | |
| mbed_official | 235:685d5f11838f | 534 | #define __TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) |
| mbed_official | 235:685d5f11838f | 535 | #define __SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) |
| mbed_official | 235:685d5f11838f | 536 | #define __SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST)) |
| mbed_official | 235:685d5f11838f | 537 | #define __SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) |
| mbed_official | 235:685d5f11838f | 538 | |
| mbed_official | 235:685d5f11838f | 539 | #if defined(STM32F429xx)|| defined(STM32F439xx) |
| mbed_official | 235:685d5f11838f | 540 | #define __LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST)) |
| mbed_official | 235:685d5f11838f | 541 | #define __LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST)) |
| mbed_official | 235:685d5f11838f | 542 | #endif /* STM32F429xx|| STM32F439xx */ |
| mbed_official | 235:685d5f11838f | 543 | |
| mbed_official | 235:685d5f11838f | 544 | /** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. |
| mbed_official | 235:685d5f11838f | 545 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| mbed_official | 235:685d5f11838f | 546 | * power consumption. |
| mbed_official | 235:685d5f11838f | 547 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| mbed_official | 235:685d5f11838f | 548 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| mbed_official | 235:685d5f11838f | 549 | */ |
| mbed_official | 235:685d5f11838f | 550 | #define __GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) |
| mbed_official | 235:685d5f11838f | 551 | #define __GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) |
| mbed_official | 235:685d5f11838f | 552 | #define __GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN)) |
| mbed_official | 235:685d5f11838f | 553 | #define __SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) |
| mbed_official | 235:685d5f11838f | 554 | #define __ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) |
| mbed_official | 235:685d5f11838f | 555 | #define __ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN)) |
| mbed_official | 235:685d5f11838f | 556 | #define __ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN)) |
| mbed_official | 235:685d5f11838f | 557 | #define __ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN)) |
| mbed_official | 235:685d5f11838f | 558 | #define __OTGHS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) |
| mbed_official | 235:685d5f11838f | 559 | #define __OTGHSULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) |
| mbed_official | 235:685d5f11838f | 560 | #define __GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN)) |
| mbed_official | 235:685d5f11838f | 561 | #define __GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN)) |
| mbed_official | 235:685d5f11838f | 562 | #define __SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN)) |
| mbed_official | 235:685d5f11838f | 563 | #define __DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN)) |
| mbed_official | 235:685d5f11838f | 564 | |
| mbed_official | 235:685d5f11838f | 565 | #define __GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) |
| mbed_official | 235:685d5f11838f | 566 | #define __GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) |
| mbed_official | 235:685d5f11838f | 567 | #define __GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) |
| mbed_official | 235:685d5f11838f | 568 | #define __SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) |
| mbed_official | 235:685d5f11838f | 569 | #define __ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN)) |
| mbed_official | 235:685d5f11838f | 570 | #define __ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN)) |
| mbed_official | 235:685d5f11838f | 571 | #define __ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN)) |
| mbed_official | 235:685d5f11838f | 572 | #define __ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) |
| mbed_official | 235:685d5f11838f | 573 | #define __OTGHS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) |
| mbed_official | 235:685d5f11838f | 574 | #define __OTGHSULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) |
| mbed_official | 235:685d5f11838f | 575 | #define __GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN)) |
| mbed_official | 235:685d5f11838f | 576 | #define __GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN)) |
| mbed_official | 235:685d5f11838f | 577 | #define __DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN)) |
| mbed_official | 235:685d5f11838f | 578 | |
| mbed_official | 235:685d5f11838f | 579 | /** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. |
| mbed_official | 235:685d5f11838f | 580 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| mbed_official | 235:685d5f11838f | 581 | * power consumption. |
| mbed_official | 235:685d5f11838f | 582 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| mbed_official | 235:685d5f11838f | 583 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| mbed_official | 235:685d5f11838f | 584 | */ |
| mbed_official | 235:685d5f11838f | 585 | #define __DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) |
| mbed_official | 235:685d5f11838f | 586 | #define __DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) |
| mbed_official | 235:685d5f11838f | 587 | |
| mbed_official | 235:685d5f11838f | 588 | #if defined(STM32F437xx)|| defined(STM32F439xx) |
| mbed_official | 235:685d5f11838f | 589 | #define __CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) |
| mbed_official | 235:685d5f11838f | 590 | #define __HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) |
| mbed_official | 235:685d5f11838f | 591 | |
| mbed_official | 235:685d5f11838f | 592 | #define __CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) |
| mbed_official | 235:685d5f11838f | 593 | #define __HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) |
| mbed_official | 235:685d5f11838f | 594 | #endif /* STM32F437xx || STM32F439xx */ |
| mbed_official | 235:685d5f11838f | 595 | |
| mbed_official | 235:685d5f11838f | 596 | /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. |
| mbed_official | 235:685d5f11838f | 597 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| mbed_official | 235:685d5f11838f | 598 | * power consumption. |
| mbed_official | 235:685d5f11838f | 599 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| mbed_official | 235:685d5f11838f | 600 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| mbed_official | 235:685d5f11838f | 601 | */ |
| mbed_official | 235:685d5f11838f | 602 | #define __FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) |
| mbed_official | 235:685d5f11838f | 603 | #define __FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN)) |
| mbed_official | 235:685d5f11838f | 604 | |
| mbed_official | 235:685d5f11838f | 605 | /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. |
| mbed_official | 235:685d5f11838f | 606 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| mbed_official | 235:685d5f11838f | 607 | * power consumption. |
| mbed_official | 235:685d5f11838f | 608 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| mbed_official | 235:685d5f11838f | 609 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| mbed_official | 235:685d5f11838f | 610 | */ |
| mbed_official | 235:685d5f11838f | 611 | #define __TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) |
| mbed_official | 235:685d5f11838f | 612 | #define __TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) |
| mbed_official | 235:685d5f11838f | 613 | #define __TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) |
| mbed_official | 235:685d5f11838f | 614 | #define __TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) |
| mbed_official | 235:685d5f11838f | 615 | #define __TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) |
| mbed_official | 235:685d5f11838f | 616 | #define __USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) |
| mbed_official | 235:685d5f11838f | 617 | #define __UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) |
| mbed_official | 235:685d5f11838f | 618 | #define __UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) |
| mbed_official | 235:685d5f11838f | 619 | #define __CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) |
| mbed_official | 235:685d5f11838f | 620 | #define __CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) |
| mbed_official | 235:685d5f11838f | 621 | #define __DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) |
| mbed_official | 235:685d5f11838f | 622 | #define __UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN)) |
| mbed_official | 235:685d5f11838f | 623 | #define __UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN)) |
| mbed_official | 235:685d5f11838f | 624 | |
| mbed_official | 235:685d5f11838f | 625 | #define __TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) |
| mbed_official | 235:685d5f11838f | 626 | #define __TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) |
| mbed_official | 235:685d5f11838f | 627 | #define __TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) |
| mbed_official | 235:685d5f11838f | 628 | #define __TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) |
| mbed_official | 235:685d5f11838f | 629 | #define __TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) |
| mbed_official | 235:685d5f11838f | 630 | #define __USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) |
| mbed_official | 235:685d5f11838f | 631 | #define __UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) |
| mbed_official | 235:685d5f11838f | 632 | #define __UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) |
| mbed_official | 235:685d5f11838f | 633 | #define __CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) |
| mbed_official | 235:685d5f11838f | 634 | #define __CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) |
| mbed_official | 235:685d5f11838f | 635 | #define __DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) |
| mbed_official | 235:685d5f11838f | 636 | #define __UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN)) |
| mbed_official | 235:685d5f11838f | 637 | #define __UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN)) |
| mbed_official | 235:685d5f11838f | 638 | |
| mbed_official | 235:685d5f11838f | 639 | /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. |
| mbed_official | 235:685d5f11838f | 640 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| mbed_official | 235:685d5f11838f | 641 | * power consumption. |
| mbed_official | 235:685d5f11838f | 642 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| mbed_official | 235:685d5f11838f | 643 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| mbed_official | 235:685d5f11838f | 644 | */ |
| mbed_official | 235:685d5f11838f | 645 | #define __TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) |
| mbed_official | 235:685d5f11838f | 646 | #define __ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) |
| mbed_official | 235:685d5f11838f | 647 | #define __ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) |
| mbed_official | 235:685d5f11838f | 648 | #define __SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) |
| mbed_official | 235:685d5f11838f | 649 | #define __SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN)) |
| mbed_official | 235:685d5f11838f | 650 | #define __SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) |
| mbed_official | 235:685d5f11838f | 651 | |
| mbed_official | 235:685d5f11838f | 652 | #define __TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) |
| mbed_official | 235:685d5f11838f | 653 | #define __ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) |
| mbed_official | 235:685d5f11838f | 654 | #define __ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) |
| mbed_official | 235:685d5f11838f | 655 | #define __SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) |
| mbed_official | 235:685d5f11838f | 656 | #define __SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN)) |
| mbed_official | 235:685d5f11838f | 657 | #define __SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) |
| mbed_official | 235:685d5f11838f | 658 | |
| mbed_official | 235:685d5f11838f | 659 | #if defined(STM32F429xx)|| defined(STM32F439xx) |
| mbed_official | 235:685d5f11838f | 660 | #define __LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN)) |
| mbed_official | 235:685d5f11838f | 661 | |
| mbed_official | 235:685d5f11838f | 662 | #define __LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN)) |
| mbed_official | 235:685d5f11838f | 663 | #endif /* STM32F429xx || STM32F439xx */ |
| mbed_official | 235:685d5f11838f | 664 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */ |
| mbed_official | 235:685d5f11838f | 665 | /*---------------------------------------------------------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 666 | |
| mbed_official | 235:685d5f11838f | 667 | /*----------------------------------- STM32F40xxx/STM32F41xxx----------------------------------*/ |
| mbed_official | 235:685d5f11838f | 668 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) |
| mbed_official | 235:685d5f11838f | 669 | /** @brief Enables or disables the AHB1 peripheral clock. |
| mbed_official | 235:685d5f11838f | 670 | * @note After reset, the peripheral clock (used for registers read/write access) |
| mbed_official | 235:685d5f11838f | 671 | * is disabled and the application software has to enable this clock before |
| mbed_official | 235:685d5f11838f | 672 | * using it. |
| mbed_official | 235:685d5f11838f | 673 | */ |
| mbed_official | 235:685d5f11838f | 674 | #define __GPIOI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOIEN)) |
| mbed_official | 235:685d5f11838f | 675 | #define __GPIOF_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOFEN)) |
| mbed_official | 235:685d5f11838f | 676 | #define __GPIOG_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOGEN)) |
| mbed_official | 235:685d5f11838f | 677 | #define __USB_OTG_HS_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSEN)) |
| mbed_official | 235:685d5f11838f | 678 | #define __USB_OTG_HS_ULPI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSULPIEN)) |
| mbed_official | 235:685d5f11838f | 679 | |
| mbed_official | 235:685d5f11838f | 680 | #define __GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) |
| mbed_official | 235:685d5f11838f | 681 | #define __GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) |
| mbed_official | 235:685d5f11838f | 682 | #define __GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) |
| mbed_official | 235:685d5f11838f | 683 | #define __USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) |
| mbed_official | 235:685d5f11838f | 684 | #define __USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) |
| mbed_official | 235:685d5f11838f | 685 | |
| mbed_official | 235:685d5f11838f | 686 | #if defined(STM32F407xx)|| defined(STM32F417xx) |
| mbed_official | 235:685d5f11838f | 687 | /** |
| mbed_official | 235:685d5f11838f | 688 | * @brief Enable ETHERNET clock. |
| mbed_official | 235:685d5f11838f | 689 | */ |
| mbed_official | 235:685d5f11838f | 690 | #define __ETHMAC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACEN)) |
| mbed_official | 235:685d5f11838f | 691 | #define __ETHMACTX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACTXEN)) |
| mbed_official | 235:685d5f11838f | 692 | #define __ETHMACRX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACRXEN)) |
| mbed_official | 235:685d5f11838f | 693 | #define __ETHMACPTP_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACPTPEN)) |
| mbed_official | 235:685d5f11838f | 694 | #define __ETH_CLK_ENABLE() do { \ |
| mbed_official | 235:685d5f11838f | 695 | __ETHMAC_CLK_ENABLE(); \ |
| mbed_official | 235:685d5f11838f | 696 | __ETHMACTX_CLK_ENABLE(); \ |
| mbed_official | 235:685d5f11838f | 697 | __ETHMACRX_CLK_ENABLE(); \ |
| mbed_official | 235:685d5f11838f | 698 | } while(0) |
| mbed_official | 235:685d5f11838f | 699 | |
| mbed_official | 235:685d5f11838f | 700 | /** |
| mbed_official | 235:685d5f11838f | 701 | * @brief Disable ETHERNET clock. |
| mbed_official | 235:685d5f11838f | 702 | */ |
| mbed_official | 235:685d5f11838f | 703 | #define __ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN)) |
| mbed_official | 235:685d5f11838f | 704 | #define __ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN)) |
| mbed_official | 235:685d5f11838f | 705 | #define __ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN)) |
| mbed_official | 235:685d5f11838f | 706 | #define __ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN)) |
| mbed_official | 235:685d5f11838f | 707 | #define __ETH_CLK_DISABLE() do { \ |
| mbed_official | 235:685d5f11838f | 708 | __ETHMACTX_CLK_DISABLE(); \ |
| mbed_official | 235:685d5f11838f | 709 | __ETHMACRX_CLK_DISABLE(); \ |
| mbed_official | 235:685d5f11838f | 710 | __ETHMAC_CLK_DISABLE(); \ |
| mbed_official | 235:685d5f11838f | 711 | } while(0) |
| mbed_official | 235:685d5f11838f | 712 | #endif /* STM32F407xx || STM32F417xx */ |
| mbed_official | 235:685d5f11838f | 713 | |
| mbed_official | 235:685d5f11838f | 714 | /** @brief Enable or disable the AHB2 peripheral clock. |
| mbed_official | 235:685d5f11838f | 715 | * @note After reset, the peripheral clock (used for registers read/write access) |
| mbed_official | 235:685d5f11838f | 716 | * is disabled and the application software has to enable this clock before |
| mbed_official | 235:685d5f11838f | 717 | * using it. |
| mbed_official | 235:685d5f11838f | 718 | */ |
| mbed_official | 235:685d5f11838f | 719 | #if defined(STM32F407xx)|| defined(STM32F417xx) |
| mbed_official | 235:685d5f11838f | 720 | #define __DCMI_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_DCMIEN)) |
| mbed_official | 235:685d5f11838f | 721 | #define __DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) |
| mbed_official | 235:685d5f11838f | 722 | #endif /* STM32F407xx || STM32F417xx */ |
| mbed_official | 235:685d5f11838f | 723 | |
| mbed_official | 235:685d5f11838f | 724 | #if defined(STM32F415xx) || defined(STM32F417xx) |
| mbed_official | 235:685d5f11838f | 725 | #define __CRYP_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_CRYPEN)) |
| mbed_official | 235:685d5f11838f | 726 | #define __HASH_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_HASHEN)) |
| mbed_official | 235:685d5f11838f | 727 | |
| mbed_official | 235:685d5f11838f | 728 | #define __CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) |
| mbed_official | 235:685d5f11838f | 729 | #define __HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) |
| mbed_official | 235:685d5f11838f | 730 | #endif /* STM32F415xx || STM32F417xx */ |
| mbed_official | 235:685d5f11838f | 731 | |
| mbed_official | 235:685d5f11838f | 732 | /** @brief Enables or disables the AHB3 peripheral clock. |
| mbed_official | 235:685d5f11838f | 733 | * @note After reset, the peripheral clock (used for registers read/write access) |
| mbed_official | 235:685d5f11838f | 734 | * is disabled and the application software has to enable this clock before |
| mbed_official | 235:685d5f11838f | 735 | * using it. |
| mbed_official | 235:685d5f11838f | 736 | */ |
| mbed_official | 235:685d5f11838f | 737 | #define __FSMC_CLK_ENABLE() (RCC->AHB3ENR |= (RCC_AHB3ENR_FSMCEN)) |
| mbed_official | 235:685d5f11838f | 738 | #define __FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN)) |
| mbed_official | 235:685d5f11838f | 739 | |
| mbed_official | 235:685d5f11838f | 740 | /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock. |
| mbed_official | 235:685d5f11838f | 741 | * @note After reset, the peripheral clock (used for registers read/write access) |
| mbed_official | 235:685d5f11838f | 742 | * is disabled and the application software has to enable this clock before |
| mbed_official | 235:685d5f11838f | 743 | * using it. |
| mbed_official | 235:685d5f11838f | 744 | */ |
| mbed_official | 235:685d5f11838f | 745 | #define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN)) |
| mbed_official | 235:685d5f11838f | 746 | #define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN)) |
| mbed_official | 235:685d5f11838f | 747 | #define __TIM12_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM12EN)) |
| mbed_official | 235:685d5f11838f | 748 | #define __TIM13_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM13EN)) |
| mbed_official | 235:685d5f11838f | 749 | #define __TIM14_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN)) |
| mbed_official | 235:685d5f11838f | 750 | #define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN)) |
| mbed_official | 235:685d5f11838f | 751 | #define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN)) |
| mbed_official | 235:685d5f11838f | 752 | #define __UART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART4EN)) |
| mbed_official | 235:685d5f11838f | 753 | #define __UART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART5EN)) |
| mbed_official | 235:685d5f11838f | 754 | #define __CAN1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN1EN)) |
| mbed_official | 235:685d5f11838f | 755 | #define __CAN2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN2EN)) |
| mbed_official | 235:685d5f11838f | 756 | #define __DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN)) |
| mbed_official | 235:685d5f11838f | 757 | |
| mbed_official | 235:685d5f11838f | 758 | #define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) |
| mbed_official | 235:685d5f11838f | 759 | #define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) |
| mbed_official | 235:685d5f11838f | 760 | #define __TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) |
| mbed_official | 235:685d5f11838f | 761 | #define __TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) |
| mbed_official | 235:685d5f11838f | 762 | #define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) |
| mbed_official | 235:685d5f11838f | 763 | #define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) |
| mbed_official | 235:685d5f11838f | 764 | #define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) |
| mbed_official | 235:685d5f11838f | 765 | #define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) |
| mbed_official | 235:685d5f11838f | 766 | #define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) |
| mbed_official | 235:685d5f11838f | 767 | #define __CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) |
| mbed_official | 235:685d5f11838f | 768 | #define __CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) |
| mbed_official | 235:685d5f11838f | 769 | #define __DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) |
| mbed_official | 235:685d5f11838f | 770 | |
| mbed_official | 235:685d5f11838f | 771 | /** @brief Enable or disable the High Speed APB (APB2) peripheral clock. |
| mbed_official | 235:685d5f11838f | 772 | * @note After reset, the peripheral clock (used for registers read/write access) |
| mbed_official | 235:685d5f11838f | 773 | * is disabled and the application software has to enable this clock before |
| mbed_official | 235:685d5f11838f | 774 | * using it. |
| mbed_official | 235:685d5f11838f | 775 | */ |
| mbed_official | 235:685d5f11838f | 776 | #define __TIM8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM8EN)) |
| mbed_official | 235:685d5f11838f | 777 | #define __ADC2_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC2EN)) |
| mbed_official | 235:685d5f11838f | 778 | #define __ADC3_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC3EN)) |
| mbed_official | 235:685d5f11838f | 779 | |
| mbed_official | 235:685d5f11838f | 780 | #define __TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) |
| mbed_official | 235:685d5f11838f | 781 | #define __ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) |
| mbed_official | 235:685d5f11838f | 782 | #define __ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) |
| mbed_official | 235:685d5f11838f | 783 | |
| mbed_official | 235:685d5f11838f | 784 | /** @brief Force or release AHB1 peripheral reset. |
| mbed_official | 235:685d5f11838f | 785 | */ |
| mbed_official | 235:685d5f11838f | 786 | #define __GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) |
| mbed_official | 235:685d5f11838f | 787 | #define __GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) |
| mbed_official | 235:685d5f11838f | 788 | #define __GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST)) |
| mbed_official | 235:685d5f11838f | 789 | #define __ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) |
| mbed_official | 235:685d5f11838f | 790 | #define __OTGHS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) |
| mbed_official | 235:685d5f11838f | 791 | |
| mbed_official | 235:685d5f11838f | 792 | #define __GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) |
| mbed_official | 235:685d5f11838f | 793 | #define __GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) |
| mbed_official | 235:685d5f11838f | 794 | #define __GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) |
| mbed_official | 235:685d5f11838f | 795 | #define __ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) |
| mbed_official | 235:685d5f11838f | 796 | #define __OTGHS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) |
| mbed_official | 235:685d5f11838f | 797 | |
| mbed_official | 235:685d5f11838f | 798 | /** @brief Force or release AHB2 peripheral reset. |
| mbed_official | 235:685d5f11838f | 799 | */ |
| mbed_official | 235:685d5f11838f | 800 | #if defined(STM32F407xx)|| defined(STM32F417xx) |
| mbed_official | 235:685d5f11838f | 801 | #define __DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) |
| mbed_official | 235:685d5f11838f | 802 | #define __DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) |
| mbed_official | 235:685d5f11838f | 803 | #endif /* STM32F407xx || STM32F417xx */ |
| mbed_official | 235:685d5f11838f | 804 | |
| mbed_official | 235:685d5f11838f | 805 | #if defined(STM32F415xx) || defined(STM32F417xx) |
| mbed_official | 235:685d5f11838f | 806 | #define __CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) |
| mbed_official | 235:685d5f11838f | 807 | #define __HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) |
| mbed_official | 235:685d5f11838f | 808 | |
| mbed_official | 235:685d5f11838f | 809 | #define __CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) |
| mbed_official | 235:685d5f11838f | 810 | #define __HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) |
| mbed_official | 235:685d5f11838f | 811 | |
| mbed_official | 235:685d5f11838f | 812 | #endif /* STM32F415xx || STM32F417xx */ |
| mbed_official | 235:685d5f11838f | 813 | |
| mbed_official | 235:685d5f11838f | 814 | /** @brief Force or release AHB3 peripheral reset |
| mbed_official | 235:685d5f11838f | 815 | */ |
| mbed_official | 235:685d5f11838f | 816 | #define __FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST)) |
| mbed_official | 235:685d5f11838f | 817 | #define __FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST)) |
| mbed_official | 235:685d5f11838f | 818 | |
| mbed_official | 235:685d5f11838f | 819 | /** @brief Force or release APB1 peripheral reset. |
| mbed_official | 235:685d5f11838f | 820 | */ |
| mbed_official | 235:685d5f11838f | 821 | #define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) |
| mbed_official | 235:685d5f11838f | 822 | #define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) |
| mbed_official | 235:685d5f11838f | 823 | #define __TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) |
| mbed_official | 235:685d5f11838f | 824 | #define __TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) |
| mbed_official | 235:685d5f11838f | 825 | #define __TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) |
| mbed_official | 235:685d5f11838f | 826 | #define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) |
| mbed_official | 235:685d5f11838f | 827 | #define __UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) |
| mbed_official | 235:685d5f11838f | 828 | #define __UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) |
| mbed_official | 235:685d5f11838f | 829 | #define __CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) |
| mbed_official | 235:685d5f11838f | 830 | #define __CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) |
| mbed_official | 235:685d5f11838f | 831 | #define __DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) |
| mbed_official | 235:685d5f11838f | 832 | |
| mbed_official | 235:685d5f11838f | 833 | #define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) |
| mbed_official | 235:685d5f11838f | 834 | #define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) |
| mbed_official | 235:685d5f11838f | 835 | #define __TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) |
| mbed_official | 235:685d5f11838f | 836 | #define __TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) |
| mbed_official | 235:685d5f11838f | 837 | #define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) |
| mbed_official | 235:685d5f11838f | 838 | #define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) |
| mbed_official | 235:685d5f11838f | 839 | #define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) |
| mbed_official | 235:685d5f11838f | 840 | #define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) |
| mbed_official | 235:685d5f11838f | 841 | #define __CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) |
| mbed_official | 235:685d5f11838f | 842 | #define __CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) |
| mbed_official | 235:685d5f11838f | 843 | #define __DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) |
| mbed_official | 235:685d5f11838f | 844 | |
| mbed_official | 235:685d5f11838f | 845 | /** @brief Force or release APB2 peripheral reset. |
| mbed_official | 235:685d5f11838f | 846 | */ |
| mbed_official | 235:685d5f11838f | 847 | #define __TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) |
| mbed_official | 235:685d5f11838f | 848 | #define __TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) |
| mbed_official | 235:685d5f11838f | 849 | |
| mbed_official | 235:685d5f11838f | 850 | /** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. |
| mbed_official | 235:685d5f11838f | 851 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| mbed_official | 235:685d5f11838f | 852 | * power consumption. |
| mbed_official | 235:685d5f11838f | 853 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| mbed_official | 235:685d5f11838f | 854 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| mbed_official | 235:685d5f11838f | 855 | */ |
| mbed_official | 235:685d5f11838f | 856 | #define __GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) |
| mbed_official | 235:685d5f11838f | 857 | #define __GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) |
| mbed_official | 235:685d5f11838f | 858 | #define __GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN)) |
| mbed_official | 235:685d5f11838f | 859 | #define __SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) |
| mbed_official | 235:685d5f11838f | 860 | #define __ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) |
| mbed_official | 235:685d5f11838f | 861 | #define __ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN)) |
| mbed_official | 235:685d5f11838f | 862 | #define __ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN)) |
| mbed_official | 235:685d5f11838f | 863 | #define __ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN)) |
| mbed_official | 235:685d5f11838f | 864 | #define __OTGHS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) |
| mbed_official | 235:685d5f11838f | 865 | #define __OTGHSULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) |
| mbed_official | 235:685d5f11838f | 866 | |
| mbed_official | 235:685d5f11838f | 867 | #define __GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) |
| mbed_official | 235:685d5f11838f | 868 | #define __GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) |
| mbed_official | 235:685d5f11838f | 869 | #define __GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) |
| mbed_official | 235:685d5f11838f | 870 | #define __SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) |
| mbed_official | 235:685d5f11838f | 871 | #define __ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN)) |
| mbed_official | 235:685d5f11838f | 872 | #define __ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN)) |
| mbed_official | 235:685d5f11838f | 873 | #define __ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN)) |
| mbed_official | 235:685d5f11838f | 874 | #define __ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) |
| mbed_official | 235:685d5f11838f | 875 | #define __OTGHS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) |
| mbed_official | 235:685d5f11838f | 876 | #define __OTGHSULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) |
| mbed_official | 235:685d5f11838f | 877 | |
| mbed_official | 235:685d5f11838f | 878 | /** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. |
| mbed_official | 235:685d5f11838f | 879 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| mbed_official | 235:685d5f11838f | 880 | * power consumption. |
| mbed_official | 235:685d5f11838f | 881 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| mbed_official | 235:685d5f11838f | 882 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| mbed_official | 235:685d5f11838f | 883 | */ |
| mbed_official | 235:685d5f11838f | 884 | #if defined(STM32F407xx)|| defined(STM32F417xx) |
| mbed_official | 235:685d5f11838f | 885 | #define __DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) |
| mbed_official | 235:685d5f11838f | 886 | #define __DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) |
| mbed_official | 235:685d5f11838f | 887 | #endif /* STM32F407xx || STM32F417xx */ |
| mbed_official | 235:685d5f11838f | 888 | |
| mbed_official | 235:685d5f11838f | 889 | #if defined(STM32F415xx) || defined(STM32F417xx) |
| mbed_official | 235:685d5f11838f | 890 | #define __CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) |
| mbed_official | 235:685d5f11838f | 891 | #define __HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) |
| mbed_official | 235:685d5f11838f | 892 | |
| mbed_official | 235:685d5f11838f | 893 | #define __CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) |
| mbed_official | 235:685d5f11838f | 894 | #define __HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) |
| mbed_official | 235:685d5f11838f | 895 | #endif /* STM32F415xx || STM32F417xx */ |
| mbed_official | 235:685d5f11838f | 896 | |
| mbed_official | 235:685d5f11838f | 897 | /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. |
| mbed_official | 235:685d5f11838f | 898 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| mbed_official | 235:685d5f11838f | 899 | * power consumption. |
| mbed_official | 235:685d5f11838f | 900 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| mbed_official | 235:685d5f11838f | 901 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| mbed_official | 235:685d5f11838f | 902 | */ |
| mbed_official | 235:685d5f11838f | 903 | #define __FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN)) |
| mbed_official | 235:685d5f11838f | 904 | #define __FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN)) |
| mbed_official | 235:685d5f11838f | 905 | |
| mbed_official | 235:685d5f11838f | 906 | /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. |
| mbed_official | 235:685d5f11838f | 907 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| mbed_official | 235:685d5f11838f | 908 | * power consumption. |
| mbed_official | 235:685d5f11838f | 909 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| mbed_official | 235:685d5f11838f | 910 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| mbed_official | 235:685d5f11838f | 911 | */ |
| mbed_official | 235:685d5f11838f | 912 | #define __TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) |
| mbed_official | 235:685d5f11838f | 913 | #define __TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) |
| mbed_official | 235:685d5f11838f | 914 | #define __TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) |
| mbed_official | 235:685d5f11838f | 915 | #define __TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) |
| mbed_official | 235:685d5f11838f | 916 | #define __TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) |
| mbed_official | 235:685d5f11838f | 917 | #define __USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) |
| mbed_official | 235:685d5f11838f | 918 | #define __UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) |
| mbed_official | 235:685d5f11838f | 919 | #define __UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) |
| mbed_official | 235:685d5f11838f | 920 | #define __CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) |
| mbed_official | 235:685d5f11838f | 921 | #define __CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) |
| mbed_official | 235:685d5f11838f | 922 | #define __DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) |
| mbed_official | 235:685d5f11838f | 923 | |
| mbed_official | 235:685d5f11838f | 924 | #define __TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) |
| mbed_official | 235:685d5f11838f | 925 | #define __TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) |
| mbed_official | 235:685d5f11838f | 926 | #define __TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) |
| mbed_official | 235:685d5f11838f | 927 | #define __TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) |
| mbed_official | 235:685d5f11838f | 928 | #define __TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) |
| mbed_official | 235:685d5f11838f | 929 | #define __USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) |
| mbed_official | 235:685d5f11838f | 930 | #define __UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) |
| mbed_official | 235:685d5f11838f | 931 | #define __UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) |
| mbed_official | 235:685d5f11838f | 932 | #define __CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) |
| mbed_official | 235:685d5f11838f | 933 | #define __CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) |
| mbed_official | 235:685d5f11838f | 934 | #define __DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) |
| mbed_official | 235:685d5f11838f | 935 | |
| mbed_official | 235:685d5f11838f | 936 | /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. |
| mbed_official | 235:685d5f11838f | 937 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| mbed_official | 235:685d5f11838f | 938 | * power consumption. |
| mbed_official | 235:685d5f11838f | 939 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| mbed_official | 235:685d5f11838f | 940 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| mbed_official | 235:685d5f11838f | 941 | */ |
| mbed_official | 235:685d5f11838f | 942 | #define __TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) |
| mbed_official | 235:685d5f11838f | 943 | #define __ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) |
| mbed_official | 235:685d5f11838f | 944 | #define __ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) |
| mbed_official | 235:685d5f11838f | 945 | |
| mbed_official | 235:685d5f11838f | 946 | #define __TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) |
| mbed_official | 235:685d5f11838f | 947 | #define __ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) |
| mbed_official | 235:685d5f11838f | 948 | #define __ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) |
| mbed_official | 235:685d5f11838f | 949 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
| mbed_official | 235:685d5f11838f | 950 | /*---------------------------------------------------------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 951 | |
| mbed_official | 235:685d5f11838f | 952 | /*------------------------------------------ STM32F411xx --------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 953 | #if defined(STM32F411xE) |
| mbed_official | 235:685d5f11838f | 954 | /** @brief Enable or disable the High Speed APB (APB2) peripheral clock. |
| mbed_official | 235:685d5f11838f | 955 | */ |
| mbed_official | 235:685d5f11838f | 956 | #define __SPI5_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI5EN)) |
| mbed_official | 235:685d5f11838f | 957 | #define __SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) |
| mbed_official | 235:685d5f11838f | 958 | |
| mbed_official | 235:685d5f11838f | 959 | /** @brief Force or release APB2 peripheral reset. |
| mbed_official | 235:685d5f11838f | 960 | */ |
| mbed_official | 235:685d5f11838f | 961 | #define __SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) |
| mbed_official | 235:685d5f11838f | 962 | #define __SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) |
| mbed_official | 235:685d5f11838f | 963 | |
| mbed_official | 235:685d5f11838f | 964 | /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. |
| mbed_official | 235:685d5f11838f | 965 | */ |
| mbed_official | 235:685d5f11838f | 966 | #define __SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) |
| mbed_official | 235:685d5f11838f | 967 | #define __SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) |
| mbed_official | 235:685d5f11838f | 968 | |
| mbed_official | 235:685d5f11838f | 969 | #endif /* STM32F411xE */ |
| mbed_official | 235:685d5f11838f | 970 | /*---------------------------------------------------------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 971 | |
| mbed_official | 235:685d5f11838f | 972 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ |
| mbed_official | 235:685d5f11838f | 973 | defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) |
| mbed_official | 235:685d5f11838f | 974 | |
| mbed_official | 235:685d5f11838f | 975 | /** @brief Macro to configure the Timers clocks prescalers |
| mbed_official | 235:685d5f11838f | 976 | * @note This feature is only available with STM32F429x/439x Devices. |
| mbed_official | 235:685d5f11838f | 977 | * @param __PRESC__ : specifies the Timers clocks prescalers selection |
| mbed_official | 235:685d5f11838f | 978 | * This parameter can be one of the following values: |
| mbed_official | 235:685d5f11838f | 979 | * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is |
| mbed_official | 235:685d5f11838f | 980 | * equal to HPRE if PPREx is corresponding to division by 1 or 2, |
| mbed_official | 235:685d5f11838f | 981 | * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to |
| mbed_official | 235:685d5f11838f | 982 | * division by 4 or more. |
| mbed_official | 235:685d5f11838f | 983 | * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is |
| mbed_official | 235:685d5f11838f | 984 | * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, |
| mbed_official | 235:685d5f11838f | 985 | * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding |
| mbed_official | 235:685d5f11838f | 986 | * to division by 8 or more. |
| mbed_official | 235:685d5f11838f | 987 | */ |
| mbed_official | 235:685d5f11838f | 988 | #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) DCKCFGR_TIMPRE_BB = (__PRESC__)) |
| mbed_official | 235:685d5f11838f | 989 | |
| mbed_official | 235:685d5f11838f | 990 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx) || STM32F401xC || STM32F401xE || STM32F411xE */ |
| mbed_official | 235:685d5f11838f | 991 | |
| mbed_official | 235:685d5f11838f | 992 | #if defined(STM32F411xE) |
| mbed_official | 235:685d5f11838f | 993 | |
| mbed_official | 235:685d5f11838f | 994 | /** @brief Macro to configure the PLLI2S clock multiplication and division factors . |
| mbed_official | 235:685d5f11838f | 995 | * @note This macro must be used only when the PLLI2S is disabled. |
| mbed_official | 235:685d5f11838f | 996 | * @note This macro must be used only when the PLLI2S is disabled. |
| mbed_official | 235:685d5f11838f | 997 | * @note PLLI2S clock source is common with the main PLL (configured in |
| mbed_official | 235:685d5f11838f | 998 | * HAL_RCC_ClockConfig() API). |
| mbed_official | 235:685d5f11838f | 999 | * @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock |
| mbed_official | 235:685d5f11838f | 1000 | * This parameter must be a number between Min_Data = 2 and Max_Data = 63. |
| mbed_official | 235:685d5f11838f | 1001 | * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input |
| mbed_official | 235:685d5f11838f | 1002 | * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency |
| mbed_official | 235:685d5f11838f | 1003 | * of 2 MHz to limit PLLI2S jitter. |
| mbed_official | 235:685d5f11838f | 1004 | * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock |
| mbed_official | 235:685d5f11838f | 1005 | * This parameter must be a number between Min_Data = 192 and Max_Data = 432. |
| mbed_official | 235:685d5f11838f | 1006 | * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO |
| mbed_official | 235:685d5f11838f | 1007 | * output frequency is between Min_Data = 192 and Max_Data = 432 MHz. |
| mbed_official | 235:685d5f11838f | 1008 | * @param __PLLI2SR__: specifies the division factor for I2S clock |
| mbed_official | 235:685d5f11838f | 1009 | * This parameter must be a number between Min_Data = 2 and Max_Data = 7. |
| mbed_official | 235:685d5f11838f | 1010 | * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz |
| mbed_official | 235:685d5f11838f | 1011 | * on the I2S clock frequency. |
| mbed_official | 235:685d5f11838f | 1012 | */ |
| mbed_official | 235:685d5f11838f | 1013 | #define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\ |
| mbed_official | 235:685d5f11838f | 1014 | ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)) | (__PLLI2SM__)) |
| mbed_official | 235:685d5f11838f | 1015 | #endif /* STM32F411xE */ |
| mbed_official | 235:685d5f11838f | 1016 | |
| mbed_official | 235:685d5f11838f | 1017 | |
| mbed_official | 235:685d5f11838f | 1018 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
| mbed_official | 235:685d5f11838f | 1019 | |
| mbed_official | 235:685d5f11838f | 1020 | /** @brief Macros to Enable or Disable the PLLISAI. |
| mbed_official | 235:685d5f11838f | 1021 | * @note The PLLSAI is only available with STM32F429x/439x Devices. |
| mbed_official | 235:685d5f11838f | 1022 | * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. |
| mbed_official | 235:685d5f11838f | 1023 | */ |
| mbed_official | 235:685d5f11838f | 1024 | #define __HAL_RCC_PLLSAI_ENABLE() (*(__IO uint32_t *) CR_PLLSAION_BB = ENABLE) |
| mbed_official | 235:685d5f11838f | 1025 | #define __HAL_RCC_PLLSAI_DISABLE() (*(__IO uint32_t *) CR_PLLSAION_BB = DISABLE) |
| mbed_official | 235:685d5f11838f | 1026 | |
| mbed_official | 235:685d5f11838f | 1027 | /** @brief Macro to configure the PLLSAI clock multiplication and division factors. |
| mbed_official | 235:685d5f11838f | 1028 | * @note The PLLSAI is only available with STM32F429x/439x Devices. |
| mbed_official | 235:685d5f11838f | 1029 | * @note This function must be used only when the PLLSAI is disabled. |
| mbed_official | 235:685d5f11838f | 1030 | * @note PLLSAI clock source is common with the main PLL (configured in |
| mbed_official | 235:685d5f11838f | 1031 | * RCC_PLLConfig function ) |
| mbed_official | 235:685d5f11838f | 1032 | * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock. |
| mbed_official | 235:685d5f11838f | 1033 | * This parameter must be a number between Min_Data = 192 and Max_Data = 432. |
| mbed_official | 235:685d5f11838f | 1034 | * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO |
| mbed_official | 235:685d5f11838f | 1035 | * output frequency is between Min_Data = 192 and Max_Data = 432 MHz. |
| mbed_official | 235:685d5f11838f | 1036 | * @param __PLLSAIQ__: specifies the division factor for SAI1 clock |
| mbed_official | 235:685d5f11838f | 1037 | * This parameter must be a number between Min_Data = 2 and Max_Data = 15. |
| mbed_official | 235:685d5f11838f | 1038 | * @param __PLLSAIR__: specifies the division factor for LTDC clock |
| mbed_official | 235:685d5f11838f | 1039 | * This parameter must be a number between Min_Data = 2 and Max_Data = 7. |
| mbed_official | 235:685d5f11838f | 1040 | */ |
| mbed_official | 235:685d5f11838f | 1041 | #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) (RCC->PLLSAICFGR = ((__PLLSAIN__) << 6) | ((__PLLSAIQ__) << 24) | ((__PLLSAIR__) << 28)) |
| mbed_official | 235:685d5f11838f | 1042 | |
| mbed_official | 235:685d5f11838f | 1043 | /** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors. |
| mbed_official | 235:685d5f11838f | 1044 | * @note This macro must be used only when the PLLI2S is disabled. |
| mbed_official | 235:685d5f11838f | 1045 | * @note PLLI2S clock source is common with the main PLL (configured in |
| mbed_official | 235:685d5f11838f | 1046 | * HAL_RCC_ClockConfig() API) |
| mbed_official | 235:685d5f11838f | 1047 | * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock. |
| mbed_official | 235:685d5f11838f | 1048 | * This parameter must be a number between Min_Data = 192 and Max_Data = 432. |
| mbed_official | 235:685d5f11838f | 1049 | * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO |
| mbed_official | 235:685d5f11838f | 1050 | * output frequency is between Min_Data = 192 and Max_Data = 432 MHz. |
| mbed_official | 235:685d5f11838f | 1051 | * @param __PLLI2SQ__: specifies the division factor for SAI1 clock. |
| mbed_official | 235:685d5f11838f | 1052 | * This parameter must be a number between Min_Data = 2 and Max_Data = 15. |
| mbed_official | 235:685d5f11838f | 1053 | * @note the PLLI2SQ parameter is only available with STM32F429x/439x Devices |
| mbed_official | 235:685d5f11838f | 1054 | * and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro |
| mbed_official | 235:685d5f11838f | 1055 | * @param __PLLI2SR__: specifies the division factor for I2S clock |
| mbed_official | 235:685d5f11838f | 1056 | * This parameter must be a number between Min_Data = 2 and Max_Data = 7. |
| mbed_official | 235:685d5f11838f | 1057 | * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz |
| mbed_official | 235:685d5f11838f | 1058 | * on the I2S clock frequency. |
| mbed_official | 235:685d5f11838f | 1059 | */ |
| mbed_official | 235:685d5f11838f | 1060 | #define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) | ((__PLLI2SQ__) << 24) | ((__PLLI2SR__) << 28)) |
| mbed_official | 235:685d5f11838f | 1061 | |
| mbed_official | 235:685d5f11838f | 1062 | /** @brief Macro to configure the SAI clock Divider coming from PLLI2S. |
| mbed_official | 235:685d5f11838f | 1063 | * @note The SAI peripheral is only available with STM32F429x/439x Devices. |
| mbed_official | 235:685d5f11838f | 1064 | * @note This function must be called before enabling the PLLI2S. |
| mbed_official | 235:685d5f11838f | 1065 | * @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock . |
| mbed_official | 235:685d5f11838f | 1066 | * This parameter must be a number between 1 and 32. |
| mbed_official | 235:685d5f11838f | 1067 | * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__ |
| mbed_official | 235:685d5f11838f | 1068 | */ |
| mbed_official | 235:685d5f11838f | 1069 | #define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1)) |
| mbed_official | 235:685d5f11838f | 1070 | |
| mbed_official | 235:685d5f11838f | 1071 | /** @brief Macro to configure the SAI clock Divider coming from PLLSAI. |
| mbed_official | 235:685d5f11838f | 1072 | * @note The SAI peripheral is only available with STM32F429x/439x Devices. |
| mbed_official | 235:685d5f11838f | 1073 | * @note This function must be called before enabling the PLLSAI. |
| mbed_official | 235:685d5f11838f | 1074 | * @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock . |
| mbed_official | 235:685d5f11838f | 1075 | * This parameter must be a number between Min_Data = 1 and Max_Data = 32. |
| mbed_official | 235:685d5f11838f | 1076 | * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__ |
| mbed_official | 235:685d5f11838f | 1077 | */ |
| mbed_official | 235:685d5f11838f | 1078 | #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8)) |
| mbed_official | 235:685d5f11838f | 1079 | |
| mbed_official | 235:685d5f11838f | 1080 | /** @brief Macro to configure the LTDC clock Divider coming from PLLSAI. |
| mbed_official | 235:685d5f11838f | 1081 | * |
| mbed_official | 235:685d5f11838f | 1082 | * @note The LTDC peripheral is only available with STM32F429x/439x Devices. |
| mbed_official | 235:685d5f11838f | 1083 | * @note This function must be called before enabling the PLLSAI. |
| mbed_official | 235:685d5f11838f | 1084 | * @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock . |
| mbed_official | 235:685d5f11838f | 1085 | * This parameter must be a number between Min_Data = 2 and Max_Data = 16. |
| mbed_official | 235:685d5f11838f | 1086 | * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ |
| mbed_official | 235:685d5f11838f | 1087 | */ |
| mbed_official | 235:685d5f11838f | 1088 | #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__))) |
| mbed_official | 235:685d5f11838f | 1089 | |
| mbed_official | 235:685d5f11838f | 1090 | /** @brief Macro to configure SAI1BlockA clock source selection. |
| mbed_official | 235:685d5f11838f | 1091 | * @note The SAI peripheral is only available with STM32F429x/439x Devices. |
| mbed_official | 235:685d5f11838f | 1092 | * @note This function must be called before enabling PLLSAI, PLLI2S and |
| mbed_official | 235:685d5f11838f | 1093 | * the SAI clock. |
| mbed_official | 235:685d5f11838f | 1094 | * @param __SOURCE__: specifies the SAI Block A clock source. |
| mbed_official | 235:685d5f11838f | 1095 | * This parameter can be one of the following values: |
| mbed_official | 235:685d5f11838f | 1096 | * @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used |
| mbed_official | 235:685d5f11838f | 1097 | * as SAI1 Block A clock. |
| mbed_official | 235:685d5f11838f | 1098 | * @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used |
| mbed_official | 235:685d5f11838f | 1099 | * as SAI1 Block A clock. |
| mbed_official | 235:685d5f11838f | 1100 | * @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin |
| mbed_official | 235:685d5f11838f | 1101 | * used as SAI1 Block A clock. |
| mbed_official | 235:685d5f11838f | 1102 | */ |
| mbed_official | 235:685d5f11838f | 1103 | #define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__))) |
| mbed_official | 235:685d5f11838f | 1104 | |
| mbed_official | 235:685d5f11838f | 1105 | /** @brief Macro to configure SAI1BlockB clock source selection. |
| mbed_official | 235:685d5f11838f | 1106 | * @note The SAI peripheral is only available with STM32F429x/439x Devices. |
| mbed_official | 235:685d5f11838f | 1107 | * @note This function must be called before enabling PLLSAI, PLLI2S and |
| mbed_official | 235:685d5f11838f | 1108 | * the SAI clock. |
| mbed_official | 235:685d5f11838f | 1109 | * @param __SOURCE__: specifies the SAI Block B clock source. |
| mbed_official | 235:685d5f11838f | 1110 | * This parameter can be one of the following values: |
| mbed_official | 235:685d5f11838f | 1111 | * @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used |
| mbed_official | 235:685d5f11838f | 1112 | * as SAI1 Block B clock. |
| mbed_official | 235:685d5f11838f | 1113 | * @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used |
| mbed_official | 235:685d5f11838f | 1114 | * as SAI1 Block B clock. |
| mbed_official | 235:685d5f11838f | 1115 | * @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin |
| mbed_official | 235:685d5f11838f | 1116 | * used as SAI1 Block B clock. |
| mbed_official | 235:685d5f11838f | 1117 | */ |
| mbed_official | 235:685d5f11838f | 1118 | #define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__))) |
| mbed_official | 235:685d5f11838f | 1119 | |
| mbed_official | 235:685d5f11838f | 1120 | /** @brief Enable PLLSAI_RDY interrupt. |
| mbed_official | 235:685d5f11838f | 1121 | */ |
| mbed_official | 235:685d5f11838f | 1122 | #define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE)) |
| mbed_official | 235:685d5f11838f | 1123 | |
| mbed_official | 235:685d5f11838f | 1124 | /** @brief Disable PLLSAI_RDY interrupt. |
| mbed_official | 235:685d5f11838f | 1125 | */ |
| mbed_official | 235:685d5f11838f | 1126 | #define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE)) |
| mbed_official | 235:685d5f11838f | 1127 | |
| mbed_official | 235:685d5f11838f | 1128 | /** @brief Clear the PLLSAI RDY interrupt pending bits. |
| mbed_official | 235:685d5f11838f | 1129 | */ |
| mbed_official | 235:685d5f11838f | 1130 | #define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF)) |
| mbed_official | 235:685d5f11838f | 1131 | |
| mbed_official | 235:685d5f11838f | 1132 | /** @brief Check the PLLSAI RDY interrupt has occurred or not. |
| mbed_official | 235:685d5f11838f | 1133 | * @retval The new state (TRUE or FALSE). |
| mbed_official | 235:685d5f11838f | 1134 | */ |
| mbed_official | 235:685d5f11838f | 1135 | #define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE)) |
| mbed_official | 235:685d5f11838f | 1136 | |
| mbed_official | 235:685d5f11838f | 1137 | /** @brief Check PLLSAI RDY flag is set or not. |
| mbed_official | 235:685d5f11838f | 1138 | * @retval The new state (TRUE or FALSE). |
| mbed_official | 235:685d5f11838f | 1139 | */ |
| mbed_official | 235:685d5f11838f | 1140 | #define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY)) |
| mbed_official | 235:685d5f11838f | 1141 | |
| mbed_official | 235:685d5f11838f | 1142 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
| mbed_official | 235:685d5f11838f | 1143 | |
| mbed_official | 235:685d5f11838f | 1144 | /* Exported functions --------------------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 1145 | HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); |
| mbed_official | 235:685d5f11838f | 1146 | void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); |
| mbed_official | 235:685d5f11838f | 1147 | |
| mbed_official | 235:685d5f11838f | 1148 | #if defined(STM32F411xE) |
| mbed_official | 235:685d5f11838f | 1149 | void HAL_RCCEx_SelectLSEMode(uint8_t Mode); |
| mbed_official | 235:685d5f11838f | 1150 | #endif /* STM32F411xE */ |
| mbed_official | 235:685d5f11838f | 1151 | /** |
| mbed_official | 235:685d5f11838f | 1152 | * @} |
| mbed_official | 235:685d5f11838f | 1153 | */ |
| mbed_official | 235:685d5f11838f | 1154 | |
| mbed_official | 235:685d5f11838f | 1155 | /** |
| mbed_official | 235:685d5f11838f | 1156 | * @} |
| mbed_official | 235:685d5f11838f | 1157 | */ |
| mbed_official | 235:685d5f11838f | 1158 | |
| mbed_official | 235:685d5f11838f | 1159 | #ifdef __cplusplus |
| mbed_official | 235:685d5f11838f | 1160 | } |
| mbed_official | 235:685d5f11838f | 1161 | #endif |
| mbed_official | 235:685d5f11838f | 1162 | |
| mbed_official | 235:685d5f11838f | 1163 | #endif /* __STM32F4xx_HAL_RCC_EX_H */ |
| mbed_official | 235:685d5f11838f | 1164 | |
| mbed_official | 235:685d5f11838f | 1165 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |