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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h@106:ced8cbb51063, 2014-02-26 (annotated)
- Committer:
- mbed_official
- Date:
- Wed Feb 26 09:45:12 2014 +0000
- Revision:
- 106:ced8cbb51063
- Parent:
- 87:085cde657901
- Child:
- 226:b062af740e40
Synchronized with git revision 4222735eff5868389433f0e9271976b39c8115cd
Full URL: https://github.com/mbedmicro/mbed/commit/4222735eff5868389433f0e9271976b39c8115cd/
[NUCLEO_xxx] Update STM32CubeF4 driver V1.0.0 + update license
Who changed what in which revision?
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mbed_official | 87:085cde657901 | 1 | /** |
mbed_official | 87:085cde657901 | 2 | ****************************************************************************** |
mbed_official | 87:085cde657901 | 3 | * @file stm32f4xx_hal_dma.h |
mbed_official | 87:085cde657901 | 4 | * @author MCD Application Team |
mbed_official | 106:ced8cbb51063 | 5 | * @version V1.0.0 |
mbed_official | 106:ced8cbb51063 | 6 | * @date 18-February-2014 |
mbed_official | 87:085cde657901 | 7 | * @brief Header file of DMA HAL module. |
mbed_official | 87:085cde657901 | 8 | ****************************************************************************** |
mbed_official | 87:085cde657901 | 9 | * @attention |
mbed_official | 87:085cde657901 | 10 | * |
mbed_official | 87:085cde657901 | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
mbed_official | 87:085cde657901 | 12 | * |
mbed_official | 87:085cde657901 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
mbed_official | 87:085cde657901 | 14 | * are permitted provided that the following conditions are met: |
mbed_official | 87:085cde657901 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
mbed_official | 87:085cde657901 | 16 | * this list of conditions and the following disclaimer. |
mbed_official | 87:085cde657901 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
mbed_official | 87:085cde657901 | 18 | * this list of conditions and the following disclaimer in the documentation |
mbed_official | 87:085cde657901 | 19 | * and/or other materials provided with the distribution. |
mbed_official | 87:085cde657901 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
mbed_official | 87:085cde657901 | 21 | * may be used to endorse or promote products derived from this software |
mbed_official | 87:085cde657901 | 22 | * without specific prior written permission. |
mbed_official | 87:085cde657901 | 23 | * |
mbed_official | 87:085cde657901 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
mbed_official | 87:085cde657901 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
mbed_official | 87:085cde657901 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
mbed_official | 87:085cde657901 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
mbed_official | 87:085cde657901 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
mbed_official | 87:085cde657901 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
mbed_official | 87:085cde657901 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
mbed_official | 87:085cde657901 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
mbed_official | 87:085cde657901 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
mbed_official | 87:085cde657901 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 87:085cde657901 | 34 | * |
mbed_official | 87:085cde657901 | 35 | ****************************************************************************** |
mbed_official | 87:085cde657901 | 36 | */ |
mbed_official | 87:085cde657901 | 37 | |
mbed_official | 87:085cde657901 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
mbed_official | 87:085cde657901 | 39 | #ifndef __STM32F4xx_HAL_DMA_H |
mbed_official | 87:085cde657901 | 40 | #define __STM32F4xx_HAL_DMA_H |
mbed_official | 87:085cde657901 | 41 | |
mbed_official | 87:085cde657901 | 42 | #ifdef __cplusplus |
mbed_official | 87:085cde657901 | 43 | extern "C" { |
mbed_official | 87:085cde657901 | 44 | #endif |
mbed_official | 87:085cde657901 | 45 | |
mbed_official | 87:085cde657901 | 46 | /* Includes ------------------------------------------------------------------*/ |
mbed_official | 87:085cde657901 | 47 | #include "stm32f4xx_hal_def.h" |
mbed_official | 87:085cde657901 | 48 | |
mbed_official | 87:085cde657901 | 49 | /** @addtogroup STM32F4xx_HAL_Driver |
mbed_official | 87:085cde657901 | 50 | * @{ |
mbed_official | 87:085cde657901 | 51 | */ |
mbed_official | 87:085cde657901 | 52 | |
mbed_official | 87:085cde657901 | 53 | /** @addtogroup DMA |
mbed_official | 87:085cde657901 | 54 | * @{ |
mbed_official | 87:085cde657901 | 55 | */ |
mbed_official | 87:085cde657901 | 56 | |
mbed_official | 87:085cde657901 | 57 | /* Exported types ------------------------------------------------------------*/ |
mbed_official | 87:085cde657901 | 58 | |
mbed_official | 87:085cde657901 | 59 | /** |
mbed_official | 87:085cde657901 | 60 | * @brief DMA Configuration Structure definition |
mbed_official | 87:085cde657901 | 61 | */ |
mbed_official | 87:085cde657901 | 62 | typedef struct |
mbed_official | 87:085cde657901 | 63 | { |
mbed_official | 87:085cde657901 | 64 | uint32_t Channel; /*!< Specifies the channel used for the specified stream. |
mbed_official | 87:085cde657901 | 65 | This parameter can be a value of @ref DMA_Channel_selection */ |
mbed_official | 87:085cde657901 | 66 | |
mbed_official | 87:085cde657901 | 67 | uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, |
mbed_official | 87:085cde657901 | 68 | from memory to memory or from peripheral to memory. |
mbed_official | 87:085cde657901 | 69 | This parameter can be a value of @ref DMA_Data_transfer_direction */ |
mbed_official | 87:085cde657901 | 70 | |
mbed_official | 87:085cde657901 | 71 | uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. |
mbed_official | 87:085cde657901 | 72 | This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ |
mbed_official | 87:085cde657901 | 73 | |
mbed_official | 87:085cde657901 | 74 | uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. |
mbed_official | 87:085cde657901 | 75 | This parameter can be a value of @ref DMA_Memory_incremented_mode */ |
mbed_official | 87:085cde657901 | 76 | |
mbed_official | 87:085cde657901 | 77 | uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. |
mbed_official | 87:085cde657901 | 78 | This parameter can be a value of @ref DMA_Peripheral_data_size */ |
mbed_official | 87:085cde657901 | 79 | |
mbed_official | 87:085cde657901 | 80 | uint32_t MemDataAlignment; /*!< Specifies the Memory data width. |
mbed_official | 87:085cde657901 | 81 | This parameter can be a value of @ref DMA_Memory_data_size */ |
mbed_official | 87:085cde657901 | 82 | |
mbed_official | 87:085cde657901 | 83 | uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx. |
mbed_official | 87:085cde657901 | 84 | This parameter can be a value of @ref DMA_mode |
mbed_official | 87:085cde657901 | 85 | @note The circular buffer mode cannot be used if the memory-to-memory |
mbed_official | 87:085cde657901 | 86 | data transfer is configured on the selected Stream */ |
mbed_official | 87:085cde657901 | 87 | |
mbed_official | 87:085cde657901 | 88 | uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx. |
mbed_official | 87:085cde657901 | 89 | This parameter can be a value of @ref DMA_Priority_level */ |
mbed_official | 87:085cde657901 | 90 | |
mbed_official | 87:085cde657901 | 91 | uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. |
mbed_official | 87:085cde657901 | 92 | This parameter can be a value of @ref DMA_FIFO_direct_mode |
mbed_official | 87:085cde657901 | 93 | @note The Direct mode (FIFO mode disabled) cannot be used if the |
mbed_official | 87:085cde657901 | 94 | memory-to-memory data transfer is configured on the selected stream */ |
mbed_official | 87:085cde657901 | 95 | |
mbed_official | 87:085cde657901 | 96 | uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. |
mbed_official | 87:085cde657901 | 97 | This parameter can be a value of @ref DMA_FIFO_threshold_level */ |
mbed_official | 87:085cde657901 | 98 | |
mbed_official | 87:085cde657901 | 99 | uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. |
mbed_official | 87:085cde657901 | 100 | It specifies the amount of data to be transferred in a single non interruptable |
mbed_official | 87:085cde657901 | 101 | transaction. |
mbed_official | 87:085cde657901 | 102 | This parameter can be a value of @ref DMA_Memory_burst |
mbed_official | 87:085cde657901 | 103 | @note The burst mode is possible only if the address Increment mode is enabled. */ |
mbed_official | 87:085cde657901 | 104 | |
mbed_official | 87:085cde657901 | 105 | uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. |
mbed_official | 87:085cde657901 | 106 | It specifies the amount of data to be transferred in a single non interruptable |
mbed_official | 87:085cde657901 | 107 | transaction. |
mbed_official | 87:085cde657901 | 108 | This parameter can be a value of @ref DMA_Peripheral_burst |
mbed_official | 87:085cde657901 | 109 | @note The burst mode is possible only if the address Increment mode is enabled. */ |
mbed_official | 87:085cde657901 | 110 | |
mbed_official | 87:085cde657901 | 111 | }DMA_InitTypeDef; |
mbed_official | 87:085cde657901 | 112 | |
mbed_official | 87:085cde657901 | 113 | /** |
mbed_official | 87:085cde657901 | 114 | * @brief HAL DMA State structures definition |
mbed_official | 87:085cde657901 | 115 | */ |
mbed_official | 87:085cde657901 | 116 | typedef enum |
mbed_official | 87:085cde657901 | 117 | { |
mbed_official | 87:085cde657901 | 118 | HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */ |
mbed_official | 87:085cde657901 | 119 | HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */ |
mbed_official | 87:085cde657901 | 120 | HAL_DMA_STATE_READY_MEM0 = 0x11, /*!< DMA Mem0 process success */ |
mbed_official | 87:085cde657901 | 121 | HAL_DMA_STATE_READY_MEM1 = 0x21, /*!< DMA Mem1 process success */ |
mbed_official | 87:085cde657901 | 122 | HAL_DMA_STATE_READY_HALF_MEM0 = 0x31, /*!< DMA Mem0 Half process success */ |
mbed_official | 87:085cde657901 | 123 | HAL_DMA_STATE_READY_HALF_MEM1 = 0x41, /*!< DMA Mem1 Half process success */ |
mbed_official | 87:085cde657901 | 124 | HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */ |
mbed_official | 87:085cde657901 | 125 | HAL_DMA_STATE_BUSY_MEM0 = 0x12, /*!< DMA Mem0 process is ongoing */ |
mbed_official | 87:085cde657901 | 126 | HAL_DMA_STATE_BUSY_MEM1 = 0x22, /*!< DMA Mem1 process is ongoing */ |
mbed_official | 87:085cde657901 | 127 | HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */ |
mbed_official | 87:085cde657901 | 128 | HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */ |
mbed_official | 87:085cde657901 | 129 | |
mbed_official | 87:085cde657901 | 130 | }HAL_DMA_StateTypeDef; |
mbed_official | 87:085cde657901 | 131 | |
mbed_official | 87:085cde657901 | 132 | /** |
mbed_official | 87:085cde657901 | 133 | * @brief HAL DMA Error Code structure definition |
mbed_official | 87:085cde657901 | 134 | */ |
mbed_official | 87:085cde657901 | 135 | typedef enum |
mbed_official | 87:085cde657901 | 136 | { |
mbed_official | 87:085cde657901 | 137 | HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */ |
mbed_official | 87:085cde657901 | 138 | HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */ |
mbed_official | 87:085cde657901 | 139 | |
mbed_official | 87:085cde657901 | 140 | }HAL_DMA_LevelCompleteTypeDef; |
mbed_official | 87:085cde657901 | 141 | |
mbed_official | 87:085cde657901 | 142 | |
mbed_official | 87:085cde657901 | 143 | /** |
mbed_official | 87:085cde657901 | 144 | * @brief DMA handle Structure definition |
mbed_official | 87:085cde657901 | 145 | */ |
mbed_official | 87:085cde657901 | 146 | typedef struct __DMA_HandleTypeDef |
mbed_official | 87:085cde657901 | 147 | { |
mbed_official | 87:085cde657901 | 148 | DMA_Stream_TypeDef *Instance; /*!< Register base address */ |
mbed_official | 87:085cde657901 | 149 | |
mbed_official | 87:085cde657901 | 150 | DMA_InitTypeDef Init; /*!< DMA communication parameters */ |
mbed_official | 87:085cde657901 | 151 | |
mbed_official | 87:085cde657901 | 152 | HAL_LockTypeDef Lock; /*!< DMA locking object */ |
mbed_official | 87:085cde657901 | 153 | |
mbed_official | 87:085cde657901 | 154 | __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ |
mbed_official | 87:085cde657901 | 155 | |
mbed_official | 87:085cde657901 | 156 | void *Parent; /*!< Parent object state */ |
mbed_official | 87:085cde657901 | 157 | |
mbed_official | 87:085cde657901 | 158 | void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ |
mbed_official | 87:085cde657901 | 159 | |
mbed_official | 87:085cde657901 | 160 | void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ |
mbed_official | 87:085cde657901 | 161 | |
mbed_official | 87:085cde657901 | 162 | void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */ |
mbed_official | 87:085cde657901 | 163 | |
mbed_official | 87:085cde657901 | 164 | void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ |
mbed_official | 87:085cde657901 | 165 | |
mbed_official | 87:085cde657901 | 166 | __IO uint32_t ErrorCode; /*!< DMA Error code */ |
mbed_official | 87:085cde657901 | 167 | |
mbed_official | 87:085cde657901 | 168 | }DMA_HandleTypeDef; |
mbed_official | 87:085cde657901 | 169 | |
mbed_official | 87:085cde657901 | 170 | /* Exported constants --------------------------------------------------------*/ |
mbed_official | 87:085cde657901 | 171 | |
mbed_official | 87:085cde657901 | 172 | /** @defgroup DMA_Exported_Constants |
mbed_official | 87:085cde657901 | 173 | * @{ |
mbed_official | 87:085cde657901 | 174 | */ |
mbed_official | 87:085cde657901 | 175 | |
mbed_official | 87:085cde657901 | 176 | /** @defgroup DMA_Error_Code |
mbed_official | 87:085cde657901 | 177 | * @{ |
mbed_official | 87:085cde657901 | 178 | */ |
mbed_official | 87:085cde657901 | 179 | #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ |
mbed_official | 87:085cde657901 | 180 | #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */ |
mbed_official | 87:085cde657901 | 181 | #define HAL_DMA_ERROR_FE ((uint32_t)0x00000002) /*!< FIFO error */ |
mbed_official | 87:085cde657901 | 182 | #define HAL_DMA_ERROR_DME ((uint32_t)0x00000004) /*!< Direct Mode error */ |
mbed_official | 87:085cde657901 | 183 | #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ |
mbed_official | 87:085cde657901 | 184 | /** |
mbed_official | 87:085cde657901 | 185 | * @} |
mbed_official | 87:085cde657901 | 186 | */ |
mbed_official | 87:085cde657901 | 187 | |
mbed_official | 87:085cde657901 | 188 | /** @defgroup DMA_Channel_selection |
mbed_official | 87:085cde657901 | 189 | * @{ |
mbed_official | 87:085cde657901 | 190 | */ |
mbed_official | 87:085cde657901 | 191 | #define DMA_CHANNEL_0 ((uint32_t)0x00000000) /*!< DMA Channel 0 */ |
mbed_official | 87:085cde657901 | 192 | #define DMA_CHANNEL_1 ((uint32_t)0x02000000) /*!< DMA Channel 1 */ |
mbed_official | 87:085cde657901 | 193 | #define DMA_CHANNEL_2 ((uint32_t)0x04000000) /*!< DMA Channel 2 */ |
mbed_official | 87:085cde657901 | 194 | #define DMA_CHANNEL_3 ((uint32_t)0x06000000) /*!< DMA Channel 3 */ |
mbed_official | 87:085cde657901 | 195 | #define DMA_CHANNEL_4 ((uint32_t)0x08000000) /*!< DMA Channel 4 */ |
mbed_official | 87:085cde657901 | 196 | #define DMA_CHANNEL_5 ((uint32_t)0x0A000000) /*!< DMA Channel 5 */ |
mbed_official | 87:085cde657901 | 197 | #define DMA_CHANNEL_6 ((uint32_t)0x0C000000) /*!< DMA Channel 6 */ |
mbed_official | 87:085cde657901 | 198 | #define DMA_CHANNEL_7 ((uint32_t)0x0E000000) /*!< DMA Channel 7 */ |
mbed_official | 87:085cde657901 | 199 | |
mbed_official | 87:085cde657901 | 200 | #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ |
mbed_official | 87:085cde657901 | 201 | ((CHANNEL) == DMA_CHANNEL_1) || \ |
mbed_official | 87:085cde657901 | 202 | ((CHANNEL) == DMA_CHANNEL_2) || \ |
mbed_official | 87:085cde657901 | 203 | ((CHANNEL) == DMA_CHANNEL_3) || \ |
mbed_official | 87:085cde657901 | 204 | ((CHANNEL) == DMA_CHANNEL_4) || \ |
mbed_official | 87:085cde657901 | 205 | ((CHANNEL) == DMA_CHANNEL_5) || \ |
mbed_official | 87:085cde657901 | 206 | ((CHANNEL) == DMA_CHANNEL_6) || \ |
mbed_official | 87:085cde657901 | 207 | ((CHANNEL) == DMA_CHANNEL_7)) |
mbed_official | 87:085cde657901 | 208 | /** |
mbed_official | 87:085cde657901 | 209 | * @} |
mbed_official | 87:085cde657901 | 210 | */ |
mbed_official | 87:085cde657901 | 211 | |
mbed_official | 87:085cde657901 | 212 | /** @defgroup DMA_Data_transfer_direction |
mbed_official | 87:085cde657901 | 213 | * @{ |
mbed_official | 87:085cde657901 | 214 | */ |
mbed_official | 87:085cde657901 | 215 | #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */ |
mbed_official | 87:085cde657901 | 216 | #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */ |
mbed_official | 87:085cde657901 | 217 | #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */ |
mbed_official | 87:085cde657901 | 218 | |
mbed_official | 87:085cde657901 | 219 | #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ |
mbed_official | 87:085cde657901 | 220 | ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ |
mbed_official | 87:085cde657901 | 221 | ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) |
mbed_official | 87:085cde657901 | 222 | /** |
mbed_official | 87:085cde657901 | 223 | * @} |
mbed_official | 87:085cde657901 | 224 | */ |
mbed_official | 87:085cde657901 | 225 | |
mbed_official | 87:085cde657901 | 226 | /** @defgroup DMA_Data_buffer_size |
mbed_official | 87:085cde657901 | 227 | * @{ |
mbed_official | 87:085cde657901 | 228 | */ |
mbed_official | 87:085cde657901 | 229 | #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) |
mbed_official | 87:085cde657901 | 230 | /** |
mbed_official | 87:085cde657901 | 231 | * @} |
mbed_official | 87:085cde657901 | 232 | */ |
mbed_official | 87:085cde657901 | 233 | |
mbed_official | 87:085cde657901 | 234 | /** @defgroup DMA_Peripheral_incremented_mode |
mbed_official | 87:085cde657901 | 235 | * @{ |
mbed_official | 87:085cde657901 | 236 | */ |
mbed_official | 87:085cde657901 | 237 | #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */ |
mbed_official | 87:085cde657901 | 238 | #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode disable */ |
mbed_official | 87:085cde657901 | 239 | |
mbed_official | 87:085cde657901 | 240 | #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ |
mbed_official | 87:085cde657901 | 241 | ((STATE) == DMA_PINC_DISABLE)) |
mbed_official | 87:085cde657901 | 242 | /** |
mbed_official | 87:085cde657901 | 243 | * @} |
mbed_official | 87:085cde657901 | 244 | */ |
mbed_official | 87:085cde657901 | 245 | |
mbed_official | 87:085cde657901 | 246 | /** @defgroup DMA_Memory_incremented_mode |
mbed_official | 87:085cde657901 | 247 | * @{ |
mbed_official | 87:085cde657901 | 248 | */ |
mbed_official | 87:085cde657901 | 249 | #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */ |
mbed_official | 87:085cde657901 | 250 | #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode disable */ |
mbed_official | 87:085cde657901 | 251 | |
mbed_official | 87:085cde657901 | 252 | #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ |
mbed_official | 87:085cde657901 | 253 | ((STATE) == DMA_MINC_DISABLE)) |
mbed_official | 87:085cde657901 | 254 | /** |
mbed_official | 87:085cde657901 | 255 | * @} |
mbed_official | 87:085cde657901 | 256 | */ |
mbed_official | 87:085cde657901 | 257 | |
mbed_official | 87:085cde657901 | 258 | /** @defgroup DMA_Peripheral_data_size |
mbed_official | 87:085cde657901 | 259 | * @{ |
mbed_official | 87:085cde657901 | 260 | */ |
mbed_official | 87:085cde657901 | 261 | #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment: Byte */ |
mbed_official | 87:085cde657901 | 262 | #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ |
mbed_official | 87:085cde657901 | 263 | #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */ |
mbed_official | 87:085cde657901 | 264 | |
mbed_official | 87:085cde657901 | 265 | #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ |
mbed_official | 87:085cde657901 | 266 | ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ |
mbed_official | 87:085cde657901 | 267 | ((SIZE) == DMA_PDATAALIGN_WORD)) |
mbed_official | 87:085cde657901 | 268 | /** |
mbed_official | 87:085cde657901 | 269 | * @} |
mbed_official | 87:085cde657901 | 270 | */ |
mbed_official | 87:085cde657901 | 271 | |
mbed_official | 87:085cde657901 | 272 | |
mbed_official | 87:085cde657901 | 273 | /** @defgroup DMA_Memory_data_size |
mbed_official | 87:085cde657901 | 274 | * @{ |
mbed_official | 87:085cde657901 | 275 | */ |
mbed_official | 87:085cde657901 | 276 | #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment: Byte */ |
mbed_official | 87:085cde657901 | 277 | #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ |
mbed_official | 87:085cde657901 | 278 | #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */ |
mbed_official | 87:085cde657901 | 279 | |
mbed_official | 87:085cde657901 | 280 | #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ |
mbed_official | 87:085cde657901 | 281 | ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ |
mbed_official | 87:085cde657901 | 282 | ((SIZE) == DMA_MDATAALIGN_WORD )) |
mbed_official | 87:085cde657901 | 283 | /** |
mbed_official | 87:085cde657901 | 284 | * @} |
mbed_official | 87:085cde657901 | 285 | */ |
mbed_official | 87:085cde657901 | 286 | |
mbed_official | 87:085cde657901 | 287 | /** @defgroup DMA_mode |
mbed_official | 87:085cde657901 | 288 | * @{ |
mbed_official | 87:085cde657901 | 289 | */ |
mbed_official | 87:085cde657901 | 290 | #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */ |
mbed_official | 87:085cde657901 | 291 | #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */ |
mbed_official | 87:085cde657901 | 292 | #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */ |
mbed_official | 87:085cde657901 | 293 | |
mbed_official | 87:085cde657901 | 294 | #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ |
mbed_official | 87:085cde657901 | 295 | ((MODE) == DMA_CIRCULAR) || \ |
mbed_official | 87:085cde657901 | 296 | ((MODE) == DMA_PFCTRL)) |
mbed_official | 87:085cde657901 | 297 | /** |
mbed_official | 87:085cde657901 | 298 | * @} |
mbed_official | 87:085cde657901 | 299 | */ |
mbed_official | 87:085cde657901 | 300 | |
mbed_official | 87:085cde657901 | 301 | /** @defgroup DMA_Priority_level |
mbed_official | 87:085cde657901 | 302 | * @{ |
mbed_official | 87:085cde657901 | 303 | */ |
mbed_official | 87:085cde657901 | 304 | #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level: Low */ |
mbed_official | 87:085cde657901 | 305 | #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */ |
mbed_official | 87:085cde657901 | 306 | #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */ |
mbed_official | 87:085cde657901 | 307 | #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */ |
mbed_official | 87:085cde657901 | 308 | |
mbed_official | 87:085cde657901 | 309 | #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ |
mbed_official | 87:085cde657901 | 310 | ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ |
mbed_official | 87:085cde657901 | 311 | ((PRIORITY) == DMA_PRIORITY_HIGH) || \ |
mbed_official | 87:085cde657901 | 312 | ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) |
mbed_official | 87:085cde657901 | 313 | /** |
mbed_official | 87:085cde657901 | 314 | * @} |
mbed_official | 87:085cde657901 | 315 | */ |
mbed_official | 87:085cde657901 | 316 | |
mbed_official | 87:085cde657901 | 317 | /** @defgroup DMA_FIFO_direct_mode |
mbed_official | 87:085cde657901 | 318 | * @{ |
mbed_official | 87:085cde657901 | 319 | */ |
mbed_official | 87:085cde657901 | 320 | #define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000) /*!< FIFO mode disable */ |
mbed_official | 87:085cde657901 | 321 | #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */ |
mbed_official | 87:085cde657901 | 322 | |
mbed_official | 87:085cde657901 | 323 | #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \ |
mbed_official | 87:085cde657901 | 324 | ((STATE) == DMA_FIFOMODE_ENABLE)) |
mbed_official | 87:085cde657901 | 325 | /** |
mbed_official | 87:085cde657901 | 326 | * @} |
mbed_official | 87:085cde657901 | 327 | */ |
mbed_official | 87:085cde657901 | 328 | |
mbed_official | 87:085cde657901 | 329 | /** @defgroup DMA_FIFO_threshold_level |
mbed_official | 87:085cde657901 | 330 | * @{ |
mbed_official | 87:085cde657901 | 331 | */ |
mbed_official | 87:085cde657901 | 332 | #define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000) /*!< FIFO threshold 1 quart full configuration */ |
mbed_official | 87:085cde657901 | 333 | #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */ |
mbed_official | 87:085cde657901 | 334 | #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */ |
mbed_official | 87:085cde657901 | 335 | #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */ |
mbed_official | 87:085cde657901 | 336 | |
mbed_official | 87:085cde657901 | 337 | #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \ |
mbed_official | 87:085cde657901 | 338 | ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \ |
mbed_official | 87:085cde657901 | 339 | ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \ |
mbed_official | 87:085cde657901 | 340 | ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL)) |
mbed_official | 87:085cde657901 | 341 | /** |
mbed_official | 87:085cde657901 | 342 | * @} |
mbed_official | 87:085cde657901 | 343 | */ |
mbed_official | 87:085cde657901 | 344 | |
mbed_official | 87:085cde657901 | 345 | /** @defgroup DMA_Memory_burst |
mbed_official | 87:085cde657901 | 346 | * @{ |
mbed_official | 87:085cde657901 | 347 | */ |
mbed_official | 87:085cde657901 | 348 | #define DMA_MBURST_SINGLE ((uint32_t)0x00000000) |
mbed_official | 87:085cde657901 | 349 | #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0) |
mbed_official | 87:085cde657901 | 350 | #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1) |
mbed_official | 87:085cde657901 | 351 | #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST) |
mbed_official | 87:085cde657901 | 352 | |
mbed_official | 87:085cde657901 | 353 | #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \ |
mbed_official | 87:085cde657901 | 354 | ((BURST) == DMA_MBURST_INC4) || \ |
mbed_official | 87:085cde657901 | 355 | ((BURST) == DMA_MBURST_INC8) || \ |
mbed_official | 87:085cde657901 | 356 | ((BURST) == DMA_MBURST_INC16)) |
mbed_official | 87:085cde657901 | 357 | /** |
mbed_official | 87:085cde657901 | 358 | * @} |
mbed_official | 87:085cde657901 | 359 | */ |
mbed_official | 87:085cde657901 | 360 | |
mbed_official | 87:085cde657901 | 361 | /** @defgroup DMA_Peripheral_burst |
mbed_official | 87:085cde657901 | 362 | * @{ |
mbed_official | 87:085cde657901 | 363 | */ |
mbed_official | 87:085cde657901 | 364 | #define DMA_PBURST_SINGLE ((uint32_t)0x00000000) |
mbed_official | 87:085cde657901 | 365 | #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0) |
mbed_official | 87:085cde657901 | 366 | #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1) |
mbed_official | 87:085cde657901 | 367 | #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST) |
mbed_official | 87:085cde657901 | 368 | |
mbed_official | 87:085cde657901 | 369 | #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \ |
mbed_official | 87:085cde657901 | 370 | ((BURST) == DMA_PBURST_INC4) || \ |
mbed_official | 87:085cde657901 | 371 | ((BURST) == DMA_PBURST_INC8) || \ |
mbed_official | 87:085cde657901 | 372 | ((BURST) == DMA_PBURST_INC16)) |
mbed_official | 87:085cde657901 | 373 | /** |
mbed_official | 87:085cde657901 | 374 | * @} |
mbed_official | 87:085cde657901 | 375 | */ |
mbed_official | 87:085cde657901 | 376 | |
mbed_official | 87:085cde657901 | 377 | /** @defgroup DMA_interrupt_enable_definitions |
mbed_official | 87:085cde657901 | 378 | * @{ |
mbed_official | 87:085cde657901 | 379 | */ |
mbed_official | 87:085cde657901 | 380 | #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE) |
mbed_official | 87:085cde657901 | 381 | #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE) |
mbed_official | 87:085cde657901 | 382 | #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE) |
mbed_official | 87:085cde657901 | 383 | #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE) |
mbed_official | 87:085cde657901 | 384 | #define DMA_IT_FE ((uint32_t)0x00000080) |
mbed_official | 87:085cde657901 | 385 | /** |
mbed_official | 87:085cde657901 | 386 | * @} |
mbed_official | 87:085cde657901 | 387 | */ |
mbed_official | 87:085cde657901 | 388 | |
mbed_official | 87:085cde657901 | 389 | /** @defgroup DMA_flag_definitions |
mbed_official | 87:085cde657901 | 390 | * @{ |
mbed_official | 87:085cde657901 | 391 | */ |
mbed_official | 87:085cde657901 | 392 | #define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001) |
mbed_official | 87:085cde657901 | 393 | #define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004) |
mbed_official | 87:085cde657901 | 394 | #define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008) |
mbed_official | 87:085cde657901 | 395 | #define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010) |
mbed_official | 87:085cde657901 | 396 | #define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020) |
mbed_official | 87:085cde657901 | 397 | #define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040) |
mbed_official | 87:085cde657901 | 398 | #define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100) |
mbed_official | 87:085cde657901 | 399 | #define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200) |
mbed_official | 87:085cde657901 | 400 | #define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400) |
mbed_official | 87:085cde657901 | 401 | #define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800) |
mbed_official | 87:085cde657901 | 402 | #define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000) |
mbed_official | 87:085cde657901 | 403 | #define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000) |
mbed_official | 87:085cde657901 | 404 | #define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000) |
mbed_official | 87:085cde657901 | 405 | #define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000) |
mbed_official | 87:085cde657901 | 406 | #define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000) |
mbed_official | 87:085cde657901 | 407 | #define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000) |
mbed_official | 87:085cde657901 | 408 | #define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000) |
mbed_official | 87:085cde657901 | 409 | #define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000) |
mbed_official | 87:085cde657901 | 410 | #define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000) |
mbed_official | 87:085cde657901 | 411 | #define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000) |
mbed_official | 87:085cde657901 | 412 | /** |
mbed_official | 87:085cde657901 | 413 | * @} |
mbed_official | 87:085cde657901 | 414 | */ |
mbed_official | 87:085cde657901 | 415 | |
mbed_official | 87:085cde657901 | 416 | /** |
mbed_official | 87:085cde657901 | 417 | * @} |
mbed_official | 87:085cde657901 | 418 | */ |
mbed_official | 87:085cde657901 | 419 | |
mbed_official | 87:085cde657901 | 420 | /* Exported macro ------------------------------------------------------------*/ |
mbed_official | 87:085cde657901 | 421 | /** |
mbed_official | 87:085cde657901 | 422 | * @brief Return the current DMA Stream FIFO filled level. |
mbed_official | 87:085cde657901 | 423 | * @param __HANDLE__: DMA handle |
mbed_official | 87:085cde657901 | 424 | * @retval The FIFO filling state. |
mbed_official | 87:085cde657901 | 425 | * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full |
mbed_official | 87:085cde657901 | 426 | * and not empty. |
mbed_official | 87:085cde657901 | 427 | * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. |
mbed_official | 87:085cde657901 | 428 | * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. |
mbed_official | 87:085cde657901 | 429 | * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. |
mbed_official | 87:085cde657901 | 430 | * - DMA_FIFOStatus_Empty: when FIFO is empty |
mbed_official | 87:085cde657901 | 431 | * - DMA_FIFOStatus_Full: when FIFO is full |
mbed_official | 87:085cde657901 | 432 | */ |
mbed_official | 87:085cde657901 | 433 | #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS))) |
mbed_official | 87:085cde657901 | 434 | |
mbed_official | 87:085cde657901 | 435 | /** |
mbed_official | 87:085cde657901 | 436 | * @brief Enable the specified DMA Stream. |
mbed_official | 87:085cde657901 | 437 | * @param __HANDLE__: DMA handle |
mbed_official | 87:085cde657901 | 438 | * @retval None |
mbed_official | 87:085cde657901 | 439 | */ |
mbed_official | 87:085cde657901 | 440 | #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN) |
mbed_official | 87:085cde657901 | 441 | |
mbed_official | 87:085cde657901 | 442 | /** |
mbed_official | 87:085cde657901 | 443 | * @brief Disable the specified DMA Stream. |
mbed_official | 87:085cde657901 | 444 | * @param __HANDLE__: DMA handle |
mbed_official | 87:085cde657901 | 445 | * @retval None |
mbed_official | 87:085cde657901 | 446 | */ |
mbed_official | 87:085cde657901 | 447 | #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN) |
mbed_official | 87:085cde657901 | 448 | |
mbed_official | 87:085cde657901 | 449 | /* Interrupt & Flag management */ |
mbed_official | 87:085cde657901 | 450 | |
mbed_official | 87:085cde657901 | 451 | /** |
mbed_official | 87:085cde657901 | 452 | * @brief Return the current DMA Stream transfer complete flag. |
mbed_official | 87:085cde657901 | 453 | * @param __HANDLE__: DMA handle |
mbed_official | 87:085cde657901 | 454 | * @retval The specified transfer complete flag index. |
mbed_official | 87:085cde657901 | 455 | */ |
mbed_official | 87:085cde657901 | 456 | #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ |
mbed_official | 87:085cde657901 | 457 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\ |
mbed_official | 87:085cde657901 | 458 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\ |
mbed_official | 87:085cde657901 | 459 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\ |
mbed_official | 87:085cde657901 | 460 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\ |
mbed_official | 87:085cde657901 | 461 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\ |
mbed_official | 87:085cde657901 | 462 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\ |
mbed_official | 87:085cde657901 | 463 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\ |
mbed_official | 87:085cde657901 | 464 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\ |
mbed_official | 87:085cde657901 | 465 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\ |
mbed_official | 87:085cde657901 | 466 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\ |
mbed_official | 87:085cde657901 | 467 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\ |
mbed_official | 87:085cde657901 | 468 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\ |
mbed_official | 87:085cde657901 | 469 | DMA_FLAG_TCIF3_7) |
mbed_official | 87:085cde657901 | 470 | |
mbed_official | 87:085cde657901 | 471 | /** |
mbed_official | 87:085cde657901 | 472 | * @brief Return the current DMA Stream half transfer complete flag. |
mbed_official | 87:085cde657901 | 473 | * @param __HANDLE__: DMA handle |
mbed_official | 87:085cde657901 | 474 | * @retval The specified half transfer complete flag index. |
mbed_official | 87:085cde657901 | 475 | */ |
mbed_official | 87:085cde657901 | 476 | #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ |
mbed_official | 87:085cde657901 | 477 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\ |
mbed_official | 87:085cde657901 | 478 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\ |
mbed_official | 87:085cde657901 | 479 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\ |
mbed_official | 87:085cde657901 | 480 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\ |
mbed_official | 87:085cde657901 | 481 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\ |
mbed_official | 87:085cde657901 | 482 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\ |
mbed_official | 87:085cde657901 | 483 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\ |
mbed_official | 87:085cde657901 | 484 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\ |
mbed_official | 87:085cde657901 | 485 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\ |
mbed_official | 87:085cde657901 | 486 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\ |
mbed_official | 87:085cde657901 | 487 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\ |
mbed_official | 87:085cde657901 | 488 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\ |
mbed_official | 87:085cde657901 | 489 | DMA_FLAG_HTIF3_7) |
mbed_official | 87:085cde657901 | 490 | |
mbed_official | 87:085cde657901 | 491 | /** |
mbed_official | 87:085cde657901 | 492 | * @brief Return the current DMA Stream transfer error flag. |
mbed_official | 87:085cde657901 | 493 | * @param __HANDLE__: DMA handle |
mbed_official | 87:085cde657901 | 494 | * @retval The specified transfer error flag index. |
mbed_official | 87:085cde657901 | 495 | */ |
mbed_official | 87:085cde657901 | 496 | #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ |
mbed_official | 87:085cde657901 | 497 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\ |
mbed_official | 87:085cde657901 | 498 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\ |
mbed_official | 87:085cde657901 | 499 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\ |
mbed_official | 87:085cde657901 | 500 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\ |
mbed_official | 87:085cde657901 | 501 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\ |
mbed_official | 87:085cde657901 | 502 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\ |
mbed_official | 87:085cde657901 | 503 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\ |
mbed_official | 87:085cde657901 | 504 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\ |
mbed_official | 87:085cde657901 | 505 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\ |
mbed_official | 87:085cde657901 | 506 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\ |
mbed_official | 87:085cde657901 | 507 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\ |
mbed_official | 87:085cde657901 | 508 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\ |
mbed_official | 87:085cde657901 | 509 | DMA_FLAG_TEIF3_7) |
mbed_official | 87:085cde657901 | 510 | |
mbed_official | 87:085cde657901 | 511 | /** |
mbed_official | 87:085cde657901 | 512 | * @brief Return the current DMA Stream FIFO error flag. |
mbed_official | 87:085cde657901 | 513 | * @param __HANDLE__: DMA handle |
mbed_official | 87:085cde657901 | 514 | * @retval The specified FIFO error flag index. |
mbed_official | 87:085cde657901 | 515 | */ |
mbed_official | 87:085cde657901 | 516 | #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\ |
mbed_official | 87:085cde657901 | 517 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\ |
mbed_official | 87:085cde657901 | 518 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\ |
mbed_official | 87:085cde657901 | 519 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\ |
mbed_official | 87:085cde657901 | 520 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\ |
mbed_official | 87:085cde657901 | 521 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\ |
mbed_official | 87:085cde657901 | 522 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\ |
mbed_official | 87:085cde657901 | 523 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\ |
mbed_official | 87:085cde657901 | 524 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\ |
mbed_official | 87:085cde657901 | 525 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\ |
mbed_official | 87:085cde657901 | 526 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\ |
mbed_official | 87:085cde657901 | 527 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\ |
mbed_official | 87:085cde657901 | 528 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\ |
mbed_official | 87:085cde657901 | 529 | DMA_FLAG_FEIF3_7) |
mbed_official | 87:085cde657901 | 530 | |
mbed_official | 87:085cde657901 | 531 | /** |
mbed_official | 87:085cde657901 | 532 | * @brief Return the current DMA Stream direct mode error flag. |
mbed_official | 87:085cde657901 | 533 | * @param __HANDLE__: DMA handle |
mbed_official | 87:085cde657901 | 534 | * @retval The specified direct mode error flag index. |
mbed_official | 87:085cde657901 | 535 | */ |
mbed_official | 87:085cde657901 | 536 | #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\ |
mbed_official | 87:085cde657901 | 537 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\ |
mbed_official | 87:085cde657901 | 538 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\ |
mbed_official | 87:085cde657901 | 539 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\ |
mbed_official | 87:085cde657901 | 540 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\ |
mbed_official | 87:085cde657901 | 541 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\ |
mbed_official | 87:085cde657901 | 542 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\ |
mbed_official | 87:085cde657901 | 543 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\ |
mbed_official | 87:085cde657901 | 544 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\ |
mbed_official | 87:085cde657901 | 545 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\ |
mbed_official | 87:085cde657901 | 546 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\ |
mbed_official | 87:085cde657901 | 547 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\ |
mbed_official | 87:085cde657901 | 548 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\ |
mbed_official | 87:085cde657901 | 549 | DMA_FLAG_DMEIF3_7) |
mbed_official | 87:085cde657901 | 550 | |
mbed_official | 87:085cde657901 | 551 | /** |
mbed_official | 87:085cde657901 | 552 | * @brief Get the DMA Stream pending flags. |
mbed_official | 87:085cde657901 | 553 | * @param __HANDLE__: DMA handle |
mbed_official | 87:085cde657901 | 554 | * @param __FLAG__: Get the specified flag. |
mbed_official | 87:085cde657901 | 555 | * This parameter can be any combination of the following values: |
mbed_official | 87:085cde657901 | 556 | * @arg DMA_FLAG_TCIFx: Transfer complete flag. |
mbed_official | 87:085cde657901 | 557 | * @arg DMA_FLAG_HTIFx: Half transfer complete flag. |
mbed_official | 87:085cde657901 | 558 | * @arg DMA_FLAG_TEIFx: Transfer error flag. |
mbed_official | 87:085cde657901 | 559 | * @arg DMA_FLAG_DMEIFx: Direct mode error flag. |
mbed_official | 87:085cde657901 | 560 | * @arg DMA_FLAG_FEIFx: FIFO error flag. |
mbed_official | 87:085cde657901 | 561 | * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. |
mbed_official | 87:085cde657901 | 562 | * @retval The state of FLAG (SET or RESET). |
mbed_official | 87:085cde657901 | 563 | */ |
mbed_official | 87:085cde657901 | 564 | #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ |
mbed_official | 87:085cde657901 | 565 | (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\ |
mbed_official | 87:085cde657901 | 566 | ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\ |
mbed_official | 87:085cde657901 | 567 | ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) |
mbed_official | 87:085cde657901 | 568 | |
mbed_official | 87:085cde657901 | 569 | /** |
mbed_official | 87:085cde657901 | 570 | * @brief Clear the DMA Stream pending flags. |
mbed_official | 87:085cde657901 | 571 | * @param __HANDLE__: DMA handle |
mbed_official | 87:085cde657901 | 572 | * @param __FLAG__: specifies the flag to clear. |
mbed_official | 87:085cde657901 | 573 | * This parameter can be any combination of the following values: |
mbed_official | 87:085cde657901 | 574 | * @arg DMA_FLAG_TCIFx: Transfer complete flag. |
mbed_official | 87:085cde657901 | 575 | * @arg DMA_FLAG_HTIFx: Half transfer complete flag. |
mbed_official | 87:085cde657901 | 576 | * @arg DMA_FLAG_TEIFx: Transfer error flag. |
mbed_official | 87:085cde657901 | 577 | * @arg DMA_FLAG_DMEIFx: Direct mode error flag. |
mbed_official | 87:085cde657901 | 578 | * @arg DMA_FLAG_FEIFx: FIFO error flag. |
mbed_official | 87:085cde657901 | 579 | * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. |
mbed_official | 87:085cde657901 | 580 | * @retval None |
mbed_official | 87:085cde657901 | 581 | */ |
mbed_official | 87:085cde657901 | 582 | #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ |
mbed_official | 87:085cde657901 | 583 | (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR |= (__FLAG__)) :\ |
mbed_official | 87:085cde657901 | 584 | ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR |= (__FLAG__)) :\ |
mbed_official | 87:085cde657901 | 585 | ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR |= (__FLAG__)) : (DMA1->LIFCR |= (__FLAG__))) |
mbed_official | 87:085cde657901 | 586 | |
mbed_official | 87:085cde657901 | 587 | /** |
mbed_official | 87:085cde657901 | 588 | * @brief Enable the specified DMA Stream interrupts. |
mbed_official | 87:085cde657901 | 589 | * @param __HANDLE__: DMA handle |
mbed_official | 87:085cde657901 | 590 | * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. |
mbed_official | 87:085cde657901 | 591 | * This parameter can be any combination of the following values: |
mbed_official | 87:085cde657901 | 592 | * @arg DMA_IT_TC: Transfer complete interrupt mask. |
mbed_official | 87:085cde657901 | 593 | * @arg DMA_IT_HT: Half transfer complete interrupt mask. |
mbed_official | 87:085cde657901 | 594 | * @arg DMA_IT_TE: Transfer error interrupt mask. |
mbed_official | 87:085cde657901 | 595 | * @arg DMA_IT_FE: FIFO error interrupt mask. |
mbed_official | 87:085cde657901 | 596 | * @arg DMA_IT_DME: Direct mode error interrupt. |
mbed_official | 87:085cde657901 | 597 | * @retval None |
mbed_official | 87:085cde657901 | 598 | */ |
mbed_official | 87:085cde657901 | 599 | #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ |
mbed_official | 87:085cde657901 | 600 | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__))) |
mbed_official | 87:085cde657901 | 601 | |
mbed_official | 87:085cde657901 | 602 | /** |
mbed_official | 87:085cde657901 | 603 | * @brief Disable the specified DMA Stream interrupts. |
mbed_official | 87:085cde657901 | 604 | * @param __HANDLE__: DMA handle |
mbed_official | 87:085cde657901 | 605 | * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. |
mbed_official | 87:085cde657901 | 606 | * This parameter can be any combination of the following values: |
mbed_official | 87:085cde657901 | 607 | * @arg DMA_IT_TC: Transfer complete interrupt mask. |
mbed_official | 87:085cde657901 | 608 | * @arg DMA_IT_HT: Half transfer complete interrupt mask. |
mbed_official | 87:085cde657901 | 609 | * @arg DMA_IT_TE: Transfer error interrupt mask. |
mbed_official | 87:085cde657901 | 610 | * @arg DMA_IT_FE: FIFO error interrupt mask. |
mbed_official | 87:085cde657901 | 611 | * @arg DMA_IT_DME: Direct mode error interrupt. |
mbed_official | 87:085cde657901 | 612 | * @retval None |
mbed_official | 87:085cde657901 | 613 | */ |
mbed_official | 87:085cde657901 | 614 | #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ |
mbed_official | 87:085cde657901 | 615 | ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__))) |
mbed_official | 87:085cde657901 | 616 | |
mbed_official | 87:085cde657901 | 617 | /** |
mbed_official | 87:085cde657901 | 618 | * @brief Check whether the specified DMA Stream interrupt has occurred or not. |
mbed_official | 87:085cde657901 | 619 | * @param __HANDLE__: DMA handle |
mbed_official | 87:085cde657901 | 620 | * @param __INTERRUPT__: specifies the DMA interrupt source to check. |
mbed_official | 87:085cde657901 | 621 | * This parameter can be one of the following values: |
mbed_official | 87:085cde657901 | 622 | * @arg DMA_IT_TC: Transfer complete interrupt mask. |
mbed_official | 87:085cde657901 | 623 | * @arg DMA_IT_HT: Half transfer complete interrupt mask. |
mbed_official | 87:085cde657901 | 624 | * @arg DMA_IT_TE: Transfer error interrupt mask. |
mbed_official | 87:085cde657901 | 625 | * @arg DMA_IT_FE: FIFO error interrupt mask. |
mbed_official | 87:085cde657901 | 626 | * @arg DMA_IT_DME: Direct mode error interrupt. |
mbed_official | 87:085cde657901 | 627 | * @retval The state of DMA_IT. |
mbed_official | 87:085cde657901 | 628 | */ |
mbed_official | 106:ced8cbb51063 | 629 | #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ |
mbed_official | 87:085cde657901 | 630 | ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \ |
mbed_official | 87:085cde657901 | 631 | ((__HANDLE__)->Instance->FCR & (__INTERRUPT__))) |
mbed_official | 87:085cde657901 | 632 | |
mbed_official | 87:085cde657901 | 633 | /** |
mbed_official | 87:085cde657901 | 634 | * @brief Writes the number of data units to be transferred on the DMA Stream. |
mbed_official | 87:085cde657901 | 635 | * @param __HANDLE__: DMA handle |
mbed_official | 87:085cde657901 | 636 | * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535) |
mbed_official | 87:085cde657901 | 637 | * Number of data items depends only on the Peripheral data format. |
mbed_official | 87:085cde657901 | 638 | * |
mbed_official | 87:085cde657901 | 639 | * @note If Peripheral data format is Bytes: number of data units is equal |
mbed_official | 87:085cde657901 | 640 | * to total number of bytes to be transferred. |
mbed_official | 87:085cde657901 | 641 | * |
mbed_official | 87:085cde657901 | 642 | * @note If Peripheral data format is Half-Word: number of data units is |
mbed_official | 87:085cde657901 | 643 | * equal to total number of bytes to be transferred / 2. |
mbed_official | 87:085cde657901 | 644 | * |
mbed_official | 87:085cde657901 | 645 | * @note If Peripheral data format is Word: number of data units is equal |
mbed_official | 87:085cde657901 | 646 | * to total number of bytes to be transferred / 4. |
mbed_official | 87:085cde657901 | 647 | * |
mbed_official | 87:085cde657901 | 648 | * @retval The number of remaining data units in the current DMAy Streamx transfer. |
mbed_official | 87:085cde657901 | 649 | */ |
mbed_official | 87:085cde657901 | 650 | #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__)) |
mbed_official | 87:085cde657901 | 651 | |
mbed_official | 87:085cde657901 | 652 | /** |
mbed_official | 87:085cde657901 | 653 | * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. |
mbed_official | 87:085cde657901 | 654 | * @param __HANDLE__: DMA handle |
mbed_official | 87:085cde657901 | 655 | * |
mbed_official | 87:085cde657901 | 656 | * @retval The number of remaining data units in the current DMA Stream transfer. |
mbed_official | 87:085cde657901 | 657 | */ |
mbed_official | 87:085cde657901 | 658 | #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR) |
mbed_official | 87:085cde657901 | 659 | |
mbed_official | 87:085cde657901 | 660 | |
mbed_official | 87:085cde657901 | 661 | /* Include DMA HAL Extension module */ |
mbed_official | 87:085cde657901 | 662 | #include "stm32f4xx_hal_dma_ex.h" |
mbed_official | 87:085cde657901 | 663 | |
mbed_official | 87:085cde657901 | 664 | /* Exported functions --------------------------------------------------------*/ |
mbed_official | 87:085cde657901 | 665 | |
mbed_official | 87:085cde657901 | 666 | /* Initialization and de-initialization functions *****************************/ |
mbed_official | 87:085cde657901 | 667 | HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); |
mbed_official | 87:085cde657901 | 668 | HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); |
mbed_official | 87:085cde657901 | 669 | |
mbed_official | 87:085cde657901 | 670 | /* IO operation functions *****************************************************/ |
mbed_official | 87:085cde657901 | 671 | HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
mbed_official | 87:085cde657901 | 672 | HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
mbed_official | 87:085cde657901 | 673 | HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); |
mbed_official | 87:085cde657901 | 674 | HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); |
mbed_official | 87:085cde657901 | 675 | void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); |
mbed_official | 87:085cde657901 | 676 | |
mbed_official | 87:085cde657901 | 677 | /* Peripheral State and Error functions ***************************************/ |
mbed_official | 87:085cde657901 | 678 | HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); |
mbed_official | 87:085cde657901 | 679 | uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); |
mbed_official | 87:085cde657901 | 680 | |
mbed_official | 87:085cde657901 | 681 | /** |
mbed_official | 87:085cde657901 | 682 | * @} |
mbed_official | 87:085cde657901 | 683 | */ |
mbed_official | 87:085cde657901 | 684 | |
mbed_official | 87:085cde657901 | 685 | /** |
mbed_official | 87:085cde657901 | 686 | * @} |
mbed_official | 87:085cde657901 | 687 | */ |
mbed_official | 87:085cde657901 | 688 | |
mbed_official | 87:085cde657901 | 689 | #ifdef __cplusplus |
mbed_official | 87:085cde657901 | 690 | } |
mbed_official | 87:085cde657901 | 691 | #endif |
mbed_official | 87:085cde657901 | 692 | |
mbed_official | 87:085cde657901 | 693 | #endif /* __STM32F4xx_HAL_DMA_H */ |
mbed_official | 87:085cde657901 | 694 | |
mbed_official | 87:085cde657901 | 695 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |