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targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x.h@636:cb7d56e6ff53, 2015-10-27 (annotated)

Committer:
marcusC
Date:
Tue Oct 27 07:54:54 2015 +0000
Revision:
636:cb7d56e6ff53
Parent:
619:034e698bc035 
Changed for DELTA_DFCM_NNN40; Do not initialize flash at mbed_sdk_init()

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 619:034e698bc035 1 /**************************************************************************//**
mbed_official 619:034e698bc035 2 * @file W7500x.h
mbed_official 619:034e698bc035 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
mbed_official 619:034e698bc035 4 * Device W7500x
mbed_official 619:034e698bc035 5 * @version V3.01
mbed_official 619:034e698bc035 6 * @date 06. March 2012
mbed_official 619:034e698bc035 7 *
mbed_official 619:034e698bc035 8 * @note
mbed_official 619:034e698bc035 9 * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
mbed_official 619:034e698bc035 10 *
mbed_official 619:034e698bc035 11 * @par
mbed_official 619:034e698bc035 12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
mbed_official 619:034e698bc035 13 * processor based microcontrollers. This file can be freely distributed
mbed_official 619:034e698bc035 14 * within development tools that are supporting such ARM based processors.
mbed_official 619:034e698bc035 15 *
mbed_official 619:034e698bc035 16 * @par
mbed_official 619:034e698bc035 17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
mbed_official 619:034e698bc035 18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
mbed_official 619:034e698bc035 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
mbed_official 619:034e698bc035 20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
mbed_official 619:034e698bc035 21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
mbed_official 619:034e698bc035 22 *
mbed_official 619:034e698bc035 23 ******************************************************************************/
mbed_official 619:034e698bc035 24
mbed_official 619:034e698bc035 25
mbed_official 619:034e698bc035 26 #ifndef W7500x_H
mbed_official 619:034e698bc035 27 #define W7500x_H
mbed_official 619:034e698bc035 28
mbed_official 619:034e698bc035 29 #ifdef __cplusplus
mbed_official 619:034e698bc035 30 extern "C" {
mbed_official 619:034e698bc035 31 #endif
mbed_official 619:034e698bc035 32
mbed_official 619:034e698bc035 33 /** @addtogroup W7500x_Definitions W7500x Definitions
mbed_official 619:034e698bc035 34 This file defines all structures and symbols for W7500x:
mbed_official 619:034e698bc035 35 - registers and bitfields
mbed_official 619:034e698bc035 36 - peripheral base address
mbed_official 619:034e698bc035 37 - peripheral ID
mbed_official 619:034e698bc035 38 - Peripheral definitions
mbed_official 619:034e698bc035 39 @{
mbed_official 619:034e698bc035 40 */
mbed_official 619:034e698bc035 41
mbed_official 619:034e698bc035 42
mbed_official 619:034e698bc035 43 /******************************************************************************/
mbed_official 619:034e698bc035 44 /* Processor and Core Peripherals */
mbed_official 619:034e698bc035 45 /******************************************************************************/
mbed_official 619:034e698bc035 46 /** @addtogroup W7500x_CMSIS Device CMSIS Definitions
mbed_official 619:034e698bc035 47 Configuration of the Cortex-M0 Processor and Core Peripherals
mbed_official 619:034e698bc035 48 @{
mbed_official 619:034e698bc035 49 */
mbed_official 619:034e698bc035 50
mbed_official 619:034e698bc035 51 /*
mbed_official 619:034e698bc035 52 * ==========================================================================
mbed_official 619:034e698bc035 53 * ---------- Interrupt Number Definition -----------------------------------
mbed_official 619:034e698bc035 54 * ==========================================================================
mbed_official 619:034e698bc035 55 */
mbed_official 619:034e698bc035 56
mbed_official 619:034e698bc035 57 typedef enum IRQn
mbed_official 619:034e698bc035 58 {
mbed_official 619:034e698bc035 59 /****** Cortex-M0 Processor Exceptions Numbers **************************************************/
mbed_official 619:034e698bc035 60
mbed_official 619:034e698bc035 61 /* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */
mbed_official 619:034e698bc035 62 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M0 Non Maskable Interrupt */
mbed_official 619:034e698bc035 63 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
mbed_official 619:034e698bc035 64 SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
mbed_official 619:034e698bc035 65 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
mbed_official 619:034e698bc035 66 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
mbed_official 619:034e698bc035 67 /****** W7500x Specific Interrupt Numbers *********************************************************/
mbed_official 619:034e698bc035 68 SSP0_IRQn = 0, /*!< SSP 0 Interrupt */
mbed_official 619:034e698bc035 69 SSP1_IRQn = 1, /*!< SSP 1 Interrupt */
mbed_official 619:034e698bc035 70 UART0_IRQn = 2, /*!< UART 0 Interrupt */
mbed_official 619:034e698bc035 71 UART1_IRQn = 3, /*!< UART 1 Interrupt */
mbed_official 619:034e698bc035 72 UART2_IRQn = 4, /*!< UART 2 Interrupt */
mbed_official 619:034e698bc035 73 I2C0_IRQn = 5, /*!< I2C 0 Interrupt */
mbed_official 619:034e698bc035 74 I2C1_IRQn = 6, /*!< I2C 1 Interrupt */
mbed_official 619:034e698bc035 75 PORT0_IRQn = 7, /*!< Port 1 combined Interrupt */
mbed_official 619:034e698bc035 76 PORT1_IRQn = 8, /*!< Port 2 combined Interrupt */
mbed_official 619:034e698bc035 77 PORT2_IRQn = 9, /*!< Port 2 combined Interrupt */
mbed_official 619:034e698bc035 78 PORT3_IRQn = 10, /*!< Port 2 combined Interrupt */
mbed_official 619:034e698bc035 79 DMA_IRQn = 11, /*!< DMA combined Interrupt */
mbed_official 619:034e698bc035 80 DUALTIMER0_IRQn = 12, /*!< Dual Timer 0 Interrupt */
mbed_official 619:034e698bc035 81 DUALTIMER1_IRQn = 13, /*!< Dual Timer 1 Interrupt */
mbed_official 619:034e698bc035 82 PWM0_IRQn = 14, /*!< PWM 0 Interrupt */
mbed_official 619:034e698bc035 83 PWM1_IRQn = 15, /*!< PWM 1 Interrupt */
mbed_official 619:034e698bc035 84 PWM2_IRQn = 16, /*!< PWM 2 Interrupt */
mbed_official 619:034e698bc035 85 PWM3_IRQn = 17, /*!< PWM 3 Interrupt */
mbed_official 619:034e698bc035 86 PWM4_IRQn = 18, /*!< PWM 4 Interrupt */
mbed_official 619:034e698bc035 87 PWM5_IRQn = 19, /*!< PWM 5 Interrupt */
mbed_official 619:034e698bc035 88 PWM6_IRQn = 20, /*!< PWM 6 Interrupt */
mbed_official 619:034e698bc035 89 PWM7_IRQn = 21, /*!< PWM 7 Interrupt */
mbed_official 619:034e698bc035 90 RTC_IRQn = 22, /*!< RTC Interrupt */
mbed_official 619:034e698bc035 91 ADC_IRQn = 23, /*!< ADC Interrupt */
mbed_official 619:034e698bc035 92 WZTOE_IRQn = 24, /*!< WZTOE Interrupt */
mbed_official 619:034e698bc035 93 EXTI_IRQn = 25 /*!< EXTI Interrupt */
mbed_official 619:034e698bc035 94 } IRQn_Type;
mbed_official 619:034e698bc035 95
mbed_official 619:034e698bc035 96 /*
mbed_official 619:034e698bc035 97 * ==========================================================================
mbed_official 619:034e698bc035 98 * ----------- Processor and Core Peripheral Section ------------------------
mbed_official 619:034e698bc035 99 * ==========================================================================
mbed_official 619:034e698bc035 100 */
mbed_official 619:034e698bc035 101
mbed_official 619:034e698bc035 102 /* Configuration of the Cortex-M0 Processor and Core Peripherals */
mbed_official 619:034e698bc035 103 #define __CM0_REV 0x0000 /*!< Core Revision r0p0 */
mbed_official 619:034e698bc035 104 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
mbed_official 619:034e698bc035 105 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
mbed_official 619:034e698bc035 106 #define __MPU_PRESENT 0 /*!< MPU present or not */
mbed_official 619:034e698bc035 107
mbed_official 619:034e698bc035 108 /*@}*/ /* end of group W7500x_CMSIS */
mbed_official 619:034e698bc035 109
mbed_official 619:034e698bc035 110
mbed_official 619:034e698bc035 111 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
mbed_official 619:034e698bc035 112 #include "system_W7500x.h" /* W7500x System include file */
mbed_official 619:034e698bc035 113
mbed_official 619:034e698bc035 114
mbed_official 619:034e698bc035 115 /** @addtogroup Exported_types
mbed_official 619:034e698bc035 116 * @{
mbed_official 619:034e698bc035 117 */
mbed_official 619:034e698bc035 118
mbed_official 619:034e698bc035 119 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
mbed_official 619:034e698bc035 120 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
mbed_official 619:034e698bc035 121 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
mbed_official 619:034e698bc035 122
mbed_official 619:034e698bc035 123 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
mbed_official 619:034e698bc035 124
mbed_official 619:034e698bc035 125
mbed_official 619:034e698bc035 126
mbed_official 619:034e698bc035 127
mbed_official 619:034e698bc035 128 /**
mbed_official 619:034e698bc035 129 * @}
mbed_official 619:034e698bc035 130 */
mbed_official 619:034e698bc035 131
mbed_official 619:034e698bc035 132
mbed_official 619:034e698bc035 133
mbed_official 619:034e698bc035 134
mbed_official 619:034e698bc035 135 /** @addtogroup Peripheral_registers_structures
mbed_official 619:034e698bc035 136 * @{
mbed_official 619:034e698bc035 137 */
mbed_official 619:034e698bc035 138
mbed_official 619:034e698bc035 139 /**
mbed_official 619:034e698bc035 140 * @brief Clock Reset Generator
mbed_official 619:034e698bc035 141 */
mbed_official 619:034e698bc035 142 typedef struct
mbed_official 619:034e698bc035 143 {
mbed_official 619:034e698bc035 144 __IO uint32_t OSC_PDR; /*!< Oscillator power down register, Address offset : 0x00 */
mbed_official 619:034e698bc035 145 uint32_t RESERVED0[3];
mbed_official 619:034e698bc035 146 __IO uint32_t PLL_PDR; /*!< PLL power down register, Address offset : 0x10 */
mbed_official 619:034e698bc035 147 __IO uint32_t PLL_FCR; /*!< PLL frequency calculating register, Address offset : 0x14 */
mbed_official 619:034e698bc035 148 __IO uint32_t PLL_OER; /*!< PLL output enable register, Address offset : 0x18 */
mbed_official 619:034e698bc035 149 __IO uint32_t PLL_BPR; /*!< PLL bypass register, Address offset : 0x1c */
mbed_official 619:034e698bc035 150 __IO uint32_t PLL_IFSR; /*!< PLL input frequency select register, Address offset : 0x20 */
mbed_official 619:034e698bc035 151 uint32_t RESERVED1[3];
mbed_official 619:034e698bc035 152 __IO uint32_t FCLK_SSR; /*!< FCLK source select register, Address offset : 0x30 */
mbed_official 619:034e698bc035 153 __IO uint32_t FCLK_PVSR; /*!< FCLK prescale value select register, Address offset : 0x34 */
mbed_official 619:034e698bc035 154 uint32_t RESERVED2[2];
mbed_official 619:034e698bc035 155 __IO uint32_t SSPCLK_SSR; /*!< SSPCLK source select register, Address offset : 0x40 */
mbed_official 619:034e698bc035 156 __IO uint32_t SSPCLK_PVSR; /*!< SSPCLK prescale value select register, Address offset : 0x44 */
mbed_official 619:034e698bc035 157 uint32_t RESERVED3[6];
mbed_official 619:034e698bc035 158 __IO uint32_t ADCCLK_SSR; /*!< ADCCLK source select register, Address offset : 0x60 */
mbed_official 619:034e698bc035 159 __IO uint32_t ADCCLK_PVSR; /*!< ADCCLK prescale value select register, Address offset : 0x64 */
mbed_official 619:034e698bc035 160 uint32_t RESERVED4[2];
mbed_official 619:034e698bc035 161 __IO uint32_t TIMER0CLK_SSR; /*!< TIMER0CLK source select register, Address offset : 0x70 */
mbed_official 619:034e698bc035 162 __IO uint32_t TIMER0CLK_PVSR; /*!< TIMER0CLK prescale value select register, Address offset : 0x74 */
mbed_official 619:034e698bc035 163 uint32_t RESERVED5[2];
mbed_official 619:034e698bc035 164 __IO uint32_t TIMER1CLK_SSR; /*!< TIMER1CLK source select register, Address offset : 0x80 */
mbed_official 619:034e698bc035 165 __IO uint32_t TIMER1CLK_PVSR; /*!< TIMER1CLK prescale value select register, Address offset : 0x84 */
mbed_official 619:034e698bc035 166 uint32_t RESERVED6[10];
mbed_official 619:034e698bc035 167 __IO uint32_t PWM0CLK_SSR; /*!< PWM0CLK source select register, Address offset : 0xb0 */
mbed_official 619:034e698bc035 168 __IO uint32_t PWM0CLK_PVSR; /*!< PWM0CLK prescale value select register, Address offset : 0xb4 */
mbed_official 619:034e698bc035 169 uint32_t RESERVED7[2];
mbed_official 619:034e698bc035 170 __IO uint32_t PWM1CLK_SSR; /*!< PWM1CLK source select register, Address offset : 0xc0 */
mbed_official 619:034e698bc035 171 __IO uint32_t PWM1CLK_PVSR; /*!< PWM1CLK prescale value select register, Address offset : 0xc4 */
mbed_official 619:034e698bc035 172 uint32_t RESERVED8[2];
mbed_official 619:034e698bc035 173 __IO uint32_t PWM2CLK_SSR; /*!< PWM2CLK source select register, Address offset : 0xd0 */
mbed_official 619:034e698bc035 174 __IO uint32_t PWM2CLK_PVSR; /*!< PWM2CLK prescale value select register, Address offset : 0xd4 */
mbed_official 619:034e698bc035 175 uint32_t RESERVED9[2];
mbed_official 619:034e698bc035 176 __IO uint32_t PWM3CLK_SSR; /*!< PWM3CLK source select register, Address offset : 0xe0 */
mbed_official 619:034e698bc035 177 __IO uint32_t PWM3CLK_PVSR; /*!< PWM3CLK prescale value select register, Address offset : 0xe4 */
mbed_official 619:034e698bc035 178 uint32_t RESERVED10[2];
mbed_official 619:034e698bc035 179 __IO uint32_t PWM4CLK_SSR; /*!< PWM4CLK source select register, Address offset : 0xf0 */
mbed_official 619:034e698bc035 180 __IO uint32_t PWM4CLK_PVSR; /*!< PWM4CLK prescale value select register, Address offset : 0xf4 */
mbed_official 619:034e698bc035 181 uint32_t RESERVED11[2];
mbed_official 619:034e698bc035 182 __IO uint32_t PWM5CLK_SSR; /*!< PWM5CLK source select register, Address offset : 0x100 */
mbed_official 619:034e698bc035 183 __IO uint32_t PWM5LK_PVSR; /*!< PWM5CLK prescale value select register, Address offset : 0x104 */
mbed_official 619:034e698bc035 184 uint32_t RESERVED12[2];
mbed_official 619:034e698bc035 185 __IO uint32_t PWM6CLK_SSR; /*!< PWM6CLK source select register, Address offset : 0x110 */
mbed_official 619:034e698bc035 186 __IO uint32_t PWM6CLK_PVSR; /*!< PWM6CLK prescale value select register, Address offset : 0x114 */
mbed_official 619:034e698bc035 187 uint32_t RESERVED13[2];
mbed_official 619:034e698bc035 188 __IO uint32_t PWM7CLK_SSR; /*!< PWM7CLK source select register, Address offset : 0x120 */
mbed_official 619:034e698bc035 189 __IO uint32_t PWM7CLK_PVSR; /*!< PWM7CLK prescale value select register, Address offset : 0x124 */
mbed_official 619:034e698bc035 190 uint32_t RESERVED14[2];
mbed_official 619:034e698bc035 191 __IO uint32_t RTC_HS_SSR; /*!< RTC High Speed source select register, Address offset : 0x130 */
mbed_official 619:034e698bc035 192 __IO uint32_t RTC_HS_PVSR; /*!< RTC High Speed prescale value select register, Address offset : 0x134 */
mbed_official 619:034e698bc035 193 uint32_t RESERVED15;
mbed_official 619:034e698bc035 194 __IO uint32_t RTC_SSR; /*!< RTC source select register, Address offset : 0x13c */
mbed_official 619:034e698bc035 195
mbed_official 619:034e698bc035 196 __IO uint32_t WDOGCLK_HS_SSR; /*!< WDOGCLK High Speed source select register, Address offset : 0x140 */
mbed_official 619:034e698bc035 197 __IO uint32_t WDOGCLK_HS_PVSR; /*!< WDOGCLK High Speed prescale value select register, Address offset : 0x144 */
mbed_official 619:034e698bc035 198 uint32_t RESERVED16;
mbed_official 619:034e698bc035 199 __IO uint32_t WDOGCLK_SSR; /*!< WDOGCLK source select register, Address offset : 0x14c */
mbed_official 619:034e698bc035 200
mbed_official 619:034e698bc035 201 __IO uint32_t UARTCLK_SSR; /*!< UARTCLK source select register, Address offset : 0x150 */
mbed_official 619:034e698bc035 202 __IO uint32_t UARTCLK_PVSR; /*!< UARTCLK prescale value select register, Address offset : 0x154 */
mbed_official 619:034e698bc035 203 uint32_t RESERVED17[2];
mbed_official 619:034e698bc035 204 __IO uint32_t MIICLK_ECR; /*!< MII clock enable control register, Address offset : 0x160 */
mbed_official 619:034e698bc035 205 uint32_t RESERVED18[3];
mbed_official 619:034e698bc035 206 __IO uint32_t MONCLK_SSR; /*!< Monitoring clock source select I found Treasure was IoT Base Station in March.register, Address offset : 0x170 */
mbed_official 619:034e698bc035 207 }CRG_TypeDef;
mbed_official 619:034e698bc035 208
mbed_official 619:034e698bc035 209
mbed_official 619:034e698bc035 210 /**
mbed_official 619:034e698bc035 211 * @brief UART
mbed_official 619:034e698bc035 212 */
mbed_official 619:034e698bc035 213 typedef struct
mbed_official 619:034e698bc035 214 {
mbed_official 619:034e698bc035 215 __IO uint32_t DR; /*!< Data, Address offset : 0x00 */
mbed_official 619:034e698bc035 216 union {
mbed_official 619:034e698bc035 217 __I uint32_t RSR; /*!< Receive Status, Address offset : 0x04 */
mbed_official 619:034e698bc035 218 __O uint32_t ECR; /*!< Error Clear, Address offset : 0x04 */
mbed_official 619:034e698bc035 219 } STATUS;
mbed_official 619:034e698bc035 220 uint32_t RESERVED0[4];
mbed_official 619:034e698bc035 221 __IO uint32_t FR; /*!< Flags, Address offset : 0x18 */
mbed_official 619:034e698bc035 222 uint32_t RESERVED1;
mbed_official 619:034e698bc035 223 __IO uint32_t ILPR; /*!< IrDA Low-power Counter, Address offset : 0x20 */
mbed_official 619:034e698bc035 224 __IO uint32_t IBRD; /*!< Integer Baud Rate, Address offset : 0x24 */
mbed_official 619:034e698bc035 225 __IO uint32_t FBRD; /*!< Fractional Baud Rate, Address offset : 0x28 */
mbed_official 619:034e698bc035 226 __IO uint32_t LCR_H; /*!< Line Control, Address offset : 0x2C */
mbed_official 619:034e698bc035 227 __IO uint32_t CR; /*!< Control, Address offset : 0x30 */
mbed_official 619:034e698bc035 228 __IO uint32_t IFLS; /*!< Interrupt FIFO Level Select, Address offset : 0x34 */
mbed_official 619:034e698bc035 229 __IO uint32_t IMSC; /*!< Interrupt Mask Set / Clear, Address offset : 0x38 */
mbed_official 619:034e698bc035 230 __IO uint32_t RIS; /*!< Raw Interrupt Status , Address offset : 0x3C */
mbed_official 619:034e698bc035 231 __IO uint32_t MIS; /*!< Masked Interrupt Status , Address offset : 0x40 */
mbed_official 619:034e698bc035 232 __O uint32_t ICR; /*!< Interrupt Clear, Address offset : 0x44 */
mbed_official 619:034e698bc035 233 __IO uint32_t DMACR; /*!< DMA Control, Address offset : 0x48 */
mbed_official 619:034e698bc035 234 } UART_TypeDef;
mbed_official 619:034e698bc035 235
mbed_official 619:034e698bc035 236
mbed_official 619:034e698bc035 237 /**
mbed_official 619:034e698bc035 238 * @brief Simple UART
mbed_official 619:034e698bc035 239 */
mbed_official 619:034e698bc035 240 typedef struct
mbed_official 619:034e698bc035 241 {
mbed_official 619:034e698bc035 242 __IO uint32_t DATA; /*!< Offset: 0x000 Data Register (R/W) */
mbed_official 619:034e698bc035 243 __IO uint32_t STATE; /*!< Offset: 0x004 Status Register (R/W) */
mbed_official 619:034e698bc035 244 __IO uint32_t CTRL; /*!< Offset: 0x008 Control Register (R/W) */
mbed_official 619:034e698bc035 245 union {
mbed_official 619:034e698bc035 246 __I uint32_t STATUS; /*!< Offset: 0x00C Interrupt Status Register (R/ ) */
mbed_official 619:034e698bc035 247 __O uint32_t CLEAR; /*!< Offset: 0x00C Interrupt Clear Register ( /W) */
mbed_official 619:034e698bc035 248 }INT;
mbed_official 619:034e698bc035 249 __IO uint32_t BAUDDIV; /*!< Offset: 0x010 Baudrate Divider Register (R/W) */
mbed_official 619:034e698bc035 250
mbed_official 619:034e698bc035 251 } S_UART_TypeDef;
mbed_official 619:034e698bc035 252
mbed_official 619:034e698bc035 253 /**
mbed_official 619:034e698bc035 254 * @brief Analog Digital Converter
mbed_official 619:034e698bc035 255 */
mbed_official 619:034e698bc035 256
mbed_official 619:034e698bc035 257 typedef struct
mbed_official 619:034e698bc035 258 {
mbed_official 619:034e698bc035 259 __IO uint32_t ADC_CTR; /* ADC control register, Address offset : 0x000 */
mbed_official 619:034e698bc035 260 __IO uint32_t ADC_CHSEL; /* ADC channel select register, Address offset : 0x004 */
mbed_official 619:034e698bc035 261 __IO uint32_t ADC_START; /* ADC start register, Address offset : 0x008 */
mbed_official 619:034e698bc035 262 __I uint32_t ADC_DATA; /* ADC conversion data register, Address offset : 0x00c */
mbed_official 619:034e698bc035 263 __IO uint32_t ADC_INT; /* ADC interrupt register, Address offset : 0x010 */
mbed_official 619:034e698bc035 264 uint32_t RESERVED0[2];
mbed_official 619:034e698bc035 265 __IO uint32_t ADC_INTCLR; /* ADC interrupt clear register, Address offset : 0x01c */
mbed_official 619:034e698bc035 266 }ADC_TypeDef;
mbed_official 619:034e698bc035 267
mbed_official 619:034e698bc035 268 /**
mbed_official 619:034e698bc035 269 * @brief dualtimer
mbed_official 619:034e698bc035 270 */
mbed_official 619:034e698bc035 271 typedef struct
mbed_official 619:034e698bc035 272 {
mbed_official 619:034e698bc035 273 __IO uint32_t TimerLoad; // <h> Timer Load </h>
mbed_official 619:034e698bc035 274 __I uint32_t TimerValue; // <h> Timer Counter Current Value <r></h>
mbed_official 619:034e698bc035 275 __IO uint32_t TimerControl; // <h> Timer Control
mbed_official 619:034e698bc035 276 // <o.7> TimerEn: Timer Enable
mbed_official 619:034e698bc035 277 // <o.6> TimerMode: Timer Mode
mbed_official 619:034e698bc035 278 // <0=> Freerunning-mode
mbed_official 619:034e698bc035 279 // <1=> Periodic mode
mbed_official 619:034e698bc035 280 // <o.5> IntEnable: Interrupt Enable
mbed_official 619:034e698bc035 281 // <o.2..3> TimerPre: Timer Prescale
mbed_official 619:034e698bc035 282 // <0=> / 1
mbed_official 619:034e698bc035 283 // <1=> / 16
mbed_official 619:034e698bc035 284 // <2=> / 256
mbed_official 619:034e698bc035 285 // <3=> Undefined!
mbed_official 619:034e698bc035 286 // <o.1> TimerSize: Timer Size
mbed_official 619:034e698bc035 287 // <0=> 16-bit counter
mbed_official 619:034e698bc035 288 // <1=> 32-bit counter
mbed_official 619:034e698bc035 289 // <o.0> OneShot: One-shoot mode
mbed_official 619:034e698bc035 290 // <0=> Wrapping mode
mbed_official 619:034e698bc035 291 // <1=> One-shot mode
mbed_official 619:034e698bc035 292 // </h>
mbed_official 619:034e698bc035 293 __O uint32_t TimerIntClr; // <h> Timer Interrupt Clear <w></h>
mbed_official 619:034e698bc035 294 __I uint32_t TimerRIS; // <h> Timer Raw Interrupt Status <r></h>
mbed_official 619:034e698bc035 295 __I uint32_t TimerMIS; // <h> Timer Masked Interrupt Status <r></h>
mbed_official 619:034e698bc035 296 __IO uint32_t TimerBGLoad; // <h> Background Load Register </h>
mbed_official 619:034e698bc035 297 } DUALTIMER_TypeDef;
mbed_official 619:034e698bc035 298
mbed_official 619:034e698bc035 299 /**
mbed_official 619:034e698bc035 300 * @brief GPIO
mbed_official 619:034e698bc035 301 */
mbed_official 619:034e698bc035 302 typedef struct
mbed_official 619:034e698bc035 303 {
mbed_official 619:034e698bc035 304 __IO uint32_t DATA; /* DATA Register (R/W), offset : 0x000 */
mbed_official 619:034e698bc035 305 __IO uint32_t DATAOUT; /* Data Output Latch Register (R/W), offset : 0x004 */
mbed_official 619:034e698bc035 306 uint32_t RESERVED0[2];
mbed_official 619:034e698bc035 307 __IO uint32_t OUTENSET; /* Output Enable Set Register (R/W) offset : 0x010 */
mbed_official 619:034e698bc035 308 __IO uint32_t OUTENCLR; /* Output Enable Clear Register (R/W) offset : 0x014 */
mbed_official 619:034e698bc035 309 __IO uint32_t RESERVED1; /* Alternate Function Set Register (R/W) offset : 0x018 */
mbed_official 619:034e698bc035 310 __IO uint32_t RESERVED2; /* Alternate Function Clear Register (R/W) offset : 0x01C */
mbed_official 619:034e698bc035 311 __IO uint32_t INTENSET; /* Interrupt Enable Set Register (R/W) offset : 0x020 */
mbed_official 619:034e698bc035 312 __IO uint32_t INTENCLR; /* Interrupt Enable Clear Register (R/W) offset : 0x024 */
mbed_official 619:034e698bc035 313 __IO uint32_t INTTYPESET; /* Interrupt Type Set Register (R/W) offset : 0x028 */
mbed_official 619:034e698bc035 314 __IO uint32_t INTTYPECLR; /* Interrupt Type Clear Register (R/W) offset : 0x02C */
mbed_official 619:034e698bc035 315 __IO uint32_t INTPOLSET; /* Interrupt Polarity Set Register (R/W) offset : 0x030 */
mbed_official 619:034e698bc035 316 __IO uint32_t INTPOLCLR; /* Interrupt Polarity Clear Register (R/W) offset : 0x034 */
mbed_official 619:034e698bc035 317 union {
mbed_official 619:034e698bc035 318 __I uint32_t INTSTATUS; /* Interrupt Status Register (R/ ) offset : 0x038 */
mbed_official 619:034e698bc035 319 __O uint32_t INTCLEAR; /* Interrupt Clear Register ( /W) offset : 0x038 */
mbed_official 619:034e698bc035 320 }Interrupt;
mbed_official 619:034e698bc035 321 uint32_t RESERVED3[241];
mbed_official 619:034e698bc035 322 __IO uint32_t LB_MASKED[256]; /* Lower byte Masked Access Register (R/W) offset : 0x400 - 0x7FC */
mbed_official 619:034e698bc035 323 __IO uint32_t UB_MASKED[256]; /* Upper byte Masked Access Register (R/W) offset : 0x800 - 0xBFC */
mbed_official 619:034e698bc035 324 } GPIO_TypeDef;
mbed_official 619:034e698bc035 325
mbed_official 619:034e698bc035 326 typedef struct
mbed_official 619:034e698bc035 327 {
mbed_official 619:034e698bc035 328 __IO uint32_t Port[16]; /* Port_00, offset : 0x00 */
mbed_official 619:034e698bc035 329 /* Port_01, offset : 0x04 */
mbed_official 619:034e698bc035 330 /* Port_02, offset : 0x08 */
mbed_official 619:034e698bc035 331 /* Port_03, offset : 0x0C */
mbed_official 619:034e698bc035 332 /* Port_04, offset : 0x10 */
mbed_official 619:034e698bc035 333 /* Port_05, offset : 0x14 */
mbed_official 619:034e698bc035 334 /* Port_06, offset : 0x18 */
mbed_official 619:034e698bc035 335 /* Port_07, offset : 0x1C */
mbed_official 619:034e698bc035 336 /* Port_08, offset : 0x20 */
mbed_official 619:034e698bc035 337 /* Port_09, offset : 0x24 */
mbed_official 619:034e698bc035 338 /* Port_10, offset : 0x28 */
mbed_official 619:034e698bc035 339 /* Port_11, offset : 0x2C */
mbed_official 619:034e698bc035 340 /* Port_12, offset : 0x30 */
mbed_official 619:034e698bc035 341 /* Port_13, offset : 0x34 */
mbed_official 619:034e698bc035 342 /* Port_14, offset : 0x38 */
mbed_official 619:034e698bc035 343 /* Port_15, offset : 0x3C */
mbed_official 619:034e698bc035 344 } P_Port_Def;
mbed_official 619:034e698bc035 345
mbed_official 619:034e698bc035 346 typedef struct
mbed_official 619:034e698bc035 347 {
mbed_official 619:034e698bc035 348 __IO uint32_t Port[5]; /* Port_00, offset : 0x00 */
mbed_official 619:034e698bc035 349 /* Port_01, offset : 0x04 */
mbed_official 619:034e698bc035 350 /* Port_02, offset : 0x08 */
mbed_official 619:034e698bc035 351 /* Port_03, offset : 0x0C */
mbed_official 619:034e698bc035 352 /* Port_04, offset : 0x10 */
mbed_official 619:034e698bc035 353 } P_Port_D_Def;
mbed_official 619:034e698bc035 354
mbed_official 619:034e698bc035 355 /**
mbed_official 619:034e698bc035 356 * @brief I2C Register structure definition
mbed_official 619:034e698bc035 357 */
mbed_official 619:034e698bc035 358 typedef struct
mbed_official 619:034e698bc035 359 {
mbed_official 619:034e698bc035 360 __IO uint32_t PRER; //0x00
mbed_official 619:034e698bc035 361 __IO uint32_t CTR; //0x04
mbed_official 619:034e698bc035 362 __IO uint32_t CMDR; //0x08
mbed_official 619:034e698bc035 363 __I uint32_t SR; //0x0C
mbed_official 619:034e698bc035 364 __IO uint32_t TSR; //0x10
mbed_official 619:034e698bc035 365 __IO uint32_t SADDR; //0x14
mbed_official 619:034e698bc035 366 __IO uint32_t TXR; //0x18
mbed_official 619:034e698bc035 367 __I uint32_t RXR; //0x1C
mbed_official 619:034e698bc035 368 __I uint32_t ISR; //0x20
mbed_official 619:034e698bc035 369 __IO uint32_t ISCR; //0x24
mbed_official 619:034e698bc035 370 __IO uint32_t ISMR; //0x28
mbed_official 619:034e698bc035 371 }I2C_TypeDef;
mbed_official 619:034e698bc035 372
mbed_official 619:034e698bc035 373 /**
mbed_official 619:034e698bc035 374 * @brief PWM Register structure definition
mbed_official 619:034e698bc035 375 */
mbed_official 619:034e698bc035 376 typedef struct
mbed_official 619:034e698bc035 377 {
mbed_official 619:034e698bc035 378 __IO uint32_t IER; //Interrupt enable register
mbed_official 619:034e698bc035 379 // <7> IE7 : Channel 7 interrupt enable <R/W>
mbed_official 619:034e698bc035 380 // <6> IE6 : Channel 6 interrupt enable <R/W>
mbed_official 619:034e698bc035 381 // <5> IE5 : Channel 5 interrupt enable <R/W>
mbed_official 619:034e698bc035 382 // <4> IE4 : Channel 4 interrupt enable <R/W>
mbed_official 619:034e698bc035 383 // <3> IE3 : Channel 3 interrupt enable <R/W>
mbed_official 619:034e698bc035 384 // <2> IE2 : Channel 2 interrupt enable <R/W>
mbed_official 619:034e698bc035 385 // <1> IE1 : Channel 1 interrupt enable <R/W>
mbed_official 619:034e698bc035 386 // <0> IE0 : Channel 0 interrupt enable <R/W>
mbed_official 619:034e698bc035 387
mbed_official 619:034e698bc035 388 __IO uint32_t SSR; //Start Stop register
mbed_official 619:034e698bc035 389 // <7> SS7 : Channel 7 TC start or stop <R/W>
mbed_official 619:034e698bc035 390 // <6> SS6 : Channel 6 TC start or stop <R/W>
mbed_official 619:034e698bc035 391 // <5> SS5 : Channel 5 TC start or stop <R/W>
mbed_official 619:034e698bc035 392 // <4> SS4 : Channel 4 TC start or stop <R/W>
mbed_official 619:034e698bc035 393 // <3> SS3 : Channel 3 TC start or stop <R/W>
mbed_official 619:034e698bc035 394 // <2> SS2 : Channel 2 TC start or stop <R/W>
mbed_official 619:034e698bc035 395 // <1> SS1 : Channel 1 TC start or stop <R/W>
mbed_official 619:034e698bc035 396 // <0> SS0 : Channel 0 TC start or stop <R/W>
mbed_official 619:034e698bc035 397
mbed_official 619:034e698bc035 398 __IO uint32_t PSR; //Pause register
mbed_official 619:034e698bc035 399 // <7> PS7 : Channel 7 TC pasue <R/W>
mbed_official 619:034e698bc035 400 // <6> PS6 : Channel 6 TC pasue <R/W>
mbed_official 619:034e698bc035 401 // <5> PS5 : Channel 5 TC pasue <R/W>
mbed_official 619:034e698bc035 402 // <4> PS4 : Channel 4 TC pasue <R/W>
mbed_official 619:034e698bc035 403 // <3> PS3 : Channel 3 TC pasue <R/W>
mbed_official 619:034e698bc035 404 // <2> PS2 : Channel 2 TC pasue <R/W>
mbed_official 619:034e698bc035 405 // <1> PS1 : Channel 1 TC pasue <R/W>
mbed_official 619:034e698bc035 406 // <0> PS0 : Channel 0 TC pasue <R/W>
mbed_official 619:034e698bc035 407 } PWM_TypeDef;
mbed_official 619:034e698bc035 408
mbed_official 619:034e698bc035 409 typedef struct
mbed_official 619:034e698bc035 410 {
mbed_official 619:034e698bc035 411 __I uint32_t IR; //Interrupt register
mbed_official 619:034e698bc035 412 // <2> CI : Capture interrupt <R>
mbed_official 619:034e698bc035 413 // <1> OI : Overflow interrupt <R>
mbed_official 619:034e698bc035 414 // <0> MI : Match interrupt <R>
mbed_official 619:034e698bc035 415
mbed_official 619:034e698bc035 416 __IO uint32_t IER; //Interrupt enable register
mbed_official 619:034e698bc035 417 // <2> CIE : Capture interrupt enable <R/W>
mbed_official 619:034e698bc035 418 // <1> OIE : Overflow interrupt enable <R/W>
mbed_official 619:034e698bc035 419 // <0> MIE : Match interrupt enable <R/W>
mbed_official 619:034e698bc035 420
mbed_official 619:034e698bc035 421 __O uint32_t ICR; //Interrupt clear register
mbed_official 619:034e698bc035 422 // <2> CIC : Capture interrupt clear <W>
mbed_official 619:034e698bc035 423 // <1> OIC : Overflow interrupt clear <W>
mbed_official 619:034e698bc035 424 // <0> MIC : Match interrupt clear <W>
mbed_official 619:034e698bc035 425
mbed_official 619:034e698bc035 426 __I uint32_t TCR; //Timer/Counter register
mbed_official 619:034e698bc035 427 // <0..31> TCR : Timer/Counter register <R>
mbed_official 619:034e698bc035 428
mbed_official 619:034e698bc035 429 __I uint32_t PCR; //Prescale counter register
mbed_official 619:034e698bc035 430 // <0..5> PCR : Prescale Counter register <R>
mbed_official 619:034e698bc035 431
mbed_official 619:034e698bc035 432 __IO uint32_t PR; //Prescale register
mbed_official 619:034e698bc035 433 // <0..5> PR : prescale register <R/W>
mbed_official 619:034e698bc035 434
mbed_official 619:034e698bc035 435 __IO uint32_t MR; //Match register
mbed_official 619:034e698bc035 436 // <0..31> MR : Match register <R/W>
mbed_official 619:034e698bc035 437
mbed_official 619:034e698bc035 438 __IO uint32_t LR; //Limit register
mbed_official 619:034e698bc035 439 // <0..31> LR : Limit register <R/W>
mbed_official 619:034e698bc035 440 __IO uint32_t UDMR; //Up-Down mode register
mbed_official 619:034e698bc035 441 // <0> UDM : Up-down mode <R/W>
mbed_official 619:034e698bc035 442
mbed_official 619:034e698bc035 443 __IO uint32_t TCMR; //Timer/Counter mode register
mbed_official 619:034e698bc035 444 // <0> TCM : Timer/Counter mode <R/W>
mbed_official 619:034e698bc035 445
mbed_official 619:034e698bc035 446 __IO uint32_t PEEER; //PWM output enable and external input enable register
mbed_official 619:034e698bc035 447 // <0..1> PEEE : PWM output enable and external input enable <R/W>
mbed_official 619:034e698bc035 448
mbed_official 619:034e698bc035 449 __IO uint32_t CMR; //Capture mode register
mbed_official 619:034e698bc035 450 // <0> CM : Capture mode <R/W>
mbed_official 619:034e698bc035 451
mbed_official 619:034e698bc035 452 __IO uint32_t CR; //Capture register
mbed_official 619:034e698bc035 453 // <0..31> CR : Capture register <R>
mbed_official 619:034e698bc035 454
mbed_official 619:034e698bc035 455 __IO uint32_t PDMR; //Periodic mode register
mbed_official 619:034e698bc035 456 // <0> PDM : Periodic mode <R/W>
mbed_official 619:034e698bc035 457
mbed_official 619:034e698bc035 458 __IO uint32_t DZER; //Dead-zone enable register
mbed_official 619:034e698bc035 459 // <0> DZE : Dead-zone enable <R/W>
mbed_official 619:034e698bc035 460
mbed_official 619:034e698bc035 461 __IO uint32_t DZCR; //Dead-zone counter register
mbed_official 619:034e698bc035 462 // <0..9> DZC : Dead-zone counter <R/W>
mbed_official 619:034e698bc035 463 } PWM_CHn_TypeDef;
mbed_official 619:034e698bc035 464
mbed_official 619:034e698bc035 465 typedef struct
mbed_official 619:034e698bc035 466 {
mbed_official 619:034e698bc035 467 __IO uint32_t PWM_CHn_PR; //Prescale register
mbed_official 619:034e698bc035 468 // <0..5> PR : prescale register <R/W>
mbed_official 619:034e698bc035 469 __IO uint32_t PWM_CHn_MR; //Match register
mbed_official 619:034e698bc035 470 // <0..31> MR : Match register <R/W>
mbed_official 619:034e698bc035 471 __IO uint32_t PWM_CHn_LR; //Limit register
mbed_official 619:034e698bc035 472 // <0..31> LR : Limit register <R/W>
mbed_official 619:034e698bc035 473 __IO uint32_t PWM_CHn_UDMR; //Up-Down mode register
mbed_official 619:034e698bc035 474 // <0> UDM : Up-down mode <R/W>
mbed_official 619:034e698bc035 475 __IO uint32_t PWM_CHn_PDMR; //Periodic mode register
mbed_official 619:034e698bc035 476 // <0> PDM : Periodic mode <R/W>
mbed_official 619:034e698bc035 477 }PWM_TimerModeInitTypeDef;
mbed_official 619:034e698bc035 478
mbed_official 619:034e698bc035 479 typedef struct
mbed_official 619:034e698bc035 480 {
mbed_official 619:034e698bc035 481 __IO uint32_t PWM_CHn_PR; //Prescale register
mbed_official 619:034e698bc035 482 // <0..5> PR : prescale register <R/W>
mbed_official 619:034e698bc035 483 __IO uint32_t PWM_CHn_MR; //Match register
mbed_official 619:034e698bc035 484 // <0..31> MR : Match register <R/W>
mbed_official 619:034e698bc035 485 __IO uint32_t PWM_CHn_LR; //Limit register
mbed_official 619:034e698bc035 486 // <0..31> LR : Limit register <R/W>
mbed_official 619:034e698bc035 487 __IO uint32_t PWM_CHn_UDMR; //Up-Down mode register
mbed_official 619:034e698bc035 488 // <0> UDM : Up-down mode <R/W>
mbed_official 619:034e698bc035 489 __IO uint32_t PWM_CHn_PDMR; //Periodic mode register
mbed_official 619:034e698bc035 490 // <0> PDM : Peiodic mode <R/W>
mbed_official 619:034e698bc035 491 __IO uint32_t PWM_CHn_CMR; //Capture mode register
mbed_official 619:034e698bc035 492 // <0> CM : Capture mode <R/W>
mbed_official 619:034e698bc035 493 }PWM_CaptureModeInitTypeDef;
mbed_official 619:034e698bc035 494
mbed_official 619:034e698bc035 495 typedef struct
mbed_official 619:034e698bc035 496 {
mbed_official 619:034e698bc035 497 __IO uint32_t PWM_CHn_MR;
mbed_official 619:034e698bc035 498 __IO uint32_t PWM_CHn_LR;
mbed_official 619:034e698bc035 499 __IO uint32_t PWM_CHn_UDMR;
mbed_official 619:034e698bc035 500 __IO uint32_t PWM_CHn_PDMR;
mbed_official 619:034e698bc035 501 __IO uint32_t PWM_CHn_TCMR;
mbed_official 619:034e698bc035 502 }PWM_CounterModeInitTypeDef;
mbed_official 619:034e698bc035 503
mbed_official 619:034e698bc035 504
mbed_official 619:034e698bc035 505 /**
mbed_official 619:034e698bc035 506 * @brief Random Number generator
mbed_official 619:034e698bc035 507 */
mbed_official 619:034e698bc035 508 typedef struct
mbed_official 619:034e698bc035 509 {
mbed_official 619:034e698bc035 510 __IO uint32_t RNG_RUN; /* RNG run register, Address offset : 0x000 */
mbed_official 619:034e698bc035 511 __IO uint32_t RNG_SEED; /* RNG seed value register, Address offset : 0x004 */
mbed_official 619:034e698bc035 512 __IO uint32_t RNG_CLKSEL; /* RNG Clock source select register, Address offset : 0x008 */
mbed_official 619:034e698bc035 513 __IO uint32_t RNG_MODE; /* RNG MODE select register, Address offset : 0x00c */
mbed_official 619:034e698bc035 514 __I uint32_t RNG_RN; /* RNG random number value register, Address offset : 0x010 */
mbed_official 619:034e698bc035 515 __IO uint32_t RNG_POLY; /* RNG polynomial register, Address offset : 0x014 */
mbed_official 619:034e698bc035 516 }RNG_TypeDef;
mbed_official 619:034e698bc035 517
mbed_official 619:034e698bc035 518 /**
mbed_official 619:034e698bc035 519 * @brief Serial Peripheral Interface
mbed_official 619:034e698bc035 520 */
mbed_official 619:034e698bc035 521 typedef struct
mbed_official 619:034e698bc035 522 {
mbed_official 619:034e698bc035 523 __IO uint32_t CR0;
mbed_official 619:034e698bc035 524 __IO uint32_t CR1;
mbed_official 619:034e698bc035 525 __IO uint32_t DR;
mbed_official 619:034e698bc035 526 __IO uint32_t SR;
mbed_official 619:034e698bc035 527 __IO uint32_t CPSR;
mbed_official 619:034e698bc035 528 __IO uint32_t IMSC;
mbed_official 619:034e698bc035 529 __IO uint32_t RIS;
mbed_official 619:034e698bc035 530 __IO uint32_t MIS;
mbed_official 619:034e698bc035 531 __IO uint32_t ICR;
mbed_official 619:034e698bc035 532 __IO uint32_t DMACR;
mbed_official 619:034e698bc035 533 } SSP_TypeDef;
mbed_official 619:034e698bc035 534
mbed_official 619:034e698bc035 535 typedef struct
mbed_official 619:034e698bc035 536 {
mbed_official 619:034e698bc035 537 __IO uint32_t WatchdogLoad; // <h> Watchdog Load Register </h>
mbed_official 619:034e698bc035 538 __I uint32_t WatchdogValue; // <h> Watchdog Value Register </h>
mbed_official 619:034e698bc035 539 __IO uint32_t WatchdogControl; // <h> Watchdog Control Register
mbed_official 619:034e698bc035 540 // <o.1> RESEN: Reset enable
mbed_official 619:034e698bc035 541 // <o.0> INTEN: Interrupt enable
mbed_official 619:034e698bc035 542 // </h>
mbed_official 619:034e698bc035 543 __O uint32_t WatchdogIntClr; // <h> Watchdog Clear Interrupt Register </h>
mbed_official 619:034e698bc035 544 __I uint32_t WatchdogRIS; // <h> Watchdog Raw Interrupt Status Register </h>
mbed_official 619:034e698bc035 545 __I uint32_t WatchdogMIS; // <h> Watchdog Interrupt Status Register </h>
mbed_official 619:034e698bc035 546 uint32_t RESERVED[762];
mbed_official 619:034e698bc035 547 __IO uint32_t WatchdogLock; // <h> Watchdog Lock Register </h>
mbed_official 619:034e698bc035 548 }WATCHDOG_TypeDef;
mbed_official 619:034e698bc035 549
mbed_official 619:034e698bc035 550 /** @addtogroup Peripheral_memory_map
mbed_official 619:034e698bc035 551 * @{
mbed_official 619:034e698bc035 552 */
mbed_official 619:034e698bc035 553
mbed_official 619:034e698bc035 554 /* Peripheral and SRAM base address */
mbed_official 619:034e698bc035 555 #define W7500x_FLASH_BASE (0x00000000UL) /*!< (FLASH ) Base Address */
mbed_official 619:034e698bc035 556 #define W7500x_SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */
mbed_official 619:034e698bc035 557 #define W7500x_PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */
mbed_official 619:034e698bc035 558
mbed_official 619:034e698bc035 559 #define W7500x_RAM_BASE (0x20000000UL)
mbed_official 619:034e698bc035 560 #define W7500x_APB1_BASE (0x40000000UL)
mbed_official 619:034e698bc035 561 #define W7500x_APB2_BASE (0x41000000UL)
mbed_official 619:034e698bc035 562 #define W7500x_AHB_BASE (0x42000000UL)
mbed_official 619:034e698bc035 563
mbed_official 619:034e698bc035 564 #define W7500x_UART0_BASE (W7500x_APB1_BASE + 0x0000C000UL)
mbed_official 619:034e698bc035 565 #define W7500x_UART1_BASE (W7500x_APB1_BASE + 0x0000D000UL)
mbed_official 619:034e698bc035 566 #define W7500x_UART2_BASE (W7500x_APB1_BASE + 0x00006000UL)
mbed_official 619:034e698bc035 567
mbed_official 619:034e698bc035 568 #define W7500x_CRG_BASE (W7500x_APB2_BASE + 0x00001000UL)
mbed_official 619:034e698bc035 569 #define W7500x_ADC_BASE (W7500x_APB2_BASE + 0x00000000UL)
mbed_official 619:034e698bc035 570
mbed_official 619:034e698bc035 571 #define W7500x_INFO_BGT (0x0003FDB8)
mbed_official 619:034e698bc035 572 #define W7500x_INFO_OSC (0x0003FDBC)
mbed_official 619:034e698bc035 573
mbed_official 619:034e698bc035 574 #define W7500x_TRIM_BGT (0x41001210)
mbed_official 619:034e698bc035 575 #define W7500x_TRIM_OSC (0x41001004)
mbed_official 619:034e698bc035 576
mbed_official 619:034e698bc035 577 #define W7500x_DUALTIMER0_BASE (W7500x_APB1_BASE + 0x00001000ul)
mbed_official 619:034e698bc035 578 #define W7500x_DUALTIMER1_BASE (W7500x_APB1_BASE + 0x00002000ul)
mbed_official 619:034e698bc035 579
mbed_official 619:034e698bc035 580 #define EXTI_Px_BASE (W7500x_APB2_BASE + 0x00002200UL)
mbed_official 619:034e698bc035 581
mbed_official 619:034e698bc035 582 #define GPIOA_BASE (W7500x_AHB_BASE + 0x00000000UL) // W7500x_AHB_BASE : 0x42000000UL
mbed_official 619:034e698bc035 583 #define GPIOB_BASE (W7500x_AHB_BASE + 0x01000000UL)
mbed_official 619:034e698bc035 584 #define GPIOC_BASE (W7500x_AHB_BASE + 0x02000000UL)
mbed_official 619:034e698bc035 585 #define GPIOD_BASE (W7500x_AHB_BASE + 0x03000000UL)
mbed_official 619:034e698bc035 586
mbed_official 619:034e698bc035 587 #define P_AFSR_BASE (W7500x_APB2_BASE + 0x00002000UL)
mbed_official 619:034e698bc035 588
mbed_official 619:034e698bc035 589 #define P_PCR_BASE (W7500x_APB2_BASE + 0x00003000UL)
mbed_official 619:034e698bc035 590
mbed_official 619:034e698bc035 591 #define I2C0_BASE (W7500x_APB1_BASE + 0x8000)
mbed_official 619:034e698bc035 592 #define I2C1_BASE (W7500x_APB1_BASE + 0x9000)
mbed_official 619:034e698bc035 593
mbed_official 619:034e698bc035 594 #define W7500x_PWM_BASE (W7500x_APB1_BASE + 0x00005000UL)
mbed_official 619:034e698bc035 595
mbed_official 619:034e698bc035 596 #define W7500x_RNG_BASE (W7500x_APB1_BASE + 0x00007000UL)
mbed_official 619:034e698bc035 597
mbed_official 619:034e698bc035 598 #define SSP0_BASE (0x4000A000)
mbed_official 619:034e698bc035 599 #define SSP1_BASE (0x4000B000)
mbed_official 619:034e698bc035 600
mbed_official 619:034e698bc035 601 #define W7500x_WATCHDOG_BASE (W7500x_APB1_BASE + 0x0000UL)
mbed_official 619:034e698bc035 602
mbed_official 619:034e698bc035 603 /**
mbed_official 619:034e698bc035 604 * @}
mbed_official 619:034e698bc035 605 */
mbed_official 619:034e698bc035 606
mbed_official 619:034e698bc035 607
mbed_official 619:034e698bc035 608 /** @addtogroup Peripheral_declaration
mbed_official 619:034e698bc035 609 * @{
mbed_official 619:034e698bc035 610 */
mbed_official 619:034e698bc035 611 #define CRG ((CRG_TypeDef *) W7500x_CRG_BASE)
mbed_official 619:034e698bc035 612
mbed_official 619:034e698bc035 613 #define UART0 ((UART_TypeDef *) W7500x_UART0_BASE)
mbed_official 619:034e698bc035 614 #define UART1 ((UART_TypeDef *) W7500x_UART1_BASE)
mbed_official 619:034e698bc035 615 #define UART2 ((S_UART_TypeDef *) W7500x_UART2_BASE)
mbed_official 619:034e698bc035 616
mbed_official 619:034e698bc035 617 #define ADC ((ADC_TypeDef *) W7500x_ADC_BASE)
mbed_official 619:034e698bc035 618
mbed_official 619:034e698bc035 619 #define DUALTIMER0_0 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER0_BASE) )
mbed_official 619:034e698bc035 620 #define DUALTIMER0_1 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER0_BASE + 0x20ul))
mbed_official 619:034e698bc035 621 #define DUALTIMER1_0 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER1_BASE) )
mbed_official 619:034e698bc035 622 #define DUALTIMER1_1 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER1_BASE + 0x20ul))
mbed_official 619:034e698bc035 623
mbed_official 619:034e698bc035 624 #define EXTI_PA ((P_Port_Def *) (EXTI_Px_BASE + 0x00000000UL)) /* PA_XX External interrupt Enable Register */
mbed_official 619:034e698bc035 625 #define EXTI_PB ((P_Port_Def *) (EXTI_Px_BASE + 0x00000040UL)) /* PB_XX External interrupt Enable Register */
mbed_official 619:034e698bc035 626 #define EXTI_PC ((P_Port_Def *) (EXTI_Px_BASE + 0x00000080UL)) /* PC_XX External interrupt Enable Register */
mbed_official 619:034e698bc035 627 #define EXTI_PD ((P_Port_D_Def *) (EXTI_Px_BASE + 0x000000C0UL)) /* PD_XX External interrupt Enable Register */
mbed_official 619:034e698bc035 628
mbed_official 619:034e698bc035 629 #define GPIOA ((GPIO_TypeDef *) (GPIOA_BASE) )
mbed_official 619:034e698bc035 630 #define GPIOB ((GPIO_TypeDef *) (GPIOB_BASE) )
mbed_official 619:034e698bc035 631 #define GPIOC ((GPIO_TypeDef *) (GPIOC_BASE) )
mbed_official 619:034e698bc035 632 #define GPIOD ((GPIO_TypeDef *) (GPIOD_BASE) )
mbed_official 619:034e698bc035 633
mbed_official 619:034e698bc035 634 #define PA_AFSR ((P_Port_Def *) (P_AFSR_BASE + 0x00000000UL)) /* PA_XX Pad Alternate Function Select Register */
mbed_official 619:034e698bc035 635 #define PB_AFSR ((P_Port_Def *) (P_AFSR_BASE + 0x00000040UL)) /* PB_XX Pad Alternate Function Select Register */
mbed_official 619:034e698bc035 636 #define PC_AFSR ((P_Port_Def *) (P_AFSR_BASE + 0x00000080UL)) /* PC_XX Pad Alternate Function Select Register */
mbed_official 619:034e698bc035 637 #define PD_AFSR ((P_Port_D_Def *) (P_AFSR_BASE + 0x000000C0UL)) /* PD_XX Pad Alternate Function Select Register */
mbed_official 619:034e698bc035 638
mbed_official 619:034e698bc035 639 #define PA_PCR ((P_Port_Def *) (P_PCR_BASE + 0x00000000UL)) /* PA_XX Pad Control Register */
mbed_official 619:034e698bc035 640 #define PB_PCR ((P_Port_Def *) (P_PCR_BASE + 0x00000040UL)) /* PB_XX Pad Control Register */
mbed_official 619:034e698bc035 641 #define PC_PCR ((P_Port_Def *) (P_PCR_BASE + 0x00000080UL)) /* PC_XX Pad Control Register */
mbed_official 619:034e698bc035 642 #define PD_PCR ((P_Port_D_Def *) (P_PCR_BASE + 0x000000C0UL)) /* PD_XX Pad Control Register */
mbed_official 619:034e698bc035 643
mbed_official 619:034e698bc035 644 #define I2C0 ((I2C_TypeDef *) I2C0_BASE)
mbed_official 619:034e698bc035 645 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
mbed_official 619:034e698bc035 646
mbed_official 619:034e698bc035 647
mbed_official 619:034e698bc035 648 #define TIMCLKEN0_0 *(uint32_t *)(W7500x_DUALTIMER0_BASE + 0x80ul)
mbed_official 619:034e698bc035 649 #define TIMCLKEN0_1 *(uint32_t *)(W7500x_DUALTIMER0_BASE + 0xA0ul)
mbed_official 619:034e698bc035 650 #define TIMCLKEN1_0 *(uint32_t *)(W7500x_DUALTIMER1_BASE + 0x80ul)
mbed_official 619:034e698bc035 651 #define TIMCLKEN1_1 *(uint32_t *)(W7500x_DUALTIMER1_BASE + 0xA0ul)
mbed_official 619:034e698bc035 652
mbed_official 619:034e698bc035 653 #define PWM ((PWM_TypeDef *) (W7500x_PWM_BASE + 0x800UL ))
mbed_official 619:034e698bc035 654 #define PWM_CH0 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE))
mbed_official 619:034e698bc035 655 #define PWM_CH1 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x100UL))
mbed_official 619:034e698bc035 656 #define PWM_CH2 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x200UL))
mbed_official 619:034e698bc035 657 #define PWM_CH3 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x300UL))
mbed_official 619:034e698bc035 658 #define PWM_CH4 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x400UL))
mbed_official 619:034e698bc035 659 #define PWM_CH5 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x500UL))
mbed_official 619:034e698bc035 660 #define PWM_CH6 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x600UL))
mbed_official 619:034e698bc035 661 #define PWM_CH7 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x700UL))
mbed_official 619:034e698bc035 662
mbed_official 619:034e698bc035 663 #define PWM_CH0_BASE (W7500x_PWM_BASE)
mbed_official 619:034e698bc035 664 #define PWM_CH1_BASE (W7500x_PWM_BASE + 0x100UL)
mbed_official 619:034e698bc035 665 #define PWM_CH2_BASE (W7500x_PWM_BASE + 0x200UL)
mbed_official 619:034e698bc035 666 #define PWM_CH3_BASE (W7500x_PWM_BASE + 0x300UL)
mbed_official 619:034e698bc035 667 #define PWM_CH4_BASE (W7500x_PWM_BASE + 0x400UL)
mbed_official 619:034e698bc035 668 #define PWM_CH5_BASE (W7500x_PWM_BASE + 0x500UL)
mbed_official 619:034e698bc035 669 #define PWM_CH6_BASE (W7500x_PWM_BASE + 0x600UL)
mbed_official 619:034e698bc035 670 #define PWM_CH7_BASE (W7500x_PWM_BASE + 0x700UL)
mbed_official 619:034e698bc035 671
mbed_official 619:034e698bc035 672 #define RNG ((RNG_TypeDef *) W7500x_RNG_BASE)
mbed_official 619:034e698bc035 673
mbed_official 619:034e698bc035 674 #define SSP0 ((SSP_TypeDef*) (SSP0_BASE))
mbed_official 619:034e698bc035 675 #define SSP1 ((SSP_TypeDef*) (SSP1_BASE))
mbed_official 619:034e698bc035 676
mbed_official 619:034e698bc035 677 #define WATCHDOG ((WATCHDOG_TypeDef *) W7500x_WATCHDOG_BASE)
mbed_official 619:034e698bc035 678
mbed_official 619:034e698bc035 679 /**
mbed_official 619:034e698bc035 680 * @}
mbed_official 619:034e698bc035 681 */
mbed_official 619:034e698bc035 682
mbed_official 619:034e698bc035 683
mbed_official 619:034e698bc035 684
mbed_official 619:034e698bc035 685 /******************************************************************************/
mbed_official 619:034e698bc035 686 /* */
mbed_official 619:034e698bc035 687 /* Clock Reset Generator */
mbed_official 619:034e698bc035 688 /* */
mbed_official 619:034e698bc035 689 /******************************************************************************/
mbed_official 619:034e698bc035 690 /**************** Bit definition for CRG_OSC_PDR **************************/
mbed_official 619:034e698bc035 691 #define CRG_OSC_PDR_NRMLOP (0x0ul) // Normal Operation
mbed_official 619:034e698bc035 692 #define CRG_OSC_PDR_PD (0x1ul) // Power Down
mbed_official 619:034e698bc035 693 /**************** Bit definition for CRG_PLL_PDR **************************/
mbed_official 619:034e698bc035 694 #define CRG_PLL_PDR_PD (0x0ul) // Power Down
mbed_official 619:034e698bc035 695 #define CRG_PLL_PDR_NRMLOP (0x1ul) // Normal Operation
mbed_official 619:034e698bc035 696 /**************** Bit definition for CRG_PLL_FCR **************************/
mbed_official 619:034e698bc035 697 //ToDo
mbed_official 619:034e698bc035 698 /**************** Bit definition for CRG_PLL_OER **************************/
mbed_official 619:034e698bc035 699 #define CRG_PLL_OER_DIS (0x0ul) // Clock out is disable
mbed_official 619:034e698bc035 700 #define CRG_PLL_OER_EN (0x1ul) // Clock out is enable
mbed_official 619:034e698bc035 701 /**************** Bit definition for CRG_PLL_BPR **************************/
mbed_official 619:034e698bc035 702 #define CRG_PLL_BPR_DIS (0x0ul) // Bypass disable. Normal operation
mbed_official 619:034e698bc035 703 #define CRG_PLL_BPR_EN (0x1ul) // Bypass enable. Clock will be set to external clock
mbed_official 619:034e698bc035 704 /**************** Bit definition for CRG_PLL_IFSR **************************/
mbed_official 619:034e698bc035 705 #define CRG_PLL_IFSR_RCLK (0x0ul) // Internal 8MHz RC oscillator clock(RCLK)
mbed_official 619:034e698bc035 706 #define CRG_PLL_IFSR_OCLK (0x1ul) // External oscillator clock (OCLK, 8MHz ~ 24MHz)
mbed_official 619:034e698bc035 707 /**************** Bit definition for CRG_FCLK_SSR **************************/
mbed_official 619:034e698bc035 708 #define CRG_FCLK_SSR_MCLK (0x01ul) // 00,01 Output clock of PLL(MCLK)
mbed_official 619:034e698bc035 709 #define CRG_FCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
mbed_official 619:034e698bc035 710 #define CRG_FCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
mbed_official 619:034e698bc035 711 /**************** Bit definition for CRG_FCLK_PVSR **************************/
mbed_official 619:034e698bc035 712 #define CRG_FCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
mbed_official 619:034e698bc035 713 #define CRG_FCLK_PVSR_DIV2 (0x01ul) // 1/2
mbed_official 619:034e698bc035 714 #define CRG_FCLK_PVSR_DIV4 (0x02ul) // 1/4
mbed_official 619:034e698bc035 715 #define CRG_FCLK_PVSR_DIV8 (0x03ul) // 1/8
mbed_official 619:034e698bc035 716 /**************** Bit definition for CRG_SSPCLK_SSR **************************/
mbed_official 619:034e698bc035 717 #define CRG_SSPCLK_SSR_DIS (0x00ul) // Disable clock
mbed_official 619:034e698bc035 718 #define CRG_SSPCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
mbed_official 619:034e698bc035 719 #define CRG_SSPCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
mbed_official 619:034e698bc035 720 #define CRG_SSPCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
mbed_official 619:034e698bc035 721 /**************** Bit definition for CRG_SSPCLK_PVSR **************************/
mbed_official 619:034e698bc035 722 #define CRG_SSPCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
mbed_official 619:034e698bc035 723 #define CRG_SSPCLK_PVSR_DIV2 (0x01ul) // 1/2
mbed_official 619:034e698bc035 724 #define CRG_SSPCLK_PVSR_DIV4 (0x02ul) // 1/4
mbed_official 619:034e698bc035 725 #define CRG_SSPCLK_PVSR_DIV8 (0x03ul) // 1/8
mbed_official 619:034e698bc035 726 /**************** Bit definition for CRG_ADCCLK_SSR **************************/
mbed_official 619:034e698bc035 727 #define CRG_ADCCLK_SSR_DIS (0x00ul) // Disable clock
mbed_official 619:034e698bc035 728 #define CRG_ADCCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
mbed_official 619:034e698bc035 729 #define CRG_ADCCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
mbed_official 619:034e698bc035 730 #define CRG_ADCCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
mbed_official 619:034e698bc035 731 /**************** Bit definition for CRG_ADCCLK_PVSR **************************/
mbed_official 619:034e698bc035 732 #define CRG_ADCCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
mbed_official 619:034e698bc035 733 #define CRG_ADCCLK_PVSR_DIV2 (0x01ul) // 1/2
mbed_official 619:034e698bc035 734 #define CRG_ADCCLK_PVSR_DIV4 (0x02ul) // 1/4
mbed_official 619:034e698bc035 735 #define CRG_ADCCLK_PVSR_DIV8 (0x03ul) // 1/8
mbed_official 619:034e698bc035 736 /**************** Bit definition for CRG_TIMER0/1CLK_SSR **************************/
mbed_official 619:034e698bc035 737 #define CRG_TIMERCLK_SSR_DIS (0x00ul) // Disable clock
mbed_official 619:034e698bc035 738 #define CRG_TIMERCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
mbed_official 619:034e698bc035 739 #define CRG_TIMERCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
mbed_official 619:034e698bc035 740 #define CRG_TIMERCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
mbed_official 619:034e698bc035 741 /**************** Bit definition for CRG_TIMER0/1CLK_PVSR **************************/
mbed_official 619:034e698bc035 742 #define CRG_TIMERCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
mbed_official 619:034e698bc035 743 #define CRG_TIMERCLK_PVSR_DIV2 (0x01ul) // 1/2
mbed_official 619:034e698bc035 744 #define CRG_TIMERCLK_PVSR_DIV4 (0x02ul) // 1/4
mbed_official 619:034e698bc035 745 #define CRG_TIMERCLK_PVSR_DIV8 (0x03ul) // 1/8
mbed_official 619:034e698bc035 746 #define CRG_TIMERCLK_PVSR_DIV16 (0x04ul) // 1/16
mbed_official 619:034e698bc035 747 #define CRG_TIMERCLK_PVSR_DIV32 (0x05ul) // 1/32
mbed_official 619:034e698bc035 748 #define CRG_TIMERCLK_PVSR_DIV64 (0x06ul) // 1/64
mbed_official 619:034e698bc035 749 #define CRG_TIMERCLK_PVSR_DIV128 (0x07ul) // 1/128
mbed_official 619:034e698bc035 750 /**************** Bit definition for CRG_PWMnCLK_SSR **************************/
mbed_official 619:034e698bc035 751 #define CRG_PWMCLK_SSR_DIS (0x00ul) // Disable clock
mbed_official 619:034e698bc035 752 #define CRG_PWMCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
mbed_official 619:034e698bc035 753 #define CRG_PWMCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
mbed_official 619:034e698bc035 754 #define CRG_PWMCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
mbed_official 619:034e698bc035 755 /**************** Bit definition for CRG_PWMnCLK_PVSR **************************/
mbed_official 619:034e698bc035 756 #define CRG_PWMCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
mbed_official 619:034e698bc035 757 #define CRG_PWMCLK_PVSR_DIV2 (0x01ul) // 1/2
mbed_official 619:034e698bc035 758 #define CRG_PWMCLK_PVSR_DIV4 (0x02ul) // 1/4
mbed_official 619:034e698bc035 759 #define CRG_PWMCLK_PVSR_DIV8 (0x03ul) // 1/8
mbed_official 619:034e698bc035 760 #define CRG_PWMCLK_PVSR_DIV16 (0x04ul) // 1/16
mbed_official 619:034e698bc035 761 #define CRG_PWMCLK_PVSR_DIV32 (0x05ul) // 1/32
mbed_official 619:034e698bc035 762 #define CRG_PWMCLK_PVSR_DIV64 (0x06ul) // 1/64
mbed_official 619:034e698bc035 763 #define CRG_PWMCLK_PVSR_DIV128 (0x07ul) // 1/128
mbed_official 619:034e698bc035 764 /**************** Bit definition for CRG_RTC_HS_SSR **************************/
mbed_official 619:034e698bc035 765 #define CRG_RTC_HS_SSR_DIS (0x00ul) // Disable clock
mbed_official 619:034e698bc035 766 #define CRG_RTC_HS_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
mbed_official 619:034e698bc035 767 #define CRG_RTC_HS_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
mbed_official 619:034e698bc035 768 #define CRG_RTC_HS_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
mbed_official 619:034e698bc035 769 /**************** Bit definition for CRG_RTC_HS_PVSR **************************/
mbed_official 619:034e698bc035 770 #define CRG_RTC_HS_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
mbed_official 619:034e698bc035 771 #define CRG_RTC_HS_PVSR_DIV2 (0x01ul) // 1/2
mbed_official 619:034e698bc035 772 #define CRG_RTC_HS_PVSR_DIV4 (0x02ul) // 1/4
mbed_official 619:034e698bc035 773 #define CRG_RTC_HS_PVSR_DIV8 (0x03ul) // 1/8
mbed_official 619:034e698bc035 774 #define CRG_RTC_HS_PVSR_DIV16 (0x04ul) // 1/16
mbed_official 619:034e698bc035 775 #define CRG_RTC_HS_PVSR_DIV32 (0x05ul) // 1/32
mbed_official 619:034e698bc035 776 #define CRG_RTC_HS_PVSR_DIV64 (0x06ul) // 1/64
mbed_official 619:034e698bc035 777 #define CRG_RTC_HS_PVSR_DIV128 (0x07ul) // 1/128
mbed_official 619:034e698bc035 778 /**************** Bit definition for CRG_RTC_SSR **************************/
mbed_official 619:034e698bc035 779 #define CRG_RTC_SSR_HS (0x00ul) // RTCCLK HS(High Speed clock)
mbed_official 619:034e698bc035 780 #define CRG_RTC_SSR_LW (0x01ul) // 32K_OSC_CLK(Low Speed external oscillator clock)
mbed_official 619:034e698bc035 781 /**************** Bit definition for CRG_WDOGCLK_HS_SSR **************************/
mbed_official 619:034e698bc035 782 #define CRG_WDOGCLK_HS_SSR_DIS (0x00ul) // Disable clock
mbed_official 619:034e698bc035 783 #define CRG_WDOGCLK_HS_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
mbed_official 619:034e698bc035 784 #define CRG_WDOGCLK_HS_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
mbed_official 619:034e698bc035 785 #define CRG_WDOGCLK_HS_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
mbed_official 619:034e698bc035 786 /**************** Bit definition for CRG_WDOGCLK_HS_PVSR **************************/
mbed_official 619:034e698bc035 787 #define CRG_WDOGCLK_HS_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
mbed_official 619:034e698bc035 788 #define CRG_WDOGCLK_HS_PVSR_DIV2 (0x01ul) // 1/2
mbed_official 619:034e698bc035 789 #define CRG_WDOGCLK_HS_PVSR_DIV4 (0x02ul) // 1/4
mbed_official 619:034e698bc035 790 #define CRG_WDOGCLK_HS_PVSR_DIV8 (0x03ul) // 1/8
mbed_official 619:034e698bc035 791 #define CRG_WDOGCLK_HS_PVSR_DIV16 (0x04ul) // 1/16
mbed_official 619:034e698bc035 792 #define CRG_WDOGCLK_HS_PVSR_DIV32 (0x05ul) // 1/32
mbed_official 619:034e698bc035 793 #define CRG_WDOGCLK_HS_PVSR_DIV64 (0x06ul) // 1/64
mbed_official 619:034e698bc035 794 #define CRG_WDOGCLK_HS_PVSR_DIV128 (0x07ul) // 1/128
mbed_official 619:034e698bc035 795 /**************** Bit definition for CRG_WDOGCLK_SSR **************************/
mbed_official 619:034e698bc035 796 #define CRG_WDOGCLK_SSR_HS (0x00ul) // RTCCLK HS(High Speed clock)
mbed_official 619:034e698bc035 797 #define CRG_WDOGCLK_SSR_LW (0x01ul) // 32K_OSC_CLK(Low Speed external oscillator clock)
mbed_official 619:034e698bc035 798 /**************** Bit definition for CRG_UARTCLK_SSR **************************/
mbed_official 619:034e698bc035 799 #define CRG_UARTCLK_SSR_DIS (0x00ul) // Disable clock
mbed_official 619:034e698bc035 800 #define CRG_UARTCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
mbed_official 619:034e698bc035 801 #define CRG_UARTCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
mbed_official 619:034e698bc035 802 #define CRG_UARTCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
mbed_official 619:034e698bc035 803 /**************** Bit definition for CRG_UARTCLK_PVSR **************************/
mbed_official 619:034e698bc035 804 #define CRG_UARTCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
mbed_official 619:034e698bc035 805 #define CRG_UARTCLK_PVSR_DIV2 (0x01ul) // 1/2
mbed_official 619:034e698bc035 806 #define CRG_UARTCLK_PVSR_DIV4 (0x02ul) // 1/4
mbed_official 619:034e698bc035 807 #define CRG_UARTCLK_PVSR_DIV8 (0x03ul) // 1/8
mbed_official 619:034e698bc035 808 /**************** Bit definition for CRG_MIICLK_ECR **************************/
mbed_official 619:034e698bc035 809 #define CRG_MIICLK_ECR_EN_RXCLK (0x01ul << 0) // Enable MII_RCK and MII_RCK_N
mbed_official 619:034e698bc035 810 #define CRG_MIICLK_ECR_EN_TXCLK (0x01ul << 1) // Enable MII_TCK and MII_TCK_N
mbed_official 619:034e698bc035 811 /**************** Bit definition for CRG_MONCLK_SSR **************************/
mbed_official 619:034e698bc035 812 #define CRG_MONCLK_SSR_MCLK (0x00ul) // PLL output clock (MCLK)
mbed_official 619:034e698bc035 813 #define CRG_MONCLK_SSR_FCLK (0x01ul) // FCLK
mbed_official 619:034e698bc035 814 #define CRG_MONCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
mbed_official 619:034e698bc035 815 #define CRG_MONCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
mbed_official 619:034e698bc035 816 #define CRG_MONCLK_SSR_ADCCLK (0x04ul) // ADCCLK
mbed_official 619:034e698bc035 817 #define CRG_MONCLK_SSR_SSPCLK (0x05ul) // SSPCLK
mbed_official 619:034e698bc035 818 #define CRG_MONCLK_SSR_TIMCLK0 (0x06ul) // TIMCLK0
mbed_official 619:034e698bc035 819 #define CRG_MONCLK_SSR_TIMCLK1 (0x07ul) // TIMCLK1
mbed_official 619:034e698bc035 820 #define CRG_MONCLK_SSR_PWMCLK0 (0x08ul) // PWMCLK0
mbed_official 619:034e698bc035 821 #define CRG_MONCLK_SSR_PWMCLK1 (0x09ul) // PWMCLK1
mbed_official 619:034e698bc035 822 #define CRG_MONCLK_SSR_PWMCLK2 (0x0Aul) // PWMCLK2
mbed_official 619:034e698bc035 823 #define CRG_MONCLK_SSR_PWMCLK3 (0x0Bul) // PWMCLK3
mbed_official 619:034e698bc035 824 #define CRG_MONCLK_SSR_PWMCLK4 (0x0Cul) // PWMCLK4
mbed_official 619:034e698bc035 825 #define CRG_MONCLK_SSR_PWMCLK5 (0x0Dul) // PWMCLK5
mbed_official 619:034e698bc035 826 #define CRG_MONCLK_SSR_PWMCLK6 (0x0Eul) // PWMCLK6
mbed_official 619:034e698bc035 827 #define CRG_MONCLK_SSR_PWMCLK7 (0x0Ful) // PWMCLK7
mbed_official 619:034e698bc035 828 #define CRG_MONCLK_SSR_UARTCLK (0x10ul) // UARTCLK
mbed_official 619:034e698bc035 829 #define CRG_MONCLK_SSR_MII_RXCLK (0x11ul) // MII_RXCLK
mbed_official 619:034e698bc035 830 #define CRG_MONCLK_SSR_MII_TXCLK (0x12ul) // MII_TXCLK
mbed_official 619:034e698bc035 831 #define CRG_MONCLK_SSR_RTCCLK (0x13ul) // RTCCLK
mbed_official 619:034e698bc035 832
mbed_official 619:034e698bc035 833 /******************************************************************************/
mbed_official 619:034e698bc035 834 /* */
mbed_official 619:034e698bc035 835 /* UART */
mbed_official 619:034e698bc035 836 /* */
mbed_official 619:034e698bc035 837 /******************************************************************************/
mbed_official 619:034e698bc035 838 /****************** Bit definition for UART Data(UARTDR) register *************************/
mbed_official 619:034e698bc035 839 #define UART_DR_OE (0x01ul << 11) // Overrun Error
mbed_official 619:034e698bc035 840 #define UART_DR_BE (0x01ul << 10) // Break Error
mbed_official 619:034e698bc035 841 #define UART_DR_PE (0x01ul << 9) // Parity Error
mbed_official 619:034e698bc035 842 #define UART_DR_FE (0x01ul << 8) // Framing Error
mbed_official 619:034e698bc035 843 //#define UART_DR_DR // ToDo
mbed_official 619:034e698bc035 844 /***************** Bit definition for UART Receive Status(UARTRSR) register ***************/
mbed_official 619:034e698bc035 845 #define UARTR_SR_OE (0x01ul << 3) // Overrun Error
mbed_official 619:034e698bc035 846 #define UARTR_SR_BE (0x01ul << 2) // Break Error
mbed_official 619:034e698bc035 847 #define UARTR_SR_PE (0x01ul << 1) // Parity Error
mbed_official 619:034e698bc035 848 #define UARTR_SR_FE (0x01ul << 0) // Framing Error
mbed_official 619:034e698bc035 849 /***************** Bit definition for UART Error Clear(UARTECR) register ******************/
mbed_official 619:034e698bc035 850 #define UARTE_CR_OE (0x01ul << 3) // Overrun Error
mbed_official 619:034e698bc035 851 #define UARTE_CR_BE (0x01ul << 2) // Break Error
mbed_official 619:034e698bc035 852 #define UARTE_CR_PE (0x01ul << 1) // Parity Error
mbed_official 619:034e698bc035 853 #define UARTE_CR_FE (0x01ul << 0) // Framing Error
mbed_official 619:034e698bc035 854 /****************** Bit definition for UART Flags(UARTFR) register ************************/
mbed_official 619:034e698bc035 855 #define UART_FR_RI (0x01ul << 8) // Ring indicator
mbed_official 619:034e698bc035 856 #define UART_FR_TXFE (0x01ul << 7) // Transmit FIFO empty
mbed_official 619:034e698bc035 857 #define UART_FR_RXFF (0x01ul << 6) // Receive FIFO full
mbed_official 619:034e698bc035 858 #define UART_FR_TXFF (0x01ul << 5) // Transmit FIFO full
mbed_official 619:034e698bc035 859 #define UART_FR_RXFE (0x01ul << 4) // Receive FIFO empty
mbed_official 619:034e698bc035 860 #define UART_FR_BUSY (0x01ul << 3) // UART busy
mbed_official 619:034e698bc035 861 #define UART_FR_DCD (0x01ul << 2) // Data carrier detect
mbed_official 619:034e698bc035 862 #define UART_FR_DSR (0x01ul << 1) // Data set ready
mbed_official 619:034e698bc035 863 #define UART_FR_CTS (0x01ul << 0) // Clear to send
mbed_official 619:034e698bc035 864 /********** Bit definition for UART Low-power Counter(UARTILPR) register *******************/
mbed_official 619:034e698bc035 865 #define UARTILPR_COUNTER (0xFFul << 0) // 8-bit low-power divisor value (0..255)
mbed_official 619:034e698bc035 866 /********************* Bit definition for Line Control(UARTLCR_H) register *****************/
mbed_official 619:034e698bc035 867 #define UART_LCR_H_SPS (0x1ul << 7) // Stick parity select
mbed_official 619:034e698bc035 868 #define UART_LCR_H_WLEN(n) ((n & 0x3ul) << 5) // Word length ( 0=5bits, 1=6bits, 2=7bits, 3=8bits )
mbed_official 619:034e698bc035 869 #define UART_LCR_H_FEN (0x1ul << 4) // Enable FIFOs
mbed_official 619:034e698bc035 870 #define UART_LCR_H_STP2 (0x1ul << 3) // Two stop bits select
mbed_official 619:034e698bc035 871 #define UART_LCR_H_EPS (0x1ul << 2) // Even parity select
mbed_official 619:034e698bc035 872 #define UART_LCR_H_PEN (0x1ul << 1) // Parity enable
mbed_official 619:034e698bc035 873 #define UART_LCR_H_BRK (0x1ul << 0) // Send break
mbed_official 619:034e698bc035 874 /********************* Bit definition for Contro(UARTCR) register *************************/
mbed_official 619:034e698bc035 875 #define UART_CR_CTSEn (0x1ul << 15) // CTS hardware flow control enable
mbed_official 619:034e698bc035 876 #define UART_CR_RTSEn (0x1ul << 14) // RTS hardware flow control enable
mbed_official 619:034e698bc035 877 #define UART_CR_Out2 (0x1ul << 13) // Complement of Out2 modem status output
mbed_official 619:034e698bc035 878 #define UART_CR_Out1 (0x1ul << 12) // Complement of Out1 modem status output
mbed_official 619:034e698bc035 879 #define UART_CR_RTS (0x1ul << 11) // Request to send
mbed_official 619:034e698bc035 880 #define UART_CR_DTR (0x1ul << 10) // Data transmit ready
mbed_official 619:034e698bc035 881 #define UART_CR_RXE (0x1ul << 9) // Receive enable
mbed_official 619:034e698bc035 882 #define UART_CR_TXE (0x1ul << 8) // Transmit enable
mbed_official 619:034e698bc035 883 #define UART_CR_LBE (0x1ul << 7) // Loop-back enable
mbed_official 619:034e698bc035 884 #define UART_CR_SIRLP (0x1ul << 2) // IrDA SIR low power mode
mbed_official 619:034e698bc035 885 #define UART_CR_SIREN (0x1ul << 1) // SIR enable
mbed_official 619:034e698bc035 886 #define UART_CR_UARTEN (0x1ul << 0) // UART enable
mbed_official 619:034e698bc035 887 /******* Bit definition for Interrupt FIFO Level Select(UARTIFLS) register *****************/
mbed_official 619:034e698bc035 888 #define UART_IFLS_RXIFLSEL(n) ((n & 0x7ul) << 3) // Receive interrupt FIFO level select(0=1/8 full, 1=1/4 full, 2=1/2 full, 3=3/4 full, 4=7/8 full)
mbed_official 619:034e698bc035 889 #define UART_IFLS_TXIFLSEL(n) ((n & 0x7ul) << 0) // Transmit interrupt FIFO level select(0=1/8 full, 1=1/4 full, 2=1/2 full, 3=3/4 full, 4=7/8 full)
mbed_official 619:034e698bc035 890 /******* Bit definition for Interrupt Mask Set/Clear(UARTIMSC) register ********************/
mbed_official 619:034e698bc035 891 #define UART_IMSC_OEIM (0x1ul << 10) // Overrun error interrupt mask
mbed_official 619:034e698bc035 892 #define UART_IMSC_BEIM (0x1ul << 9) // Break error interrupt mask
mbed_official 619:034e698bc035 893 #define UART_IMSC_PEIM (0x1ul << 8) // Parity error interrupt mask
mbed_official 619:034e698bc035 894 #define UART_IMSC_FEIM (0x1ul << 7) // Framing error interrupt mask
mbed_official 619:034e698bc035 895 #define UART_IMSC_RTIM (0x1ul << 6) // Receive interrupt mask
mbed_official 619:034e698bc035 896 #define UART_IMSC_TXIM (0x1ul << 5) // Transmit interrupt mask
mbed_official 619:034e698bc035 897 #define UART_IMSC_RXIM (0x1ul << 4) // Receive interrupt mask
mbed_official 619:034e698bc035 898 #define UART_IMSC_DSRMIM (0x1ul << 3) // nUARTDSR modem interrupt mask
mbed_official 619:034e698bc035 899 #define UART_IMSC_DCDMIM (0x1ul << 2) // nUARTDCD modem interrupt mask
mbed_official 619:034e698bc035 900 #define UART_IMSC_CTSMIM (0x1ul << 1) // nUARTCTS modem interrupt mask
mbed_official 619:034e698bc035 901 #define UART_IMSC_RIMIM (0x1ul << 0) // nUARTRI modem interrupt mask
mbed_official 619:034e698bc035 902 /*************** Bit definition for Raw Interrupt Status(UARTRIS) register *****************/
mbed_official 619:034e698bc035 903 #define UART_RIS_OEIM (0x1ul << 10) // Overrun error interrupt status
mbed_official 619:034e698bc035 904 #define UART_RIS_BEIM (0x1ul << 9) // Break error interrupt status
mbed_official 619:034e698bc035 905 #define UART_RIS_PEIM (0x1ul << 8) // Parity error interrupt status
mbed_official 619:034e698bc035 906 #define UART_RIS_FEIM (0x1ul << 7) // Framing error interrupt status
mbed_official 619:034e698bc035 907 #define UART_RIS_RTIM (0x1ul << 6) // Receive interrupt status
mbed_official 619:034e698bc035 908 #define UART_RIS_TXIM (0x1ul << 5) // Transmit interrupt status
mbed_official 619:034e698bc035 909 #define UART_RIS_RXIM (0x1ul << 4) // Receive interrupt status
mbed_official 619:034e698bc035 910 #define UART_RIS_DSRMIM (0x1ul << 3) // nUARTDSR modem interrupt status
mbed_official 619:034e698bc035 911 #define UART_RIS_DCDMIM (0x1ul << 2) // nUARTDCD modem interrupt status
mbed_official 619:034e698bc035 912 #define UART_RIS_CTSMIM (0x1ul << 1) // nUARTCTS modem interrupt status
mbed_official 619:034e698bc035 913 #define UART_RIS_RIMIM (0x1ul << 0) // nUARTRI modem interrupt status
mbed_official 619:034e698bc035 914 /************** Bit definition for Masked Interrupt Status(UARTMIS) register ****************/
mbed_official 619:034e698bc035 915 #define UART_MIS_OEIM (0x1ul << 10) // Overrun error masked interrupt status
mbed_official 619:034e698bc035 916 #define UART_MIS_BEIM (0x1ul << 9) // Break error masked interrupt status
mbed_official 619:034e698bc035 917 #define UART_MIS_PEIM (0x1ul << 8) // Parity error masked interrupt status
mbed_official 619:034e698bc035 918 #define UART_MIS_FEIM (0x1ul << 7) // Framing error masked interrupt status
mbed_official 619:034e698bc035 919 #define UART_MIS_RTIM (0x1ul << 6) // Receive masked interrupt status
mbed_official 619:034e698bc035 920 #define UART_MIS_TXIM (0x1ul << 5) // Transmit masked interrupt status
mbed_official 619:034e698bc035 921 #define UART_MIS_RXIM (0x1ul << 4) // Receive masked interrupt status
mbed_official 619:034e698bc035 922 #define UART_MIS_DSRMIM (0x1ul << 3) // nUARTDSR modem masked interrupt status
mbed_official 619:034e698bc035 923 #define UART_MIS_DCDMIM (0x1ul << 2) // nUARTDCD modem masked interrupt status
mbed_official 619:034e698bc035 924 #define UART_MIS_CTSMIM (0x1ul << 1) // nUARTCTS modem masked interrupt status
mbed_official 619:034e698bc035 925 #define UART_MIS_RIMIM (0x1ul << 0) // nUARTRI modem masked interrupt status
mbed_official 619:034e698bc035 926 /*************** Bit definition for Interrupt Clear(UARTICR) register ************************/
mbed_official 619:034e698bc035 927 #define UART_ICR_OEIM (0x1ul << 10) // Overrun error interrupt clear
mbed_official 619:034e698bc035 928 #define UART_ICR_BEIM (0x1ul << 9) // Break error interrupt clear
mbed_official 619:034e698bc035 929 #define UART_ICR_PEIM (0x1ul << 8) // Parity error interrupt clear
mbed_official 619:034e698bc035 930 #define UART_ICR_FEIM (0x1ul << 7) // Framing error interrupt clear
mbed_official 619:034e698bc035 931 #define UART_ICR_RTIM (0x1ul << 6) // Receive interrupt clear
mbed_official 619:034e698bc035 932 #define UART_ICR_TXIM (0x1ul << 5) // Transmit interrupt clear
mbed_official 619:034e698bc035 933 #define UART_ICR_RXIM (0x1ul << 4) // Receive interrupt clear
mbed_official 619:034e698bc035 934 #define UART_ICR_DSRMIM (0x1ul << 3) // nUARTDSR modem interrupt clear
mbed_official 619:034e698bc035 935 #define UART_ICR_DCDMIM (0x1ul << 2) // nUARTDCD modem interrupt clear
mbed_official 619:034e698bc035 936 #define UART_ICR_CTSMIM (0x1ul << 1) // nUARTCTS modem interrupt clear
mbed_official 619:034e698bc035 937 #define UART_ICR_RIMIM (0x1ul << 0) // nUARTRI modem interrupt clear
mbed_official 619:034e698bc035 938 /***************** Bit definition for DMA Control(UARTDMACR) register ************************/
mbed_official 619:034e698bc035 939 #define UART_DMACR_DMAONERR (0x1ul << 2) // DMA on error
mbed_official 619:034e698bc035 940 #define UART_DMACR_TXDMAE (0x1ul << 1) // Transmit DMA enable
mbed_official 619:034e698bc035 941 #define UART_DMACR_RXDMAE (0x1ul << 0) // Receive DMA enable
mbed_official 619:034e698bc035 942
mbed_official 619:034e698bc035 943 /******************************************************************************/
mbed_official 619:034e698bc035 944 /* */
mbed_official 619:034e698bc035 945 /* Simple UART */
mbed_official 619:034e698bc035 946 /* */
mbed_official 619:034e698bc035 947 /******************************************************************************/
mbed_official 619:034e698bc035 948 /***************** Bit definition for S_UART Data () register ************************/
mbed_official 619:034e698bc035 949 #define S_UART_DATA (0xFFul << 0)
mbed_official 619:034e698bc035 950 /***************** Bit definition for S_UART State() register ************************/
mbed_official 619:034e698bc035 951 #define S_UART_STATE_TX_BUF_OVERRUN (0x01ul << 2) // TX buffer overrun, wirte 1 to clear.
mbed_official 619:034e698bc035 952 #define S_UART_STATE_RX_BUF_FULL (0x01ul << 1) // RX buffer full, read only.
mbed_official 619:034e698bc035 953 #define S_UART_STATE_TX_BUF_FULL (0x01ul << 0) // TX buffer full, read only.
mbed_official 619:034e698bc035 954 /***************** Bit definition for S_UART Control() register ************************/
mbed_official 619:034e698bc035 955 #define S_UART_CTRL_HIGH_SPEED_TEST (0x01ul << 6) // High-speed test mode for TX only.
mbed_official 619:034e698bc035 956 #define S_UART_CTRL_RX_OVERRUN_EN (0x01ul << 5) // RX overrun interrupt enable.
mbed_official 619:034e698bc035 957 #define S_UART_CTRL_TX_OVERRUN_EN (0x01ul << 4) // TX overrun interrupt enable.
mbed_official 619:034e698bc035 958 #define S_UART_CTRL_RX_INT_EN (0x01ul << 3) // RX interrupt enable.
mbed_official 619:034e698bc035 959 #define S_UART_CTRL_TX_INT_EN (0x01ul << 2) // TX interrupt enable.
mbed_official 619:034e698bc035 960 #define S_UART_CTRL_RX_EN (0x01ul << 1) // RX enable.
mbed_official 619:034e698bc035 961 #define S_UART_CTRL_TX_EN (0x01ul << 0) // TX enable.
mbed_official 619:034e698bc035 962 /***************** Bit definition for S_UART Interrupt() register ************************/
mbed_official 619:034e698bc035 963 #define S_UART_INT_RX_OVERRUN (0x01ul << 3) // RX overrun interrupt. Wirte 1 to clear
mbed_official 619:034e698bc035 964 #define S_UART_INT_TX_OVERRUN (0x01ul << 2) // TX overrun interrupt. Write 1 to clear
mbed_official 619:034e698bc035 965 #define S_UART_INT_RX (0x01ul << 1) // RX interrupt. Write 1 to clear
mbed_official 619:034e698bc035 966 #define S_UART_INT_TX (0x01ul << 0) // TX interrupt. Write 1 to clear
mbed_official 619:034e698bc035 967
mbed_official 619:034e698bc035 968 /******************************************************************************/
mbed_official 619:034e698bc035 969 /* */
mbed_official 619:034e698bc035 970 /* Analog Digital Register */
mbed_official 619:034e698bc035 971 /* */
mbed_official 619:034e698bc035 972 /******************************************************************************/
mbed_official 619:034e698bc035 973
mbed_official 619:034e698bc035 974 /*********************** Bit definition for ADC_CTR ***********************/
mbed_official 619:034e698bc035 975 //#define ADC_CTR_SAMSEL_ABNORMAL (0x0ul) // Abnormal Operation
mbed_official 619:034e698bc035 976 //#define ADC_CTR_SAMSEL_NORMAL (0x1ul) // Normal Operation
mbed_official 619:034e698bc035 977 #define ADC_CTR_PWD_NRMOP (0x1ul) // Active Operation
mbed_official 619:034e698bc035 978 #define ADC_CTR_PWD_PD (0x3ul) // Power down
mbed_official 619:034e698bc035 979 /*********************** Bit definition for ADC_CHSEL ***********************/
mbed_official 619:034e698bc035 980 #define ADC_CHSEL_CH0 (0x0ul) // Channel 0
mbed_official 619:034e698bc035 981 #define ADC_CHSEL_CH1 (0x1ul) // Channel 1
mbed_official 619:034e698bc035 982 #define ADC_CHSEL_CH2 (0x2ul) // Channel 2
mbed_official 619:034e698bc035 983 #define ADC_CHSEL_CH3 (0x3ul) // Channel 3
mbed_official 619:034e698bc035 984 #define ADC_CHSEL_CH4 (0x4ul) // Channel 4
mbed_official 619:034e698bc035 985 #define ADC_CHSEL_CH5 (0x5ul) // Channel 5
mbed_official 619:034e698bc035 986 #define ADC_CHSEL_CH6 (0x6ul) // Channel 6
mbed_official 619:034e698bc035 987 #define ADC_CHSEL_CH7 (0x7ul) // Channel 7
mbed_official 619:034e698bc035 988 #define ADC_CHSEL_CH15 (0xful) // LDO output(1.5V)
mbed_official 619:034e698bc035 989 /*********************** Bit definition for ADC_START ***********************/
mbed_official 619:034e698bc035 990 #define ADC_START_START (0x1ul) // ADC conversion start
mbed_official 619:034e698bc035 991 /*********************** Bit definition for ADC_DATA ***********************/
mbed_official 619:034e698bc035 992 //ToDo (Readonly)
mbed_official 619:034e698bc035 993
mbed_official 619:034e698bc035 994 /*********************** Bit definition for ADC_INT ***********************/
mbed_official 619:034e698bc035 995 #define ADC_INT_MASK_DIS (0x0ul << 1) // Interrupt disable
mbed_official 619:034e698bc035 996 #define ADC_INT_MASK_ENA (0x1ul << 1) // Interrupt enable
mbed_official 619:034e698bc035 997 //ToDo (Readonly)
mbed_official 619:034e698bc035 998
mbed_official 619:034e698bc035 999 /*********************** Bit definition for ADC_INTCLR ***********************/
mbed_official 619:034e698bc035 1000 #define ADC_INTCLEAR (0x1ul) // ADC Interrupt clear
mbed_official 619:034e698bc035 1001
mbed_official 619:034e698bc035 1002 #define W7500x_ADC_BASE (W7500x_APB2_BASE + 0x00000000UL)
mbed_official 619:034e698bc035 1003 #define ADC ((ADC_TypeDef *) W7500x_ADC_BASE)
mbed_official 619:034e698bc035 1004
mbed_official 619:034e698bc035 1005 /******************************************************************************/
mbed_official 619:034e698bc035 1006 /* */
mbed_official 619:034e698bc035 1007 /* Dual Timer */
mbed_official 619:034e698bc035 1008 /* */
mbed_official 619:034e698bc035 1009 /******************************************************************************/
mbed_official 619:034e698bc035 1010
mbed_official 619:034e698bc035 1011 /*********************** Bit definition for dualtimer ***********************/
mbed_official 619:034e698bc035 1012 #define DUALTIMER_TimerControl_TimerDIsable 0x0ul
mbed_official 619:034e698bc035 1013 #define DUALTIMER_TimerControl_TimerEnable 0x1ul
mbed_official 619:034e698bc035 1014 #define DUALTIMER_TimerControl_TimerEnable_Pos 7
mbed_official 619:034e698bc035 1015
mbed_official 619:034e698bc035 1016 #define DUALTIMER_TimerControl_FreeRunning 0x0ul
mbed_official 619:034e698bc035 1017 #define DUALTIMER_TimerControl_Periodic 0x1ul
mbed_official 619:034e698bc035 1018 #define DUALTIMER_TimerControl_TimerMode_Pos 6
mbed_official 619:034e698bc035 1019
mbed_official 619:034e698bc035 1020 #define DUALTIMER_TimerControl_IntDisable 0x0ul
mbed_official 619:034e698bc035 1021 #define DUALTIMER_TimerControl_IntEnable 0x1ul
mbed_official 619:034e698bc035 1022 #define DUALTIMER_TimerControl_IntEnable_Pos 5
mbed_official 619:034e698bc035 1023
mbed_official 619:034e698bc035 1024 #define DUALTIMER_TimerControl_Pre_1 0x0ul
mbed_official 619:034e698bc035 1025 #define DUALTIMER_TimerControl_Pre_16 0x1ul
mbed_official 619:034e698bc035 1026 #define DUALTIMER_TimerControl_Pre_256 0x2ul
mbed_official 619:034e698bc035 1027 #define DUALTIMER_TimerControl_Pre_Pos 2
mbed_official 619:034e698bc035 1028
mbed_official 619:034e698bc035 1029 #define DUALTIMER_TimerControl_Size_16 0x0ul
mbed_official 619:034e698bc035 1030 #define DUALTIMER_TimerControl_Size_32 0x1ul
mbed_official 619:034e698bc035 1031 #define DUALTIMER_TimerControl_Size_Pos 1
mbed_official 619:034e698bc035 1032
mbed_official 619:034e698bc035 1033 #define DUALTIMER_TimerControl_Wrapping 0x0ul
mbed_official 619:034e698bc035 1034 #define DUALTIMER_TimerControl_OneShot 0x1ul
mbed_official 619:034e698bc035 1035 #define DUALTIMER_TimerControl_OneShot_Pos 0
mbed_official 619:034e698bc035 1036
mbed_official 619:034e698bc035 1037 /******************************************************************************/
mbed_official 619:034e698bc035 1038 /* */
mbed_official 619:034e698bc035 1039 /* External Interrupt */
mbed_official 619:034e698bc035 1040 /* */
mbed_official 619:034e698bc035 1041 /******************************************************************************/
mbed_official 619:034e698bc035 1042
mbed_official 619:034e698bc035 1043 /**************** Bit definition for Px_IER **************************/
mbed_official 619:034e698bc035 1044 #define EXTI_Px_INTPOR_RISING_EDGE (0x00ul << 0)
mbed_official 619:034e698bc035 1045 #define EXTI_Px_INTPOR_FALLING_EDGE (0x01ul << 0)
mbed_official 619:034e698bc035 1046 #define EXTI_Px_INTEN_DISABLE (0x00ul << 1)
mbed_official 619:034e698bc035 1047 #define EXTI_Px_INTEN_ENABLE (0x01ul << 1)
mbed_official 619:034e698bc035 1048
mbed_official 619:034e698bc035 1049 /******************************************************************************/
mbed_official 619:034e698bc035 1050 /* */
mbed_official 619:034e698bc035 1051 /* GPIO */
mbed_official 619:034e698bc035 1052 /* */
mbed_official 619:034e698bc035 1053 /******************************************************************************/
mbed_official 619:034e698bc035 1054
mbed_official 619:034e698bc035 1055 /**************** Bit definition for Px_AFSR **************************/
mbed_official 619:034e698bc035 1056 #define Px_AFSR_AF0 (0x00ul)
mbed_official 619:034e698bc035 1057 #define Px_AFSR_AF1 (0x01ul)
mbed_official 619:034e698bc035 1058 #define Px_AFSR_AF2 (0x02ul)
mbed_official 619:034e698bc035 1059 #define Px_AFSR_AF3 (0x03ul)
mbed_official 619:034e698bc035 1060 /**************** Bit definition for Px_PCR **************************/
mbed_official 619:034e698bc035 1061 #define Px_PCR_PUPD_DOWN (0x01ul << 0) // Pull Down
mbed_official 619:034e698bc035 1062 #define Px_PCR_PUPD_UP (0x01ul << 1) // Pull Up
mbed_official 619:034e698bc035 1063 #define Px_PCR_DS_HIGH (0x01ul << 2) // High Driving
mbed_official 619:034e698bc035 1064 #define Px_PCR_OD (0x01ul << 3) // Open Drain
mbed_official 619:034e698bc035 1065 #define Px_PCR_IE (0x01ul << 5) // Input Buffer Enable
mbed_official 619:034e698bc035 1066 #define Px_PCR_CS_SUMMIT (0x01ul << 6) // Use Summit Trigger Input Buffer
mbed_official 619:034e698bc035 1067
mbed_official 619:034e698bc035 1068 /******************************************************************************/
mbed_official 619:034e698bc035 1069 /* */
mbed_official 619:034e698bc035 1070 /* I2C */
mbed_official 619:034e698bc035 1071 /* */
mbed_official 619:034e698bc035 1072 /******************************************************************************/
mbed_official 619:034e698bc035 1073
mbed_official 619:034e698bc035 1074 /**************** Bit definition for I2C_CTR **************************/
mbed_official 619:034e698bc035 1075 #define I2C_CTR_COREEN (0x01ul << 7 ) // 0x80
mbed_official 619:034e698bc035 1076 #define I2C_CTR_INTEREN (0x01ul << 6 ) // 0x40
mbed_official 619:034e698bc035 1077 #define I2C_CTR_MODE (0x01ul << 5 ) // 0x20
mbed_official 619:034e698bc035 1078 #define I2C_CTR_ADDR10 (0x01ul << 4 ) // 0x10
mbed_official 619:034e698bc035 1079 #define I2C_CTR_CTRRWN (0x01ul << 3 ) // 0x08
mbed_official 619:034e698bc035 1080 #define I2C_CTR_CTEN (0x01ul << 2 ) // 0x04
mbed_official 619:034e698bc035 1081
mbed_official 619:034e698bc035 1082 /**************** Bit definition for I2C_CMDR **************************/
mbed_official 619:034e698bc035 1083 #define I2C_CMDR_STA (0x01ul << 7 ) // 0x80
mbed_official 619:034e698bc035 1084 #define I2C_CMDR_STO (0x01ul << 6 ) // 0x40
mbed_official 619:034e698bc035 1085 #define I2C_CMDR_ACK (0x01ul << 5 ) // 0x20
mbed_official 619:034e698bc035 1086 #define I2C_CMDR_RESTA (0x01ul << 4 ) // 0x10
mbed_official 619:034e698bc035 1087
mbed_official 619:034e698bc035 1088 /**************** Bit definition for I2C_ISCR **************************/
mbed_official 619:034e698bc035 1089 #define I2C_ISCR_RST (0x01ul << 1) // 0x01
mbed_official 619:034e698bc035 1090
mbed_official 619:034e698bc035 1091 /**************** Bit definition for I2C_SR **************************/
mbed_official 619:034e698bc035 1092 #define I2C_SR_TX (0x01ul << 9 ) // 0x200
mbed_official 619:034e698bc035 1093 #define I2C_SR_RX (0x01ul << 8 ) // 0x100
mbed_official 619:034e698bc035 1094 #define I2C_SR_ACKT (0x01ul << 7 ) // 0x080
mbed_official 619:034e698bc035 1095 #define I2C_SR_BT (0x01ul << 6 ) // 0x040
mbed_official 619:034e698bc035 1096 #define I2C_SR_SA (0x01ul << 5 ) // 0x020
mbed_official 619:034e698bc035 1097 #define I2C_SR_SB (0x01ul << 4 ) // 0x010
mbed_official 619:034e698bc035 1098 #define I2C_SR_AL (0x01ul << 3 ) // 0x008
mbed_official 619:034e698bc035 1099 #define I2C_SR_TO (0x01ul << 2 ) // 0x004
mbed_official 619:034e698bc035 1100 #define I2C_SR_SRW (0x01ul << 1 ) // 0x002
mbed_official 619:034e698bc035 1101 #define I2C_SR_ACKR (0x01ul << 0 ) // 0x001
mbed_official 619:034e698bc035 1102
mbed_official 619:034e698bc035 1103 /**************** Bit definition for I2C_ISR **************************/
mbed_official 619:034e698bc035 1104 #define I2C_ISR_STAE (0x01ul << 4 ) // 0x010
mbed_official 619:034e698bc035 1105 #define I2C_ISR_STOE (0x01ul << 3 ) // 0x008
mbed_official 619:034e698bc035 1106 #define I2C_ISR_TOE (0x01ul << 2 ) // 0x004
mbed_official 619:034e698bc035 1107 #define I2C_ISR_ACK_RXE (0x01ul << 1 ) // 0x002
mbed_official 619:034e698bc035 1108 #define I2C_ISR_ACK_TXE (0x01ul << 0 ) // 0x001
mbed_official 619:034e698bc035 1109
mbed_official 619:034e698bc035 1110 /**************** Bit definition for I2C_ISMR **************************/
mbed_official 619:034e698bc035 1111 #define I2C_ISR_STAEM (0x01ul << 4 ) // 0x010
mbed_official 619:034e698bc035 1112 #define I2C_ISR_STOEM (0x01ul << 3 ) // 0x008
mbed_official 619:034e698bc035 1113 #define I2C_ISR_TOEM (0x01ul << 2 ) // 0x004
mbed_official 619:034e698bc035 1114 #define I2C_ISR_ACK_RXEM (0x01ul << 1 ) // 0x002
mbed_official 619:034e698bc035 1115 #define I2C_ISR_ACK_TXEM (0x01ul << 0 ) // 0x001
mbed_official 619:034e698bc035 1116
mbed_official 619:034e698bc035 1117 /******************************************************************************/
mbed_official 619:034e698bc035 1118 /* */
mbed_official 619:034e698bc035 1119 /* PWM */
mbed_official 619:034e698bc035 1120 /* */
mbed_official 619:034e698bc035 1121 /******************************************************************************/
mbed_official 619:034e698bc035 1122
mbed_official 619:034e698bc035 1123 /******************************************************************************/
mbed_official 619:034e698bc035 1124 /* */
mbed_official 619:034e698bc035 1125 /* Random number generator Register */
mbed_official 619:034e698bc035 1126 /* */
mbed_official 619:034e698bc035 1127 /******************************************************************************/
mbed_official 619:034e698bc035 1128
mbed_official 619:034e698bc035 1129 /*********************** Bit definition for RNG_RUN ***********************/
mbed_official 619:034e698bc035 1130 #define RNG_RUN_STOP (0x0ul) // STOP RNG shift register
mbed_official 619:034e698bc035 1131 #define RNG_RUN_RUN (0x1ul) // RUN RNG shift register
mbed_official 619:034e698bc035 1132 /*********************** Bit definition for RNG_SEED ***********************/
mbed_official 619:034e698bc035 1133 //ToDo
mbed_official 619:034e698bc035 1134
mbed_official 619:034e698bc035 1135 /*********************** Bit definition for RNG_CLKSEL ***********************/
mbed_official 619:034e698bc035 1136 #define RNG_CLKSEL_RNGCLK (0x0ul) // RNGCLK is source clock for rng shift register
mbed_official 619:034e698bc035 1137 #define RNG_CLKSEL_APBCLK (0x1ul) // APBCLK is source clock for rng shift register
mbed_official 619:034e698bc035 1138 /*********************** Bit definition for RNG_ENABLE ***********************/
mbed_official 619:034e698bc035 1139 #define RNG_MANUAL_DISABLE (0x0ul) // RNG disble
mbed_official 619:034e698bc035 1140 #define RNG_MANUAL_ENABLE (0x1ul) // RNG enable
mbed_official 619:034e698bc035 1141 /*********************** Bit definition for RNG_RN ***********************/
mbed_official 619:034e698bc035 1142 //ToDo
mbed_official 619:034e698bc035 1143
mbed_official 619:034e698bc035 1144 /*********************** Bit definition for RNG_POLY ***********************/
mbed_official 619:034e698bc035 1145 //ToDo
mbed_official 619:034e698bc035 1146
mbed_official 619:034e698bc035 1147
mbed_official 619:034e698bc035 1148
mbed_official 619:034e698bc035 1149 typedef enum
mbed_official 619:034e698bc035 1150 {
mbed_official 619:034e698bc035 1151 PAD_PA = 0,
mbed_official 619:034e698bc035 1152 PAD_PB,
mbed_official 619:034e698bc035 1153 PAD_PC,
mbed_official 619:034e698bc035 1154 PAD_PD
mbed_official 619:034e698bc035 1155 }PAD_Type;
mbed_official 619:034e698bc035 1156
mbed_official 619:034e698bc035 1157 typedef enum
mbed_official 619:034e698bc035 1158 {
mbed_official 619:034e698bc035 1159 PAD_AF0 = Px_AFSR_AF0,
mbed_official 619:034e698bc035 1160 PAD_AF1 = Px_AFSR_AF1,
mbed_official 619:034e698bc035 1161 PAD_AF2 = Px_AFSR_AF2,
mbed_official 619:034e698bc035 1162 PAD_AF3 = Px_AFSR_AF3
mbed_official 619:034e698bc035 1163 }PAD_AF_TypeDef;
mbed_official 619:034e698bc035 1164
mbed_official 619:034e698bc035 1165
mbed_official 619:034e698bc035 1166 #if !defined (USE_HAL_DRIVER)
mbed_official 619:034e698bc035 1167 #define USE_HAL_DRIVER
mbed_official 619:034e698bc035 1168 #endif /* USE_HAL_DRIVER */
mbed_official 619:034e698bc035 1169
mbed_official 619:034e698bc035 1170
mbed_official 619:034e698bc035 1171
mbed_official 619:034e698bc035 1172 #if defined (USE_HAL_DRIVER)
mbed_official 619:034e698bc035 1173 // #include "system_W7500x.h"
mbed_official 619:034e698bc035 1174 // #include "W7500x_conf.h"
mbed_official 619:034e698bc035 1175 #endif
mbed_official 619:034e698bc035 1176
mbed_official 619:034e698bc035 1177 #ifdef USE_FULL_ASSERT
mbed_official 619:034e698bc035 1178 #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__,__LINE__))
mbed_official 619:034e698bc035 1179 #else
mbed_official 619:034e698bc035 1180 #define assert_param(expr) ((void)0)
mbed_official 619:034e698bc035 1181 #endif /* USE_FULL_ASSERT */
mbed_official 619:034e698bc035 1182
mbed_official 619:034e698bc035 1183 #ifdef __cplusplus
mbed_official 619:034e698bc035 1184 }
mbed_official 619:034e698bc035 1185 #endif
mbed_official 619:034e698bc035 1186
mbed_official 619:034e698bc035 1187 #endif /* W7500x_H */
mbed_official 619:034e698bc035 1188
mbed_official 619:034e698bc035 1189
mbed_official 619:034e698bc035 1190
mbed_official 619:034e698bc035 1191 /************************ (C) COPYRIGHT Wiznet *****END OF FILE****/