marcus chiou / mbed-src

mbed library sources

Fork of mbed-src by mbed official

targets/hal/TARGET_NXP/TARGET_LPC82X/gpio_irq_api.c@613:bc40b8d2aec4, 2015-08-20 (annotated)

Committer:
mbed_official
Date:
Thu Aug 20 10:45:13 2015 +0100
Revision:
613:bc40b8d2aec4
Parent:
337:6ed01c00b962 
Synchronized with git revision 92ca8c7b60a283b6bb60eb65b183dac1599f0ade



Full URL: https://github.com/mbedmicro/mbed/commit/92ca8c7b60a283b6bb60eb65b183dac1599f0ade/



Nordic: update application start address in GCC linker script

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 337:6ed01c00b962 1 /* mbed Microcontroller Library
mbed_official 337:6ed01c00b962 2 * Copyright (c) 2006-2013 ARM Limited
mbed_official 337:6ed01c00b962 3 *
mbed_official 337:6ed01c00b962 4 * Licensed under the Apache License, Version 2.0 (the "License");
mbed_official 337:6ed01c00b962 5 * you may not use this file except in compliance with the License.
mbed_official 337:6ed01c00b962 6 * You may obtain a copy of the License at
mbed_official 337:6ed01c00b962 7 *
mbed_official 337:6ed01c00b962 8 * http://www.apache.org/licenses/LICENSE-2.0
mbed_official 337:6ed01c00b962 9 *
mbed_official 337:6ed01c00b962 10 * Unless required by applicable law or agreed to in writing, software
mbed_official 337:6ed01c00b962 11 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 337:6ed01c00b962 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 337:6ed01c00b962 13 * See the License for the specific language governing permissions and
mbed_official 337:6ed01c00b962 14 * limitations under the License.
mbed_official 337:6ed01c00b962 15 */
mbed_official 337:6ed01c00b962 16 #include <stddef.h>
mbed_official 337:6ed01c00b962 17
mbed_official 337:6ed01c00b962 18 #include "cmsis.h"
mbed_official 337:6ed01c00b962 19 #include "gpio_irq_api.h"
mbed_official 337:6ed01c00b962 20 #include "mbed_error.h"
mbed_official 337:6ed01c00b962 21
mbed_official 337:6ed01c00b962 22 #if DEVICE_INTERRUPTIN
mbed_official 337:6ed01c00b962 23
mbed_official 337:6ed01c00b962 24 #define CHANNEL_NUM 8
mbed_official 337:6ed01c00b962 25 #define LPC_GPIO_X LPC_PIN_INT
mbed_official 337:6ed01c00b962 26 #define PININT_IRQ PIN_INT0_IRQn
mbed_official 337:6ed01c00b962 27
mbed_official 337:6ed01c00b962 28 static uint32_t channel_ids[CHANNEL_NUM] = {0};
mbed_official 337:6ed01c00b962 29 static gpio_irq_handler irq_handler;
mbed_official 337:6ed01c00b962 30
mbed_official 337:6ed01c00b962 31 static inline void handle_interrupt_in(uint32_t channel)
mbed_official 337:6ed01c00b962 32 {
mbed_official 337:6ed01c00b962 33 uint32_t ch_bit = (1 << channel);
mbed_official 337:6ed01c00b962 34 // Return immediately if:
mbed_official 337:6ed01c00b962 35 // * The interrupt was already served
mbed_official 337:6ed01c00b962 36 // * There is no user handler
mbed_official 337:6ed01c00b962 37 // * It is a level interrupt, not an edge interrupt
mbed_official 337:6ed01c00b962 38 if ( ((LPC_GPIO_X->IST & ch_bit) == 0) ||
mbed_official 337:6ed01c00b962 39 (channel_ids[channel] == 0 ) ||
mbed_official 337:6ed01c00b962 40 (LPC_GPIO_X->ISEL & ch_bit ) ) return;
mbed_official 337:6ed01c00b962 41
mbed_official 337:6ed01c00b962 42 if ((LPC_GPIO_X->IENR & ch_bit) && (LPC_GPIO_X->RISE & ch_bit)) {
mbed_official 337:6ed01c00b962 43 irq_handler(channel_ids[channel], IRQ_RISE);
mbed_official 337:6ed01c00b962 44 LPC_GPIO_X->RISE = ch_bit;
mbed_official 337:6ed01c00b962 45 }
mbed_official 337:6ed01c00b962 46 if ((LPC_GPIO_X->IENF & ch_bit) && (LPC_GPIO_X->FALL & ch_bit)) {
mbed_official 337:6ed01c00b962 47 irq_handler(channel_ids[channel], IRQ_FALL);
mbed_official 337:6ed01c00b962 48 }
mbed_official 337:6ed01c00b962 49 LPC_GPIO_X->IST = ch_bit;
mbed_official 337:6ed01c00b962 50 }
mbed_official 337:6ed01c00b962 51
mbed_official 337:6ed01c00b962 52 void gpio_irq0(void) {handle_interrupt_in(0);}
mbed_official 337:6ed01c00b962 53 void gpio_irq1(void) {handle_interrupt_in(1);}
mbed_official 337:6ed01c00b962 54 void gpio_irq2(void) {handle_interrupt_in(2);}
mbed_official 337:6ed01c00b962 55 void gpio_irq3(void) {handle_interrupt_in(3);}
mbed_official 337:6ed01c00b962 56 void gpio_irq4(void) {handle_interrupt_in(4);}
mbed_official 337:6ed01c00b962 57 void gpio_irq5(void) {handle_interrupt_in(5);}
mbed_official 337:6ed01c00b962 58 void gpio_irq6(void) {handle_interrupt_in(6);}
mbed_official 337:6ed01c00b962 59 void gpio_irq7(void) {handle_interrupt_in(7);}
mbed_official 337:6ed01c00b962 60
mbed_official 337:6ed01c00b962 61 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
mbed_official 337:6ed01c00b962 62 {
mbed_official 337:6ed01c00b962 63 if (pin == NC) return -1;
mbed_official 337:6ed01c00b962 64
mbed_official 337:6ed01c00b962 65 irq_handler = handler;
mbed_official 337:6ed01c00b962 66
mbed_official 337:6ed01c00b962 67 int found_free_channel = 0;
mbed_official 337:6ed01c00b962 68 int i = 0;
mbed_official 337:6ed01c00b962 69 for (i=0; i<CHANNEL_NUM; i++) {
mbed_official 337:6ed01c00b962 70 if (channel_ids[i] == 0) {
mbed_official 337:6ed01c00b962 71 channel_ids[i] = id;
mbed_official 337:6ed01c00b962 72 obj->ch = i;
mbed_official 337:6ed01c00b962 73 found_free_channel = 1;
mbed_official 337:6ed01c00b962 74 break;
mbed_official 337:6ed01c00b962 75 }
mbed_official 337:6ed01c00b962 76 }
mbed_official 337:6ed01c00b962 77 if (!found_free_channel) return -1;
mbed_official 337:6ed01c00b962 78
mbed_official 337:6ed01c00b962 79 /* Enable AHB clock to the GPIO domain. */
mbed_official 337:6ed01c00b962 80 LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6);
mbed_official 337:6ed01c00b962 81
mbed_official 337:6ed01c00b962 82 LPC_SYSCON->PINTSEL[obj->ch] = (pin >> PIN_SHIFT);
mbed_official 337:6ed01c00b962 83
mbed_official 337:6ed01c00b962 84 // Interrupt Wake-Up Enable
mbed_official 337:6ed01c00b962 85 LPC_SYSCON->STARTERP0 |= 1 << obj->ch;
mbed_official 337:6ed01c00b962 86
mbed_official 337:6ed01c00b962 87 void (*channels_irq)(void) = NULL;
mbed_official 337:6ed01c00b962 88 switch (obj->ch) {
mbed_official 337:6ed01c00b962 89 case 0: channels_irq = &gpio_irq0; break;
mbed_official 337:6ed01c00b962 90 case 1: channels_irq = &gpio_irq1; break;
mbed_official 337:6ed01c00b962 91 case 2: channels_irq = &gpio_irq2; break;
mbed_official 337:6ed01c00b962 92 case 3: channels_irq = &gpio_irq3; break;
mbed_official 337:6ed01c00b962 93 case 4: channels_irq = &gpio_irq4; break;
mbed_official 337:6ed01c00b962 94 case 5: channels_irq = &gpio_irq5; break;
mbed_official 337:6ed01c00b962 95 case 6: channels_irq = &gpio_irq6; break;
mbed_official 337:6ed01c00b962 96 case 7: channels_irq = &gpio_irq7; break;
mbed_official 337:6ed01c00b962 97 }
mbed_official 337:6ed01c00b962 98 NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
mbed_official 337:6ed01c00b962 99 NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
mbed_official 337:6ed01c00b962 100
mbed_official 337:6ed01c00b962 101 return 0;
mbed_official 337:6ed01c00b962 102 }
mbed_official 337:6ed01c00b962 103
mbed_official 337:6ed01c00b962 104 void gpio_irq_free(gpio_irq_t *obj)
mbed_official 337:6ed01c00b962 105 {
mbed_official 337:6ed01c00b962 106 channel_ids[obj->ch] = 0;
mbed_official 337:6ed01c00b962 107 LPC_SYSCON->STARTERP0 &= ~(1 << obj->ch);
mbed_official 337:6ed01c00b962 108 }
mbed_official 337:6ed01c00b962 109
mbed_official 337:6ed01c00b962 110 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
mbed_official 337:6ed01c00b962 111 {
mbed_official 337:6ed01c00b962 112 unsigned int ch_bit = (1 << obj->ch);
mbed_official 337:6ed01c00b962 113
mbed_official 337:6ed01c00b962 114 // Clear interrupt
mbed_official 337:6ed01c00b962 115 if (!(LPC_GPIO_X->ISEL & ch_bit))
mbed_official 337:6ed01c00b962 116 LPC_GPIO_X->IST = ch_bit;
mbed_official 337:6ed01c00b962 117
mbed_official 337:6ed01c00b962 118 // Edge trigger
mbed_official 337:6ed01c00b962 119 LPC_GPIO_X->ISEL &= ~ch_bit;
mbed_official 337:6ed01c00b962 120 if (event == IRQ_RISE) {
mbed_official 337:6ed01c00b962 121 if (enable) {
mbed_official 337:6ed01c00b962 122 LPC_GPIO_X->IENR |= ch_bit;
mbed_official 337:6ed01c00b962 123 } else {
mbed_official 337:6ed01c00b962 124 LPC_GPIO_X->IENR &= ~ch_bit;
mbed_official 337:6ed01c00b962 125 }
mbed_official 337:6ed01c00b962 126 } else {
mbed_official 337:6ed01c00b962 127 if (enable) {
mbed_official 337:6ed01c00b962 128 LPC_GPIO_X->IENF |= ch_bit;
mbed_official 337:6ed01c00b962 129 } else {
mbed_official 337:6ed01c00b962 130 LPC_GPIO_X->IENF &= ~ch_bit;
mbed_official 337:6ed01c00b962 131 }
mbed_official 337:6ed01c00b962 132 }
mbed_official 337:6ed01c00b962 133 }
mbed_official 337:6ed01c00b962 134
mbed_official 337:6ed01c00b962 135 void gpio_irq_enable(gpio_irq_t *obj)
mbed_official 337:6ed01c00b962 136 {
mbed_official 337:6ed01c00b962 137 NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
mbed_official 337:6ed01c00b962 138 }
mbed_official 337:6ed01c00b962 139
mbed_official 337:6ed01c00b962 140 void gpio_irq_disable(gpio_irq_t *obj)
mbed_official 337:6ed01c00b962 141 {
mbed_official 337:6ed01c00b962 142 NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
mbed_official 337:6ed01c00b962 143 }
mbed_official 337:6ed01c00b962 144
mbed_official 337:6ed01c00b962 145 #endif