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targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rcc.h@634:ac7d6880524d, 2015-09-28 (annotated)
- Committer:
- mbed_official
- Date:
- Mon Sep 28 20:15:09 2015 +0100
- Revision:
- 634:ac7d6880524d
- Parent:
- 632:7687fb9c4f91
Synchronized with git revision 9b7d23d47153c298a6d24de9a415202705889d11
Full URL: https://github.com/mbedmicro/mbed/commit/9b7d23d47153c298a6d24de9a415202705889d11/
Revert "[NUCLEO_F303K8] add support of the STM32F303K8"
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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mbed_official | 330:c80ac197fa6a | 1 | /** |
mbed_official | 330:c80ac197fa6a | 2 | ****************************************************************************** |
mbed_official | 330:c80ac197fa6a | 3 | * @file stm32f3xx_hal_rcc.h |
mbed_official | 330:c80ac197fa6a | 4 | * @author MCD Application Team |
mbed_official | 634:ac7d6880524d | 5 | * @version V1.1.0 |
mbed_official | 634:ac7d6880524d | 6 | * @date 12-Sept-2014 |
mbed_official | 330:c80ac197fa6a | 7 | * @brief Header file of RCC HAL module. |
mbed_official | 330:c80ac197fa6a | 8 | ****************************************************************************** |
mbed_official | 330:c80ac197fa6a | 9 | * @attention |
mbed_official | 330:c80ac197fa6a | 10 | * |
mbed_official | 634:ac7d6880524d | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
mbed_official | 330:c80ac197fa6a | 12 | * |
mbed_official | 330:c80ac197fa6a | 13 | * Redistribution and use in source and binary forms, with or without modification, |
mbed_official | 330:c80ac197fa6a | 14 | * are permitted provided that the following conditions are met: |
mbed_official | 330:c80ac197fa6a | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
mbed_official | 330:c80ac197fa6a | 16 | * this list of conditions and the following disclaimer. |
mbed_official | 330:c80ac197fa6a | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
mbed_official | 330:c80ac197fa6a | 18 | * this list of conditions and the following disclaimer in the documentation |
mbed_official | 330:c80ac197fa6a | 19 | * and/or other materials provided with the distribution. |
mbed_official | 330:c80ac197fa6a | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
mbed_official | 330:c80ac197fa6a | 21 | * may be used to endorse or promote products derived from this software |
mbed_official | 330:c80ac197fa6a | 22 | * without specific prior written permission. |
mbed_official | 330:c80ac197fa6a | 23 | * |
mbed_official | 330:c80ac197fa6a | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
mbed_official | 330:c80ac197fa6a | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
mbed_official | 330:c80ac197fa6a | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
mbed_official | 330:c80ac197fa6a | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
mbed_official | 330:c80ac197fa6a | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
mbed_official | 330:c80ac197fa6a | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
mbed_official | 330:c80ac197fa6a | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
mbed_official | 330:c80ac197fa6a | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
mbed_official | 330:c80ac197fa6a | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
mbed_official | 330:c80ac197fa6a | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 330:c80ac197fa6a | 34 | * |
mbed_official | 330:c80ac197fa6a | 35 | ****************************************************************************** |
mbed_official | 330:c80ac197fa6a | 36 | */ |
mbed_official | 330:c80ac197fa6a | 37 | |
mbed_official | 330:c80ac197fa6a | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
mbed_official | 330:c80ac197fa6a | 39 | #ifndef __STM32F3xx_HAL_RCC_H |
mbed_official | 330:c80ac197fa6a | 40 | #define __STM32F3xx_HAL_RCC_H |
mbed_official | 330:c80ac197fa6a | 41 | |
mbed_official | 330:c80ac197fa6a | 42 | #ifdef __cplusplus |
mbed_official | 330:c80ac197fa6a | 43 | extern "C" { |
mbed_official | 330:c80ac197fa6a | 44 | #endif |
mbed_official | 330:c80ac197fa6a | 45 | |
mbed_official | 330:c80ac197fa6a | 46 | /* Includes ------------------------------------------------------------------*/ |
mbed_official | 330:c80ac197fa6a | 47 | #include "stm32f3xx_hal_def.h" |
mbed_official | 330:c80ac197fa6a | 48 | |
mbed_official | 330:c80ac197fa6a | 49 | /** @addtogroup STM32F3xx_HAL_Driver |
mbed_official | 330:c80ac197fa6a | 50 | * @{ |
mbed_official | 330:c80ac197fa6a | 51 | */ |
mbed_official | 330:c80ac197fa6a | 52 | |
mbed_official | 330:c80ac197fa6a | 53 | /** @addtogroup RCC |
mbed_official | 330:c80ac197fa6a | 54 | * @{ |
mbed_official | 330:c80ac197fa6a | 55 | */ |
mbed_official | 330:c80ac197fa6a | 56 | |
mbed_official | 330:c80ac197fa6a | 57 | /* Exported types ------------------------------------------------------------*/ |
mbed_official | 330:c80ac197fa6a | 58 | |
mbed_official | 330:c80ac197fa6a | 59 | /** @defgroup RCC_Exported_Types RCC Exported Types |
mbed_official | 330:c80ac197fa6a | 60 | * @{ |
mbed_official | 330:c80ac197fa6a | 61 | */ |
mbed_official | 330:c80ac197fa6a | 62 | |
mbed_official | 330:c80ac197fa6a | 63 | /** |
mbed_official | 330:c80ac197fa6a | 64 | * @brief RCC System, AHB and APB busses clock configuration structure definition |
mbed_official | 330:c80ac197fa6a | 65 | */ |
mbed_official | 330:c80ac197fa6a | 66 | typedef struct |
mbed_official | 330:c80ac197fa6a | 67 | { |
mbed_official | 330:c80ac197fa6a | 68 | uint32_t ClockType; /*!< The clock to be configured. |
mbed_official | 330:c80ac197fa6a | 69 | This parameter can be a value of @ref RCC_System_Clock_Type */ |
mbed_official | 330:c80ac197fa6a | 70 | |
mbed_official | 330:c80ac197fa6a | 71 | uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. |
mbed_official | 330:c80ac197fa6a | 72 | This parameter can be a value of @ref RCC_System_Clock_Source */ |
mbed_official | 330:c80ac197fa6a | 73 | |
mbed_official | 330:c80ac197fa6a | 74 | uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). |
mbed_official | 330:c80ac197fa6a | 75 | This parameter can be a value of @ref RCC_AHB_Clock_Source */ |
mbed_official | 330:c80ac197fa6a | 76 | |
mbed_official | 330:c80ac197fa6a | 77 | uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). |
mbed_official | 330:c80ac197fa6a | 78 | This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ |
mbed_official | 330:c80ac197fa6a | 79 | |
mbed_official | 330:c80ac197fa6a | 80 | uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). |
mbed_official | 330:c80ac197fa6a | 81 | This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ |
mbed_official | 330:c80ac197fa6a | 82 | |
mbed_official | 330:c80ac197fa6a | 83 | }RCC_ClkInitTypeDef; |
mbed_official | 330:c80ac197fa6a | 84 | |
mbed_official | 330:c80ac197fa6a | 85 | /** |
mbed_official | 330:c80ac197fa6a | 86 | * @} |
mbed_official | 330:c80ac197fa6a | 87 | */ |
mbed_official | 330:c80ac197fa6a | 88 | |
mbed_official | 330:c80ac197fa6a | 89 | /* Exported constants --------------------------------------------------------*/ |
mbed_official | 330:c80ac197fa6a | 90 | /** @defgroup RCC_Exported_Constants RCC Exported Constants |
mbed_official | 330:c80ac197fa6a | 91 | * @{ |
mbed_official | 330:c80ac197fa6a | 92 | */ |
mbed_official | 330:c80ac197fa6a | 93 | |
mbed_official | 330:c80ac197fa6a | 94 | /** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion |
mbed_official | 330:c80ac197fa6a | 95 | * @brief RCC registers bit address in the alias region |
mbed_official | 330:c80ac197fa6a | 96 | * @{ |
mbed_official | 330:c80ac197fa6a | 97 | */ |
mbed_official | 330:c80ac197fa6a | 98 | #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) |
mbed_official | 330:c80ac197fa6a | 99 | /* --- CR Register ---*/ |
mbed_official | 330:c80ac197fa6a | 100 | #define RCC_CR_OFFSET (RCC_OFFSET + 0x00) |
mbed_official | 330:c80ac197fa6a | 101 | /* Alias word address of HSION bit */ |
mbed_official | 330:c80ac197fa6a | 102 | #define HSION_BitNumber 0 |
mbed_official | 330:c80ac197fa6a | 103 | #define CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (HSION_BitNumber * 4)) |
mbed_official | 330:c80ac197fa6a | 104 | /* Alias word address of HSEON bit */ |
mbed_official | 330:c80ac197fa6a | 105 | #define HSEON_BitNumber 16 |
mbed_official | 330:c80ac197fa6a | 106 | #define CR_HSEON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (HSEON_BitNumber * 4)) |
mbed_official | 330:c80ac197fa6a | 107 | /* Alias word address of CSSON bit */ |
mbed_official | 330:c80ac197fa6a | 108 | #define CSSON_BitNumber 19 |
mbed_official | 330:c80ac197fa6a | 109 | #define CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (CSSON_BitNumber * 4)) |
mbed_official | 330:c80ac197fa6a | 110 | /* Alias word address of PLLON bit */ |
mbed_official | 330:c80ac197fa6a | 111 | #define PLLON_BitNumber 24 |
mbed_official | 330:c80ac197fa6a | 112 | #define CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLON_BitNumber * 4)) |
mbed_official | 330:c80ac197fa6a | 113 | |
mbed_official | 330:c80ac197fa6a | 114 | /* --- CFGR Register ---*/ |
mbed_official | 330:c80ac197fa6a | 115 | #define RCC_CFGR_OFFSET (RCC_OFFSET + 0x04) |
mbed_official | 330:c80ac197fa6a | 116 | /* Alias word address of PLLSRC bit */ |
mbed_official | 330:c80ac197fa6a | 117 | #define PLLSRC_BitNumber 16 |
mbed_official | 330:c80ac197fa6a | 118 | #define CFGR_PLLSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (PLLSRC_BitNumber * 4)) |
mbed_official | 330:c80ac197fa6a | 119 | |
mbed_official | 330:c80ac197fa6a | 120 | /* --- CIR Register ---*/ |
mbed_official | 330:c80ac197fa6a | 121 | #define RCC_CIR_OFFSET (RCC_OFFSET + 0x08) |
mbed_official | 330:c80ac197fa6a | 122 | |
mbed_official | 330:c80ac197fa6a | 123 | /* --- BDCR Register ---*/ |
mbed_official | 330:c80ac197fa6a | 124 | #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x20) |
mbed_official | 330:c80ac197fa6a | 125 | /* Alias word address of LSEON bit */ |
mbed_official | 330:c80ac197fa6a | 126 | #define LSEON_BitNumber 0 |
mbed_official | 330:c80ac197fa6a | 127 | #define BDCR_LSEON_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (LSEON_BitNumber * 4)) |
mbed_official | 330:c80ac197fa6a | 128 | /* Alias word address of RTCEN bit */ |
mbed_official | 330:c80ac197fa6a | 129 | #define RTCEN_BitNumber 15 |
mbed_official | 330:c80ac197fa6a | 130 | #define BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) |
mbed_official | 330:c80ac197fa6a | 131 | /* Alias word address of BDRST bit */ |
mbed_official | 330:c80ac197fa6a | 132 | #define BDRST_BitNumber 16 |
mbed_official | 330:c80ac197fa6a | 133 | #define BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) |
mbed_official | 330:c80ac197fa6a | 134 | |
mbed_official | 330:c80ac197fa6a | 135 | /* --- CSR Register ---*/ |
mbed_official | 330:c80ac197fa6a | 136 | #define RCC_CSR_OFFSET (RCC_OFFSET + 0x24) |
mbed_official | 330:c80ac197fa6a | 137 | /* Alias word address of LSION bit */ |
mbed_official | 330:c80ac197fa6a | 138 | #define LSION_BitNumber 0 |
mbed_official | 330:c80ac197fa6a | 139 | #define CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (LSION_BitNumber * 4)) |
mbed_official | 330:c80ac197fa6a | 140 | /* Alias word address of RMVF bit */ |
mbed_official | 330:c80ac197fa6a | 141 | #define RMVF_BitNumber 24 |
mbed_official | 330:c80ac197fa6a | 142 | #define CSR_RMVF_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (RMVF_BitNumber * 4)) |
mbed_official | 330:c80ac197fa6a | 143 | |
mbed_official | 330:c80ac197fa6a | 144 | /* CR register byte 2 (Bits[23:16]) base address */ |
mbed_official | 330:c80ac197fa6a | 145 | #define CR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CR_OFFSET + 0x02) |
mbed_official | 330:c80ac197fa6a | 146 | |
mbed_official | 330:c80ac197fa6a | 147 | /* CIR register byte 1 (Bits[15:8]) base address */ |
mbed_official | 330:c80ac197fa6a | 148 | #define CIR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x01) |
mbed_official | 330:c80ac197fa6a | 149 | |
mbed_official | 330:c80ac197fa6a | 150 | /* CIR register byte 2 (Bits[23:16]) base address */ |
mbed_official | 330:c80ac197fa6a | 151 | #define CIR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x02) |
mbed_official | 330:c80ac197fa6a | 152 | |
mbed_official | 330:c80ac197fa6a | 153 | /* CSR register byte 1 (Bits[15:8]) base address */ |
mbed_official | 330:c80ac197fa6a | 154 | #define CSR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CSR_OFFSET + 0x01) |
mbed_official | 330:c80ac197fa6a | 155 | |
mbed_official | 330:c80ac197fa6a | 156 | /* BDCR register byte 0 (Bits[7:0] base address */ |
mbed_official | 330:c80ac197fa6a | 157 | #define BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET) |
mbed_official | 330:c80ac197fa6a | 158 | |
mbed_official | 330:c80ac197fa6a | 159 | /** |
mbed_official | 330:c80ac197fa6a | 160 | * @} |
mbed_official | 330:c80ac197fa6a | 161 | */ |
mbed_official | 330:c80ac197fa6a | 162 | |
mbed_official | 330:c80ac197fa6a | 163 | /** @defgroup RCC_Timeout RCC Timeout |
mbed_official | 330:c80ac197fa6a | 164 | * @{ |
mbed_official | 330:c80ac197fa6a | 165 | */ |
mbed_official | 330:c80ac197fa6a | 166 | /* LSE state change timeout */ |
mbed_official | 330:c80ac197fa6a | 167 | #define LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ |
mbed_official | 330:c80ac197fa6a | 168 | |
mbed_official | 330:c80ac197fa6a | 169 | /* Disable Backup domain write protection state change timeout */ |
mbed_official | 330:c80ac197fa6a | 170 | #define DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ |
mbed_official | 330:c80ac197fa6a | 171 | /** |
mbed_official | 330:c80ac197fa6a | 172 | * @} |
mbed_official | 330:c80ac197fa6a | 173 | */ |
mbed_official | 330:c80ac197fa6a | 174 | |
mbed_official | 330:c80ac197fa6a | 175 | /** @defgroup RCC_Oscillator_Type RCC Oscillator Type |
mbed_official | 330:c80ac197fa6a | 176 | * @{ |
mbed_official | 330:c80ac197fa6a | 177 | */ |
mbed_official | 330:c80ac197fa6a | 178 | #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000) |
mbed_official | 330:c80ac197fa6a | 179 | #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001) |
mbed_official | 330:c80ac197fa6a | 180 | #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002) |
mbed_official | 330:c80ac197fa6a | 181 | #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004) |
mbed_official | 330:c80ac197fa6a | 182 | #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008) |
mbed_official | 330:c80ac197fa6a | 183 | |
mbed_official | 330:c80ac197fa6a | 184 | #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \ |
mbed_official | 330:c80ac197fa6a | 185 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ |
mbed_official | 330:c80ac197fa6a | 186 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ |
mbed_official | 330:c80ac197fa6a | 187 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ |
mbed_official | 330:c80ac197fa6a | 188 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) |
mbed_official | 330:c80ac197fa6a | 189 | /** |
mbed_official | 330:c80ac197fa6a | 190 | * @} |
mbed_official | 330:c80ac197fa6a | 191 | */ |
mbed_official | 330:c80ac197fa6a | 192 | |
mbed_official | 330:c80ac197fa6a | 193 | /** @defgroup RCC_HSE_Config RCC HSE Config |
mbed_official | 330:c80ac197fa6a | 194 | * @{ |
mbed_official | 330:c80ac197fa6a | 195 | */ |
mbed_official | 330:c80ac197fa6a | 196 | #define RCC_HSE_OFF ((uint32_t)0x00000000) |
mbed_official | 330:c80ac197fa6a | 197 | #define RCC_HSE_ON ((uint32_t)0x00000001) |
mbed_official | 330:c80ac197fa6a | 198 | #define RCC_HSE_BYPASS ((uint32_t)0x00000005) |
mbed_official | 330:c80ac197fa6a | 199 | |
mbed_official | 330:c80ac197fa6a | 200 | #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ |
mbed_official | 330:c80ac197fa6a | 201 | ((HSE) == RCC_HSE_BYPASS)) |
mbed_official | 330:c80ac197fa6a | 202 | /** |
mbed_official | 330:c80ac197fa6a | 203 | * @} |
mbed_official | 330:c80ac197fa6a | 204 | */ |
mbed_official | 330:c80ac197fa6a | 205 | |
mbed_official | 330:c80ac197fa6a | 206 | /** @defgroup RCC_LSE_Config RCC_LSE_Config |
mbed_official | 330:c80ac197fa6a | 207 | * @{ |
mbed_official | 330:c80ac197fa6a | 208 | */ |
mbed_official | 330:c80ac197fa6a | 209 | #define RCC_LSE_OFF ((uint32_t)0x00000000) |
mbed_official | 330:c80ac197fa6a | 210 | #define RCC_LSE_ON ((uint32_t)0x00000001) |
mbed_official | 330:c80ac197fa6a | 211 | #define RCC_LSE_BYPASS ((uint32_t)0x00000005) |
mbed_official | 330:c80ac197fa6a | 212 | |
mbed_official | 330:c80ac197fa6a | 213 | #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ |
mbed_official | 330:c80ac197fa6a | 214 | ((LSE) == RCC_LSE_BYPASS)) |
mbed_official | 330:c80ac197fa6a | 215 | /** |
mbed_official | 330:c80ac197fa6a | 216 | * @} |
mbed_official | 330:c80ac197fa6a | 217 | */ |
mbed_official | 330:c80ac197fa6a | 218 | |
mbed_official | 330:c80ac197fa6a | 219 | /** @defgroup RCC_HSI_Config RCC HSI Config |
mbed_official | 330:c80ac197fa6a | 220 | * @{ |
mbed_official | 330:c80ac197fa6a | 221 | */ |
mbed_official | 330:c80ac197fa6a | 222 | #define RCC_HSI_OFF ((uint32_t)0x00000000) |
mbed_official | 330:c80ac197fa6a | 223 | #define RCC_HSI_ON ((uint32_t)0x00000001) |
mbed_official | 330:c80ac197fa6a | 224 | |
mbed_official | 330:c80ac197fa6a | 225 | #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON)) |
mbed_official | 330:c80ac197fa6a | 226 | |
mbed_official | 330:c80ac197fa6a | 227 | #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */ |
mbed_official | 330:c80ac197fa6a | 228 | |
mbed_official | 330:c80ac197fa6a | 229 | #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F) |
mbed_official | 330:c80ac197fa6a | 230 | /** |
mbed_official | 330:c80ac197fa6a | 231 | * @} |
mbed_official | 330:c80ac197fa6a | 232 | */ |
mbed_official | 330:c80ac197fa6a | 233 | |
mbed_official | 330:c80ac197fa6a | 234 | /** @defgroup RCC_LSI_Config RCC LSI Config |
mbed_official | 330:c80ac197fa6a | 235 | * @{ |
mbed_official | 330:c80ac197fa6a | 236 | */ |
mbed_official | 330:c80ac197fa6a | 237 | #define RCC_LSI_OFF ((uint32_t)0x00000000) |
mbed_official | 330:c80ac197fa6a | 238 | #define RCC_LSI_ON ((uint32_t)0x00000001) |
mbed_official | 330:c80ac197fa6a | 239 | |
mbed_official | 330:c80ac197fa6a | 240 | #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON)) |
mbed_official | 330:c80ac197fa6a | 241 | /** |
mbed_official | 330:c80ac197fa6a | 242 | * @} |
mbed_official | 330:c80ac197fa6a | 243 | */ |
mbed_official | 330:c80ac197fa6a | 244 | |
mbed_official | 330:c80ac197fa6a | 245 | /** @defgroup RCC_PLL_Config RCC PLL Config |
mbed_official | 330:c80ac197fa6a | 246 | * @{ |
mbed_official | 330:c80ac197fa6a | 247 | */ |
mbed_official | 330:c80ac197fa6a | 248 | #define RCC_PLL_NONE ((uint32_t)0x00000000) |
mbed_official | 330:c80ac197fa6a | 249 | #define RCC_PLL_OFF ((uint32_t)0x00000001) |
mbed_official | 330:c80ac197fa6a | 250 | #define RCC_PLL_ON ((uint32_t)0x00000002) |
mbed_official | 330:c80ac197fa6a | 251 | |
mbed_official | 330:c80ac197fa6a | 252 | #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON)) |
mbed_official | 330:c80ac197fa6a | 253 | /** |
mbed_official | 330:c80ac197fa6a | 254 | * @} |
mbed_official | 330:c80ac197fa6a | 255 | */ |
mbed_official | 330:c80ac197fa6a | 256 | |
mbed_official | 330:c80ac197fa6a | 257 | /** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor |
mbed_official | 330:c80ac197fa6a | 258 | * @{ |
mbed_official | 330:c80ac197fa6a | 259 | */ |
mbed_official | 330:c80ac197fa6a | 260 | #define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2 |
mbed_official | 330:c80ac197fa6a | 261 | #define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3 |
mbed_official | 330:c80ac197fa6a | 262 | #define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4 |
mbed_official | 330:c80ac197fa6a | 263 | #define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5 |
mbed_official | 330:c80ac197fa6a | 264 | #define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6 |
mbed_official | 330:c80ac197fa6a | 265 | #define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7 |
mbed_official | 330:c80ac197fa6a | 266 | #define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8 |
mbed_official | 330:c80ac197fa6a | 267 | #define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9 |
mbed_official | 330:c80ac197fa6a | 268 | #define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10 |
mbed_official | 330:c80ac197fa6a | 269 | #define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11 |
mbed_official | 330:c80ac197fa6a | 270 | #define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12 |
mbed_official | 330:c80ac197fa6a | 271 | #define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13 |
mbed_official | 330:c80ac197fa6a | 272 | #define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14 |
mbed_official | 330:c80ac197fa6a | 273 | #define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15 |
mbed_official | 330:c80ac197fa6a | 274 | #define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16 |
mbed_official | 330:c80ac197fa6a | 275 | |
mbed_official | 330:c80ac197fa6a | 276 | #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLL_MUL2) || ((MUL) == RCC_PLL_MUL3) || \ |
mbed_official | 330:c80ac197fa6a | 277 | ((MUL) == RCC_PLL_MUL4) || ((MUL) == RCC_PLL_MUL5) || \ |
mbed_official | 330:c80ac197fa6a | 278 | ((MUL) == RCC_PLL_MUL6) || ((MUL) == RCC_PLL_MUL7) || \ |
mbed_official | 330:c80ac197fa6a | 279 | ((MUL) == RCC_PLL_MUL8) || ((MUL) == RCC_PLL_MUL9) || \ |
mbed_official | 330:c80ac197fa6a | 280 | ((MUL) == RCC_PLL_MUL10) || ((MUL) == RCC_PLL_MUL11) || \ |
mbed_official | 330:c80ac197fa6a | 281 | ((MUL) == RCC_PLL_MUL12) || ((MUL) == RCC_PLL_MUL13) || \ |
mbed_official | 330:c80ac197fa6a | 282 | ((MUL) == RCC_PLL_MUL14) || ((MUL) == RCC_PLL_MUL15) || \ |
mbed_official | 330:c80ac197fa6a | 283 | ((MUL) == RCC_PLL_MUL16)) |
mbed_official | 330:c80ac197fa6a | 284 | /** |
mbed_official | 330:c80ac197fa6a | 285 | * @} |
mbed_official | 330:c80ac197fa6a | 286 | */ |
mbed_official | 330:c80ac197fa6a | 287 | |
mbed_official | 330:c80ac197fa6a | 288 | /** @defgroup RCC_System_Clock_Type RCC System Clock Type |
mbed_official | 330:c80ac197fa6a | 289 | * @{ |
mbed_official | 330:c80ac197fa6a | 290 | */ |
mbed_official | 330:c80ac197fa6a | 291 | #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) |
mbed_official | 330:c80ac197fa6a | 292 | #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) |
mbed_official | 330:c80ac197fa6a | 293 | #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) |
mbed_official | 330:c80ac197fa6a | 294 | #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) |
mbed_official | 330:c80ac197fa6a | 295 | |
mbed_official | 330:c80ac197fa6a | 296 | #define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \ |
mbed_official | 330:c80ac197fa6a | 297 | (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \ |
mbed_official | 330:c80ac197fa6a | 298 | (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \ |
mbed_official | 330:c80ac197fa6a | 299 | (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)) |
mbed_official | 330:c80ac197fa6a | 300 | /** |
mbed_official | 330:c80ac197fa6a | 301 | * @} |
mbed_official | 330:c80ac197fa6a | 302 | */ |
mbed_official | 330:c80ac197fa6a | 303 | |
mbed_official | 330:c80ac197fa6a | 304 | /** @defgroup RCC_System_Clock_Source RCC System Clock Source |
mbed_official | 330:c80ac197fa6a | 305 | * @{ |
mbed_official | 330:c80ac197fa6a | 306 | */ |
mbed_official | 330:c80ac197fa6a | 307 | #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI |
mbed_official | 330:c80ac197fa6a | 308 | #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE |
mbed_official | 330:c80ac197fa6a | 309 | #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL |
mbed_official | 330:c80ac197fa6a | 310 | |
mbed_official | 330:c80ac197fa6a | 311 | #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ |
mbed_official | 330:c80ac197fa6a | 312 | ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ |
mbed_official | 330:c80ac197fa6a | 313 | ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK)) |
mbed_official | 330:c80ac197fa6a | 314 | /** |
mbed_official | 330:c80ac197fa6a | 315 | * @} |
mbed_official | 330:c80ac197fa6a | 316 | */ |
mbed_official | 330:c80ac197fa6a | 317 | |
mbed_official | 330:c80ac197fa6a | 318 | /** @defgroup RCC_System_Clock_Source_Status RCC System Clock Source Status |
mbed_official | 330:c80ac197fa6a | 319 | * @{ |
mbed_official | 330:c80ac197fa6a | 320 | */ |
mbed_official | 330:c80ac197fa6a | 321 | #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI |
mbed_official | 330:c80ac197fa6a | 322 | #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE |
mbed_official | 330:c80ac197fa6a | 323 | #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL |
mbed_official | 330:c80ac197fa6a | 324 | |
mbed_official | 330:c80ac197fa6a | 325 | #define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ |
mbed_official | 330:c80ac197fa6a | 326 | ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ |
mbed_official | 330:c80ac197fa6a | 327 | ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))) |
mbed_official | 330:c80ac197fa6a | 328 | /** |
mbed_official | 330:c80ac197fa6a | 329 | * @} |
mbed_official | 330:c80ac197fa6a | 330 | */ |
mbed_official | 330:c80ac197fa6a | 331 | |
mbed_official | 330:c80ac197fa6a | 332 | /** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source |
mbed_official | 330:c80ac197fa6a | 333 | * @{ |
mbed_official | 330:c80ac197fa6a | 334 | */ |
mbed_official | 330:c80ac197fa6a | 335 | #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 |
mbed_official | 330:c80ac197fa6a | 336 | #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 |
mbed_official | 330:c80ac197fa6a | 337 | #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 |
mbed_official | 330:c80ac197fa6a | 338 | #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 |
mbed_official | 330:c80ac197fa6a | 339 | #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 |
mbed_official | 330:c80ac197fa6a | 340 | #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 |
mbed_official | 330:c80ac197fa6a | 341 | #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 |
mbed_official | 330:c80ac197fa6a | 342 | #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 |
mbed_official | 330:c80ac197fa6a | 343 | #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 |
mbed_official | 330:c80ac197fa6a | 344 | |
mbed_official | 330:c80ac197fa6a | 345 | #define IS_RCC_SYSCLK_DIV(DIV) (((DIV) == RCC_SYSCLK_DIV1) || ((DIV) == RCC_SYSCLK_DIV2) || \ |
mbed_official | 330:c80ac197fa6a | 346 | ((DIV) == RCC_SYSCLK_DIV4) || ((DIV) == RCC_SYSCLK_DIV8) || \ |
mbed_official | 330:c80ac197fa6a | 347 | ((DIV) == RCC_SYSCLK_DIV16) || ((DIV) == RCC_SYSCLK_DIV64) || \ |
mbed_official | 330:c80ac197fa6a | 348 | ((DIV) == RCC_SYSCLK_DIV128) || ((DIV) == RCC_SYSCLK_DIV256) || \ |
mbed_official | 330:c80ac197fa6a | 349 | ((DIV) == RCC_SYSCLK_DIV512)) |
mbed_official | 330:c80ac197fa6a | 350 | /** |
mbed_official | 330:c80ac197fa6a | 351 | * @} |
mbed_official | 330:c80ac197fa6a | 352 | */ |
mbed_official | 330:c80ac197fa6a | 353 | |
mbed_official | 330:c80ac197fa6a | 354 | /** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1 APB2 Clock Source |
mbed_official | 330:c80ac197fa6a | 355 | * @{ |
mbed_official | 330:c80ac197fa6a | 356 | */ |
mbed_official | 330:c80ac197fa6a | 357 | #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 |
mbed_official | 330:c80ac197fa6a | 358 | #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 |
mbed_official | 330:c80ac197fa6a | 359 | #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 |
mbed_official | 330:c80ac197fa6a | 360 | #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 |
mbed_official | 330:c80ac197fa6a | 361 | #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 |
mbed_official | 330:c80ac197fa6a | 362 | |
mbed_official | 330:c80ac197fa6a | 363 | #define IS_RCC_HCLK_DIV(DIV) (((DIV) == RCC_HCLK_DIV1) || ((DIV) == RCC_HCLK_DIV2) || \ |
mbed_official | 330:c80ac197fa6a | 364 | ((DIV) == RCC_HCLK_DIV4) || ((DIV) == RCC_HCLK_DIV8) || \ |
mbed_official | 330:c80ac197fa6a | 365 | ((DIV) == RCC_HCLK_DIV16)) |
mbed_official | 330:c80ac197fa6a | 366 | /** |
mbed_official | 330:c80ac197fa6a | 367 | * @} |
mbed_official | 330:c80ac197fa6a | 368 | */ |
mbed_official | 330:c80ac197fa6a | 369 | |
mbed_official | 330:c80ac197fa6a | 370 | /** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source |
mbed_official | 330:c80ac197fa6a | 371 | * @{ |
mbed_official | 330:c80ac197fa6a | 372 | */ |
mbed_official | 330:c80ac197fa6a | 373 | #define RCC_RTCCLKSOURCE_NONE RCC_BDCR_RTCSEL_NOCLOCK |
mbed_official | 330:c80ac197fa6a | 374 | #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE |
mbed_official | 330:c80ac197fa6a | 375 | #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI |
mbed_official | 330:c80ac197fa6a | 376 | #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE |
mbed_official | 330:c80ac197fa6a | 377 | |
mbed_official | 330:c80ac197fa6a | 378 | #define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_NONE) || \ |
mbed_official | 330:c80ac197fa6a | 379 | ((SOURCE) == RCC_RTCCLKSOURCE_LSE) || \ |
mbed_official | 330:c80ac197fa6a | 380 | ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \ |
mbed_official | 330:c80ac197fa6a | 381 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32)) |
mbed_official | 330:c80ac197fa6a | 382 | /** |
mbed_official | 330:c80ac197fa6a | 383 | * @} |
mbed_official | 330:c80ac197fa6a | 384 | */ |
mbed_official | 330:c80ac197fa6a | 385 | |
mbed_official | 330:c80ac197fa6a | 386 | /** @defgroup RCC_USART2_Clock_Source RCC USART2 Clock Source |
mbed_official | 330:c80ac197fa6a | 387 | * @{ |
mbed_official | 330:c80ac197fa6a | 388 | */ |
mbed_official | 330:c80ac197fa6a | 389 | #define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK |
mbed_official | 330:c80ac197fa6a | 390 | #define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK |
mbed_official | 330:c80ac197fa6a | 391 | #define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE |
mbed_official | 330:c80ac197fa6a | 392 | #define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI |
mbed_official | 330:c80ac197fa6a | 393 | |
mbed_official | 330:c80ac197fa6a | 394 | #define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \ |
mbed_official | 330:c80ac197fa6a | 395 | ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \ |
mbed_official | 330:c80ac197fa6a | 396 | ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \ |
mbed_official | 330:c80ac197fa6a | 397 | ((SOURCE) == RCC_USART2CLKSOURCE_HSI)) |
mbed_official | 330:c80ac197fa6a | 398 | /** |
mbed_official | 330:c80ac197fa6a | 399 | * @} |
mbed_official | 330:c80ac197fa6a | 400 | */ |
mbed_official | 330:c80ac197fa6a | 401 | |
mbed_official | 330:c80ac197fa6a | 402 | /** @defgroup RCC_USART3_Clock_Source RCC USART3 Clock Source |
mbed_official | 330:c80ac197fa6a | 403 | * @{ |
mbed_official | 330:c80ac197fa6a | 404 | */ |
mbed_official | 330:c80ac197fa6a | 405 | #define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK |
mbed_official | 330:c80ac197fa6a | 406 | #define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK |
mbed_official | 330:c80ac197fa6a | 407 | #define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE |
mbed_official | 330:c80ac197fa6a | 408 | #define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI |
mbed_official | 330:c80ac197fa6a | 409 | |
mbed_official | 330:c80ac197fa6a | 410 | #define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \ |
mbed_official | 330:c80ac197fa6a | 411 | ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \ |
mbed_official | 330:c80ac197fa6a | 412 | ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \ |
mbed_official | 330:c80ac197fa6a | 413 | ((SOURCE) == RCC_USART3CLKSOURCE_HSI)) |
mbed_official | 330:c80ac197fa6a | 414 | /** |
mbed_official | 330:c80ac197fa6a | 415 | * @} |
mbed_official | 330:c80ac197fa6a | 416 | */ |
mbed_official | 330:c80ac197fa6a | 417 | |
mbed_official | 330:c80ac197fa6a | 418 | /** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source |
mbed_official | 330:c80ac197fa6a | 419 | * @{ |
mbed_official | 330:c80ac197fa6a | 420 | */ |
mbed_official | 330:c80ac197fa6a | 421 | #define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI |
mbed_official | 330:c80ac197fa6a | 422 | #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK |
mbed_official | 330:c80ac197fa6a | 423 | |
mbed_official | 330:c80ac197fa6a | 424 | #define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_HSI) || \ |
mbed_official | 330:c80ac197fa6a | 425 | ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)) |
mbed_official | 330:c80ac197fa6a | 426 | /** |
mbed_official | 330:c80ac197fa6a | 427 | * @} |
mbed_official | 330:c80ac197fa6a | 428 | */ |
mbed_official | 330:c80ac197fa6a | 429 | |
mbed_official | 330:c80ac197fa6a | 430 | /** @defgroup RCC_MCOx_Index RCC MCOx Index |
mbed_official | 330:c80ac197fa6a | 431 | * @{ |
mbed_official | 330:c80ac197fa6a | 432 | */ |
mbed_official | 330:c80ac197fa6a | 433 | #define RCC_MCO ((uint32_t)0x00000000) |
mbed_official | 330:c80ac197fa6a | 434 | |
mbed_official | 330:c80ac197fa6a | 435 | #define IS_RCC_MCO(MCOx) ((MCOx) == RCC_MCO) |
mbed_official | 330:c80ac197fa6a | 436 | /** |
mbed_official | 330:c80ac197fa6a | 437 | * @} |
mbed_official | 330:c80ac197fa6a | 438 | */ |
mbed_official | 330:c80ac197fa6a | 439 | |
mbed_official | 330:c80ac197fa6a | 440 | /** @defgroup RCC_Interrupt RCC Interrupt |
mbed_official | 330:c80ac197fa6a | 441 | * @{ |
mbed_official | 330:c80ac197fa6a | 442 | */ |
mbed_official | 330:c80ac197fa6a | 443 | #define RCC_IT_LSIRDY ((uint32_t)0x00000001) |
mbed_official | 330:c80ac197fa6a | 444 | #define RCC_IT_LSERDY ((uint32_t)0x00000002) |
mbed_official | 330:c80ac197fa6a | 445 | #define RCC_IT_HSIRDY ((uint32_t)0x00000004) |
mbed_official | 330:c80ac197fa6a | 446 | #define RCC_IT_HSERDY ((uint32_t)0x00000008) |
mbed_official | 330:c80ac197fa6a | 447 | #define RCC_IT_PLLRDY ((uint32_t)0x00000010) |
mbed_official | 330:c80ac197fa6a | 448 | #define RCC_IT_CSS ((uint32_t)0x00000080) |
mbed_official | 330:c80ac197fa6a | 449 | /** |
mbed_official | 330:c80ac197fa6a | 450 | * @} |
mbed_official | 330:c80ac197fa6a | 451 | */ |
mbed_official | 330:c80ac197fa6a | 452 | |
mbed_official | 330:c80ac197fa6a | 453 | /** @defgroup RCC_Flag RCC Flag |
mbed_official | 330:c80ac197fa6a | 454 | * Elements values convention: 0XXYYYYYb |
mbed_official | 330:c80ac197fa6a | 455 | * - YYYYY : Flag position in the register |
mbed_official | 330:c80ac197fa6a | 456 | * - XX : Register index |
mbed_official | 330:c80ac197fa6a | 457 | * - 01: CR register |
mbed_official | 330:c80ac197fa6a | 458 | * - 10: BDCR register |
mbed_official | 330:c80ac197fa6a | 459 | * - 11: CSR register |
mbed_official | 330:c80ac197fa6a | 460 | * @{ |
mbed_official | 330:c80ac197fa6a | 461 | */ |
mbed_official | 330:c80ac197fa6a | 462 | #define CR_REG_INDEX 1U |
mbed_official | 330:c80ac197fa6a | 463 | #define BDCR_REG_INDEX 2U |
mbed_official | 330:c80ac197fa6a | 464 | #define CSR_REG_INDEX 3U |
mbed_official | 330:c80ac197fa6a | 465 | |
mbed_official | 330:c80ac197fa6a | 466 | /* Flags in the CR register */ |
mbed_official | 330:c80ac197fa6a | 467 | #define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CR_HSIRDY)))) |
mbed_official | 330:c80ac197fa6a | 468 | #define RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CR_HSERDY)))) |
mbed_official | 330:c80ac197fa6a | 469 | #define RCC_FLAG_PLLRDY ((uint32_t)((CR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CR_PLLRDY)))) |
mbed_official | 330:c80ac197fa6a | 470 | |
mbed_official | 330:c80ac197fa6a | 471 | /* Flags in the BDCR register */ |
mbed_official | 330:c80ac197fa6a | 472 | #define RCC_FLAG_LSERDY ((uint32_t)((BDCR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_BDCR_LSERDY)))) |
mbed_official | 330:c80ac197fa6a | 473 | |
mbed_official | 330:c80ac197fa6a | 474 | /* Flags in the CSR register */ |
mbed_official | 330:c80ac197fa6a | 475 | #define RCC_FLAG_LSIRDY ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_LSIRDY)))) |
mbed_official | 330:c80ac197fa6a | 476 | #define RCC_FLAG_RMV ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_RMVF)))) |
mbed_official | 330:c80ac197fa6a | 477 | #define RCC_FLAG_OBLRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_OBLRSTF)))) |
mbed_official | 330:c80ac197fa6a | 478 | #define RCC_FLAG_PINRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_PINRSTF)))) |
mbed_official | 330:c80ac197fa6a | 479 | #define RCC_FLAG_PORRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_PORRSTF)))) |
mbed_official | 330:c80ac197fa6a | 480 | #define RCC_FLAG_SFTRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_SFTRSTF)))) |
mbed_official | 330:c80ac197fa6a | 481 | #define RCC_FLAG_IWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_IWDGRSTF)))) |
mbed_official | 330:c80ac197fa6a | 482 | #define RCC_FLAG_WWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_WWDGRSTF)))) |
mbed_official | 330:c80ac197fa6a | 483 | #define RCC_FLAG_LPWRRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_LPWRRSTF)))) |
mbed_official | 330:c80ac197fa6a | 484 | /** |
mbed_official | 330:c80ac197fa6a | 485 | * @} |
mbed_official | 330:c80ac197fa6a | 486 | */ |
mbed_official | 330:c80ac197fa6a | 487 | |
mbed_official | 330:c80ac197fa6a | 488 | /** |
mbed_official | 330:c80ac197fa6a | 489 | * @} |
mbed_official | 330:c80ac197fa6a | 490 | */ |
mbed_official | 330:c80ac197fa6a | 491 | /* Exported macro ------------------------------------------------------------*/ |
mbed_official | 330:c80ac197fa6a | 492 | |
mbed_official | 330:c80ac197fa6a | 493 | /** @defgroup RCC_Exported_Macros RCC Exported Macros |
mbed_official | 330:c80ac197fa6a | 494 | * @{ |
mbed_official | 330:c80ac197fa6a | 495 | */ |
mbed_official | 330:c80ac197fa6a | 496 | |
mbed_official | 330:c80ac197fa6a | 497 | /** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable |
mbed_official | 330:c80ac197fa6a | 498 | * @brief Enable or disable the AHB peripheral clock. |
mbed_official | 330:c80ac197fa6a | 499 | * @note After reset, the peripheral clock (used for registers read/write access) |
mbed_official | 330:c80ac197fa6a | 500 | * is disabled and the application software has to enable this clock before |
mbed_official | 330:c80ac197fa6a | 501 | * using it. |
mbed_official | 330:c80ac197fa6a | 502 | * @{ |
mbed_official | 330:c80ac197fa6a | 503 | */ |
mbed_official | 330:c80ac197fa6a | 504 | #define __GPIOA_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOAEN)) |
mbed_official | 330:c80ac197fa6a | 505 | #define __GPIOB_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOBEN)) |
mbed_official | 330:c80ac197fa6a | 506 | #define __GPIOC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOCEN)) |
mbed_official | 330:c80ac197fa6a | 507 | #define __GPIOD_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIODEN)) |
mbed_official | 330:c80ac197fa6a | 508 | #define __GPIOF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOFEN)) |
mbed_official | 330:c80ac197fa6a | 509 | #define __CRC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_CRCEN)) |
mbed_official | 330:c80ac197fa6a | 510 | #define __DMA1_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA1EN)) |
mbed_official | 330:c80ac197fa6a | 511 | #define __SRAM_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_SRAMEN)) |
mbed_official | 330:c80ac197fa6a | 512 | #define __FLITF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_FLITFEN)) |
mbed_official | 330:c80ac197fa6a | 513 | #define __TSC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_TSCEN)) |
mbed_official | 330:c80ac197fa6a | 514 | |
mbed_official | 330:c80ac197fa6a | 515 | #define __GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN)) |
mbed_official | 330:c80ac197fa6a | 516 | #define __GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN)) |
mbed_official | 330:c80ac197fa6a | 517 | #define __GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN)) |
mbed_official | 330:c80ac197fa6a | 518 | #define __GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN)) |
mbed_official | 330:c80ac197fa6a | 519 | #define __GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN)) |
mbed_official | 330:c80ac197fa6a | 520 | #define __CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN)) |
mbed_official | 330:c80ac197fa6a | 521 | #define __DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) |
mbed_official | 330:c80ac197fa6a | 522 | #define __SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN)) |
mbed_official | 330:c80ac197fa6a | 523 | #define __FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN)) |
mbed_official | 330:c80ac197fa6a | 524 | #define __TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN)) |
mbed_official | 330:c80ac197fa6a | 525 | /** |
mbed_official | 330:c80ac197fa6a | 526 | * @} |
mbed_official | 330:c80ac197fa6a | 527 | */ |
mbed_official | 330:c80ac197fa6a | 528 | |
mbed_official | 330:c80ac197fa6a | 529 | /** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable |
mbed_official | 330:c80ac197fa6a | 530 | * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. |
mbed_official | 330:c80ac197fa6a | 531 | * @note After reset, the peripheral clock (used for registers read/write access) |
mbed_official | 330:c80ac197fa6a | 532 | * is disabled and the application software has to enable this clock before |
mbed_official | 330:c80ac197fa6a | 533 | * using it. |
mbed_official | 330:c80ac197fa6a | 534 | * @{ |
mbed_official | 330:c80ac197fa6a | 535 | */ |
mbed_official | 330:c80ac197fa6a | 536 | #define __TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN)) |
mbed_official | 330:c80ac197fa6a | 537 | #define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN)) |
mbed_official | 330:c80ac197fa6a | 538 | #define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN)) |
mbed_official | 330:c80ac197fa6a | 539 | #define __USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN)) |
mbed_official | 330:c80ac197fa6a | 540 | #define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN)) |
mbed_official | 330:c80ac197fa6a | 541 | #define __I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN)) |
mbed_official | 330:c80ac197fa6a | 542 | #define __PWR_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_PWREN)) |
mbed_official | 330:c80ac197fa6a | 543 | #define __DAC1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DAC1EN)) |
mbed_official | 330:c80ac197fa6a | 544 | |
mbed_official | 330:c80ac197fa6a | 545 | #define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) |
mbed_official | 330:c80ac197fa6a | 546 | #define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) |
mbed_official | 330:c80ac197fa6a | 547 | #define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) |
mbed_official | 330:c80ac197fa6a | 548 | #define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) |
mbed_official | 330:c80ac197fa6a | 549 | #define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) |
mbed_official | 330:c80ac197fa6a | 550 | #define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) |
mbed_official | 330:c80ac197fa6a | 551 | #define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) |
mbed_official | 330:c80ac197fa6a | 552 | #define __DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC1EN)) |
mbed_official | 330:c80ac197fa6a | 553 | /** |
mbed_official | 330:c80ac197fa6a | 554 | * @} |
mbed_official | 330:c80ac197fa6a | 555 | */ |
mbed_official | 330:c80ac197fa6a | 556 | |
mbed_official | 330:c80ac197fa6a | 557 | /** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable |
mbed_official | 330:c80ac197fa6a | 558 | * @brief Enable or disable the High Speed APB (APB2) peripheral clock. |
mbed_official | 330:c80ac197fa6a | 559 | * @note After reset, the peripheral clock (used for registers read/write access) |
mbed_official | 330:c80ac197fa6a | 560 | * is disabled and the application software has to enable this clock before |
mbed_official | 330:c80ac197fa6a | 561 | * using it. |
mbed_official | 330:c80ac197fa6a | 562 | * @{ |
mbed_official | 330:c80ac197fa6a | 563 | */ |
mbed_official | 330:c80ac197fa6a | 564 | #define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SYSCFGEN)) |
mbed_official | 330:c80ac197fa6a | 565 | #define __TIM15_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM15EN)) |
mbed_official | 330:c80ac197fa6a | 566 | #define __TIM16_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM16EN)) |
mbed_official | 330:c80ac197fa6a | 567 | #define __TIM17_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM17EN)) |
mbed_official | 330:c80ac197fa6a | 568 | #define __USART1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN)) |
mbed_official | 330:c80ac197fa6a | 569 | |
mbed_official | 330:c80ac197fa6a | 570 | #define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) |
mbed_official | 330:c80ac197fa6a | 571 | #define __TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN)) |
mbed_official | 330:c80ac197fa6a | 572 | #define __TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN)) |
mbed_official | 330:c80ac197fa6a | 573 | #define __TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN)) |
mbed_official | 330:c80ac197fa6a | 574 | #define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) |
mbed_official | 330:c80ac197fa6a | 575 | /** |
mbed_official | 330:c80ac197fa6a | 576 | * @} |
mbed_official | 330:c80ac197fa6a | 577 | */ |
mbed_official | 330:c80ac197fa6a | 578 | |
mbed_official | 330:c80ac197fa6a | 579 | /** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset |
mbed_official | 330:c80ac197fa6a | 580 | * @brief Force or release AHB peripheral reset. |
mbed_official | 330:c80ac197fa6a | 581 | * @{ |
mbed_official | 330:c80ac197fa6a | 582 | */ |
mbed_official | 330:c80ac197fa6a | 583 | #define __AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF) |
mbed_official | 330:c80ac197fa6a | 584 | #define __GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST)) |
mbed_official | 330:c80ac197fa6a | 585 | #define __GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST)) |
mbed_official | 330:c80ac197fa6a | 586 | #define __GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST)) |
mbed_official | 330:c80ac197fa6a | 587 | #define __GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST)) |
mbed_official | 330:c80ac197fa6a | 588 | #define __GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST)) |
mbed_official | 330:c80ac197fa6a | 589 | #define __TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST)) |
mbed_official | 330:c80ac197fa6a | 590 | |
mbed_official | 330:c80ac197fa6a | 591 | #define __AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00) |
mbed_official | 330:c80ac197fa6a | 592 | #define __GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST)) |
mbed_official | 330:c80ac197fa6a | 593 | #define __GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST)) |
mbed_official | 330:c80ac197fa6a | 594 | #define __GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST)) |
mbed_official | 330:c80ac197fa6a | 595 | #define __GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST)) |
mbed_official | 330:c80ac197fa6a | 596 | #define __GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST)) |
mbed_official | 330:c80ac197fa6a | 597 | #define __TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST)) |
mbed_official | 330:c80ac197fa6a | 598 | /** |
mbed_official | 330:c80ac197fa6a | 599 | * @} |
mbed_official | 330:c80ac197fa6a | 600 | */ |
mbed_official | 330:c80ac197fa6a | 601 | |
mbed_official | 330:c80ac197fa6a | 602 | /** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset |
mbed_official | 330:c80ac197fa6a | 603 | * @brief Force or release APB1 peripheral reset. |
mbed_official | 330:c80ac197fa6a | 604 | * @{ |
mbed_official | 330:c80ac197fa6a | 605 | */ |
mbed_official | 330:c80ac197fa6a | 606 | #define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF) |
mbed_official | 330:c80ac197fa6a | 607 | #define __TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) |
mbed_official | 330:c80ac197fa6a | 608 | #define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) |
mbed_official | 330:c80ac197fa6a | 609 | #define __WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) |
mbed_official | 330:c80ac197fa6a | 610 | #define __USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) |
mbed_official | 330:c80ac197fa6a | 611 | #define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) |
mbed_official | 330:c80ac197fa6a | 612 | #define __I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) |
mbed_official | 330:c80ac197fa6a | 613 | #define __PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) |
mbed_official | 330:c80ac197fa6a | 614 | #define __DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC1RST)) |
mbed_official | 330:c80ac197fa6a | 615 | |
mbed_official | 330:c80ac197fa6a | 616 | #define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00) |
mbed_official | 330:c80ac197fa6a | 617 | #define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) |
mbed_official | 330:c80ac197fa6a | 618 | #define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) |
mbed_official | 330:c80ac197fa6a | 619 | #define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) |
mbed_official | 330:c80ac197fa6a | 620 | #define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) |
mbed_official | 330:c80ac197fa6a | 621 | #define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) |
mbed_official | 330:c80ac197fa6a | 622 | #define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) |
mbed_official | 330:c80ac197fa6a | 623 | #define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) |
mbed_official | 330:c80ac197fa6a | 624 | #define __DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC1RST)) |
mbed_official | 330:c80ac197fa6a | 625 | /** |
mbed_official | 330:c80ac197fa6a | 626 | * @} |
mbed_official | 330:c80ac197fa6a | 627 | */ |
mbed_official | 330:c80ac197fa6a | 628 | |
mbed_official | 330:c80ac197fa6a | 629 | /** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset |
mbed_official | 330:c80ac197fa6a | 630 | * @brief Force or release APB2 peripheral reset. |
mbed_official | 330:c80ac197fa6a | 631 | * @{ |
mbed_official | 330:c80ac197fa6a | 632 | */ |
mbed_official | 330:c80ac197fa6a | 633 | #define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF) |
mbed_official | 330:c80ac197fa6a | 634 | #define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) |
mbed_official | 330:c80ac197fa6a | 635 | #define __TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST)) |
mbed_official | 330:c80ac197fa6a | 636 | #define __TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST)) |
mbed_official | 330:c80ac197fa6a | 637 | #define __TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST)) |
mbed_official | 330:c80ac197fa6a | 638 | #define __USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) |
mbed_official | 330:c80ac197fa6a | 639 | |
mbed_official | 330:c80ac197fa6a | 640 | #define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00) |
mbed_official | 330:c80ac197fa6a | 641 | #define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) |
mbed_official | 330:c80ac197fa6a | 642 | #define __TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST)) |
mbed_official | 330:c80ac197fa6a | 643 | #define __TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST)) |
mbed_official | 330:c80ac197fa6a | 644 | #define __TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST)) |
mbed_official | 330:c80ac197fa6a | 645 | #define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) |
mbed_official | 330:c80ac197fa6a | 646 | /** |
mbed_official | 330:c80ac197fa6a | 647 | * @} |
mbed_official | 330:c80ac197fa6a | 648 | */ |
mbed_official | 330:c80ac197fa6a | 649 | |
mbed_official | 330:c80ac197fa6a | 650 | /** @defgroup RCC_HSI_Configuration RCC HSI Configuration |
mbed_official | 330:c80ac197fa6a | 651 | * @{ |
mbed_official | 330:c80ac197fa6a | 652 | */ |
mbed_official | 330:c80ac197fa6a | 653 | |
mbed_official | 330:c80ac197fa6a | 654 | /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). |
mbed_official | 330:c80ac197fa6a | 655 | * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. |
mbed_official | 330:c80ac197fa6a | 656 | * It is used (enabled by hardware) as system clock source after startup |
mbed_official | 330:c80ac197fa6a | 657 | * from Reset, wakeup from STOP and STANDBY mode, or in case of failure |
mbed_official | 330:c80ac197fa6a | 658 | * of the HSE used directly or indirectly as system clock (if the Clock |
mbed_official | 330:c80ac197fa6a | 659 | * Security System CSS is enabled). |
mbed_official | 330:c80ac197fa6a | 660 | * @note HSI can not be stopped if it is used as system clock source. In this case, |
mbed_official | 330:c80ac197fa6a | 661 | * you have to select another source of the system clock then stop the HSI. |
mbed_official | 330:c80ac197fa6a | 662 | * @note After enabling the HSI, the application software should wait on HSIRDY |
mbed_official | 330:c80ac197fa6a | 663 | * flag to be set indicating that HSI clock is stable and can be used as |
mbed_official | 330:c80ac197fa6a | 664 | * system clock source. |
mbed_official | 330:c80ac197fa6a | 665 | * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator |
mbed_official | 330:c80ac197fa6a | 666 | * clock cycles. |
mbed_official | 330:c80ac197fa6a | 667 | */ |
mbed_official | 330:c80ac197fa6a | 668 | #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *)CR_HSION_BB = ENABLE) |
mbed_official | 330:c80ac197fa6a | 669 | #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *)CR_HSION_BB = DISABLE) |
mbed_official | 330:c80ac197fa6a | 670 | |
mbed_official | 330:c80ac197fa6a | 671 | |
mbed_official | 330:c80ac197fa6a | 672 | /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. |
mbed_official | 330:c80ac197fa6a | 673 | * @note The calibration is used to compensate for the variations in voltage |
mbed_official | 330:c80ac197fa6a | 674 | * and temperature that influence the frequency of the internal HSI RC. |
mbed_official | 330:c80ac197fa6a | 675 | * @param __HSICalibrationValue__: specifies the calibration trimming value. |
mbed_official | 330:c80ac197fa6a | 676 | * This parameter must be a number between 0 and 0x1F. |
mbed_official | 330:c80ac197fa6a | 677 | */ |
mbed_official | 330:c80ac197fa6a | 678 | #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \ |
mbed_official | 330:c80ac197fa6a | 679 | MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)) |
mbed_official | 330:c80ac197fa6a | 680 | /** |
mbed_official | 330:c80ac197fa6a | 681 | * @} |
mbed_official | 330:c80ac197fa6a | 682 | */ |
mbed_official | 330:c80ac197fa6a | 683 | |
mbed_official | 330:c80ac197fa6a | 684 | /** @defgroup RCC_LSI_Configuration RCC LSI Configuration |
mbed_official | 330:c80ac197fa6a | 685 | * @{ |
mbed_official | 330:c80ac197fa6a | 686 | */ |
mbed_official | 330:c80ac197fa6a | 687 | |
mbed_official | 330:c80ac197fa6a | 688 | /** @brief Macro to enable or disable the Internal Low Speed oscillator (LSI). |
mbed_official | 330:c80ac197fa6a | 689 | * @note After enabling the LSI, the application software should wait on |
mbed_official | 330:c80ac197fa6a | 690 | * LSIRDY flag to be set indicating that LSI clock is stable and can |
mbed_official | 330:c80ac197fa6a | 691 | * be used to clock the IWDG and/or the RTC. |
mbed_official | 330:c80ac197fa6a | 692 | * @note LSI can not be disabled if the IWDG is running. |
mbed_official | 330:c80ac197fa6a | 693 | * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator |
mbed_official | 330:c80ac197fa6a | 694 | * clock cycles. |
mbed_official | 330:c80ac197fa6a | 695 | */ |
mbed_official | 330:c80ac197fa6a | 696 | #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *)CSR_LSION_BB = ENABLE) |
mbed_official | 330:c80ac197fa6a | 697 | #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *)CSR_LSION_BB = DISABLE) |
mbed_official | 330:c80ac197fa6a | 698 | /** |
mbed_official | 330:c80ac197fa6a | 699 | * @} |
mbed_official | 330:c80ac197fa6a | 700 | */ |
mbed_official | 330:c80ac197fa6a | 701 | |
mbed_official | 330:c80ac197fa6a | 702 | /** @defgroup RCC_HSE_Configuration RCC HSE Configuration |
mbed_official | 330:c80ac197fa6a | 703 | * @{ |
mbed_official | 330:c80ac197fa6a | 704 | */ |
mbed_official | 330:c80ac197fa6a | 705 | |
mbed_official | 330:c80ac197fa6a | 706 | /** |
mbed_official | 330:c80ac197fa6a | 707 | * @brief Macro to configure the External High Speed oscillator (HSE). |
mbed_official | 330:c80ac197fa6a | 708 | * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application |
mbed_official | 330:c80ac197fa6a | 709 | * software should wait on HSERDY flag to be set indicating that HSE clock |
mbed_official | 330:c80ac197fa6a | 710 | * is stable and can be used to clock the PLL and/or system clock. |
mbed_official | 330:c80ac197fa6a | 711 | * @note HSE state can not be changed if it is used directly or through the |
mbed_official | 330:c80ac197fa6a | 712 | * PLL as system clock. In this case, you have to select another source |
mbed_official | 330:c80ac197fa6a | 713 | * of the system clock then change the HSE state (ex. disable it). |
mbed_official | 330:c80ac197fa6a | 714 | * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. |
mbed_official | 330:c80ac197fa6a | 715 | * @note This function reset the CSSON bit, so if the Clock security system(CSS) |
mbed_official | 330:c80ac197fa6a | 716 | * was previously enabled you have to enable it again after calling this |
mbed_official | 330:c80ac197fa6a | 717 | * function. |
mbed_official | 330:c80ac197fa6a | 718 | * @param __STATE__: specifies the new state of the HSE. |
mbed_official | 330:c80ac197fa6a | 719 | * This parameter can be one of the following values: |
mbed_official | 330:c80ac197fa6a | 720 | * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after |
mbed_official | 330:c80ac197fa6a | 721 | * 6 HSE oscillator clock cycles. |
mbed_official | 330:c80ac197fa6a | 722 | * @arg RCC_HSE_ON: turn ON the HSE oscillator |
mbed_official | 330:c80ac197fa6a | 723 | * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock |
mbed_official | 330:c80ac197fa6a | 724 | */ |
mbed_official | 330:c80ac197fa6a | 725 | #define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *)CR_BYTE2_ADDRESS = (__STATE__)) |
mbed_official | 330:c80ac197fa6a | 726 | /** |
mbed_official | 330:c80ac197fa6a | 727 | * @} |
mbed_official | 330:c80ac197fa6a | 728 | */ |
mbed_official | 330:c80ac197fa6a | 729 | |
mbed_official | 330:c80ac197fa6a | 730 | /** @defgroup RCC_LSE_Configuration RCC LSE Configuration |
mbed_official | 330:c80ac197fa6a | 731 | * @{ |
mbed_official | 330:c80ac197fa6a | 732 | */ |
mbed_official | 330:c80ac197fa6a | 733 | /** |
mbed_official | 330:c80ac197fa6a | 734 | * @brief Macro to configure the External Low Speed oscillator (LSE). |
mbed_official | 330:c80ac197fa6a | 735 | * @note As the LSE is in the Backup domain and write access is denied to |
mbed_official | 330:c80ac197fa6a | 736 | * this domain after reset, you have to enable write access using |
mbed_official | 330:c80ac197fa6a | 737 | * HAL_PWR_EnableBkUpAccess() function before to configure the LSE |
mbed_official | 330:c80ac197fa6a | 738 | * (to be done once after reset). |
mbed_official | 330:c80ac197fa6a | 739 | * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application |
mbed_official | 330:c80ac197fa6a | 740 | * software should wait on LSERDY flag to be set indicating that LSE clock |
mbed_official | 330:c80ac197fa6a | 741 | * is stable and can be used to clock the RTC. |
mbed_official | 330:c80ac197fa6a | 742 | * @param __STATE__: specifies the new state of the LSE. |
mbed_official | 330:c80ac197fa6a | 743 | * This parameter can be one of the following values: |
mbed_official | 330:c80ac197fa6a | 744 | * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after |
mbed_official | 330:c80ac197fa6a | 745 | * 6 LSE oscillator clock cycles. |
mbed_official | 330:c80ac197fa6a | 746 | * @arg RCC_LSE_ON: turn ON the LSE oscillator |
mbed_official | 330:c80ac197fa6a | 747 | * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock |
mbed_official | 330:c80ac197fa6a | 748 | */ |
mbed_official | 330:c80ac197fa6a | 749 | #define __HAL_RCC_LSE_CONFIG(__STATE__) \ |
mbed_official | 330:c80ac197fa6a | 750 | MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEON|RCC_BDCR_LSEBYP, (uint32_t)(__STATE__)) |
mbed_official | 330:c80ac197fa6a | 751 | /** |
mbed_official | 330:c80ac197fa6a | 752 | * @} |
mbed_official | 330:c80ac197fa6a | 753 | */ |
mbed_official | 330:c80ac197fa6a | 754 | |
mbed_official | 330:c80ac197fa6a | 755 | /** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config |
mbed_official | 330:c80ac197fa6a | 756 | * @{ |
mbed_official | 330:c80ac197fa6a | 757 | */ |
mbed_official | 330:c80ac197fa6a | 758 | /** @brief Macro to configure the I2C1 clock (I2C1CLK). |
mbed_official | 330:c80ac197fa6a | 759 | * @param __I2C1CLKSource__: specifies the I2C1 clock source. |
mbed_official | 330:c80ac197fa6a | 760 | * This parameter can be one of the following values: |
mbed_official | 330:c80ac197fa6a | 761 | * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock |
mbed_official | 330:c80ac197fa6a | 762 | * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock |
mbed_official | 330:c80ac197fa6a | 763 | */ |
mbed_official | 330:c80ac197fa6a | 764 | #define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) \ |
mbed_official | 330:c80ac197fa6a | 765 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSource__)) |
mbed_official | 330:c80ac197fa6a | 766 | |
mbed_official | 330:c80ac197fa6a | 767 | /** @brief Macro to get the I2C1 clock source. |
mbed_official | 330:c80ac197fa6a | 768 | * @retval The clock source can be one of the following values: |
mbed_official | 330:c80ac197fa6a | 769 | * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock |
mbed_official | 330:c80ac197fa6a | 770 | * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock |
mbed_official | 330:c80ac197fa6a | 771 | */ |
mbed_official | 330:c80ac197fa6a | 772 | #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW))) |
mbed_official | 330:c80ac197fa6a | 773 | /** |
mbed_official | 330:c80ac197fa6a | 774 | * @} |
mbed_official | 330:c80ac197fa6a | 775 | */ |
mbed_official | 330:c80ac197fa6a | 776 | |
mbed_official | 330:c80ac197fa6a | 777 | /** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config |
mbed_official | 330:c80ac197fa6a | 778 | * @{ |
mbed_official | 330:c80ac197fa6a | 779 | */ |
mbed_official | 330:c80ac197fa6a | 780 | |
mbed_official | 330:c80ac197fa6a | 781 | /** @brief Macro to configure the USART1 clock (USART1CLK). |
mbed_official | 330:c80ac197fa6a | 782 | * @param __USART1CLKSource__: specifies the USART1 clock source. |
mbed_official | 330:c80ac197fa6a | 783 | * This parameter can be one of the following values: |
mbed_official | 330:c80ac197fa6a | 784 | * @arg RCC_USART1CLKSOURCE_PCLK2 or RCC_USART1CLKSOURCE_PCLK1: PCLK2 or PCLK1 selected as USART1 clock |
mbed_official | 330:c80ac197fa6a | 785 | * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock |
mbed_official | 330:c80ac197fa6a | 786 | * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock |
mbed_official | 330:c80ac197fa6a | 787 | * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock |
mbed_official | 330:c80ac197fa6a | 788 | */ |
mbed_official | 330:c80ac197fa6a | 789 | #define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \ |
mbed_official | 330:c80ac197fa6a | 790 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSource__)) |
mbed_official | 330:c80ac197fa6a | 791 | |
mbed_official | 330:c80ac197fa6a | 792 | /** @brief Macro to get the USART1 clock source. |
mbed_official | 330:c80ac197fa6a | 793 | * @retval The clock source can be one of the following values: |
mbed_official | 330:c80ac197fa6a | 794 | * @arg RCC_USART1CLKSOURCE_PCLK2 or RCC_USART1CLKSOURCE_PCLK1: PCLK2 or PCLK1 selected as USART1 clock |
mbed_official | 330:c80ac197fa6a | 795 | * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock |
mbed_official | 330:c80ac197fa6a | 796 | * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock |
mbed_official | 330:c80ac197fa6a | 797 | * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock |
mbed_official | 330:c80ac197fa6a | 798 | */ |
mbed_official | 330:c80ac197fa6a | 799 | #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW))) |
mbed_official | 330:c80ac197fa6a | 800 | |
mbed_official | 330:c80ac197fa6a | 801 | /** @brief Macro to configure the USART2 clock (USART2CLK). |
mbed_official | 330:c80ac197fa6a | 802 | * @param __USART2CLKSource__: specifies the USART2 clock source. |
mbed_official | 330:c80ac197fa6a | 803 | * This parameter can be one of the following values: |
mbed_official | 330:c80ac197fa6a | 804 | * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock |
mbed_official | 330:c80ac197fa6a | 805 | * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock |
mbed_official | 330:c80ac197fa6a | 806 | * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock |
mbed_official | 330:c80ac197fa6a | 807 | * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock |
mbed_official | 330:c80ac197fa6a | 808 | */ |
mbed_official | 330:c80ac197fa6a | 809 | #define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \ |
mbed_official | 330:c80ac197fa6a | 810 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSource__)) |
mbed_official | 330:c80ac197fa6a | 811 | |
mbed_official | 330:c80ac197fa6a | 812 | /** @brief Macro to get the USART2 clock source. |
mbed_official | 330:c80ac197fa6a | 813 | * @retval The clock source can be one of the following values: |
mbed_official | 330:c80ac197fa6a | 814 | * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock |
mbed_official | 330:c80ac197fa6a | 815 | * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock |
mbed_official | 330:c80ac197fa6a | 816 | * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock |
mbed_official | 330:c80ac197fa6a | 817 | * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock |
mbed_official | 330:c80ac197fa6a | 818 | */ |
mbed_official | 330:c80ac197fa6a | 819 | #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW))) |
mbed_official | 330:c80ac197fa6a | 820 | |
mbed_official | 330:c80ac197fa6a | 821 | /** @brief Macro to configure the USART3 clock (USART3CLK). |
mbed_official | 330:c80ac197fa6a | 822 | * @param __USART3CLKSource__: specifies the USART3 clock source. |
mbed_official | 330:c80ac197fa6a | 823 | * This parameter can be one of the following values: |
mbed_official | 330:c80ac197fa6a | 824 | * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock |
mbed_official | 330:c80ac197fa6a | 825 | * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock |
mbed_official | 330:c80ac197fa6a | 826 | * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock |
mbed_official | 330:c80ac197fa6a | 827 | * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock |
mbed_official | 330:c80ac197fa6a | 828 | */ |
mbed_official | 330:c80ac197fa6a | 829 | #define __HAL_RCC_USART3_CONFIG(__USART3CLKSource__) \ |
mbed_official | 330:c80ac197fa6a | 830 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSource__)) |
mbed_official | 330:c80ac197fa6a | 831 | |
mbed_official | 330:c80ac197fa6a | 832 | /** @brief Macro to get the USART3 clock source. |
mbed_official | 330:c80ac197fa6a | 833 | * @retval The clock source can be one of the following values: |
mbed_official | 330:c80ac197fa6a | 834 | * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock |
mbed_official | 330:c80ac197fa6a | 835 | * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock |
mbed_official | 330:c80ac197fa6a | 836 | * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock |
mbed_official | 330:c80ac197fa6a | 837 | * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock |
mbed_official | 330:c80ac197fa6a | 838 | */ |
mbed_official | 330:c80ac197fa6a | 839 | #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW))) |
mbed_official | 330:c80ac197fa6a | 840 | /** |
mbed_official | 330:c80ac197fa6a | 841 | * @} |
mbed_official | 330:c80ac197fa6a | 842 | */ |
mbed_official | 330:c80ac197fa6a | 843 | |
mbed_official | 330:c80ac197fa6a | 844 | /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration |
mbed_official | 330:c80ac197fa6a | 845 | * @{ |
mbed_official | 330:c80ac197fa6a | 846 | */ |
mbed_official | 330:c80ac197fa6a | 847 | /** @brief Macros to enable or disable the the RTC clock. |
mbed_official | 330:c80ac197fa6a | 848 | * @note These macros must be used only after the RTC clock source was selected. |
mbed_official | 330:c80ac197fa6a | 849 | */ |
mbed_official | 330:c80ac197fa6a | 850 | #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *)BDCR_RTCEN_BB = ENABLE) |
mbed_official | 330:c80ac197fa6a | 851 | #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *)BDCR_RTCEN_BB = DISABLE) |
mbed_official | 330:c80ac197fa6a | 852 | |
mbed_official | 330:c80ac197fa6a | 853 | /** @brief Macro to configure the RTC clock (RTCCLK). |
mbed_official | 330:c80ac197fa6a | 854 | * @note As the RTC clock configuration bits are in the Backup domain and write |
mbed_official | 330:c80ac197fa6a | 855 | * access is denied to this domain after reset, you have to enable write |
mbed_official | 330:c80ac197fa6a | 856 | * access using the Power Backup Access macro before to configure |
mbed_official | 330:c80ac197fa6a | 857 | * the RTC clock source (to be done once after reset). |
mbed_official | 330:c80ac197fa6a | 858 | * @note Once the RTC clock is configured it can't be changed unless the |
mbed_official | 330:c80ac197fa6a | 859 | * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by |
mbed_official | 330:c80ac197fa6a | 860 | * a Power On Reset (POR). |
mbed_official | 330:c80ac197fa6a | 861 | * @param __RTCCLKSource__: specifies the RTC clock source. |
mbed_official | 330:c80ac197fa6a | 862 | * This parameter can be one of the following values: |
mbed_official | 330:c80ac197fa6a | 863 | * @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock |
mbed_official | 330:c80ac197fa6a | 864 | * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock |
mbed_official | 330:c80ac197fa6a | 865 | * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock |
mbed_official | 330:c80ac197fa6a | 866 | * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32 |
mbed_official | 330:c80ac197fa6a | 867 | * |
mbed_official | 330:c80ac197fa6a | 868 | * @note If the LSE is used as RTC clock source, the RTC continues to |
mbed_official | 330:c80ac197fa6a | 869 | * work in STOP and STANDBY modes, and can be used as wakeup source. |
mbed_official | 330:c80ac197fa6a | 870 | * However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source, |
mbed_official | 330:c80ac197fa6a | 871 | * the RTC cannot be used in STOP and STANDBY modes. |
mbed_official | 330:c80ac197fa6a | 872 | * @note The system must always be configured so as to get a PCLK frequency greater than or |
mbed_official | 330:c80ac197fa6a | 873 | * equal to the RTCCLK frequency for a proper operation of the RTC. |
mbed_official | 330:c80ac197fa6a | 874 | */ |
mbed_official | 330:c80ac197fa6a | 875 | #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) \ |
mbed_official | 330:c80ac197fa6a | 876 | MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (uint32_t)(__RTCCLKSource__)) |
mbed_official | 330:c80ac197fa6a | 877 | |
mbed_official | 330:c80ac197fa6a | 878 | /** @brief Macro to get the RTC clock source. |
mbed_official | 330:c80ac197fa6a | 879 | * @retval The clock source can be one of the following values: |
mbed_official | 330:c80ac197fa6a | 880 | * @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock |
mbed_official | 330:c80ac197fa6a | 881 | * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock |
mbed_official | 330:c80ac197fa6a | 882 | * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock |
mbed_official | 330:c80ac197fa6a | 883 | * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32 selected as RTC clock |
mbed_official | 330:c80ac197fa6a | 884 | */ |
mbed_official | 330:c80ac197fa6a | 885 | #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))) |
mbed_official | 330:c80ac197fa6a | 886 | /** |
mbed_official | 330:c80ac197fa6a | 887 | * @} |
mbed_official | 330:c80ac197fa6a | 888 | */ |
mbed_official | 330:c80ac197fa6a | 889 | |
mbed_official | 330:c80ac197fa6a | 890 | /** @defgroup RCC_Force_Release_Backup RCC Force Release Backup |
mbed_official | 330:c80ac197fa6a | 891 | * @{ |
mbed_official | 330:c80ac197fa6a | 892 | */ |
mbed_official | 330:c80ac197fa6a | 893 | |
mbed_official | 330:c80ac197fa6a | 894 | /** @brief Macro to force or release the Backup domain reset. |
mbed_official | 330:c80ac197fa6a | 895 | * @note These macros reset the RTC peripheral (including the backup registers) |
mbed_official | 330:c80ac197fa6a | 896 | * and the RTC clock source selection in RCC_CSR register. |
mbed_official | 330:c80ac197fa6a | 897 | * @note The BKPSRAM is not affected by this reset. |
mbed_official | 330:c80ac197fa6a | 898 | */ |
mbed_official | 330:c80ac197fa6a | 899 | #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *)BDCR_BDRST_BB = ENABLE) |
mbed_official | 330:c80ac197fa6a | 900 | #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *)BDCR_BDRST_BB = DISABLE) |
mbed_official | 330:c80ac197fa6a | 901 | /** |
mbed_official | 330:c80ac197fa6a | 902 | * @} |
mbed_official | 330:c80ac197fa6a | 903 | */ |
mbed_official | 330:c80ac197fa6a | 904 | |
mbed_official | 330:c80ac197fa6a | 905 | /** @defgroup RCC_PLL_Configuration RCC PLL Configuration |
mbed_official | 330:c80ac197fa6a | 906 | * @{ |
mbed_official | 330:c80ac197fa6a | 907 | */ |
mbed_official | 330:c80ac197fa6a | 908 | |
mbed_official | 330:c80ac197fa6a | 909 | /** @brief Macro to enable or disable the PLL. |
mbed_official | 330:c80ac197fa6a | 910 | * @note After enabling the PLL, the application software should wait on |
mbed_official | 330:c80ac197fa6a | 911 | * PLLRDY flag to be set indicating that PLL clock is stable and can |
mbed_official | 330:c80ac197fa6a | 912 | * be used as system clock source. |
mbed_official | 330:c80ac197fa6a | 913 | * @note The PLL can not be disabled if it is used as system clock source |
mbed_official | 330:c80ac197fa6a | 914 | * @note The PLL is disabled by hardware when entering STOP and STANDBY modes. |
mbed_official | 330:c80ac197fa6a | 915 | */ |
mbed_official | 330:c80ac197fa6a | 916 | #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *)CR_PLLON_BB = ENABLE) |
mbed_official | 330:c80ac197fa6a | 917 | #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *)CR_PLLON_BB = DISABLE) |
mbed_official | 330:c80ac197fa6a | 918 | /** |
mbed_official | 330:c80ac197fa6a | 919 | * @} |
mbed_official | 330:c80ac197fa6a | 920 | */ |
mbed_official | 330:c80ac197fa6a | 921 | |
mbed_official | 330:c80ac197fa6a | 922 | /** @defgroup RCC_Get_Clock_source RCC Get Clock source |
mbed_official | 330:c80ac197fa6a | 923 | * @{ |
mbed_official | 330:c80ac197fa6a | 924 | */ |
mbed_official | 330:c80ac197fa6a | 925 | |
mbed_official | 330:c80ac197fa6a | 926 | /** @brief Macro to get the clock source used as system clock. |
mbed_official | 330:c80ac197fa6a | 927 | * @retval The clock source used as system clock. |
mbed_official | 330:c80ac197fa6a | 928 | * The returned value can be one of the following value: |
mbed_official | 330:c80ac197fa6a | 929 | * @arg RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock |
mbed_official | 330:c80ac197fa6a | 930 | * @arg RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock |
mbed_official | 330:c80ac197fa6a | 931 | * @arg RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock |
mbed_official | 330:c80ac197fa6a | 932 | */ |
mbed_official | 330:c80ac197fa6a | 933 | #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS))) |
mbed_official | 330:c80ac197fa6a | 934 | |
mbed_official | 330:c80ac197fa6a | 935 | /** @brief Macro to get the oscillator used as PLL clock source. |
mbed_official | 330:c80ac197fa6a | 936 | * @retval The oscillator used as PLL clock source. The returned value can be one |
mbed_official | 330:c80ac197fa6a | 937 | * of the following: |
mbed_official | 330:c80ac197fa6a | 938 | * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. |
mbed_official | 330:c80ac197fa6a | 939 | * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. |
mbed_official | 330:c80ac197fa6a | 940 | */ |
mbed_official | 330:c80ac197fa6a | 941 | #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC))) |
mbed_official | 330:c80ac197fa6a | 942 | /** |
mbed_official | 330:c80ac197fa6a | 943 | * @} |
mbed_official | 330:c80ac197fa6a | 944 | */ |
mbed_official | 330:c80ac197fa6a | 945 | |
mbed_official | 330:c80ac197fa6a | 946 | /** @defgroup RCC_Flags_Interrupts_Management RCC Flags Interrupts Management |
mbed_official | 330:c80ac197fa6a | 947 | * @brief macros to manage the specified RCC Flags and interrupts. |
mbed_official | 330:c80ac197fa6a | 948 | * @{ |
mbed_official | 330:c80ac197fa6a | 949 | */ |
mbed_official | 330:c80ac197fa6a | 950 | |
mbed_official | 330:c80ac197fa6a | 951 | /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to enable |
mbed_official | 330:c80ac197fa6a | 952 | * the selected interrupts.). |
mbed_official | 330:c80ac197fa6a | 953 | * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. |
mbed_official | 330:c80ac197fa6a | 954 | * This parameter can be any combination of the following values: |
mbed_official | 330:c80ac197fa6a | 955 | * @arg RCC_IT_LSIRDY: LSI ready interrupt enable |
mbed_official | 330:c80ac197fa6a | 956 | * @arg RCC_IT_LSERDY: LSE ready interrupt enable |
mbed_official | 330:c80ac197fa6a | 957 | * @arg RCC_IT_HSIRDY: HSI ready interrupt enable |
mbed_official | 330:c80ac197fa6a | 958 | * @arg RCC_IT_HSERDY: HSE ready interrupt enable |
mbed_official | 330:c80ac197fa6a | 959 | * @arg RCC_IT_PLLRDY: PLL ready interrupt enable |
mbed_official | 330:c80ac197fa6a | 960 | */ |
mbed_official | 330:c80ac197fa6a | 961 | #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) |
mbed_official | 330:c80ac197fa6a | 962 | |
mbed_official | 330:c80ac197fa6a | 963 | /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to disable |
mbed_official | 330:c80ac197fa6a | 964 | * the selected interrupts.). |
mbed_official | 330:c80ac197fa6a | 965 | * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. |
mbed_official | 330:c80ac197fa6a | 966 | * This parameter can be any combination of the following values: |
mbed_official | 330:c80ac197fa6a | 967 | * @arg RCC_IT_LSIRDYIE: LSI ready interrupt enable |
mbed_official | 330:c80ac197fa6a | 968 | * @arg RCC_IT_LSERDYIE: LSE ready interrupt enable |
mbed_official | 330:c80ac197fa6a | 969 | * @arg RCC_IT_HSIRDYIE: HSI ready interrupt enable |
mbed_official | 330:c80ac197fa6a | 970 | * @arg RCC_IT_HSERDYIE: HSE ready interrupt enable |
mbed_official | 330:c80ac197fa6a | 971 | * @arg RCC_IT_PLLRDYIE: PLL ready interrupt enable |
mbed_official | 330:c80ac197fa6a | 972 | */ |
mbed_official | 330:c80ac197fa6a | 973 | #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__)) |
mbed_official | 330:c80ac197fa6a | 974 | |
mbed_official | 330:c80ac197fa6a | 975 | /** @brief Clear the RCC's interrupt pending bits ( Perform Byte access to RCC_CIR[23:16] |
mbed_official | 330:c80ac197fa6a | 976 | * bits to clear the selected interrupt pending bits. |
mbed_official | 330:c80ac197fa6a | 977 | * @param __IT__: specifies the interrupt pending bit to clear. |
mbed_official | 330:c80ac197fa6a | 978 | * This parameter can be any combination of the following values: |
mbed_official | 330:c80ac197fa6a | 979 | * @arg RCC_IT_LSIRDYC: LSI ready interrupt clear |
mbed_official | 330:c80ac197fa6a | 980 | * @arg RCC_IT_LSERDYC: LSE ready interrupt clear |
mbed_official | 330:c80ac197fa6a | 981 | * @arg RCC_IT_HSIRDYC: HSI ready interrupt clear |
mbed_official | 330:c80ac197fa6a | 982 | * @arg RCC_IT_HSERDYC: HSE ready interrupt clear |
mbed_official | 330:c80ac197fa6a | 983 | * @arg RCC_IT_PLLRDYC: PLL ready interrupt clear |
mbed_official | 330:c80ac197fa6a | 984 | * @arg RCC_IT_CSSC: Clock Security System interrupt clear |
mbed_official | 330:c80ac197fa6a | 985 | */ |
mbed_official | 330:c80ac197fa6a | 986 | #define __HAL_RCC_CLEAR_IT(__IT__) (*(__IO uint8_t *)CIR_BYTE2_ADDRESS = (__IT__)) |
mbed_official | 330:c80ac197fa6a | 987 | |
mbed_official | 330:c80ac197fa6a | 988 | /** @brief Check the RCC's interrupt has occurred or not. |
mbed_official | 330:c80ac197fa6a | 989 | * @param __IT__: specifies the RCC interrupt source to check. |
mbed_official | 330:c80ac197fa6a | 990 | * This parameter can be one of the following values: |
mbed_official | 330:c80ac197fa6a | 991 | * @arg RCC_IT_LSIRDYF: LSI ready interrupt flag |
mbed_official | 330:c80ac197fa6a | 992 | * @arg RCC_IT_LSERDYF: LSE ready interrupt flag |
mbed_official | 330:c80ac197fa6a | 993 | * @arg RCC_IT_HSIRDYF: HSI ready interrupt flag |
mbed_official | 330:c80ac197fa6a | 994 | * @arg RCC_IT_HSERDYF: HSE ready interrupt flag |
mbed_official | 330:c80ac197fa6a | 995 | * @arg RCC_IT_PLLRDYF: PLL ready interrupt flag |
mbed_official | 330:c80ac197fa6a | 996 | * @arg RCC_IT_CSSF: Clock Security System interrupt flag |
mbed_official | 330:c80ac197fa6a | 997 | * @retval The new state of __IT__ (TRUE or FALSE). |
mbed_official | 330:c80ac197fa6a | 998 | */ |
mbed_official | 330:c80ac197fa6a | 999 | #define __HAL_RCC_GET_IT(__IT__) ((RCC->CIR & (__IT__)) == (__IT__)) |
mbed_official | 330:c80ac197fa6a | 1000 | |
mbed_official | 330:c80ac197fa6a | 1001 | /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, |
mbed_official | 330:c80ac197fa6a | 1002 | * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST |
mbed_official | 330:c80ac197fa6a | 1003 | */ |
mbed_official | 330:c80ac197fa6a | 1004 | #define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)CSR_RMVF_BB = ENABLE) |
mbed_official | 330:c80ac197fa6a | 1005 | |
mbed_official | 330:c80ac197fa6a | 1006 | /** @brief Check RCC flag is set or not. |
mbed_official | 330:c80ac197fa6a | 1007 | * @param __FLAG__: specifies the flag to check. |
mbed_official | 330:c80ac197fa6a | 1008 | * This parameter can be one of the following values: |
mbed_official | 330:c80ac197fa6a | 1009 | * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready |
mbed_official | 330:c80ac197fa6a | 1010 | * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready |
mbed_official | 330:c80ac197fa6a | 1011 | * @arg RCC_FLAG_PLLRDY: PLL clock ready |
mbed_official | 330:c80ac197fa6a | 1012 | * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready |
mbed_official | 330:c80ac197fa6a | 1013 | * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready |
mbed_official | 330:c80ac197fa6a | 1014 | * @arg RCC_FLAG_OBLRST: Option Byte Load reset |
mbed_official | 330:c80ac197fa6a | 1015 | * @arg RCC_FLAG_PINRST: Pin reset |
mbed_official | 330:c80ac197fa6a | 1016 | * @arg RCC_FLAG_PORRST: POR/PDR reset |
mbed_official | 330:c80ac197fa6a | 1017 | * @arg RCC_FLAG_SFTRST: Software reset |
mbed_official | 330:c80ac197fa6a | 1018 | * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset |
mbed_official | 330:c80ac197fa6a | 1019 | * @arg RCC_FLAG_WWDGRST: Window Watchdog reset |
mbed_official | 330:c80ac197fa6a | 1020 | * @arg RCC_FLAG_LPWRRST: Low Power reset |
mbed_official | 330:c80ac197fa6a | 1021 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
mbed_official | 330:c80ac197fa6a | 1022 | */ |
mbed_official | 330:c80ac197fa6a | 1023 | #define RCC_FLAG_MASK ((uint32_t)0x0000001F) |
mbed_official | 330:c80ac197fa6a | 1024 | #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR : \ |
mbed_official | 330:c80ac197fa6a | 1025 | ((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \ |
mbed_official | 330:c80ac197fa6a | 1026 | RCC->CSR)) & (1U << ((__FLAG__) & RCC_FLAG_MASK))) |
mbed_official | 330:c80ac197fa6a | 1027 | |
mbed_official | 330:c80ac197fa6a | 1028 | |
mbed_official | 330:c80ac197fa6a | 1029 | /** |
mbed_official | 330:c80ac197fa6a | 1030 | * @} |
mbed_official | 330:c80ac197fa6a | 1031 | */ |
mbed_official | 330:c80ac197fa6a | 1032 | |
mbed_official | 330:c80ac197fa6a | 1033 | /** |
mbed_official | 330:c80ac197fa6a | 1034 | * @} |
mbed_official | 330:c80ac197fa6a | 1035 | */ |
mbed_official | 330:c80ac197fa6a | 1036 | |
mbed_official | 330:c80ac197fa6a | 1037 | /* Include RCC HAL Extended module */ |
mbed_official | 330:c80ac197fa6a | 1038 | #include "stm32f3xx_hal_rcc_ex.h" |
mbed_official | 330:c80ac197fa6a | 1039 | |
mbed_official | 330:c80ac197fa6a | 1040 | /* Exported functions --------------------------------------------------------*/ |
mbed_official | 330:c80ac197fa6a | 1041 | |
mbed_official | 330:c80ac197fa6a | 1042 | /** @addtogroup RCC_Exported_Functions |
mbed_official | 330:c80ac197fa6a | 1043 | * @{ |
mbed_official | 330:c80ac197fa6a | 1044 | */ |
mbed_official | 330:c80ac197fa6a | 1045 | |
mbed_official | 330:c80ac197fa6a | 1046 | /** @addtogroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions |
mbed_official | 330:c80ac197fa6a | 1047 | * @{ |
mbed_official | 330:c80ac197fa6a | 1048 | */ |
mbed_official | 330:c80ac197fa6a | 1049 | |
mbed_official | 330:c80ac197fa6a | 1050 | /* Initialization and de-initialization functions ***************************/ |
mbed_official | 330:c80ac197fa6a | 1051 | void HAL_RCC_DeInit(void); |
mbed_official | 330:c80ac197fa6a | 1052 | HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); |
mbed_official | 330:c80ac197fa6a | 1053 | HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); |
mbed_official | 330:c80ac197fa6a | 1054 | |
mbed_official | 330:c80ac197fa6a | 1055 | /** |
mbed_official | 330:c80ac197fa6a | 1056 | * @} |
mbed_official | 330:c80ac197fa6a | 1057 | */ |
mbed_official | 330:c80ac197fa6a | 1058 | |
mbed_official | 330:c80ac197fa6a | 1059 | /** @addtogroup RCC_Exported_Functions_Group2 Peripheral Control functions |
mbed_official | 330:c80ac197fa6a | 1060 | * @{ |
mbed_official | 330:c80ac197fa6a | 1061 | */ |
mbed_official | 330:c80ac197fa6a | 1062 | |
mbed_official | 330:c80ac197fa6a | 1063 | /* Peripheral Control functions *********************************************/ |
mbed_official | 330:c80ac197fa6a | 1064 | void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); |
mbed_official | 330:c80ac197fa6a | 1065 | void HAL_RCC_EnableCSS(void); |
mbed_official | 330:c80ac197fa6a | 1066 | void HAL_RCC_DisableCSS(void); |
mbed_official | 330:c80ac197fa6a | 1067 | uint32_t HAL_RCC_GetSysClockFreq(void); |
mbed_official | 330:c80ac197fa6a | 1068 | uint32_t HAL_RCC_GetHCLKFreq(void); |
mbed_official | 330:c80ac197fa6a | 1069 | uint32_t HAL_RCC_GetPCLK1Freq(void); |
mbed_official | 330:c80ac197fa6a | 1070 | uint32_t HAL_RCC_GetPCLK2Freq(void); |
mbed_official | 330:c80ac197fa6a | 1071 | void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); |
mbed_official | 330:c80ac197fa6a | 1072 | void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); |
mbed_official | 330:c80ac197fa6a | 1073 | |
mbed_official | 330:c80ac197fa6a | 1074 | /* CSS NMI IRQ handler */ |
mbed_official | 330:c80ac197fa6a | 1075 | void HAL_RCC_NMI_IRQHandler(void); |
mbed_official | 330:c80ac197fa6a | 1076 | |
mbed_official | 330:c80ac197fa6a | 1077 | /* User Callbacks in non blocking mode (IT mode) */ |
mbed_official | 330:c80ac197fa6a | 1078 | void HAL_RCC_CCSCallback(void); |
mbed_official | 330:c80ac197fa6a | 1079 | |
mbed_official | 330:c80ac197fa6a | 1080 | /** |
mbed_official | 330:c80ac197fa6a | 1081 | * @} |
mbed_official | 330:c80ac197fa6a | 1082 | */ |
mbed_official | 330:c80ac197fa6a | 1083 | |
mbed_official | 330:c80ac197fa6a | 1084 | /** |
mbed_official | 330:c80ac197fa6a | 1085 | * @} |
mbed_official | 330:c80ac197fa6a | 1086 | */ |
mbed_official | 330:c80ac197fa6a | 1087 | |
mbed_official | 330:c80ac197fa6a | 1088 | /** |
mbed_official | 330:c80ac197fa6a | 1089 | * @} |
mbed_official | 330:c80ac197fa6a | 1090 | */ |
mbed_official | 330:c80ac197fa6a | 1091 | |
mbed_official | 330:c80ac197fa6a | 1092 | /** |
mbed_official | 330:c80ac197fa6a | 1093 | * @} |
mbed_official | 330:c80ac197fa6a | 1094 | */ |
mbed_official | 330:c80ac197fa6a | 1095 | |
mbed_official | 330:c80ac197fa6a | 1096 | #ifdef __cplusplus |
mbed_official | 330:c80ac197fa6a | 1097 | } |
mbed_official | 330:c80ac197fa6a | 1098 | #endif |
mbed_official | 330:c80ac197fa6a | 1099 | |
mbed_official | 330:c80ac197fa6a | 1100 | #endif /* __STM32F3xx_HAL_RCC_H */ |
mbed_official | 330:c80ac197fa6a | 1101 | |
mbed_official | 330:c80ac197fa6a | 1102 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |