marcus chiou
mbed library sources
Fork of
mbed-src
by 
mbed official
targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/clock_samd21_r21/clock.c@592:a274ee790e56, 2015-07-17 (annotated)
- Committer:
- mbed_official
- Date:
- Fri Jul 17 09:15:10 2015 +0100
- Revision:
- 592:a274ee790e56
- Parent:
- 579:53297373a894
Synchronized with git revision e7144f83a8d75df80c4877936b6ffe552b0be9e6
Full URL: https://github.com/mbedmicro/mbed/commit/e7144f83a8d75df80c4877936b6ffe552b0be9e6/
More API implementation for SAMR21
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 579:53297373a894 | 1 | #include <compiler.h> |
| mbed_official | 579:53297373a894 | 2 | #include <clock.h> |
| mbed_official | 579:53297373a894 | 3 | #include <conf_clocks.h> |
| mbed_official | 579:53297373a894 | 4 | #include <system.h> |
| mbed_official | 579:53297373a894 | 5 | |
| mbed_official | 579:53297373a894 | 6 | #ifndef SYSCTRL_FUSES_OSC32K_ADDR |
| mbed_official | 579:53297373a894 | 7 | # define SYSCTRL_FUSES_OSC32K_ADDR SYSCTRL_FUSES_OSC32K_CAL_ADDR |
| mbed_official | 579:53297373a894 | 8 | # define SYSCTRL_FUSES_OSC32K_Pos SYSCTRL_FUSES_OSC32K_CAL_Pos |
| mbed_official | 579:53297373a894 | 9 | #endif |
| mbed_official | 579:53297373a894 | 10 | |
| mbed_official | 579:53297373a894 | 11 | /** |
| mbed_official | 579:53297373a894 | 12 | * \internal |
| mbed_official | 579:53297373a894 | 13 | * \brief DFLL-specific data container. |
| mbed_official | 579:53297373a894 | 14 | */ |
| mbed_official | 579:53297373a894 | 15 | struct _system_clock_dfll_config { |
| mbed_official | 579:53297373a894 | 16 | uint32_t control; |
| mbed_official | 579:53297373a894 | 17 | uint32_t val; |
| mbed_official | 579:53297373a894 | 18 | uint32_t mul; |
| mbed_official | 579:53297373a894 | 19 | }; |
| mbed_official | 579:53297373a894 | 20 | |
| mbed_official | 579:53297373a894 | 21 | /** |
| mbed_official | 579:53297373a894 | 22 | * \internal |
| mbed_official | 579:53297373a894 | 23 | * \brief DPLL-specific data container. |
| mbed_official | 579:53297373a894 | 24 | */ |
| mbed_official | 579:53297373a894 | 25 | struct _system_clock_dpll_config { |
| mbed_official | 579:53297373a894 | 26 | uint32_t frequency; |
| mbed_official | 579:53297373a894 | 27 | }; |
| mbed_official | 579:53297373a894 | 28 | |
| mbed_official | 579:53297373a894 | 29 | |
| mbed_official | 579:53297373a894 | 30 | /** |
| mbed_official | 579:53297373a894 | 31 | * \internal |
| mbed_official | 579:53297373a894 | 32 | * \brief XOSC-specific data container. |
| mbed_official | 579:53297373a894 | 33 | */ |
| mbed_official | 579:53297373a894 | 34 | struct _system_clock_xosc_config { |
| mbed_official | 579:53297373a894 | 35 | uint32_t frequency; |
| mbed_official | 579:53297373a894 | 36 | }; |
| mbed_official | 579:53297373a894 | 37 | |
| mbed_official | 579:53297373a894 | 38 | /** |
| mbed_official | 579:53297373a894 | 39 | * \internal |
| mbed_official | 579:53297373a894 | 40 | * \brief System clock module data container. |
| mbed_official | 579:53297373a894 | 41 | */ |
| mbed_official | 579:53297373a894 | 42 | struct _system_clock_module { |
| mbed_official | 579:53297373a894 | 43 | volatile struct _system_clock_dfll_config dfll; |
| mbed_official | 579:53297373a894 | 44 | |
| mbed_official | 579:53297373a894 | 45 | #ifdef FEATURE_SYSTEM_CLOCK_DPLL |
| mbed_official | 579:53297373a894 | 46 | volatile struct _system_clock_dpll_config dpll; |
| mbed_official | 579:53297373a894 | 47 | #endif |
| mbed_official | 579:53297373a894 | 48 | |
| mbed_official | 579:53297373a894 | 49 | volatile struct _system_clock_xosc_config xosc; |
| mbed_official | 579:53297373a894 | 50 | volatile struct _system_clock_xosc_config xosc32k; |
| mbed_official | 579:53297373a894 | 51 | }; |
| mbed_official | 579:53297373a894 | 52 | |
| mbed_official | 579:53297373a894 | 53 | /** |
| mbed_official | 579:53297373a894 | 54 | * \internal |
| mbed_official | 579:53297373a894 | 55 | * \brief Internal module instance to cache configuration values. |
| mbed_official | 579:53297373a894 | 56 | */ |
| mbed_official | 579:53297373a894 | 57 | static struct _system_clock_module _system_clock_inst = { |
| mbed_official | 579:53297373a894 | 58 | .dfll = { |
| mbed_official | 579:53297373a894 | 59 | .control = 0, |
| mbed_official | 579:53297373a894 | 60 | .val = 0, |
| mbed_official | 579:53297373a894 | 61 | .mul = 0, |
| mbed_official | 579:53297373a894 | 62 | }, |
| mbed_official | 579:53297373a894 | 63 | |
| mbed_official | 579:53297373a894 | 64 | #ifdef FEATURE_SYSTEM_CLOCK_DPLL |
| mbed_official | 579:53297373a894 | 65 | .dpll = { |
| mbed_official | 579:53297373a894 | 66 | .frequency = 0, |
| mbed_official | 579:53297373a894 | 67 | }, |
| mbed_official | 579:53297373a894 | 68 | #endif |
| mbed_official | 579:53297373a894 | 69 | .xosc = { |
| mbed_official | 579:53297373a894 | 70 | .frequency = 0, |
| mbed_official | 579:53297373a894 | 71 | }, |
| mbed_official | 579:53297373a894 | 72 | .xosc32k = { |
| mbed_official | 579:53297373a894 | 73 | .frequency = 0, |
| mbed_official | 579:53297373a894 | 74 | }, |
| mbed_official | 579:53297373a894 | 75 | }; |
| mbed_official | 579:53297373a894 | 76 | |
| mbed_official | 579:53297373a894 | 77 | /** |
| mbed_official | 579:53297373a894 | 78 | * \internal |
| mbed_official | 579:53297373a894 | 79 | * \brief Wait for sync to the DFLL control registers. |
| mbed_official | 579:53297373a894 | 80 | */ |
| mbed_official | 579:53297373a894 | 81 | static inline void _system_dfll_wait_for_sync(void) |
| mbed_official | 579:53297373a894 | 82 | { |
| mbed_official | 579:53297373a894 | 83 | while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY)) { |
| mbed_official | 579:53297373a894 | 84 | /* Wait for DFLL sync */ |
| mbed_official | 579:53297373a894 | 85 | } |
| mbed_official | 579:53297373a894 | 86 | } |
| mbed_official | 579:53297373a894 | 87 | |
| mbed_official | 579:53297373a894 | 88 | /** |
| mbed_official | 579:53297373a894 | 89 | * \internal |
| mbed_official | 579:53297373a894 | 90 | * \brief Wait for sync to the OSC32K control registers. |
| mbed_official | 579:53297373a894 | 91 | */ |
| mbed_official | 579:53297373a894 | 92 | static inline void _system_osc32k_wait_for_sync(void) |
| mbed_official | 579:53297373a894 | 93 | { |
| mbed_official | 579:53297373a894 | 94 | while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_OSC32KRDY)) { |
| mbed_official | 579:53297373a894 | 95 | /* Wait for OSC32K sync */ |
| mbed_official | 579:53297373a894 | 96 | } |
| mbed_official | 579:53297373a894 | 97 | } |
| mbed_official | 579:53297373a894 | 98 | |
| mbed_official | 579:53297373a894 | 99 | static inline void _system_clock_source_dfll_set_config_errata_9905(void) |
| mbed_official | 579:53297373a894 | 100 | { |
| mbed_official | 579:53297373a894 | 101 | |
| mbed_official | 579:53297373a894 | 102 | /* Disable ONDEMAND mode while writing configurations */ |
| mbed_official | 579:53297373a894 | 103 | SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control & ~SYSCTRL_DFLLCTRL_ONDEMAND; |
| mbed_official | 579:53297373a894 | 104 | _system_dfll_wait_for_sync(); |
| mbed_official | 579:53297373a894 | 105 | |
| mbed_official | 579:53297373a894 | 106 | SYSCTRL->DFLLMUL.reg = _system_clock_inst.dfll.mul; |
| mbed_official | 579:53297373a894 | 107 | SYSCTRL->DFLLVAL.reg = _system_clock_inst.dfll.val; |
| mbed_official | 579:53297373a894 | 108 | |
| mbed_official | 579:53297373a894 | 109 | /* Write full configuration to DFLL control register */ |
| mbed_official | 579:53297373a894 | 110 | SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control; |
| mbed_official | 579:53297373a894 | 111 | } |
| mbed_official | 579:53297373a894 | 112 | |
| mbed_official | 579:53297373a894 | 113 | /** |
| mbed_official | 579:53297373a894 | 114 | * \brief Retrieve the frequency of a clock source. |
| mbed_official | 579:53297373a894 | 115 | * |
| mbed_official | 579:53297373a894 | 116 | * Determines the current operating frequency of a given clock source. |
| mbed_official | 579:53297373a894 | 117 | * |
| mbed_official | 579:53297373a894 | 118 | * \param[in] clock_source Clock source to get the frequency |
| mbed_official | 579:53297373a894 | 119 | * |
| mbed_official | 579:53297373a894 | 120 | * \returns Frequency of the given clock source, in Hz. |
| mbed_official | 579:53297373a894 | 121 | */ |
| mbed_official | 579:53297373a894 | 122 | uint32_t system_clock_source_get_hz( |
| mbed_official | 579:53297373a894 | 123 | const enum system_clock_source clock_source) |
| mbed_official | 579:53297373a894 | 124 | { |
| mbed_official | 579:53297373a894 | 125 | switch (clock_source) { |
| mbed_official | 579:53297373a894 | 126 | case SYSTEM_CLOCK_SOURCE_XOSC: |
| mbed_official | 579:53297373a894 | 127 | return _system_clock_inst.xosc.frequency; |
| mbed_official | 579:53297373a894 | 128 | |
| mbed_official | 579:53297373a894 | 129 | case SYSTEM_CLOCK_SOURCE_OSC8M: |
| mbed_official | 579:53297373a894 | 130 | return 8000000UL >> SYSCTRL->OSC8M.bit.PRESC; |
| mbed_official | 579:53297373a894 | 131 | |
| mbed_official | 579:53297373a894 | 132 | case SYSTEM_CLOCK_SOURCE_OSC32K: |
| mbed_official | 579:53297373a894 | 133 | return 32768UL; |
| mbed_official | 579:53297373a894 | 134 | |
| mbed_official | 579:53297373a894 | 135 | case SYSTEM_CLOCK_SOURCE_ULP32K: |
| mbed_official | 579:53297373a894 | 136 | return 32768UL; |
| mbed_official | 579:53297373a894 | 137 | |
| mbed_official | 579:53297373a894 | 138 | case SYSTEM_CLOCK_SOURCE_XOSC32K: |
| mbed_official | 579:53297373a894 | 139 | return _system_clock_inst.xosc32k.frequency; |
| mbed_official | 579:53297373a894 | 140 | |
| mbed_official | 579:53297373a894 | 141 | case SYSTEM_CLOCK_SOURCE_DFLL: |
| mbed_official | 579:53297373a894 | 142 | |
| mbed_official | 579:53297373a894 | 143 | /* Check if the DFLL has been configured */ |
| mbed_official | 579:53297373a894 | 144 | if (!(_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_ENABLE)) |
| mbed_official | 579:53297373a894 | 145 | return 0; |
| mbed_official | 579:53297373a894 | 146 | |
| mbed_official | 579:53297373a894 | 147 | /* Make sure that the DFLL module is ready */ |
| mbed_official | 579:53297373a894 | 148 | _system_dfll_wait_for_sync(); |
| mbed_official | 579:53297373a894 | 149 | |
| mbed_official | 579:53297373a894 | 150 | /* Check if operating in closed loop mode */ |
| mbed_official | 579:53297373a894 | 151 | if (_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_MODE) { |
| mbed_official | 579:53297373a894 | 152 | return system_gclk_chan_get_hz(SYSCTRL_GCLK_ID_DFLL48) * |
| mbed_official | 579:53297373a894 | 153 | (_system_clock_inst.dfll.mul & 0xffff); |
| mbed_official | 579:53297373a894 | 154 | } |
| mbed_official | 579:53297373a894 | 155 | |
| mbed_official | 579:53297373a894 | 156 | return 48000000UL; |
| mbed_official | 579:53297373a894 | 157 | |
| mbed_official | 579:53297373a894 | 158 | #ifdef FEATURE_SYSTEM_CLOCK_DPLL |
| mbed_official | 579:53297373a894 | 159 | case SYSTEM_CLOCK_SOURCE_DPLL: |
| mbed_official | 579:53297373a894 | 160 | if (!(SYSCTRL->DPLLSTATUS.reg & SYSCTRL_DPLLSTATUS_ENABLE)) { |
| mbed_official | 579:53297373a894 | 161 | return 0; |
| mbed_official | 579:53297373a894 | 162 | } |
| mbed_official | 579:53297373a894 | 163 | |
| mbed_official | 579:53297373a894 | 164 | return _system_clock_inst.dpll.frequency; |
| mbed_official | 579:53297373a894 | 165 | #endif |
| mbed_official | 579:53297373a894 | 166 | |
| mbed_official | 579:53297373a894 | 167 | default: |
| mbed_official | 579:53297373a894 | 168 | return 0; |
| mbed_official | 579:53297373a894 | 169 | } |
| mbed_official | 579:53297373a894 | 170 | } |
| mbed_official | 579:53297373a894 | 171 | |
| mbed_official | 579:53297373a894 | 172 | /** |
| mbed_official | 579:53297373a894 | 173 | * \brief Configure the internal OSC8M oscillator clock source. |
| mbed_official | 579:53297373a894 | 174 | * |
| mbed_official | 579:53297373a894 | 175 | * Configures the 8MHz (nominal) internal RC oscillator with the given |
| mbed_official | 579:53297373a894 | 176 | * configuration settings. |
| mbed_official | 579:53297373a894 | 177 | * |
| mbed_official | 579:53297373a894 | 178 | * \param[in] config OSC8M configuration structure containing the new config |
| mbed_official | 579:53297373a894 | 179 | */ |
| mbed_official | 579:53297373a894 | 180 | void system_clock_source_osc8m_set_config( |
| mbed_official | 579:53297373a894 | 181 | struct system_clock_source_osc8m_config *const config) |
| mbed_official | 579:53297373a894 | 182 | { |
| mbed_official | 579:53297373a894 | 183 | SYSCTRL_OSC8M_Type temp = SYSCTRL->OSC8M; |
| mbed_official | 579:53297373a894 | 184 | |
| mbed_official | 579:53297373a894 | 185 | /* Use temporary struct to reduce register access */ |
| mbed_official | 579:53297373a894 | 186 | temp.bit.PRESC = config->prescaler; |
| mbed_official | 579:53297373a894 | 187 | temp.bit.ONDEMAND = config->on_demand; |
| mbed_official | 579:53297373a894 | 188 | temp.bit.RUNSTDBY = config->run_in_standby; |
| mbed_official | 579:53297373a894 | 189 | |
| mbed_official | 579:53297373a894 | 190 | SYSCTRL->OSC8M = temp; |
| mbed_official | 579:53297373a894 | 191 | } |
| mbed_official | 579:53297373a894 | 192 | |
| mbed_official | 579:53297373a894 | 193 | /** |
| mbed_official | 579:53297373a894 | 194 | * \brief Configure the internal OSC32K oscillator clock source. |
| mbed_official | 579:53297373a894 | 195 | * |
| mbed_official | 579:53297373a894 | 196 | * Configures the 32KHz (nominal) internal RC oscillator with the given |
| mbed_official | 579:53297373a894 | 197 | * configuration settings. |
| mbed_official | 579:53297373a894 | 198 | * |
| mbed_official | 579:53297373a894 | 199 | * \param[in] config OSC32K configuration structure containing the new config |
| mbed_official | 579:53297373a894 | 200 | */ |
| mbed_official | 579:53297373a894 | 201 | void system_clock_source_osc32k_set_config( |
| mbed_official | 579:53297373a894 | 202 | struct system_clock_source_osc32k_config *const config) |
| mbed_official | 579:53297373a894 | 203 | { |
| mbed_official | 579:53297373a894 | 204 | SYSCTRL_OSC32K_Type temp = SYSCTRL->OSC32K; |
| mbed_official | 579:53297373a894 | 205 | |
| mbed_official | 579:53297373a894 | 206 | /* Update settings via a temporary struct to reduce register access */ |
| mbed_official | 579:53297373a894 | 207 | temp.bit.EN1K = config->enable_1khz_output; |
| mbed_official | 579:53297373a894 | 208 | temp.bit.EN32K = config->enable_32khz_output; |
| mbed_official | 579:53297373a894 | 209 | temp.bit.STARTUP = config->startup_time; |
| mbed_official | 579:53297373a894 | 210 | temp.bit.ONDEMAND = config->on_demand; |
| mbed_official | 579:53297373a894 | 211 | temp.bit.RUNSTDBY = config->run_in_standby; |
| mbed_official | 579:53297373a894 | 212 | temp.bit.WRTLOCK = config->write_once; |
| mbed_official | 579:53297373a894 | 213 | |
| mbed_official | 579:53297373a894 | 214 | SYSCTRL->OSC32K = temp; |
| mbed_official | 579:53297373a894 | 215 | } |
| mbed_official | 579:53297373a894 | 216 | |
| mbed_official | 579:53297373a894 | 217 | /** |
| mbed_official | 579:53297373a894 | 218 | * \brief Configure the external oscillator clock source. |
| mbed_official | 579:53297373a894 | 219 | * |
| mbed_official | 579:53297373a894 | 220 | * Configures the external oscillator clock source with the given configuration |
| mbed_official | 579:53297373a894 | 221 | * settings. |
| mbed_official | 579:53297373a894 | 222 | * |
| mbed_official | 579:53297373a894 | 223 | * \param[in] config External oscillator configuration structure containing |
| mbed_official | 579:53297373a894 | 224 | * the new config |
| mbed_official | 579:53297373a894 | 225 | */ |
| mbed_official | 579:53297373a894 | 226 | void system_clock_source_xosc_set_config( |
| mbed_official | 579:53297373a894 | 227 | struct system_clock_source_xosc_config *const config) |
| mbed_official | 579:53297373a894 | 228 | { |
| mbed_official | 579:53297373a894 | 229 | SYSCTRL_XOSC_Type temp = SYSCTRL->XOSC; |
| mbed_official | 579:53297373a894 | 230 | |
| mbed_official | 579:53297373a894 | 231 | temp.bit.STARTUP = config->startup_time; |
| mbed_official | 579:53297373a894 | 232 | |
| mbed_official | 579:53297373a894 | 233 | if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) { |
| mbed_official | 579:53297373a894 | 234 | temp.bit.XTALEN = 1; |
| mbed_official | 579:53297373a894 | 235 | } else { |
| mbed_official | 579:53297373a894 | 236 | temp.bit.XTALEN = 0; |
| mbed_official | 579:53297373a894 | 237 | } |
| mbed_official | 579:53297373a894 | 238 | |
| mbed_official | 579:53297373a894 | 239 | temp.bit.AMPGC = config->auto_gain_control; |
| mbed_official | 579:53297373a894 | 240 | |
| mbed_official | 579:53297373a894 | 241 | /* Set gain if automatic gain control is not selected */ |
| mbed_official | 579:53297373a894 | 242 | if (!config->auto_gain_control) { |
| mbed_official | 579:53297373a894 | 243 | if (config->frequency <= 2000000) { |
| mbed_official | 579:53297373a894 | 244 | temp.bit.GAIN = 0; |
| mbed_official | 579:53297373a894 | 245 | } else if (config->frequency <= 4000000) { |
| mbed_official | 579:53297373a894 | 246 | temp.bit.GAIN = 1; |
| mbed_official | 579:53297373a894 | 247 | } else if (config->frequency <= 8000000) { |
| mbed_official | 579:53297373a894 | 248 | temp.bit.GAIN = 2; |
| mbed_official | 579:53297373a894 | 249 | } else if (config->frequency <= 16000000) { |
| mbed_official | 579:53297373a894 | 250 | temp.bit.GAIN = 3; |
| mbed_official | 579:53297373a894 | 251 | } else if (config->frequency <= 30000000) { |
| mbed_official | 579:53297373a894 | 252 | temp.bit.GAIN = 4; |
| mbed_official | 579:53297373a894 | 253 | } |
| mbed_official | 579:53297373a894 | 254 | |
| mbed_official | 579:53297373a894 | 255 | } |
| mbed_official | 579:53297373a894 | 256 | |
| mbed_official | 579:53297373a894 | 257 | temp.bit.ONDEMAND = config->on_demand; |
| mbed_official | 579:53297373a894 | 258 | temp.bit.RUNSTDBY = config->run_in_standby; |
| mbed_official | 579:53297373a894 | 259 | |
| mbed_official | 579:53297373a894 | 260 | /* Store XOSC frequency for internal use */ |
| mbed_official | 579:53297373a894 | 261 | _system_clock_inst.xosc.frequency = config->frequency; |
| mbed_official | 579:53297373a894 | 262 | |
| mbed_official | 579:53297373a894 | 263 | SYSCTRL->XOSC = temp; |
| mbed_official | 579:53297373a894 | 264 | } |
| mbed_official | 579:53297373a894 | 265 | |
| mbed_official | 579:53297373a894 | 266 | /** |
| mbed_official | 579:53297373a894 | 267 | * \brief Configure the XOSC32K external 32KHz oscillator clock source. |
| mbed_official | 579:53297373a894 | 268 | * |
| mbed_official | 579:53297373a894 | 269 | * Configures the external 32KHz oscillator clock source with the given |
| mbed_official | 579:53297373a894 | 270 | * configuration settings. |
| mbed_official | 579:53297373a894 | 271 | * |
| mbed_official | 579:53297373a894 | 272 | * \param[in] config XOSC32K configuration structure containing the new config |
| mbed_official | 579:53297373a894 | 273 | */ |
| mbed_official | 579:53297373a894 | 274 | void system_clock_source_xosc32k_set_config( |
| mbed_official | 579:53297373a894 | 275 | struct system_clock_source_xosc32k_config *const config) |
| mbed_official | 579:53297373a894 | 276 | { |
| mbed_official | 579:53297373a894 | 277 | SYSCTRL_XOSC32K_Type temp = SYSCTRL->XOSC32K; |
| mbed_official | 579:53297373a894 | 278 | |
| mbed_official | 579:53297373a894 | 279 | temp.bit.STARTUP = config->startup_time; |
| mbed_official | 579:53297373a894 | 280 | |
| mbed_official | 579:53297373a894 | 281 | if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) { |
| mbed_official | 579:53297373a894 | 282 | temp.bit.XTALEN = 1; |
| mbed_official | 579:53297373a894 | 283 | } else { |
| mbed_official | 579:53297373a894 | 284 | temp.bit.XTALEN = 0; |
| mbed_official | 579:53297373a894 | 285 | } |
| mbed_official | 579:53297373a894 | 286 | |
| mbed_official | 579:53297373a894 | 287 | temp.bit.AAMPEN = config->auto_gain_control; |
| mbed_official | 579:53297373a894 | 288 | temp.bit.EN1K = config->enable_1khz_output; |
| mbed_official | 579:53297373a894 | 289 | temp.bit.EN32K = config->enable_32khz_output; |
| mbed_official | 579:53297373a894 | 290 | |
| mbed_official | 579:53297373a894 | 291 | temp.bit.ONDEMAND = config->on_demand; |
| mbed_official | 579:53297373a894 | 292 | temp.bit.RUNSTDBY = config->run_in_standby; |
| mbed_official | 579:53297373a894 | 293 | temp.bit.WRTLOCK = config->write_once; |
| mbed_official | 579:53297373a894 | 294 | |
| mbed_official | 579:53297373a894 | 295 | /* Cache the new frequency in case the user needs to check the current |
| mbed_official | 579:53297373a894 | 296 | * operating frequency later */ |
| mbed_official | 579:53297373a894 | 297 | _system_clock_inst.xosc32k.frequency = config->frequency; |
| mbed_official | 579:53297373a894 | 298 | |
| mbed_official | 579:53297373a894 | 299 | SYSCTRL->XOSC32K = temp; |
| mbed_official | 579:53297373a894 | 300 | } |
| mbed_official | 579:53297373a894 | 301 | |
| mbed_official | 579:53297373a894 | 302 | /** |
| mbed_official | 579:53297373a894 | 303 | * \brief Configure the DFLL clock source. |
| mbed_official | 579:53297373a894 | 304 | * |
| mbed_official | 579:53297373a894 | 305 | * Configures the Digital Frequency Locked Loop clock source with the given |
| mbed_official | 579:53297373a894 | 306 | * configuration settings. |
| mbed_official | 579:53297373a894 | 307 | * |
| mbed_official | 579:53297373a894 | 308 | * \note The DFLL will be running when this function returns, as the DFLL module |
| mbed_official | 579:53297373a894 | 309 | * needs to be enabled in order to perform the module configuration. |
| mbed_official | 579:53297373a894 | 310 | * |
| mbed_official | 579:53297373a894 | 311 | * \param[in] config DFLL configuration structure containing the new config |
| mbed_official | 579:53297373a894 | 312 | */ |
| mbed_official | 579:53297373a894 | 313 | void system_clock_source_dfll_set_config( |
| mbed_official | 579:53297373a894 | 314 | struct system_clock_source_dfll_config *const config) |
| mbed_official | 579:53297373a894 | 315 | { |
| mbed_official | 579:53297373a894 | 316 | _system_clock_inst.dfll.val = |
| mbed_official | 579:53297373a894 | 317 | SYSCTRL_DFLLVAL_COARSE(config->coarse_value) | |
| mbed_official | 579:53297373a894 | 318 | SYSCTRL_DFLLVAL_FINE(config->fine_value); |
| mbed_official | 579:53297373a894 | 319 | |
| mbed_official | 579:53297373a894 | 320 | _system_clock_inst.dfll.control = |
| mbed_official | 579:53297373a894 | 321 | (uint32_t)config->wakeup_lock | |
| mbed_official | 579:53297373a894 | 322 | (uint32_t)config->stable_tracking | |
| mbed_official | 579:53297373a894 | 323 | (uint32_t)config->quick_lock | |
| mbed_official | 579:53297373a894 | 324 | (uint32_t)config->chill_cycle | |
| mbed_official | 579:53297373a894 | 325 | ((uint32_t)config->on_demand << SYSCTRL_DFLLCTRL_ONDEMAND_Pos); |
| mbed_official | 579:53297373a894 | 326 | |
| mbed_official | 579:53297373a894 | 327 | if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { |
| mbed_official | 579:53297373a894 | 328 | |
| mbed_official | 579:53297373a894 | 329 | _system_clock_inst.dfll.mul = |
| mbed_official | 579:53297373a894 | 330 | SYSCTRL_DFLLMUL_CSTEP(config->coarse_max_step) | |
| mbed_official | 579:53297373a894 | 331 | SYSCTRL_DFLLMUL_FSTEP(config->fine_max_step) | |
| mbed_official | 579:53297373a894 | 332 | SYSCTRL_DFLLMUL_MUL(config->multiply_factor); |
| mbed_official | 579:53297373a894 | 333 | |
| mbed_official | 579:53297373a894 | 334 | /* Enable the closed loop mode */ |
| mbed_official | 579:53297373a894 | 335 | _system_clock_inst.dfll.control |= config->loop_mode; |
| mbed_official | 579:53297373a894 | 336 | } |
| mbed_official | 579:53297373a894 | 337 | if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY) { |
| mbed_official | 579:53297373a894 | 338 | |
| mbed_official | 579:53297373a894 | 339 | _system_clock_inst.dfll.mul = |
| mbed_official | 579:53297373a894 | 340 | SYSCTRL_DFLLMUL_MUL(config->multiply_factor); |
| mbed_official | 579:53297373a894 | 341 | |
| mbed_official | 579:53297373a894 | 342 | /* Enable the USB recovery mode */ |
| mbed_official | 579:53297373a894 | 343 | _system_clock_inst.dfll.control |= config->loop_mode | |
| mbed_official | 579:53297373a894 | 344 | SYSCTRL_DFLLCTRL_BPLCKC; |
| mbed_official | 579:53297373a894 | 345 | } |
| mbed_official | 579:53297373a894 | 346 | } |
| mbed_official | 579:53297373a894 | 347 | |
| mbed_official | 579:53297373a894 | 348 | #ifdef FEATURE_SYSTEM_CLOCK_DPLL |
| mbed_official | 579:53297373a894 | 349 | /** |
| mbed_official | 579:53297373a894 | 350 | * \brief Configure the DPLL clock source. |
| mbed_official | 579:53297373a894 | 351 | * |
| mbed_official | 579:53297373a894 | 352 | * Configures the Digital Phase-Locked Loop clock source with the given |
| mbed_official | 579:53297373a894 | 353 | * configuration settings. |
| mbed_official | 579:53297373a894 | 354 | * |
| mbed_official | 579:53297373a894 | 355 | * \note The DPLL will be running when this function returns, as the DPLL module |
| mbed_official | 579:53297373a894 | 356 | * needs to be enabled in order to perform the module configuration. |
| mbed_official | 579:53297373a894 | 357 | * |
| mbed_official | 579:53297373a894 | 358 | * \param[in] config DPLL configuration structure containing the new config |
| mbed_official | 579:53297373a894 | 359 | */ |
| mbed_official | 579:53297373a894 | 360 | void system_clock_source_dpll_set_config( |
| mbed_official | 579:53297373a894 | 361 | struct system_clock_source_dpll_config *const config) |
| mbed_official | 579:53297373a894 | 362 | { |
| mbed_official | 579:53297373a894 | 363 | |
| mbed_official | 579:53297373a894 | 364 | uint32_t tmpldr; |
| mbed_official | 579:53297373a894 | 365 | uint8_t tmpldrfrac; |
| mbed_official | 579:53297373a894 | 366 | uint32_t refclk; |
| mbed_official | 579:53297373a894 | 367 | |
| mbed_official | 579:53297373a894 | 368 | refclk = config->reference_frequency; |
| mbed_official | 579:53297373a894 | 369 | |
| mbed_official | 579:53297373a894 | 370 | /* Only reference clock REF1 can be divided */ |
| mbed_official | 579:53297373a894 | 371 | if (config->reference_clock == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_REF1) { |
| mbed_official | 579:53297373a894 | 372 | refclk = refclk / config->reference_divider; |
| mbed_official | 579:53297373a894 | 373 | } |
| mbed_official | 579:53297373a894 | 374 | |
| mbed_official | 579:53297373a894 | 375 | /* Calculate LDRFRAC and LDR */ |
| mbed_official | 579:53297373a894 | 376 | tmpldr = (config->output_frequency << 4) / refclk; |
| mbed_official | 579:53297373a894 | 377 | tmpldrfrac = tmpldr & 0x0f; |
| mbed_official | 579:53297373a894 | 378 | tmpldr = (tmpldr >> 4) - 1; |
| mbed_official | 579:53297373a894 | 379 | |
| mbed_official | 579:53297373a894 | 380 | SYSCTRL->DPLLCTRLA.reg = |
| mbed_official | 579:53297373a894 | 381 | ((uint32_t)config->on_demand << SYSCTRL_DPLLCTRLA_ONDEMAND_Pos) | |
| mbed_official | 579:53297373a894 | 382 | ((uint32_t)config->run_in_standby << SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos); |
| mbed_official | 579:53297373a894 | 383 | |
| mbed_official | 579:53297373a894 | 384 | SYSCTRL->DPLLRATIO.reg = |
| mbed_official | 579:53297373a894 | 385 | SYSCTRL_DPLLRATIO_LDRFRAC(tmpldrfrac) | |
| mbed_official | 579:53297373a894 | 386 | SYSCTRL_DPLLRATIO_LDR(tmpldr); |
| mbed_official | 579:53297373a894 | 387 | |
| mbed_official | 579:53297373a894 | 388 | SYSCTRL->DPLLCTRLB.reg = |
| mbed_official | 579:53297373a894 | 389 | SYSCTRL_DPLLCTRLB_DIV(config->reference_divider) | |
| mbed_official | 579:53297373a894 | 390 | ((uint32_t)config->lock_bypass << SYSCTRL_DPLLCTRLB_LBYPASS_Pos) | |
| mbed_official | 579:53297373a894 | 391 | SYSCTRL_DPLLCTRLB_LTIME(config->lock_time) | |
| mbed_official | 579:53297373a894 | 392 | SYSCTRL_DPLLCTRLB_REFCLK(config->reference_clock) | |
| mbed_official | 579:53297373a894 | 393 | ((uint32_t)config->wake_up_fast << SYSCTRL_DPLLCTRLB_WUF_Pos) | |
| mbed_official | 579:53297373a894 | 394 | ((uint32_t)config->low_power_enable << SYSCTRL_DPLLCTRLB_LPEN_Pos) | |
| mbed_official | 579:53297373a894 | 395 | SYSCTRL_DPLLCTRLB_FILTER(config->filter); |
| mbed_official | 579:53297373a894 | 396 | |
| mbed_official | 579:53297373a894 | 397 | /* |
| mbed_official | 579:53297373a894 | 398 | * Fck = Fckrx * (LDR + 1 + LDRFRAC / 16) |
| mbed_official | 579:53297373a894 | 399 | */ |
| mbed_official | 579:53297373a894 | 400 | _system_clock_inst.dpll.frequency = |
| mbed_official | 579:53297373a894 | 401 | (config->reference_frequency * |
| mbed_official | 579:53297373a894 | 402 | (((tmpldr + 1) << 4) + tmpldrfrac) |
| mbed_official | 579:53297373a894 | 403 | ) >> 4; |
| mbed_official | 579:53297373a894 | 404 | } |
| mbed_official | 579:53297373a894 | 405 | #endif |
| mbed_official | 579:53297373a894 | 406 | |
| mbed_official | 579:53297373a894 | 407 | /** |
| mbed_official | 579:53297373a894 | 408 | * \brief Writes the calibration values for a given oscillator clock source. |
| mbed_official | 579:53297373a894 | 409 | * |
| mbed_official | 579:53297373a894 | 410 | * Writes an oscillator calibration value to the given oscillator control |
| mbed_official | 579:53297373a894 | 411 | * registers. The acceptable ranges are: |
| mbed_official | 579:53297373a894 | 412 | * |
| mbed_official | 579:53297373a894 | 413 | * For OSC32K: |
| mbed_official | 579:53297373a894 | 414 | * - 7 bits (max value 128) |
| mbed_official | 579:53297373a894 | 415 | * For OSC8MHZ: |
| mbed_official | 579:53297373a894 | 416 | * - 8 bits (Max value 255) |
| mbed_official | 579:53297373a894 | 417 | * For OSCULP: |
| mbed_official | 579:53297373a894 | 418 | * - 5 bits (Max value 32) |
| mbed_official | 579:53297373a894 | 419 | * |
| mbed_official | 579:53297373a894 | 420 | * \note The frequency range parameter applies only when configuring the 8MHz |
| mbed_official | 579:53297373a894 | 421 | * oscillator and will be ignored for the other oscillators. |
| mbed_official | 579:53297373a894 | 422 | * |
| mbed_official | 579:53297373a894 | 423 | * \param[in] clock_source Clock source to calibrate |
| mbed_official | 579:53297373a894 | 424 | * \param[in] calibration_value Calibration value to write |
| mbed_official | 579:53297373a894 | 425 | * \param[in] freq_range Frequency range (8MHz oscillator only) |
| mbed_official | 579:53297373a894 | 426 | * |
| mbed_official | 579:53297373a894 | 427 | * \retval STATUS_OK The calibration value was written |
| mbed_official | 579:53297373a894 | 428 | * successfully. |
| mbed_official | 579:53297373a894 | 429 | * \retval STATUS_ERR_INVALID_ARG The setting is not valid for selected clock |
| mbed_official | 579:53297373a894 | 430 | * source. |
| mbed_official | 579:53297373a894 | 431 | */ |
| mbed_official | 579:53297373a894 | 432 | enum status_code system_clock_source_write_calibration( |
| mbed_official | 579:53297373a894 | 433 | const enum system_clock_source clock_source, |
| mbed_official | 579:53297373a894 | 434 | const uint16_t calibration_value, |
| mbed_official | 579:53297373a894 | 435 | const uint8_t freq_range) |
| mbed_official | 579:53297373a894 | 436 | { |
| mbed_official | 579:53297373a894 | 437 | switch (clock_source) { |
| mbed_official | 579:53297373a894 | 438 | case SYSTEM_CLOCK_SOURCE_OSC8M: |
| mbed_official | 579:53297373a894 | 439 | |
| mbed_official | 579:53297373a894 | 440 | if (calibration_value > 0xfff || freq_range > 4) { |
| mbed_official | 579:53297373a894 | 441 | return STATUS_ERR_INVALID_ARG; |
| mbed_official | 579:53297373a894 | 442 | } |
| mbed_official | 579:53297373a894 | 443 | |
| mbed_official | 579:53297373a894 | 444 | SYSCTRL->OSC8M.bit.CALIB = calibration_value; |
| mbed_official | 579:53297373a894 | 445 | SYSCTRL->OSC8M.bit.FRANGE = freq_range; |
| mbed_official | 579:53297373a894 | 446 | break; |
| mbed_official | 579:53297373a894 | 447 | |
| mbed_official | 579:53297373a894 | 448 | case SYSTEM_CLOCK_SOURCE_OSC32K: |
| mbed_official | 579:53297373a894 | 449 | |
| mbed_official | 579:53297373a894 | 450 | if (calibration_value > 128) { |
| mbed_official | 579:53297373a894 | 451 | return STATUS_ERR_INVALID_ARG; |
| mbed_official | 579:53297373a894 | 452 | } |
| mbed_official | 579:53297373a894 | 453 | |
| mbed_official | 579:53297373a894 | 454 | _system_osc32k_wait_for_sync(); |
| mbed_official | 579:53297373a894 | 455 | SYSCTRL->OSC32K.bit.CALIB = calibration_value; |
| mbed_official | 579:53297373a894 | 456 | break; |
| mbed_official | 579:53297373a894 | 457 | |
| mbed_official | 579:53297373a894 | 458 | case SYSTEM_CLOCK_SOURCE_ULP32K: |
| mbed_official | 579:53297373a894 | 459 | |
| mbed_official | 579:53297373a894 | 460 | if (calibration_value > 32) { |
| mbed_official | 579:53297373a894 | 461 | return STATUS_ERR_INVALID_ARG; |
| mbed_official | 579:53297373a894 | 462 | } |
| mbed_official | 579:53297373a894 | 463 | |
| mbed_official | 579:53297373a894 | 464 | SYSCTRL->OSCULP32K.bit.CALIB = calibration_value; |
| mbed_official | 579:53297373a894 | 465 | break; |
| mbed_official | 579:53297373a894 | 466 | |
| mbed_official | 579:53297373a894 | 467 | default: |
| mbed_official | 579:53297373a894 | 468 | Assert(false); |
| mbed_official | 579:53297373a894 | 469 | return STATUS_ERR_INVALID_ARG; |
| mbed_official | 579:53297373a894 | 470 | break; |
| mbed_official | 579:53297373a894 | 471 | } |
| mbed_official | 579:53297373a894 | 472 | |
| mbed_official | 579:53297373a894 | 473 | return STATUS_OK; |
| mbed_official | 579:53297373a894 | 474 | } |
| mbed_official | 579:53297373a894 | 475 | |
| mbed_official | 579:53297373a894 | 476 | /** |
| mbed_official | 579:53297373a894 | 477 | * \brief Enables a clock source. |
| mbed_official | 579:53297373a894 | 478 | * |
| mbed_official | 579:53297373a894 | 479 | * Enables a clock source which has been previously configured. |
| mbed_official | 579:53297373a894 | 480 | * |
| mbed_official | 579:53297373a894 | 481 | * \param[in] clock_source Clock source to enable |
| mbed_official | 579:53297373a894 | 482 | * |
| mbed_official | 579:53297373a894 | 483 | * \retval STATUS_OK Clock source was enabled successfully and |
| mbed_official | 579:53297373a894 | 484 | * is ready |
| mbed_official | 579:53297373a894 | 485 | * \retval STATUS_ERR_INVALID_ARG The clock source is not available on this |
| mbed_official | 579:53297373a894 | 486 | * device |
| mbed_official | 579:53297373a894 | 487 | */ |
| mbed_official | 579:53297373a894 | 488 | enum status_code system_clock_source_enable( |
| mbed_official | 579:53297373a894 | 489 | const enum system_clock_source clock_source) |
| mbed_official | 579:53297373a894 | 490 | { |
| mbed_official | 579:53297373a894 | 491 | switch (clock_source) { |
| mbed_official | 579:53297373a894 | 492 | case SYSTEM_CLOCK_SOURCE_OSC8M: |
| mbed_official | 579:53297373a894 | 493 | SYSCTRL->OSC8M.reg |= SYSCTRL_OSC8M_ENABLE; |
| mbed_official | 579:53297373a894 | 494 | return STATUS_OK; |
| mbed_official | 579:53297373a894 | 495 | |
| mbed_official | 579:53297373a894 | 496 | case SYSTEM_CLOCK_SOURCE_OSC32K: |
| mbed_official | 579:53297373a894 | 497 | SYSCTRL->OSC32K.reg |= SYSCTRL_OSC32K_ENABLE; |
| mbed_official | 579:53297373a894 | 498 | break; |
| mbed_official | 579:53297373a894 | 499 | |
| mbed_official | 579:53297373a894 | 500 | case SYSTEM_CLOCK_SOURCE_XOSC: |
| mbed_official | 579:53297373a894 | 501 | SYSCTRL->XOSC.reg |= SYSCTRL_XOSC_ENABLE; |
| mbed_official | 579:53297373a894 | 502 | break; |
| mbed_official | 579:53297373a894 | 503 | |
| mbed_official | 579:53297373a894 | 504 | case SYSTEM_CLOCK_SOURCE_XOSC32K: |
| mbed_official | 579:53297373a894 | 505 | SYSCTRL->XOSC32K.reg |= SYSCTRL_XOSC32K_ENABLE; |
| mbed_official | 579:53297373a894 | 506 | break; |
| mbed_official | 579:53297373a894 | 507 | |
| mbed_official | 579:53297373a894 | 508 | case SYSTEM_CLOCK_SOURCE_DFLL: |
| mbed_official | 579:53297373a894 | 509 | _system_clock_inst.dfll.control |= SYSCTRL_DFLLCTRL_ENABLE; |
| mbed_official | 579:53297373a894 | 510 | _system_clock_source_dfll_set_config_errata_9905(); |
| mbed_official | 579:53297373a894 | 511 | break; |
| mbed_official | 579:53297373a894 | 512 | |
| mbed_official | 579:53297373a894 | 513 | #ifdef FEATURE_SYSTEM_CLOCK_DPLL |
| mbed_official | 579:53297373a894 | 514 | case SYSTEM_CLOCK_SOURCE_DPLL: |
| mbed_official | 579:53297373a894 | 515 | SYSCTRL->DPLLCTRLA.reg |= SYSCTRL_DPLLCTRLA_ENABLE; |
| mbed_official | 579:53297373a894 | 516 | break; |
| mbed_official | 579:53297373a894 | 517 | #endif |
| mbed_official | 579:53297373a894 | 518 | |
| mbed_official | 579:53297373a894 | 519 | case SYSTEM_CLOCK_SOURCE_ULP32K: |
| mbed_official | 579:53297373a894 | 520 | /* Always enabled */ |
| mbed_official | 579:53297373a894 | 521 | return STATUS_OK; |
| mbed_official | 579:53297373a894 | 522 | |
| mbed_official | 579:53297373a894 | 523 | default: |
| mbed_official | 579:53297373a894 | 524 | Assert(false); |
| mbed_official | 579:53297373a894 | 525 | return STATUS_ERR_INVALID_ARG; |
| mbed_official | 579:53297373a894 | 526 | } |
| mbed_official | 579:53297373a894 | 527 | |
| mbed_official | 579:53297373a894 | 528 | return STATUS_OK; |
| mbed_official | 579:53297373a894 | 529 | } |
| mbed_official | 579:53297373a894 | 530 | |
| mbed_official | 579:53297373a894 | 531 | /** |
| mbed_official | 579:53297373a894 | 532 | * \brief Disables a clock source. |
| mbed_official | 579:53297373a894 | 533 | * |
| mbed_official | 579:53297373a894 | 534 | * Disables a clock source that was previously enabled. |
| mbed_official | 579:53297373a894 | 535 | * |
| mbed_official | 579:53297373a894 | 536 | * \param[in] clock_source Clock source to disable |
| mbed_official | 579:53297373a894 | 537 | * |
| mbed_official | 579:53297373a894 | 538 | * \retval STATUS_OK Clock source was disabled successfully |
| mbed_official | 579:53297373a894 | 539 | * \retval STATUS_ERR_INVALID_ARG An invalid or unavailable clock source was |
| mbed_official | 579:53297373a894 | 540 | * given |
| mbed_official | 579:53297373a894 | 541 | */ |
| mbed_official | 579:53297373a894 | 542 | enum status_code system_clock_source_disable( |
| mbed_official | 579:53297373a894 | 543 | const enum system_clock_source clock_source) |
| mbed_official | 579:53297373a894 | 544 | { |
| mbed_official | 579:53297373a894 | 545 | switch (clock_source) { |
| mbed_official | 579:53297373a894 | 546 | case SYSTEM_CLOCK_SOURCE_OSC8M: |
| mbed_official | 579:53297373a894 | 547 | SYSCTRL->OSC8M.reg &= ~SYSCTRL_OSC8M_ENABLE; |
| mbed_official | 579:53297373a894 | 548 | break; |
| mbed_official | 579:53297373a894 | 549 | |
| mbed_official | 579:53297373a894 | 550 | case SYSTEM_CLOCK_SOURCE_OSC32K: |
| mbed_official | 579:53297373a894 | 551 | SYSCTRL->OSC32K.reg &= ~SYSCTRL_OSC32K_ENABLE; |
| mbed_official | 579:53297373a894 | 552 | break; |
| mbed_official | 579:53297373a894 | 553 | |
| mbed_official | 579:53297373a894 | 554 | case SYSTEM_CLOCK_SOURCE_XOSC: |
| mbed_official | 579:53297373a894 | 555 | SYSCTRL->XOSC.reg &= ~SYSCTRL_XOSC_ENABLE; |
| mbed_official | 579:53297373a894 | 556 | break; |
| mbed_official | 579:53297373a894 | 557 | |
| mbed_official | 579:53297373a894 | 558 | case SYSTEM_CLOCK_SOURCE_XOSC32K: |
| mbed_official | 579:53297373a894 | 559 | SYSCTRL->XOSC32K.reg &= ~SYSCTRL_XOSC32K_ENABLE; |
| mbed_official | 579:53297373a894 | 560 | break; |
| mbed_official | 579:53297373a894 | 561 | |
| mbed_official | 579:53297373a894 | 562 | case SYSTEM_CLOCK_SOURCE_DFLL: |
| mbed_official | 579:53297373a894 | 563 | _system_clock_inst.dfll.control &= ~SYSCTRL_DFLLCTRL_ENABLE; |
| mbed_official | 579:53297373a894 | 564 | SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control; |
| mbed_official | 579:53297373a894 | 565 | break; |
| mbed_official | 579:53297373a894 | 566 | |
| mbed_official | 579:53297373a894 | 567 | #ifdef FEATURE_SYSTEM_CLOCK_DPLL |
| mbed_official | 579:53297373a894 | 568 | case SYSTEM_CLOCK_SOURCE_DPLL: |
| mbed_official | 579:53297373a894 | 569 | SYSCTRL->DPLLCTRLA.reg &= ~SYSCTRL_DPLLCTRLA_ENABLE; |
| mbed_official | 579:53297373a894 | 570 | break; |
| mbed_official | 579:53297373a894 | 571 | #endif |
| mbed_official | 579:53297373a894 | 572 | |
| mbed_official | 579:53297373a894 | 573 | case SYSTEM_CLOCK_SOURCE_ULP32K: |
| mbed_official | 579:53297373a894 | 574 | /* Not possible to disable */ |
| mbed_official | 579:53297373a894 | 575 | |
| mbed_official | 579:53297373a894 | 576 | default: |
| mbed_official | 579:53297373a894 | 577 | Assert(false); |
| mbed_official | 579:53297373a894 | 578 | return STATUS_ERR_INVALID_ARG; |
| mbed_official | 579:53297373a894 | 579 | |
| mbed_official | 579:53297373a894 | 580 | } |
| mbed_official | 579:53297373a894 | 581 | |
| mbed_official | 579:53297373a894 | 582 | return STATUS_OK; |
| mbed_official | 579:53297373a894 | 583 | } |
| mbed_official | 579:53297373a894 | 584 | |
| mbed_official | 579:53297373a894 | 585 | /** |
| mbed_official | 579:53297373a894 | 586 | * \brief Checks if a clock source is ready. |
| mbed_official | 579:53297373a894 | 587 | * |
| mbed_official | 579:53297373a894 | 588 | * Checks if a given clock source is ready to be used. |
| mbed_official | 579:53297373a894 | 589 | * |
| mbed_official | 579:53297373a894 | 590 | * \param[in] clock_source Clock source to check if ready |
| mbed_official | 579:53297373a894 | 591 | * |
| mbed_official | 579:53297373a894 | 592 | * \returns Ready state of the given clock source. |
| mbed_official | 579:53297373a894 | 593 | * |
| mbed_official | 579:53297373a894 | 594 | * \retval true Clock source is enabled and ready |
| mbed_official | 579:53297373a894 | 595 | * \retval false Clock source is disabled or not yet ready |
| mbed_official | 579:53297373a894 | 596 | */ |
| mbed_official | 579:53297373a894 | 597 | bool system_clock_source_is_ready( |
| mbed_official | 579:53297373a894 | 598 | const enum system_clock_source clock_source) |
| mbed_official | 579:53297373a894 | 599 | { |
| mbed_official | 579:53297373a894 | 600 | uint32_t mask = 0; |
| mbed_official | 579:53297373a894 | 601 | |
| mbed_official | 579:53297373a894 | 602 | switch (clock_source) { |
| mbed_official | 579:53297373a894 | 603 | case SYSTEM_CLOCK_SOURCE_OSC8M: |
| mbed_official | 579:53297373a894 | 604 | mask = SYSCTRL_PCLKSR_OSC8MRDY; |
| mbed_official | 579:53297373a894 | 605 | break; |
| mbed_official | 579:53297373a894 | 606 | |
| mbed_official | 579:53297373a894 | 607 | case SYSTEM_CLOCK_SOURCE_OSC32K: |
| mbed_official | 579:53297373a894 | 608 | mask = SYSCTRL_PCLKSR_OSC32KRDY; |
| mbed_official | 579:53297373a894 | 609 | break; |
| mbed_official | 579:53297373a894 | 610 | |
| mbed_official | 579:53297373a894 | 611 | case SYSTEM_CLOCK_SOURCE_XOSC: |
| mbed_official | 579:53297373a894 | 612 | mask = SYSCTRL_PCLKSR_XOSCRDY; |
| mbed_official | 579:53297373a894 | 613 | break; |
| mbed_official | 579:53297373a894 | 614 | |
| mbed_official | 579:53297373a894 | 615 | case SYSTEM_CLOCK_SOURCE_XOSC32K: |
| mbed_official | 579:53297373a894 | 616 | mask = SYSCTRL_PCLKSR_XOSC32KRDY; |
| mbed_official | 579:53297373a894 | 617 | break; |
| mbed_official | 579:53297373a894 | 618 | |
| mbed_official | 579:53297373a894 | 619 | case SYSTEM_CLOCK_SOURCE_DFLL: |
| mbed_official | 579:53297373a894 | 620 | if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { |
| mbed_official | 579:53297373a894 | 621 | mask = (SYSCTRL_PCLKSR_DFLLRDY | |
| mbed_official | 579:53297373a894 | 622 | SYSCTRL_PCLKSR_DFLLLCKF | SYSCTRL_PCLKSR_DFLLLCKC); |
| mbed_official | 579:53297373a894 | 623 | } else { |
| mbed_official | 579:53297373a894 | 624 | mask = SYSCTRL_PCLKSR_DFLLRDY; |
| mbed_official | 579:53297373a894 | 625 | } |
| mbed_official | 579:53297373a894 | 626 | break; |
| mbed_official | 579:53297373a894 | 627 | |
| mbed_official | 579:53297373a894 | 628 | #ifdef FEATURE_SYSTEM_CLOCK_DPLL |
| mbed_official | 579:53297373a894 | 629 | case SYSTEM_CLOCK_SOURCE_DPLL: |
| mbed_official | 579:53297373a894 | 630 | return ((SYSCTRL->DPLLSTATUS.reg & |
| mbed_official | 579:53297373a894 | 631 | (SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK)) == |
| mbed_official | 579:53297373a894 | 632 | (SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK)); |
| mbed_official | 579:53297373a894 | 633 | #endif |
| mbed_official | 579:53297373a894 | 634 | |
| mbed_official | 579:53297373a894 | 635 | case SYSTEM_CLOCK_SOURCE_ULP32K: |
| mbed_official | 579:53297373a894 | 636 | /* Not possible to disable */ |
| mbed_official | 579:53297373a894 | 637 | return true; |
| mbed_official | 579:53297373a894 | 638 | |
| mbed_official | 579:53297373a894 | 639 | default: |
| mbed_official | 579:53297373a894 | 640 | return false; |
| mbed_official | 579:53297373a894 | 641 | } |
| mbed_official | 579:53297373a894 | 642 | |
| mbed_official | 579:53297373a894 | 643 | return ((SYSCTRL->PCLKSR.reg & mask) == mask); |
| mbed_official | 579:53297373a894 | 644 | } |
| mbed_official | 579:53297373a894 | 645 | |
| mbed_official | 579:53297373a894 | 646 | /* Include some checks for conf_clocks.h validation */ |
| mbed_official | 579:53297373a894 | 647 | #include "clock_config_check.h" |
| mbed_official | 579:53297373a894 | 648 | |
| mbed_official | 579:53297373a894 | 649 | #if !defined(__DOXYGEN__) |
| mbed_official | 579:53297373a894 | 650 | /** \internal |
| mbed_official | 579:53297373a894 | 651 | * |
| mbed_official | 579:53297373a894 | 652 | * Configures a Generic Clock Generator with the configuration from \c conf_clocks.h. |
| mbed_official | 579:53297373a894 | 653 | */ |
| mbed_official | 579:53297373a894 | 654 | # define _CONF_CLOCK_GCLK_CONFIG(n, unused) \ |
| mbed_official | 579:53297373a894 | 655 | if (CONF_CLOCK_GCLK_##n##_ENABLE == true) { \ |
| mbed_official | 579:53297373a894 | 656 | struct system_gclk_gen_config gclk_conf; \ |
| mbed_official | 579:53297373a894 | 657 | system_gclk_gen_get_config_defaults(&gclk_conf); \ |
| mbed_official | 579:53297373a894 | 658 | gclk_conf.source_clock = CONF_CLOCK_GCLK_##n##_CLOCK_SOURCE; \ |
| mbed_official | 579:53297373a894 | 659 | gclk_conf.division_factor = CONF_CLOCK_GCLK_##n##_PRESCALER; \ |
| mbed_official | 579:53297373a894 | 660 | gclk_conf.run_in_standby = CONF_CLOCK_GCLK_##n##_RUN_IN_STANDBY; \ |
| mbed_official | 579:53297373a894 | 661 | gclk_conf.output_enable = CONF_CLOCK_GCLK_##n##_OUTPUT_ENABLE; \ |
| mbed_official | 579:53297373a894 | 662 | system_gclk_gen_set_config(GCLK_GENERATOR_##n, &gclk_conf); \ |
| mbed_official | 579:53297373a894 | 663 | system_gclk_gen_enable(GCLK_GENERATOR_##n); \ |
| mbed_official | 579:53297373a894 | 664 | } |
| mbed_official | 579:53297373a894 | 665 | |
| mbed_official | 579:53297373a894 | 666 | /** \internal |
| mbed_official | 579:53297373a894 | 667 | * |
| mbed_official | 579:53297373a894 | 668 | * Configures a Generic Clock Generator with the configuration from \c conf_clocks.h, |
| mbed_official | 579:53297373a894 | 669 | * provided that it is not the main Generic Clock Generator channel. |
| mbed_official | 579:53297373a894 | 670 | */ |
| mbed_official | 579:53297373a894 | 671 | # define _CONF_CLOCK_GCLK_CONFIG_NONMAIN(n, unused) \ |
| mbed_official | 579:53297373a894 | 672 | if (n > 0) { _CONF_CLOCK_GCLK_CONFIG(n, unused); } |
| mbed_official | 579:53297373a894 | 673 | #endif |
| mbed_official | 579:53297373a894 | 674 | |
| mbed_official | 579:53297373a894 | 675 | /** \internal |
| mbed_official | 579:53297373a894 | 676 | * |
| mbed_official | 579:53297373a894 | 677 | * Switch all peripheral clock to a not enabled general clock |
| mbed_official | 579:53297373a894 | 678 | * to save power. |
| mbed_official | 579:53297373a894 | 679 | */ |
| mbed_official | 579:53297373a894 | 680 | static void _switch_peripheral_gclk(void) |
| mbed_official | 579:53297373a894 | 681 | { |
| mbed_official | 579:53297373a894 | 682 | uint32_t gclk_id; |
| mbed_official | 579:53297373a894 | 683 | struct system_gclk_chan_config gclk_conf; |
| mbed_official | 579:53297373a894 | 684 | |
| mbed_official | 579:53297373a894 | 685 | #if CONF_CLOCK_GCLK_1_ENABLE == false |
| mbed_official | 579:53297373a894 | 686 | gclk_conf.source_generator = GCLK_GENERATOR_1; |
| mbed_official | 579:53297373a894 | 687 | #elif CONF_CLOCK_GCLK_2_ENABLE == false |
| mbed_official | 579:53297373a894 | 688 | gclk_conf.source_generator = GCLK_GENERATOR_2; |
| mbed_official | 579:53297373a894 | 689 | #elif CONF_CLOCK_GCLK_3_ENABLE == false |
| mbed_official | 579:53297373a894 | 690 | gclk_conf.source_generator = GCLK_GENERATOR_3; |
| mbed_official | 579:53297373a894 | 691 | #elif CONF_CLOCK_GCLK_4_ENABLE == false |
| mbed_official | 579:53297373a894 | 692 | gclk_conf.source_generator = GCLK_GENERATOR_4; |
| mbed_official | 579:53297373a894 | 693 | #elif CONF_CLOCK_GCLK_5_ENABLE == false |
| mbed_official | 579:53297373a894 | 694 | gclk_conf.source_generator = GCLK_GENERATOR_5; |
| mbed_official | 579:53297373a894 | 695 | #elif CONF_CLOCK_GCLK_6_ENABLE == false |
| mbed_official | 579:53297373a894 | 696 | gclk_conf.source_generator = GCLK_GENERATOR_6; |
| mbed_official | 579:53297373a894 | 697 | #elif CONF_CLOCK_GCLK_7_ENABLE == false |
| mbed_official | 579:53297373a894 | 698 | gclk_conf.source_generator = GCLK_GENERATOR_7; |
| mbed_official | 579:53297373a894 | 699 | #else |
| mbed_official | 579:53297373a894 | 700 | gclk_conf.source_generator = GCLK_GENERATOR_7; |
| mbed_official | 579:53297373a894 | 701 | #endif |
| mbed_official | 579:53297373a894 | 702 | |
| mbed_official | 579:53297373a894 | 703 | for (gclk_id = 0; gclk_id < GCLK_NUM; gclk_id++) { |
| mbed_official | 579:53297373a894 | 704 | system_gclk_chan_set_config(gclk_id, &gclk_conf); |
| mbed_official | 579:53297373a894 | 705 | } |
| mbed_official | 579:53297373a894 | 706 | } |
| mbed_official | 579:53297373a894 | 707 | |
| mbed_official | 579:53297373a894 | 708 | /** |
| mbed_official | 579:53297373a894 | 709 | * \brief Initialize clock system based on the configuration in conf_clocks.h. |
| mbed_official | 579:53297373a894 | 710 | * |
| mbed_official | 579:53297373a894 | 711 | * This function will apply the settings in conf_clocks.h when run from the user |
| mbed_official | 579:53297373a894 | 712 | * application. All clock sources and GCLK generators are running when this function |
| mbed_official | 579:53297373a894 | 713 | * returns. |
| mbed_official | 579:53297373a894 | 714 | * |
| mbed_official | 579:53297373a894 | 715 | * \note OSC8M is always enabled and if user selects other clocks for GCLK generators, |
| mbed_official | 579:53297373a894 | 716 | * the OSC8M default enable can be disabled after system_clock_init. Make sure the |
| mbed_official | 579:53297373a894 | 717 | * clock switch successfully before disabling OSC8M. |
| mbed_official | 579:53297373a894 | 718 | */ |
| mbed_official | 579:53297373a894 | 719 | void system_clock_init(void) |
| mbed_official | 579:53297373a894 | 720 | { |
| mbed_official | 579:53297373a894 | 721 | /* Various bits in the INTFLAG register can be set to one at startup. |
| mbed_official | 579:53297373a894 | 722 | This will ensure that these bits are cleared */ |
| mbed_official | 579:53297373a894 | 723 | SYSCTRL->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33RDY | SYSCTRL_INTFLAG_BOD33DET | |
| mbed_official | 579:53297373a894 | 724 | SYSCTRL_INTFLAG_DFLLRDY; |
| mbed_official | 579:53297373a894 | 725 | |
| mbed_official | 579:53297373a894 | 726 | system_flash_set_waitstates(CONF_CLOCK_FLASH_WAIT_STATES); |
| mbed_official | 579:53297373a894 | 727 | |
| mbed_official | 579:53297373a894 | 728 | /* Switch all peripheral clock to a not enabled general clock to save power. */ |
| mbed_official | 579:53297373a894 | 729 | _switch_peripheral_gclk(); |
| mbed_official | 579:53297373a894 | 730 | |
| mbed_official | 579:53297373a894 | 731 | /* XOSC */ |
| mbed_official | 579:53297373a894 | 732 | #if CONF_CLOCK_XOSC_ENABLE == true |
| mbed_official | 579:53297373a894 | 733 | struct system_clock_source_xosc_config xosc_conf; |
| mbed_official | 579:53297373a894 | 734 | system_clock_source_xosc_get_config_defaults(&xosc_conf); |
| mbed_official | 579:53297373a894 | 735 | |
| mbed_official | 579:53297373a894 | 736 | xosc_conf.external_clock = CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL; |
| mbed_official | 579:53297373a894 | 737 | xosc_conf.startup_time = CONF_CLOCK_XOSC_STARTUP_TIME; |
| mbed_official | 579:53297373a894 | 738 | xosc_conf.auto_gain_control = CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL; |
| mbed_official | 579:53297373a894 | 739 | xosc_conf.frequency = CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY; |
| mbed_official | 579:53297373a894 | 740 | xosc_conf.on_demand = CONF_CLOCK_XOSC_ON_DEMAND; |
| mbed_official | 579:53297373a894 | 741 | xosc_conf.run_in_standby = CONF_CLOCK_XOSC_RUN_IN_STANDBY; |
| mbed_official | 579:53297373a894 | 742 | |
| mbed_official | 579:53297373a894 | 743 | system_clock_source_xosc_set_config(&xosc_conf); |
| mbed_official | 579:53297373a894 | 744 | system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC); |
| mbed_official | 579:53297373a894 | 745 | #endif |
| mbed_official | 579:53297373a894 | 746 | |
| mbed_official | 579:53297373a894 | 747 | |
| mbed_official | 579:53297373a894 | 748 | /* XOSC32K */ |
| mbed_official | 579:53297373a894 | 749 | #if CONF_CLOCK_XOSC32K_ENABLE == true |
| mbed_official | 579:53297373a894 | 750 | struct system_clock_source_xosc32k_config xosc32k_conf; |
| mbed_official | 579:53297373a894 | 751 | system_clock_source_xosc32k_get_config_defaults(&xosc32k_conf); |
| mbed_official | 579:53297373a894 | 752 | |
| mbed_official | 579:53297373a894 | 753 | xosc32k_conf.frequency = 32768UL; |
| mbed_official | 579:53297373a894 | 754 | xosc32k_conf.external_clock = CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL; |
| mbed_official | 579:53297373a894 | 755 | xosc32k_conf.startup_time = CONF_CLOCK_XOSC32K_STARTUP_TIME; |
| mbed_official | 579:53297373a894 | 756 | xosc32k_conf.auto_gain_control = CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL; |
| mbed_official | 579:53297373a894 | 757 | xosc32k_conf.enable_1khz_output = CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT; |
| mbed_official | 579:53297373a894 | 758 | xosc32k_conf.enable_32khz_output = CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT; |
| mbed_official | 579:53297373a894 | 759 | xosc32k_conf.on_demand = false; |
| mbed_official | 579:53297373a894 | 760 | xosc32k_conf.run_in_standby = CONF_CLOCK_XOSC32K_RUN_IN_STANDBY; |
| mbed_official | 579:53297373a894 | 761 | |
| mbed_official | 579:53297373a894 | 762 | system_clock_source_xosc32k_set_config(&xosc32k_conf); |
| mbed_official | 579:53297373a894 | 763 | system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC32K); |
| mbed_official | 579:53297373a894 | 764 | while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_XOSC32K)); |
| mbed_official | 579:53297373a894 | 765 | if (CONF_CLOCK_XOSC32K_ON_DEMAND) { |
| mbed_official | 579:53297373a894 | 766 | SYSCTRL->XOSC32K.bit.ONDEMAND = 1; |
| mbed_official | 579:53297373a894 | 767 | } |
| mbed_official | 579:53297373a894 | 768 | #endif |
| mbed_official | 579:53297373a894 | 769 | |
| mbed_official | 579:53297373a894 | 770 | |
| mbed_official | 579:53297373a894 | 771 | /* OSCK32K */ |
| mbed_official | 579:53297373a894 | 772 | #if CONF_CLOCK_OSC32K_ENABLE == true |
| mbed_official | 579:53297373a894 | 773 | SYSCTRL->OSC32K.bit.CALIB = |
| mbed_official | 579:53297373a894 | 774 | (*(uint32_t *)SYSCTRL_FUSES_OSC32K_ADDR >> SYSCTRL_FUSES_OSC32K_Pos); |
| mbed_official | 579:53297373a894 | 775 | |
| mbed_official | 579:53297373a894 | 776 | struct system_clock_source_osc32k_config osc32k_conf; |
| mbed_official | 579:53297373a894 | 777 | system_clock_source_osc32k_get_config_defaults(&osc32k_conf); |
| mbed_official | 579:53297373a894 | 778 | |
| mbed_official | 579:53297373a894 | 779 | osc32k_conf.startup_time = CONF_CLOCK_OSC32K_STARTUP_TIME; |
| mbed_official | 579:53297373a894 | 780 | osc32k_conf.enable_1khz_output = CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT; |
| mbed_official | 579:53297373a894 | 781 | osc32k_conf.enable_32khz_output = CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT; |
| mbed_official | 579:53297373a894 | 782 | osc32k_conf.on_demand = CONF_CLOCK_OSC32K_ON_DEMAND; |
| mbed_official | 579:53297373a894 | 783 | osc32k_conf.run_in_standby = CONF_CLOCK_OSC32K_RUN_IN_STANDBY; |
| mbed_official | 579:53297373a894 | 784 | |
| mbed_official | 579:53297373a894 | 785 | system_clock_source_osc32k_set_config(&osc32k_conf); |
| mbed_official | 579:53297373a894 | 786 | system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC32K); |
| mbed_official | 579:53297373a894 | 787 | #endif |
| mbed_official | 579:53297373a894 | 788 | |
| mbed_official | 579:53297373a894 | 789 | |
| mbed_official | 579:53297373a894 | 790 | /* DFLL Config (Open and Closed Loop) */ |
| mbed_official | 579:53297373a894 | 791 | #if CONF_CLOCK_DFLL_ENABLE == true |
| mbed_official | 579:53297373a894 | 792 | struct system_clock_source_dfll_config dfll_conf; |
| mbed_official | 579:53297373a894 | 793 | system_clock_source_dfll_get_config_defaults(&dfll_conf); |
| mbed_official | 579:53297373a894 | 794 | |
| mbed_official | 579:53297373a894 | 795 | dfll_conf.loop_mode = CONF_CLOCK_DFLL_LOOP_MODE; |
| mbed_official | 579:53297373a894 | 796 | dfll_conf.on_demand = false; |
| mbed_official | 579:53297373a894 | 797 | |
| mbed_official | 579:53297373a894 | 798 | if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN) { |
| mbed_official | 579:53297373a894 | 799 | dfll_conf.coarse_value = CONF_CLOCK_DFLL_COARSE_VALUE; |
| mbed_official | 579:53297373a894 | 800 | dfll_conf.fine_value = CONF_CLOCK_DFLL_FINE_VALUE; |
| mbed_official | 579:53297373a894 | 801 | } |
| mbed_official | 579:53297373a894 | 802 | |
| mbed_official | 579:53297373a894 | 803 | # if CONF_CLOCK_DFLL_QUICK_LOCK == true |
| mbed_official | 579:53297373a894 | 804 | dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE; |
| mbed_official | 579:53297373a894 | 805 | # else |
| mbed_official | 579:53297373a894 | 806 | dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE; |
| mbed_official | 579:53297373a894 | 807 | # endif |
| mbed_official | 579:53297373a894 | 808 | |
| mbed_official | 579:53297373a894 | 809 | # if CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK == true |
| mbed_official | 579:53297373a894 | 810 | dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK; |
| mbed_official | 579:53297373a894 | 811 | # else |
| mbed_official | 579:53297373a894 | 812 | dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK; |
| mbed_official | 579:53297373a894 | 813 | # endif |
| mbed_official | 579:53297373a894 | 814 | |
| mbed_official | 579:53297373a894 | 815 | # if CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP == true |
| mbed_official | 579:53297373a894 | 816 | dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP; |
| mbed_official | 579:53297373a894 | 817 | # else |
| mbed_official | 579:53297373a894 | 818 | dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE; |
| mbed_official | 579:53297373a894 | 819 | # endif |
| mbed_official | 579:53297373a894 | 820 | |
| mbed_official | 579:53297373a894 | 821 | # if CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE == true |
| mbed_official | 579:53297373a894 | 822 | dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE; |
| mbed_official | 579:53297373a894 | 823 | # else |
| mbed_official | 579:53297373a894 | 824 | dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE; |
| mbed_official | 579:53297373a894 | 825 | # endif |
| mbed_official | 579:53297373a894 | 826 | |
| mbed_official | 579:53297373a894 | 827 | if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { |
| mbed_official | 579:53297373a894 | 828 | dfll_conf.multiply_factor = CONF_CLOCK_DFLL_MULTIPLY_FACTOR; |
| mbed_official | 579:53297373a894 | 829 | } |
| mbed_official | 579:53297373a894 | 830 | |
| mbed_official | 579:53297373a894 | 831 | dfll_conf.coarse_max_step = CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE; |
| mbed_official | 579:53297373a894 | 832 | dfll_conf.fine_max_step = CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE; |
| mbed_official | 579:53297373a894 | 833 | |
| mbed_official | 579:53297373a894 | 834 | if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY) { |
| mbed_official | 579:53297373a894 | 835 | #define NVM_DFLL_COARSE_POS 58 |
| mbed_official | 579:53297373a894 | 836 | #define NVM_DFLL_COARSE_SIZE 6 |
| mbed_official | 579:53297373a894 | 837 | #define NVM_DFLL_FINE_POS 64 |
| mbed_official | 579:53297373a894 | 838 | #define NVM_DFLL_FINE_SIZE 10 |
| mbed_official | 579:53297373a894 | 839 | uint32_t coarse =( *((uint32_t *)(NVMCTRL_OTP4) |
| mbed_official | 579:53297373a894 | 840 | + (NVM_DFLL_COARSE_POS / 32)) |
| mbed_official | 579:53297373a894 | 841 | >> (NVM_DFLL_COARSE_POS % 32)) |
| mbed_official | 579:53297373a894 | 842 | & ((1 << NVM_DFLL_COARSE_SIZE) - 1); |
| mbed_official | 579:53297373a894 | 843 | if (coarse == 0x3f) { |
| mbed_official | 579:53297373a894 | 844 | coarse = 0x1f; |
| mbed_official | 579:53297373a894 | 845 | } |
| mbed_official | 579:53297373a894 | 846 | uint32_t fine =( *((uint32_t *)(NVMCTRL_OTP4) |
| mbed_official | 579:53297373a894 | 847 | + (NVM_DFLL_FINE_POS / 32)) |
| mbed_official | 579:53297373a894 | 848 | >> (NVM_DFLL_FINE_POS % 32)) |
| mbed_official | 579:53297373a894 | 849 | & ((1 << NVM_DFLL_FINE_SIZE) - 1); |
| mbed_official | 579:53297373a894 | 850 | if (fine == 0x3ff) { |
| mbed_official | 579:53297373a894 | 851 | fine = 0x1ff; |
| mbed_official | 579:53297373a894 | 852 | } |
| mbed_official | 579:53297373a894 | 853 | dfll_conf.coarse_value = coarse; |
| mbed_official | 579:53297373a894 | 854 | dfll_conf.fine_value = fine; |
| mbed_official | 579:53297373a894 | 855 | |
| mbed_official | 579:53297373a894 | 856 | dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE; |
| mbed_official | 579:53297373a894 | 857 | dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK; |
| mbed_official | 579:53297373a894 | 858 | dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP; |
| mbed_official | 579:53297373a894 | 859 | dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE; |
| mbed_official | 579:53297373a894 | 860 | |
| mbed_official | 579:53297373a894 | 861 | dfll_conf.multiply_factor = 48000; |
| mbed_official | 579:53297373a894 | 862 | } |
| mbed_official | 579:53297373a894 | 863 | |
| mbed_official | 579:53297373a894 | 864 | system_clock_source_dfll_set_config(&dfll_conf); |
| mbed_official | 579:53297373a894 | 865 | #endif |
| mbed_official | 579:53297373a894 | 866 | |
| mbed_official | 579:53297373a894 | 867 | |
| mbed_official | 579:53297373a894 | 868 | /* OSC8M */ |
| mbed_official | 579:53297373a894 | 869 | struct system_clock_source_osc8m_config osc8m_conf; |
| mbed_official | 579:53297373a894 | 870 | system_clock_source_osc8m_get_config_defaults(&osc8m_conf); |
| mbed_official | 579:53297373a894 | 871 | |
| mbed_official | 579:53297373a894 | 872 | osc8m_conf.prescaler = CONF_CLOCK_OSC8M_PRESCALER; |
| mbed_official | 579:53297373a894 | 873 | osc8m_conf.on_demand = CONF_CLOCK_OSC8M_ON_DEMAND; |
| mbed_official | 579:53297373a894 | 874 | osc8m_conf.run_in_standby = CONF_CLOCK_OSC8M_RUN_IN_STANDBY; |
| mbed_official | 579:53297373a894 | 875 | |
| mbed_official | 579:53297373a894 | 876 | system_clock_source_osc8m_set_config(&osc8m_conf); |
| mbed_official | 579:53297373a894 | 877 | system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC8M); |
| mbed_official | 579:53297373a894 | 878 | |
| mbed_official | 579:53297373a894 | 879 | |
| mbed_official | 579:53297373a894 | 880 | /* GCLK */ |
| mbed_official | 579:53297373a894 | 881 | #if CONF_CLOCK_CONFIGURE_GCLK == true |
| mbed_official | 579:53297373a894 | 882 | system_gclk_init(); |
| mbed_official | 579:53297373a894 | 883 | |
| mbed_official | 579:53297373a894 | 884 | /* Configure all GCLK generators except for the main generator, which |
| mbed_official | 579:53297373a894 | 885 | * is configured later after all other clock systems are set up */ |
| mbed_official | 579:53297373a894 | 886 | MREPEAT(8, _CONF_CLOCK_GCLK_CONFIG_NONMAIN, ~); |
| mbed_official | 579:53297373a894 | 887 | |
| mbed_official | 579:53297373a894 | 888 | # if CONF_CLOCK_DFLL_ENABLE == true |
| mbed_official | 579:53297373a894 | 889 | /* Enable DFLL reference clock if in closed loop mode */ |
| mbed_official | 579:53297373a894 | 890 | if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { |
| mbed_official | 579:53297373a894 | 891 | struct system_gclk_chan_config dfll_gclk_chan_conf; |
| mbed_official | 579:53297373a894 | 892 | |
| mbed_official | 579:53297373a894 | 893 | system_gclk_chan_get_config_defaults(&dfll_gclk_chan_conf); |
| mbed_official | 579:53297373a894 | 894 | dfll_gclk_chan_conf.source_generator = CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR; |
| mbed_official | 579:53297373a894 | 895 | system_gclk_chan_set_config(SYSCTRL_GCLK_ID_DFLL48, &dfll_gclk_chan_conf); |
| mbed_official | 579:53297373a894 | 896 | system_gclk_chan_enable(SYSCTRL_GCLK_ID_DFLL48); |
| mbed_official | 579:53297373a894 | 897 | } |
| mbed_official | 579:53297373a894 | 898 | # endif |
| mbed_official | 579:53297373a894 | 899 | #endif |
| mbed_official | 579:53297373a894 | 900 | |
| mbed_official | 579:53297373a894 | 901 | |
| mbed_official | 579:53297373a894 | 902 | /* DFLL Enable (Open and Closed Loop) */ |
| mbed_official | 579:53297373a894 | 903 | #if CONF_CLOCK_DFLL_ENABLE == true |
| mbed_official | 579:53297373a894 | 904 | system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DFLL); |
| mbed_official | 579:53297373a894 | 905 | while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DFLL)); |
| mbed_official | 579:53297373a894 | 906 | if (CONF_CLOCK_DFLL_ON_DEMAND) { |
| mbed_official | 579:53297373a894 | 907 | SYSCTRL->DFLLCTRL.bit.ONDEMAND = 1; |
| mbed_official | 579:53297373a894 | 908 | } |
| mbed_official | 579:53297373a894 | 909 | #endif |
| mbed_official | 579:53297373a894 | 910 | |
| mbed_official | 579:53297373a894 | 911 | /* DPLL */ |
| mbed_official | 579:53297373a894 | 912 | #ifdef FEATURE_SYSTEM_CLOCK_DPLL |
| mbed_official | 579:53297373a894 | 913 | # if (CONF_CLOCK_DPLL_ENABLE == true) |
| mbed_official | 579:53297373a894 | 914 | |
| mbed_official | 579:53297373a894 | 915 | /* Enable DPLL reference clock */ |
| mbed_official | 579:53297373a894 | 916 | if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_REF0) { |
| mbed_official | 579:53297373a894 | 917 | /* XOSC32K should have been enabled for DPLL_REF0 */ |
| mbed_official | 579:53297373a894 | 918 | Assert(CONF_CLOCK_XOSC32K_ENABLE); |
| mbed_official | 579:53297373a894 | 919 | } |
| mbed_official | 579:53297373a894 | 920 | |
| mbed_official | 579:53297373a894 | 921 | struct system_clock_source_dpll_config dpll_config; |
| mbed_official | 579:53297373a894 | 922 | system_clock_source_dpll_get_config_defaults(&dpll_config); |
| mbed_official | 579:53297373a894 | 923 | |
| mbed_official | 579:53297373a894 | 924 | dpll_config.on_demand = false; |
| mbed_official | 579:53297373a894 | 925 | dpll_config.run_in_standby = CONF_CLOCK_DPLL_RUN_IN_STANDBY; |
| mbed_official | 579:53297373a894 | 926 | dpll_config.lock_bypass = CONF_CLOCK_DPLL_LOCK_BYPASS; |
| mbed_official | 579:53297373a894 | 927 | dpll_config.wake_up_fast = CONF_CLOCK_DPLL_WAKE_UP_FAST; |
| mbed_official | 579:53297373a894 | 928 | dpll_config.low_power_enable = CONF_CLOCK_DPLL_LOW_POWER_ENABLE; |
| mbed_official | 579:53297373a894 | 929 | |
| mbed_official | 579:53297373a894 | 930 | dpll_config.filter = CONF_CLOCK_DPLL_FILTER; |
| mbed_official | 579:53297373a894 | 931 | |
| mbed_official | 579:53297373a894 | 932 | dpll_config.reference_clock = CONF_CLOCK_DPLL_REFERENCE_CLOCK; |
| mbed_official | 579:53297373a894 | 933 | dpll_config.reference_frequency = CONF_CLOCK_DPLL_REFERENCE_FREQUENCY; |
| mbed_official | 579:53297373a894 | 934 | dpll_config.reference_divider = CONF_CLOCK_DPLL_REFEREMCE_DIVIDER; |
| mbed_official | 579:53297373a894 | 935 | dpll_config.output_frequency = CONF_CLOCK_DPLL_OUTPUT_FREQUENCY; |
| mbed_official | 579:53297373a894 | 936 | |
| mbed_official | 579:53297373a894 | 937 | system_clock_source_dpll_set_config(&dpll_config); |
| mbed_official | 579:53297373a894 | 938 | system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DPLL); |
| mbed_official | 579:53297373a894 | 939 | while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DPLL)); |
| mbed_official | 579:53297373a894 | 940 | if (CONF_CLOCK_DPLL_ON_DEMAND) { |
| mbed_official | 579:53297373a894 | 941 | SYSCTRL->DPLLCTRLA.bit.ONDEMAND = 1; |
| mbed_official | 579:53297373a894 | 942 | } |
| mbed_official | 579:53297373a894 | 943 | |
| mbed_official | 579:53297373a894 | 944 | # endif |
| mbed_official | 579:53297373a894 | 945 | #endif |
| mbed_official | 579:53297373a894 | 946 | |
| mbed_official | 579:53297373a894 | 947 | /* CPU and BUS clocks */ |
| mbed_official | 579:53297373a894 | 948 | system_cpu_clock_set_divider(CONF_CLOCK_CPU_DIVIDER); |
| mbed_official | 579:53297373a894 | 949 | |
| mbed_official | 579:53297373a894 | 950 | system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBA, CONF_CLOCK_APBA_DIVIDER); |
| mbed_official | 579:53297373a894 | 951 | system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBB, CONF_CLOCK_APBB_DIVIDER); |
| mbed_official | 579:53297373a894 | 952 | |
| mbed_official | 579:53297373a894 | 953 | /* GCLK 0 */ |
| mbed_official | 579:53297373a894 | 954 | #if CONF_CLOCK_CONFIGURE_GCLK == true |
| mbed_official | 579:53297373a894 | 955 | /* Configure the main GCLK last as it might depend on other generators */ |
| mbed_official | 579:53297373a894 | 956 | _CONF_CLOCK_GCLK_CONFIG(0, ~); |
| mbed_official | 579:53297373a894 | 957 | #endif |
| mbed_official | 579:53297373a894 | 958 | } |