marcus chiou / mbed-src

mbed library sources

Fork of mbed-src by mbed official

targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/samr21g18a.h@592:a274ee790e56, 2015-07-17 (annotated)

Committer:
mbed_official
Date:
Fri Jul 17 09:15:10 2015 +0100
Revision:
592:a274ee790e56
Parent:
579:53297373a894 
Synchronized with git revision e7144f83a8d75df80c4877936b6ffe552b0be9e6



Full URL: https://github.com/mbedmicro/mbed/commit/e7144f83a8d75df80c4877936b6ffe552b0be9e6/



More API implementation for SAMR21

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 579:53297373a894 1 #ifndef _SAMR21G18A_
mbed_official 579:53297373a894 2 #define _SAMR21G18A_
mbed_official 579:53297373a894 3
mbed_official 579:53297373a894 4 /**
mbed_official 579:53297373a894 5 * \ingroup SAMR21_definitions
mbed_official 579:53297373a894 6 * \addtogroup SAMR21G18A_definitions SAMR21G18A definitions
mbed_official 579:53297373a894 7 * This file defines all structures and symbols for SAMR21G18A:
mbed_official 579:53297373a894 8 * - registers and bitfields
mbed_official 579:53297373a894 9 * - peripheral base address
mbed_official 579:53297373a894 10 * - peripheral ID
mbed_official 579:53297373a894 11 * - PIO definitions
mbed_official 579:53297373a894 12 */
mbed_official 579:53297373a894 13 /*@{*/
mbed_official 579:53297373a894 14
mbed_official 579:53297373a894 15 #ifdef __cplusplus
mbed_official 579:53297373a894 16 extern "C" {
mbed_official 579:53297373a894 17 #endif
mbed_official 579:53297373a894 18
mbed_official 579:53297373a894 19 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 20 #include <stdint.h>
mbed_official 579:53297373a894 21 #ifndef __cplusplus
mbed_official 579:53297373a894 22 typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
mbed_official 579:53297373a894 23 typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
mbed_official 579:53297373a894 24 typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
mbed_official 579:53297373a894 25 #else
mbed_official 579:53297373a894 26 typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
mbed_official 579:53297373a894 27 typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
mbed_official 579:53297373a894 28 typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
mbed_official 579:53297373a894 29 #endif
mbed_official 579:53297373a894 30 typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
mbed_official 579:53297373a894 31 typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
mbed_official 579:53297373a894 32 typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
mbed_official 579:53297373a894 33 typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
mbed_official 579:53297373a894 34 typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
mbed_official 579:53297373a894 35 typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
mbed_official 579:53297373a894 36 #define CAST(type, value) ((type *)(value))
mbed_official 579:53297373a894 37 #define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
mbed_official 579:53297373a894 38 #else
mbed_official 579:53297373a894 39 #define CAST(type, value) (value)
mbed_official 579:53297373a894 40 #define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
mbed_official 579:53297373a894 41 #endif
mbed_official 579:53297373a894 42
mbed_official 579:53297373a894 43 /* ************************************************************************** */
mbed_official 579:53297373a894 44 /** CMSIS DEFINITIONS FOR SAMR21G18A */
mbed_official 579:53297373a894 45 /* ************************************************************************** */
mbed_official 579:53297373a894 46 /** \defgroup SAMR21G18A_cmsis CMSIS Definitions */
mbed_official 579:53297373a894 47 /*@{*/
mbed_official 579:53297373a894 48
mbed_official 579:53297373a894 49 /** Interrupt Number Definition */
mbed_official 579:53297373a894 50 typedef enum IRQn {
mbed_official 579:53297373a894 51 /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
mbed_official 579:53297373a894 52 NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
mbed_official 579:53297373a894 53 HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
mbed_official 579:53297373a894 54 SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
mbed_official 579:53297373a894 55 PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
mbed_official 579:53297373a894 56 SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
mbed_official 579:53297373a894 57 /****** SAMR21G18A-specific Interrupt Numbers ***********************/
mbed_official 579:53297373a894 58 PM_IRQn = 0, /**< 0 SAMR21G18A Power Manager (PM) */
mbed_official 579:53297373a894 59 SYSCTRL_IRQn = 1, /**< 1 SAMR21G18A System Control (SYSCTRL) */
mbed_official 579:53297373a894 60 WDT_IRQn = 2, /**< 2 SAMR21G18A Watchdog Timer (WDT) */
mbed_official 579:53297373a894 61 RTC_IRQn = 3, /**< 3 SAMR21G18A Real-Time Counter (RTC) */
mbed_official 579:53297373a894 62 EIC_IRQn = 4, /**< 4 SAMR21G18A External Interrupt Controller (EIC) */
mbed_official 579:53297373a894 63 NVMCTRL_IRQn = 5, /**< 5 SAMR21G18A Non-Volatile Memory Controller (NVMCTRL) */
mbed_official 579:53297373a894 64 DMAC_IRQn = 6, /**< 6 SAMR21G18A Direct Memory Access Controller (DMAC) */
mbed_official 579:53297373a894 65 USB_IRQn = 7, /**< 7 SAMR21G18A Universal Serial Bus (USB) */
mbed_official 579:53297373a894 66 EVSYS_IRQn = 8, /**< 8 SAMR21G18A Event System Interface (EVSYS) */
mbed_official 579:53297373a894 67 SERCOM0_IRQn = 9, /**< 9 SAMR21G18A Serial Communication Interface 0 (SERCOM0) */
mbed_official 579:53297373a894 68 SERCOM1_IRQn = 10, /**< 10 SAMR21G18A Serial Communication Interface 1 (SERCOM1) */
mbed_official 579:53297373a894 69 SERCOM2_IRQn = 11, /**< 11 SAMR21G18A Serial Communication Interface 2 (SERCOM2) */
mbed_official 579:53297373a894 70 SERCOM3_IRQn = 12, /**< 12 SAMR21G18A Serial Communication Interface 3 (SERCOM3) */
mbed_official 579:53297373a894 71 SERCOM4_IRQn = 13, /**< 13 SAMR21G18A Serial Communication Interface 4 (SERCOM4) */
mbed_official 579:53297373a894 72 SERCOM5_IRQn = 14, /**< 14 SAMR21G18A Serial Communication Interface 5 (SERCOM5) */
mbed_official 579:53297373a894 73 TCC0_IRQn = 15, /**< 15 SAMR21G18A Timer Counter Control 0 (TCC0) */
mbed_official 579:53297373a894 74 TCC1_IRQn = 16, /**< 16 SAMR21G18A Timer Counter Control 1 (TCC1) */
mbed_official 579:53297373a894 75 TCC2_IRQn = 17, /**< 17 SAMR21G18A Timer Counter Control 2 (TCC2) */
mbed_official 579:53297373a894 76 TC3_IRQn = 18, /**< 18 SAMR21G18A Basic Timer Counter 3 (TC3) */
mbed_official 579:53297373a894 77 TC4_IRQn = 19, /**< 19 SAMR21G18A Basic Timer Counter 4 (TC4) */
mbed_official 579:53297373a894 78 TC5_IRQn = 20, /**< 20 SAMR21G18A Basic Timer Counter 5 (TC5) */
mbed_official 579:53297373a894 79 TC6_IRQn = 21, /**< 21 SAMR21G18A Basic Timer Counter 6 (TC6) */
mbed_official 579:53297373a894 80 TC7_IRQn = 22, /**< 22 SAMR21G18A Basic Timer Counter 7 (TC7) */
mbed_official 579:53297373a894 81 ADC_IRQn = 23, /**< 23 SAMR21G18A Analog Digital Converter (ADC) */
mbed_official 579:53297373a894 82 AC_IRQn = 24, /**< 24 SAMR21G18A Analog Comparators (AC) */
mbed_official 579:53297373a894 83 DAC_IRQn = 25, /**< 25 SAMR21G18A Digital Analog Converter (DAC) */
mbed_official 579:53297373a894 84 PTC_IRQn = 26, /**< 26 SAMR21G18A Peripheral Touch Controller (PTC) */
mbed_official 579:53297373a894 85 I2S_IRQn = 27, /**< 27 SAMR21G18A Inter-IC Sound Interface (I2S) */
mbed_official 579:53297373a894 86
mbed_official 579:53297373a894 87 PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
mbed_official 579:53297373a894 88 } IRQn_Type;
mbed_official 579:53297373a894 89
mbed_official 579:53297373a894 90 typedef struct _DeviceVectors {
mbed_official 579:53297373a894 91 /* Stack pointer */
mbed_official 579:53297373a894 92 void* pvStack;
mbed_official 579:53297373a894 93
mbed_official 579:53297373a894 94 /* Cortex-M handlers */
mbed_official 579:53297373a894 95 void* pfnReset_Handler;
mbed_official 579:53297373a894 96 void* pfnNMI_Handler;
mbed_official 579:53297373a894 97 void* pfnHardFault_Handler;
mbed_official 579:53297373a894 98 void* pfnReservedM12;
mbed_official 579:53297373a894 99 void* pfnReservedM11;
mbed_official 579:53297373a894 100 void* pfnReservedM10;
mbed_official 579:53297373a894 101 void* pfnReservedM9;
mbed_official 579:53297373a894 102 void* pfnReservedM8;
mbed_official 579:53297373a894 103 void* pfnReservedM7;
mbed_official 579:53297373a894 104 void* pfnReservedM6;
mbed_official 579:53297373a894 105 void* pfnSVC_Handler;
mbed_official 579:53297373a894 106 void* pfnReservedM4;
mbed_official 579:53297373a894 107 void* pfnReservedM3;
mbed_official 579:53297373a894 108 void* pfnPendSV_Handler;
mbed_official 579:53297373a894 109 void* pfnSysTick_Handler;
mbed_official 579:53297373a894 110
mbed_official 579:53297373a894 111 /* Peripheral handlers */
mbed_official 579:53297373a894 112 void* pfnPM_Handler; /* 0 Power Manager */
mbed_official 579:53297373a894 113 void* pfnSYSCTRL_Handler; /* 1 System Control */
mbed_official 579:53297373a894 114 void* pfnWDT_Handler; /* 2 Watchdog Timer */
mbed_official 579:53297373a894 115 void* pfnRTC_Handler; /* 3 Real-Time Counter */
mbed_official 579:53297373a894 116 void* pfnEIC_Handler; /* 4 External Interrupt Controller */
mbed_official 579:53297373a894 117 void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
mbed_official 579:53297373a894 118 void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
mbed_official 579:53297373a894 119 void* pfnUSB_Handler; /* 7 Universal Serial Bus */
mbed_official 579:53297373a894 120 void* pfnEVSYS_Handler; /* 8 Event System Interface */
mbed_official 579:53297373a894 121 void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
mbed_official 579:53297373a894 122 void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
mbed_official 579:53297373a894 123 void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
mbed_official 579:53297373a894 124 void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
mbed_official 579:53297373a894 125 void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
mbed_official 579:53297373a894 126 void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
mbed_official 579:53297373a894 127 void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
mbed_official 579:53297373a894 128 void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
mbed_official 579:53297373a894 129 void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
mbed_official 579:53297373a894 130 void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
mbed_official 579:53297373a894 131 void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
mbed_official 579:53297373a894 132 void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
mbed_official 579:53297373a894 133 void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
mbed_official 579:53297373a894 134 void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
mbed_official 579:53297373a894 135 void* pfnADC_Handler; /* 23 Analog Digital Converter */
mbed_official 579:53297373a894 136 void* pfnAC_Handler; /* 24 Analog Comparators */
mbed_official 579:53297373a894 137 void* pfnDAC_Handler; /* 25 Digital Analog Converter */
mbed_official 579:53297373a894 138 void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
mbed_official 579:53297373a894 139 void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
mbed_official 579:53297373a894 140 } DeviceVectors;
mbed_official 579:53297373a894 141
mbed_official 579:53297373a894 142 /* Cortex-M0+ processor handlers */
mbed_official 579:53297373a894 143 void Reset_Handler ( void );
mbed_official 579:53297373a894 144 void NMI_Handler ( void );
mbed_official 579:53297373a894 145 void HardFault_Handler ( void );
mbed_official 579:53297373a894 146 void SVC_Handler ( void );
mbed_official 579:53297373a894 147 void PendSV_Handler ( void );
mbed_official 579:53297373a894 148 void SysTick_Handler ( void );
mbed_official 579:53297373a894 149
mbed_official 579:53297373a894 150 /* Peripherals handlers */
mbed_official 579:53297373a894 151 void PM_Handler ( void );
mbed_official 579:53297373a894 152 void SYSCTRL_Handler ( void );
mbed_official 579:53297373a894 153 void WDT_Handler ( void );
mbed_official 579:53297373a894 154 void RTC_Handler ( void );
mbed_official 579:53297373a894 155 void EIC_Handler ( void );
mbed_official 579:53297373a894 156 void NVMCTRL_Handler ( void );
mbed_official 579:53297373a894 157 void DMAC_Handler ( void );
mbed_official 579:53297373a894 158 void USB_Handler ( void );
mbed_official 579:53297373a894 159 void EVSYS_Handler ( void );
mbed_official 579:53297373a894 160 void SERCOM0_Handler ( void );
mbed_official 579:53297373a894 161 void SERCOM1_Handler ( void );
mbed_official 579:53297373a894 162 void SERCOM2_Handler ( void );
mbed_official 579:53297373a894 163 void SERCOM3_Handler ( void );
mbed_official 579:53297373a894 164 void SERCOM4_Handler ( void );
mbed_official 579:53297373a894 165 void SERCOM5_Handler ( void );
mbed_official 579:53297373a894 166 void TCC0_Handler ( void );
mbed_official 579:53297373a894 167 void TCC1_Handler ( void );
mbed_official 579:53297373a894 168 void TCC2_Handler ( void );
mbed_official 579:53297373a894 169 void TC3_Handler ( void );
mbed_official 579:53297373a894 170 void TC4_Handler ( void );
mbed_official 579:53297373a894 171 void TC5_Handler ( void );
mbed_official 579:53297373a894 172 void TC6_Handler ( void );
mbed_official 579:53297373a894 173 void TC7_Handler ( void );
mbed_official 579:53297373a894 174 void ADC_Handler ( void );
mbed_official 579:53297373a894 175 void AC_Handler ( void );
mbed_official 579:53297373a894 176 void DAC_Handler ( void );
mbed_official 579:53297373a894 177 void PTC_Handler ( void );
mbed_official 579:53297373a894 178 void I2S_Handler ( void );
mbed_official 579:53297373a894 179
mbed_official 579:53297373a894 180 /*
mbed_official 579:53297373a894 181 * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
mbed_official 579:53297373a894 182 */
mbed_official 579:53297373a894 183
mbed_official 579:53297373a894 184 #define LITTLE_ENDIAN 1
mbed_official 579:53297373a894 185 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
mbed_official 579:53297373a894 186 #define __MPU_PRESENT 0 /*!< MPU present or not */
mbed_official 579:53297373a894 187 #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
mbed_official 579:53297373a894 188 #define __VTOR_PRESENT 1 /*!< VTOR present or not */
mbed_official 579:53297373a894 189 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
mbed_official 579:53297373a894 190
mbed_official 579:53297373a894 191 /**
mbed_official 579:53297373a894 192 * \brief CMSIS includes
mbed_official 579:53297373a894 193 */
mbed_official 579:53297373a894 194
mbed_official 579:53297373a894 195 #include <core_cm0plus.h>
mbed_official 579:53297373a894 196 #if !defined DONT_USE_CMSIS_INIT
mbed_official 579:53297373a894 197 #include "system_samr21.h"
mbed_official 579:53297373a894 198 #endif /* DONT_USE_CMSIS_INIT */
mbed_official 579:53297373a894 199
mbed_official 579:53297373a894 200 /*@}*/
mbed_official 579:53297373a894 201
mbed_official 579:53297373a894 202 /* ************************************************************************** */
mbed_official 579:53297373a894 203 /** SOFTWARE PERIPHERAL API DEFINITION FOR SAMR21G18A */
mbed_official 579:53297373a894 204 /* ************************************************************************** */
mbed_official 579:53297373a894 205 /** \defgroup SAMR21G18A_api Peripheral Software API */
mbed_official 579:53297373a894 206 /*@{*/
mbed_official 579:53297373a894 207
mbed_official 579:53297373a894 208 #include "comp_ac.h"
mbed_official 579:53297373a894 209 #include "comp_adc.h"
mbed_official 579:53297373a894 210 #include "comp_dmac.h"
mbed_official 579:53297373a894 211 #include "comp_dsu.h"
mbed_official 579:53297373a894 212 #include "comp_eic.h"
mbed_official 579:53297373a894 213 #include "comp_evsys.h"
mbed_official 579:53297373a894 214 #include "comp_gclk.h"
mbed_official 579:53297373a894 215 #include "comp_hmatrixb.h"
mbed_official 579:53297373a894 216 #include "comp_mtb.h"
mbed_official 579:53297373a894 217 #include "comp_nvmctrl.h"
mbed_official 579:53297373a894 218 #include "comp_pac.h"
mbed_official 579:53297373a894 219 #include "comp_pm.h"
mbed_official 579:53297373a894 220 #include "comp_port.h"
mbed_official 579:53297373a894 221 #include "comp_rfctrl.h"
mbed_official 579:53297373a894 222 #include "comp_rtc.h"
mbed_official 579:53297373a894 223 #include "comp_sercom.h"
mbed_official 579:53297373a894 224 #include "comp_sysctrl.h"
mbed_official 579:53297373a894 225 #include "comp_tc.h"
mbed_official 579:53297373a894 226 #include "comp_tcc.h"
mbed_official 579:53297373a894 227 #include "comp_usb.h"
mbed_official 579:53297373a894 228 #include "comp_wdt.h"
mbed_official 579:53297373a894 229 /*@}*/
mbed_official 579:53297373a894 230
mbed_official 579:53297373a894 231 /* ************************************************************************** */
mbed_official 579:53297373a894 232 /** REGISTERS ACCESS DEFINITIONS FOR SAMR21G18A */
mbed_official 579:53297373a894 233 /* ************************************************************************** */
mbed_official 579:53297373a894 234 /** \defgroup SAMR21G18A_reg Registers Access Definitions */
mbed_official 579:53297373a894 235 /*@{*/
mbed_official 579:53297373a894 236
mbed_official 579:53297373a894 237 #include "ins_ac.h"
mbed_official 579:53297373a894 238 #include "ins_adc.h"
mbed_official 579:53297373a894 239 #include "ins_dmac.h"
mbed_official 579:53297373a894 240 #include "ins_dsu.h"
mbed_official 579:53297373a894 241 #include "ins_eic.h"
mbed_official 579:53297373a894 242 #include "ins_evsys.h"
mbed_official 579:53297373a894 243 #include "ins_gclk.h"
mbed_official 579:53297373a894 244 #include "ins_sbmatrix.h"
mbed_official 579:53297373a894 245 #include "ins_mtb.h"
mbed_official 579:53297373a894 246 #include "ins_nvmctrl.h"
mbed_official 579:53297373a894 247 #include "ins_pac0.h"
mbed_official 579:53297373a894 248 #include "ins_pac1.h"
mbed_official 579:53297373a894 249 #include "ins_pac2.h"
mbed_official 579:53297373a894 250 #include "ins_pm.h"
mbed_official 579:53297373a894 251 #include "ins_port.h"
mbed_official 579:53297373a894 252 #include "ins_rfctrl.h"
mbed_official 579:53297373a894 253 #include "ins_rtc.h"
mbed_official 579:53297373a894 254 #include "ins_sercom0.h"
mbed_official 579:53297373a894 255 #include "ins_sercom1.h"
mbed_official 579:53297373a894 256 #include "ins_sercom2.h"
mbed_official 579:53297373a894 257 #include "ins_sercom3.h"
mbed_official 579:53297373a894 258 #include "ins_sercom4.h"
mbed_official 579:53297373a894 259 #include "ins_sercom5.h"
mbed_official 579:53297373a894 260 #include "ins_sysctrl.h"
mbed_official 579:53297373a894 261 #include "ins_tc3.h"
mbed_official 579:53297373a894 262 #include "ins_tc4.h"
mbed_official 579:53297373a894 263 #include "ins_tc5.h"
mbed_official 579:53297373a894 264 #include "ins_tcc0.h"
mbed_official 579:53297373a894 265 #include "ins_tcc1.h"
mbed_official 579:53297373a894 266 #include "ins_tcc2.h"
mbed_official 579:53297373a894 267 #include "ins_usb.h"
mbed_official 579:53297373a894 268 #include "ins_wdt.h"
mbed_official 579:53297373a894 269 /*@}*/
mbed_official 579:53297373a894 270
mbed_official 579:53297373a894 271 /* ************************************************************************** */
mbed_official 579:53297373a894 272 /** PERIPHERAL ID DEFINITIONS FOR SAMR21G18A */
mbed_official 579:53297373a894 273 /* ************************************************************************** */
mbed_official 579:53297373a894 274 /** \defgroup SAMR21G18A_id Peripheral Ids Definitions */
mbed_official 579:53297373a894 275 /*@{*/
mbed_official 579:53297373a894 276
mbed_official 579:53297373a894 277 // Peripheral instances on HPB0 bridge
mbed_official 579:53297373a894 278 #define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */
mbed_official 579:53297373a894 279 #define ID_PM 1 /**< \brief Power Manager (PM) */
mbed_official 579:53297373a894 280 #define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
mbed_official 579:53297373a894 281 #define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
mbed_official 579:53297373a894 282 #define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
mbed_official 579:53297373a894 283 #define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
mbed_official 579:53297373a894 284 #define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
mbed_official 579:53297373a894 285
mbed_official 579:53297373a894 286 // Peripheral instances on HPB1 bridge
mbed_official 579:53297373a894 287 #define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */
mbed_official 579:53297373a894 288 #define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
mbed_official 579:53297373a894 289 #define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
mbed_official 579:53297373a894 290 #define ID_PORT 35 /**< \brief Port Module (PORT) */
mbed_official 579:53297373a894 291 #define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
mbed_official 579:53297373a894 292 #define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
mbed_official 579:53297373a894 293 #define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
mbed_official 579:53297373a894 294 #define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */
mbed_official 579:53297373a894 295
mbed_official 579:53297373a894 296 // Peripheral instances on HPB2 bridge
mbed_official 579:53297373a894 297 #define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */
mbed_official 579:53297373a894 298 #define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
mbed_official 579:53297373a894 299 #define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
mbed_official 579:53297373a894 300 #define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
mbed_official 579:53297373a894 301 #define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
mbed_official 579:53297373a894 302 #define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
mbed_official 579:53297373a894 303 #define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
mbed_official 579:53297373a894 304 #define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
mbed_official 579:53297373a894 305 #define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */
mbed_official 579:53297373a894 306 #define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */
mbed_official 579:53297373a894 307 #define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */
mbed_official 579:53297373a894 308 #define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */
mbed_official 579:53297373a894 309 #define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */
mbed_official 579:53297373a894 310 #define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */
mbed_official 579:53297373a894 311 #define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
mbed_official 579:53297373a894 312 #define ID_AC 81 /**< \brief Analog Comparators (AC) */
mbed_official 579:53297373a894 313 #define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
mbed_official 579:53297373a894 314 #define ID_RFCTRL 85 /**< \brief RF233 control module (RFCTRL) */
mbed_official 579:53297373a894 315
mbed_official 579:53297373a894 316 #define ID_PERIPH_COUNT 86 /**< \brief Number of peripheral IDs */
mbed_official 579:53297373a894 317 /*@}*/
mbed_official 579:53297373a894 318
mbed_official 579:53297373a894 319 /* ************************************************************************** */
mbed_official 579:53297373a894 320 /** BASE ADDRESS DEFINITIONS FOR SAMR21G18A */
mbed_official 579:53297373a894 321 /* ************************************************************************** */
mbed_official 579:53297373a894 322 /** \defgroup SAMR21G18A_base Peripheral Base Address Definitions */
mbed_official 579:53297373a894 323 /*@{*/
mbed_official 579:53297373a894 324
mbed_official 579:53297373a894 325 #if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
mbed_official 579:53297373a894 326 #define AC (0x42004400UL) /**< \brief (AC) APB Base Address */
mbed_official 579:53297373a894 327 #define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */
mbed_official 579:53297373a894 328 #define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */
mbed_official 579:53297373a894 329 #define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */
mbed_official 579:53297373a894 330 #define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */
mbed_official 579:53297373a894 331 #define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
mbed_official 579:53297373a894 332 #define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
mbed_official 579:53297373a894 333 #define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
mbed_official 579:53297373a894 334 #define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */
mbed_official 579:53297373a894 335 #define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
mbed_official 579:53297373a894 336 #define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
mbed_official 579:53297373a894 337 #define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
mbed_official 579:53297373a894 338 #define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
mbed_official 579:53297373a894 339 #define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
mbed_official 579:53297373a894 340 #define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
mbed_official 579:53297373a894 341 #define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
mbed_official 579:53297373a894 342 #define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
mbed_official 579:53297373a894 343 #define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */
mbed_official 579:53297373a894 344 #define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */
mbed_official 579:53297373a894 345 #define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */
mbed_official 579:53297373a894 346 #define PM (0x40000400UL) /**< \brief (PM) APB Base Address */
mbed_official 579:53297373a894 347 #define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */
mbed_official 579:53297373a894 348 #define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
mbed_official 579:53297373a894 349 #define RFCTRL (0x42005400UL) /**< \brief (RFCTRL) APB Base Address */
mbed_official 579:53297373a894 350 #define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */
mbed_official 579:53297373a894 351 #define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
mbed_official 579:53297373a894 352 #define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
mbed_official 579:53297373a894 353 #define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
mbed_official 579:53297373a894 354 #define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
mbed_official 579:53297373a894 355 #define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
mbed_official 579:53297373a894 356 #define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
mbed_official 579:53297373a894 357 #define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
mbed_official 579:53297373a894 358 #define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */
mbed_official 579:53297373a894 359 #define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */
mbed_official 579:53297373a894 360 #define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */
mbed_official 579:53297373a894 361 #define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */
mbed_official 579:53297373a894 362 #define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */
mbed_official 579:53297373a894 363 #define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */
mbed_official 579:53297373a894 364 #define USB (0x41005000UL) /**< \brief (USB) APB Base Address */
mbed_official 579:53297373a894 365 #define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */
mbed_official 579:53297373a894 366 #else
mbed_official 579:53297373a894 367 #define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */
mbed_official 579:53297373a894 368 #define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
mbed_official 579:53297373a894 369 #define AC_INSTS { AC } /**< \brief (AC) Instances List */
mbed_official 579:53297373a894 370
mbed_official 579:53297373a894 371 #define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */
mbed_official 579:53297373a894 372 #define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
mbed_official 579:53297373a894 373 #define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
mbed_official 579:53297373a894 374
mbed_official 579:53297373a894 375 #define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
mbed_official 579:53297373a894 376 #define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
mbed_official 579:53297373a894 377 #define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
mbed_official 579:53297373a894 378
mbed_official 579:53297373a894 379 #define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
mbed_official 579:53297373a894 380 #define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
mbed_official 579:53297373a894 381 #define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
mbed_official 579:53297373a894 382
mbed_official 579:53297373a894 383 #define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */
mbed_official 579:53297373a894 384 #define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
mbed_official 579:53297373a894 385 #define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
mbed_official 579:53297373a894 386
mbed_official 579:53297373a894 387 #define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
mbed_official 579:53297373a894 388 #define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
mbed_official 579:53297373a894 389 #define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
mbed_official 579:53297373a894 390
mbed_official 579:53297373a894 391 #define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
mbed_official 579:53297373a894 392 #define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
mbed_official 579:53297373a894 393 #define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
mbed_official 579:53297373a894 394
mbed_official 579:53297373a894 395 #define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
mbed_official 579:53297373a894 396 #define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
mbed_official 579:53297373a894 397 #define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */
mbed_official 579:53297373a894 398
mbed_official 579:53297373a894 399 #define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */
mbed_official 579:53297373a894 400 #define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
mbed_official 579:53297373a894 401 #define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
mbed_official 579:53297373a894 402
mbed_official 579:53297373a894 403 #define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
mbed_official 579:53297373a894 404 #define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
mbed_official 579:53297373a894 405 #define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
mbed_official 579:53297373a894 406 #define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
mbed_official 579:53297373a894 407 #define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
mbed_official 579:53297373a894 408 #define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
mbed_official 579:53297373a894 409 #define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
mbed_official 579:53297373a894 410 #define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
mbed_official 579:53297373a894 411 #define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
mbed_official 579:53297373a894 412 #define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
mbed_official 579:53297373a894 413
mbed_official 579:53297373a894 414 #define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
mbed_official 579:53297373a894 415 #define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
mbed_official 579:53297373a894 416 #define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
mbed_official 579:53297373a894 417 #define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
mbed_official 579:53297373a894 418 #define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
mbed_official 579:53297373a894 419
mbed_official 579:53297373a894 420 #define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
mbed_official 579:53297373a894 421 #define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
mbed_official 579:53297373a894 422 #define PM_INSTS { PM } /**< \brief (PM) Instances List */
mbed_official 579:53297373a894 423
mbed_official 579:53297373a894 424 #define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */
mbed_official 579:53297373a894 425 #define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
mbed_official 579:53297373a894 426 #define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
mbed_official 579:53297373a894 427 #define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
mbed_official 579:53297373a894 428
mbed_official 579:53297373a894 429 #define PTC_GCLK_ID 34
mbed_official 579:53297373a894 430 #define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
mbed_official 579:53297373a894 431 #define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
mbed_official 579:53297373a894 432
mbed_official 579:53297373a894 433 #define RFCTRL ((Rfctrl *)0x42005400UL) /**< \brief (RFCTRL) APB Base Address */
mbed_official 579:53297373a894 434 #define RFCTRL_INST_NUM 1 /**< \brief (RFCTRL) Number of instances */
mbed_official 579:53297373a894 435 #define RFCTRL_INSTS { RFCTRL } /**< \brief (RFCTRL) Instances List */
mbed_official 579:53297373a894 436
mbed_official 579:53297373a894 437 #define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */
mbed_official 579:53297373a894 438 #define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
mbed_official 579:53297373a894 439 #define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
mbed_official 579:53297373a894 440
mbed_official 579:53297373a894 441 #define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
mbed_official 579:53297373a894 442 #define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
mbed_official 579:53297373a894 443 #define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
mbed_official 579:53297373a894 444 #define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
mbed_official 579:53297373a894 445 #define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
mbed_official 579:53297373a894 446 #define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
mbed_official 579:53297373a894 447 #define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
mbed_official 579:53297373a894 448 #define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
mbed_official 579:53297373a894 449
mbed_official 579:53297373a894 450 #define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
mbed_official 579:53297373a894 451 #define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
mbed_official 579:53297373a894 452 #define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
mbed_official 579:53297373a894 453
mbed_official 579:53297373a894 454 #define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
mbed_official 579:53297373a894 455 #define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */
mbed_official 579:53297373a894 456 #define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */
mbed_official 579:53297373a894 457 #define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
mbed_official 579:53297373a894 458 #define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
mbed_official 579:53297373a894 459
mbed_official 579:53297373a894 460 #define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
mbed_official 579:53297373a894 461 #define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
mbed_official 579:53297373a894 462 #define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
mbed_official 579:53297373a894 463 #define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
mbed_official 579:53297373a894 464 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
mbed_official 579:53297373a894 465
mbed_official 579:53297373a894 466 #define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */
mbed_official 579:53297373a894 467 #define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
mbed_official 579:53297373a894 468 #define USB_INSTS { USB } /**< \brief (USB) Instances List */
mbed_official 579:53297373a894 469
mbed_official 579:53297373a894 470 #define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */
mbed_official 579:53297373a894 471 #define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
mbed_official 579:53297373a894 472 #define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
mbed_official 579:53297373a894 473
mbed_official 579:53297373a894 474 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 475 /*@}*/
mbed_official 579:53297373a894 476
mbed_official 579:53297373a894 477 /* ************************************************************************** */
mbed_official 579:53297373a894 478 /** PORT DEFINITIONS FOR SAMR21G18A */
mbed_official 579:53297373a894 479 /* ************************************************************************** */
mbed_official 579:53297373a894 480 /** \defgroup SAMR21G18A_port PORT Definitions */
mbed_official 579:53297373a894 481 /*@{*/
mbed_official 579:53297373a894 482
mbed_official 579:53297373a894 483 #include "pio_samr21g18a.h"
mbed_official 579:53297373a894 484 /*@}*/
mbed_official 579:53297373a894 485
mbed_official 579:53297373a894 486 /* ************************************************************************** */
mbed_official 579:53297373a894 487 /** MEMORY MAPPING DEFINITIONS FOR SAMR21G18A */
mbed_official 579:53297373a894 488 /* ************************************************************************** */
mbed_official 579:53297373a894 489
mbed_official 579:53297373a894 490 #define FLASH_SIZE 0x40000UL /* 256 kB */
mbed_official 579:53297373a894 491 #define FLASH_PAGE_SIZE 64
mbed_official 579:53297373a894 492 #define FLASH_NB_OF_PAGES 4096
mbed_official 579:53297373a894 493 #define FLASH_USER_PAGE_SIZE 64
mbed_official 579:53297373a894 494 #define HMCRAMC0_SIZE 0x8000UL /* 32 kB */
mbed_official 579:53297373a894 495 #define FLASH_ADDR (0x00000000UL) /**< FLASH base address */
mbed_official 579:53297373a894 496 #define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */
mbed_official 579:53297373a894 497 #define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */
mbed_official 579:53297373a894 498
mbed_official 579:53297373a894 499 #define DSU_DID_RESETVALUE 0x10010019UL
mbed_official 579:53297373a894 500 #define EIC_EXTINT_NUM 16
mbed_official 579:53297373a894 501 #define PORT_GROUPS 3
mbed_official 579:53297373a894 502 #define SIP_CONFIG RF233
mbed_official 579:53297373a894 503
mbed_official 579:53297373a894 504 /* ************************************************************************** */
mbed_official 579:53297373a894 505 /** ELECTRICAL DEFINITIONS FOR SAMR21G18A */
mbed_official 579:53297373a894 506 /* ************************************************************************** */
mbed_official 579:53297373a894 507
mbed_official 579:53297373a894 508
mbed_official 579:53297373a894 509 #ifdef __cplusplus
mbed_official 579:53297373a894 510 }
mbed_official 579:53297373a894 511 #endif
mbed_official 579:53297373a894 512
mbed_official 579:53297373a894 513 /*@}*/
mbed_official 579:53297373a894 514
mbed_official 579:53297373a894 515 #endif /* SAMR21G18A_H */