marcus chiou / mbed-src

mbed library sources

Fork of mbed-src by mbed official

targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_rtc.h@592:a274ee790e56, 2015-07-17 (annotated)

Committer:
mbed_official
Date:
Fri Jul 17 09:15:10 2015 +0100
Revision:
592:a274ee790e56
Parent:
579:53297373a894 
Synchronized with git revision e7144f83a8d75df80c4877936b6ffe552b0be9e6



Full URL: https://github.com/mbedmicro/mbed/commit/e7144f83a8d75df80c4877936b6ffe552b0be9e6/



More API implementation for SAMR21

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 579:53297373a894 1 #ifndef _SAMD21_RTC_INSTANCE_
mbed_official 579:53297373a894 2 #define _SAMD21_RTC_INSTANCE_
mbed_official 579:53297373a894 3
mbed_official 579:53297373a894 4 /* ========== Register definition for RTC peripheral ========== */
mbed_official 579:53297373a894 5 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 6 #define REG_RTC_READREQ (0x40001402U) /**< \brief (RTC) Read Request */
mbed_official 579:53297373a894 7 #define REG_RTC_STATUS (0x4000140AU) /**< \brief (RTC) Status */
mbed_official 579:53297373a894 8 #define REG_RTC_DBGCTRL (0x4000140BU) /**< \brief (RTC) Debug Control */
mbed_official 579:53297373a894 9 #define REG_RTC_FREQCORR (0x4000140CU) /**< \brief (RTC) Frequency Correction */
mbed_official 579:53297373a894 10 #define REG_RTC_MODE0_CTRL (0x40001400U) /**< \brief (RTC) MODE0 Control */
mbed_official 579:53297373a894 11 #define REG_RTC_MODE0_EVCTRL (0x40001404U) /**< \brief (RTC) MODE0 Event Control */
mbed_official 579:53297373a894 12 #define REG_RTC_MODE0_INTENCLR (0x40001406U) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
mbed_official 579:53297373a894 13 #define REG_RTC_MODE0_INTENSET (0x40001407U) /**< \brief (RTC) MODE0 Interrupt Enable Set */
mbed_official 579:53297373a894 14 #define REG_RTC_MODE0_INTFLAG (0x40001408U) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 15 #define REG_RTC_MODE0_COUNT (0x40001410U) /**< \brief (RTC) MODE0 Counter Value */
mbed_official 579:53297373a894 16 #define REG_RTC_MODE0_COMP0 (0x40001418U) /**< \brief (RTC) MODE0 Compare 0 Value */
mbed_official 579:53297373a894 17 #define REG_RTC_MODE1_CTRL (0x40001400U) /**< \brief (RTC) MODE1 Control */
mbed_official 579:53297373a894 18 #define REG_RTC_MODE1_EVCTRL (0x40001404U) /**< \brief (RTC) MODE1 Event Control */
mbed_official 579:53297373a894 19 #define REG_RTC_MODE1_INTENCLR (0x40001406U) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
mbed_official 579:53297373a894 20 #define REG_RTC_MODE1_INTENSET (0x40001407U) /**< \brief (RTC) MODE1 Interrupt Enable Set */
mbed_official 579:53297373a894 21 #define REG_RTC_MODE1_INTFLAG (0x40001408U) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 22 #define REG_RTC_MODE1_COUNT (0x40001410U) /**< \brief (RTC) MODE1 Counter Value */
mbed_official 579:53297373a894 23 #define REG_RTC_MODE1_PER (0x40001414U) /**< \brief (RTC) MODE1 Counter Period */
mbed_official 579:53297373a894 24 #define REG_RTC_MODE1_COMP0 (0x40001418U) /**< \brief (RTC) MODE1 Compare 0 Value */
mbed_official 579:53297373a894 25 #define REG_RTC_MODE1_COMP1 (0x4000141AU) /**< \brief (RTC) MODE1 Compare 1 Value */
mbed_official 579:53297373a894 26 #define REG_RTC_MODE2_CTRL (0x40001400U) /**< \brief (RTC) MODE2 Control */
mbed_official 579:53297373a894 27 #define REG_RTC_MODE2_EVCTRL (0x40001404U) /**< \brief (RTC) MODE2 Event Control */
mbed_official 579:53297373a894 28 #define REG_RTC_MODE2_INTENCLR (0x40001406U) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
mbed_official 579:53297373a894 29 #define REG_RTC_MODE2_INTENSET (0x40001407U) /**< \brief (RTC) MODE2 Interrupt Enable Set */
mbed_official 579:53297373a894 30 #define REG_RTC_MODE2_INTFLAG (0x40001408U) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 31 #define REG_RTC_MODE2_CLOCK (0x40001410U) /**< \brief (RTC) MODE2 Clock Value */
mbed_official 579:53297373a894 32 #define REG_RTC_MODE2_ALARM_ALARM0 (0x40001418U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
mbed_official 579:53297373a894 33 #define REG_RTC_MODE2_ALARM_MASK0 (0x4000141CU) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
mbed_official 579:53297373a894 34 #else
mbed_official 579:53297373a894 35 #define REG_RTC_READREQ (*(RwReg16*)0x40001402U) /**< \brief (RTC) Read Request */
mbed_official 579:53297373a894 36 #define REG_RTC_STATUS (*(RwReg8 *)0x4000140AU) /**< \brief (RTC) Status */
mbed_official 579:53297373a894 37 #define REG_RTC_DBGCTRL (*(RwReg8 *)0x4000140BU) /**< \brief (RTC) Debug Control */
mbed_official 579:53297373a894 38 #define REG_RTC_FREQCORR (*(RwReg8 *)0x4000140CU) /**< \brief (RTC) Frequency Correction */
mbed_official 579:53297373a894 39 #define REG_RTC_MODE0_CTRL (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE0 Control */
mbed_official 579:53297373a894 40 #define REG_RTC_MODE0_EVCTRL (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE0 Event Control */
mbed_official 579:53297373a894 41 #define REG_RTC_MODE0_INTENCLR (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
mbed_official 579:53297373a894 42 #define REG_RTC_MODE0_INTENSET (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE0 Interrupt Enable Set */
mbed_official 579:53297373a894 43 #define REG_RTC_MODE0_INTFLAG (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 44 #define REG_RTC_MODE0_COUNT (*(RwReg *)0x40001410U) /**< \brief (RTC) MODE0 Counter Value */
mbed_official 579:53297373a894 45 #define REG_RTC_MODE0_COMP0 (*(RwReg *)0x40001418U) /**< \brief (RTC) MODE0 Compare 0 Value */
mbed_official 579:53297373a894 46 #define REG_RTC_MODE1_CTRL (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE1 Control */
mbed_official 579:53297373a894 47 #define REG_RTC_MODE1_EVCTRL (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE1 Event Control */
mbed_official 579:53297373a894 48 #define REG_RTC_MODE1_INTENCLR (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
mbed_official 579:53297373a894 49 #define REG_RTC_MODE1_INTENSET (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE1 Interrupt Enable Set */
mbed_official 579:53297373a894 50 #define REG_RTC_MODE1_INTFLAG (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 51 #define REG_RTC_MODE1_COUNT (*(RwReg16*)0x40001410U) /**< \brief (RTC) MODE1 Counter Value */
mbed_official 579:53297373a894 52 #define REG_RTC_MODE1_PER (*(RwReg16*)0x40001414U) /**< \brief (RTC) MODE1 Counter Period */
mbed_official 579:53297373a894 53 #define REG_RTC_MODE1_COMP0 (*(RwReg16*)0x40001418U) /**< \brief (RTC) MODE1 Compare 0 Value */
mbed_official 579:53297373a894 54 #define REG_RTC_MODE1_COMP1 (*(RwReg16*)0x4000141AU) /**< \brief (RTC) MODE1 Compare 1 Value */
mbed_official 579:53297373a894 55 #define REG_RTC_MODE2_CTRL (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE2 Control */
mbed_official 579:53297373a894 56 #define REG_RTC_MODE2_EVCTRL (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE2 Event Control */
mbed_official 579:53297373a894 57 #define REG_RTC_MODE2_INTENCLR (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
mbed_official 579:53297373a894 58 #define REG_RTC_MODE2_INTENSET (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE2 Interrupt Enable Set */
mbed_official 579:53297373a894 59 #define REG_RTC_MODE2_INTFLAG (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 60 #define REG_RTC_MODE2_CLOCK (*(RwReg *)0x40001410U) /**< \brief (RTC) MODE2 Clock Value */
mbed_official 579:53297373a894 61 #define REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg *)0x40001418U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
mbed_official 579:53297373a894 62 #define REG_RTC_MODE2_ALARM_MASK0 (*(RwReg *)0x4000141CU) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
mbed_official 579:53297373a894 63 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 64
mbed_official 579:53297373a894 65 /* ========== Instance parameters for RTC peripheral ========== */
mbed_official 579:53297373a894 66 #define RTC_ALARM_NUM 1 // Number of Alarms
mbed_official 579:53297373a894 67 #define RTC_COMP16_NUM 2 // Number of 16-bit Comparators
mbed_official 579:53297373a894 68 #define RTC_COMP32_NUM 1 // Number of 32-bit Comparators
mbed_official 579:53297373a894 69 #define RTC_GCLK_ID 4 // Index of Generic Clock
mbed_official 579:53297373a894 70 #define RTC_NUM_OF_ALARMS 1 // Number of Alarms (obsolete)
mbed_official 579:53297373a894 71 #define RTC_NUM_OF_COMP16 2 // Number of 16-bit Comparators (obsolete)
mbed_official 579:53297373a894 72 #define RTC_NUM_OF_COMP32 1 // Number of 32-bit Comparators (obsolete)
mbed_official 579:53297373a894 73
mbed_official 579:53297373a894 74 #endif /* _SAMD21_RTC_INSTANCE_ */