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targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_tcc.h@592:a274ee790e56, 2015-07-17 (annotated)

Committer:
mbed_official
Date:
Fri Jul 17 09:15:10 2015 +0100
Revision:
592:a274ee790e56
Parent:
579:53297373a894 
Synchronized with git revision e7144f83a8d75df80c4877936b6ffe552b0be9e6



Full URL: https://github.com/mbedmicro/mbed/commit/e7144f83a8d75df80c4877936b6ffe552b0be9e6/



More API implementation for SAMR21

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UserRevisionLine numberNew contents of line
mbed_official 579:53297373a894 1 #ifndef _SAMD21_TCC_COMPONENT_
mbed_official 579:53297373a894 2 #define _SAMD21_TCC_COMPONENT_
mbed_official 579:53297373a894 3
mbed_official 579:53297373a894 4 /* ========================================================================== */
mbed_official 579:53297373a894 5 /** SOFTWARE API DEFINITION FOR TCC */
mbed_official 579:53297373a894 6 /* ========================================================================== */
mbed_official 579:53297373a894 7 /** \addtogroup SAMD21_TCC Timer Counter Control */
mbed_official 579:53297373a894 8 /*@{*/
mbed_official 579:53297373a894 9
mbed_official 579:53297373a894 10 #define TCC_U2213
mbed_official 579:53297373a894 11 #define REV_TCC 0x101
mbed_official 579:53297373a894 12
mbed_official 579:53297373a894 13 /* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */
mbed_official 579:53297373a894 14 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 15 typedef union {
mbed_official 579:53297373a894 16 struct {
mbed_official 579:53297373a894 17 uint32_t SWRST:1; /*!< bit: 0 Software Reset */
mbed_official 579:53297373a894 18 uint32_t ENABLE:1; /*!< bit: 1 Enable */
mbed_official 579:53297373a894 19 uint32_t :3; /*!< bit: 2.. 4 Reserved */
mbed_official 579:53297373a894 20 uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */
mbed_official 579:53297373a894 21 uint32_t :1; /*!< bit: 7 Reserved */
mbed_official 579:53297373a894 22 uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
mbed_official 579:53297373a894 23 uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
mbed_official 579:53297373a894 24 uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */
mbed_official 579:53297373a894 25 uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */
mbed_official 579:53297373a894 26 uint32_t :9; /*!< bit: 15..23 Reserved */
mbed_official 579:53297373a894 27 uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */
mbed_official 579:53297373a894 28 uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */
mbed_official 579:53297373a894 29 uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */
mbed_official 579:53297373a894 30 uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */
mbed_official 579:53297373a894 31 uint32_t :4; /*!< bit: 28..31 Reserved */
mbed_official 579:53297373a894 32 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 33 struct {
mbed_official 579:53297373a894 34 uint32_t :24; /*!< bit: 0..23 Reserved */
mbed_official 579:53297373a894 35 uint32_t CPTEN:4; /*!< bit: 24..27 Capture Channel x Enable */
mbed_official 579:53297373a894 36 uint32_t :4; /*!< bit: 28..31 Reserved */
mbed_official 579:53297373a894 37 } vec; /*!< Structure used for vec access */
mbed_official 579:53297373a894 38 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 39 } TCC_CTRLA_Type;
mbed_official 579:53297373a894 40 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 41
mbed_official 579:53297373a894 42 #define TCC_CTRLA_OFFSET 0x00 /**< \brief (TCC_CTRLA offset) Control A */
mbed_official 579:53297373a894 43 #define TCC_CTRLA_RESETVALUE 0x00000000ul /**< \brief (TCC_CTRLA reset_value) Control A */
mbed_official 579:53297373a894 44
mbed_official 579:53297373a894 45 #define TCC_CTRLA_SWRST_Pos 0 /**< \brief (TCC_CTRLA) Software Reset */
mbed_official 579:53297373a894 46 #define TCC_CTRLA_SWRST (0x1ul << TCC_CTRLA_SWRST_Pos)
mbed_official 579:53297373a894 47 #define TCC_CTRLA_ENABLE_Pos 1 /**< \brief (TCC_CTRLA) Enable */
mbed_official 579:53297373a894 48 #define TCC_CTRLA_ENABLE (0x1ul << TCC_CTRLA_ENABLE_Pos)
mbed_official 579:53297373a894 49 #define TCC_CTRLA_RESOLUTION_Pos 5 /**< \brief (TCC_CTRLA) Enhanced Resolution */
mbed_official 579:53297373a894 50 #define TCC_CTRLA_RESOLUTION_Msk (0x3ul << TCC_CTRLA_RESOLUTION_Pos)
mbed_official 579:53297373a894 51 #define TCC_CTRLA_RESOLUTION(value) ((TCC_CTRLA_RESOLUTION_Msk & ((value) << TCC_CTRLA_RESOLUTION_Pos)))
mbed_official 579:53297373a894 52 #define TCC_CTRLA_RESOLUTION_NONE_Val 0x0ul /**< \brief (TCC_CTRLA) Dithering is disabled */
mbed_official 579:53297373a894 53 #define TCC_CTRLA_RESOLUTION_DITH4_Val 0x1ul /**< \brief (TCC_CTRLA) Dithering is done every 16 PWM frames */
mbed_official 579:53297373a894 54 #define TCC_CTRLA_RESOLUTION_DITH5_Val 0x2ul /**< \brief (TCC_CTRLA) Dithering is done every 32 PWM frames */
mbed_official 579:53297373a894 55 #define TCC_CTRLA_RESOLUTION_DITH6_Val 0x3ul /**< \brief (TCC_CTRLA) Dithering is done every 64 PWM frames */
mbed_official 579:53297373a894 56 #define TCC_CTRLA_RESOLUTION_NONE (TCC_CTRLA_RESOLUTION_NONE_Val << TCC_CTRLA_RESOLUTION_Pos)
mbed_official 579:53297373a894 57 #define TCC_CTRLA_RESOLUTION_DITH4 (TCC_CTRLA_RESOLUTION_DITH4_Val << TCC_CTRLA_RESOLUTION_Pos)
mbed_official 579:53297373a894 58 #define TCC_CTRLA_RESOLUTION_DITH5 (TCC_CTRLA_RESOLUTION_DITH5_Val << TCC_CTRLA_RESOLUTION_Pos)
mbed_official 579:53297373a894 59 #define TCC_CTRLA_RESOLUTION_DITH6 (TCC_CTRLA_RESOLUTION_DITH6_Val << TCC_CTRLA_RESOLUTION_Pos)
mbed_official 579:53297373a894 60 #define TCC_CTRLA_PRESCALER_Pos 8 /**< \brief (TCC_CTRLA) Prescaler */
mbed_official 579:53297373a894 61 #define TCC_CTRLA_PRESCALER_Msk (0x7ul << TCC_CTRLA_PRESCALER_Pos)
mbed_official 579:53297373a894 62 #define TCC_CTRLA_PRESCALER(value) ((TCC_CTRLA_PRESCALER_Msk & ((value) << TCC_CTRLA_PRESCALER_Pos)))
mbed_official 579:53297373a894 63 #define TCC_CTRLA_PRESCALER_DIV1_Val 0x0ul /**< \brief (TCC_CTRLA) No division */
mbed_official 579:53297373a894 64 #define TCC_CTRLA_PRESCALER_DIV2_Val 0x1ul /**< \brief (TCC_CTRLA) Divide by 2 */
mbed_official 579:53297373a894 65 #define TCC_CTRLA_PRESCALER_DIV4_Val 0x2ul /**< \brief (TCC_CTRLA) Divide by 4 */
mbed_official 579:53297373a894 66 #define TCC_CTRLA_PRESCALER_DIV8_Val 0x3ul /**< \brief (TCC_CTRLA) Divide by 8 */
mbed_official 579:53297373a894 67 #define TCC_CTRLA_PRESCALER_DIV16_Val 0x4ul /**< \brief (TCC_CTRLA) Divide by 16 */
mbed_official 579:53297373a894 68 #define TCC_CTRLA_PRESCALER_DIV64_Val 0x5ul /**< \brief (TCC_CTRLA) Divide by 64 */
mbed_official 579:53297373a894 69 #define TCC_CTRLA_PRESCALER_DIV256_Val 0x6ul /**< \brief (TCC_CTRLA) Divide by 256 */
mbed_official 579:53297373a894 70 #define TCC_CTRLA_PRESCALER_DIV1024_Val 0x7ul /**< \brief (TCC_CTRLA) Divide by 1024 */
mbed_official 579:53297373a894 71 #define TCC_CTRLA_PRESCALER_DIV1 (TCC_CTRLA_PRESCALER_DIV1_Val << TCC_CTRLA_PRESCALER_Pos)
mbed_official 579:53297373a894 72 #define TCC_CTRLA_PRESCALER_DIV2 (TCC_CTRLA_PRESCALER_DIV2_Val << TCC_CTRLA_PRESCALER_Pos)
mbed_official 579:53297373a894 73 #define TCC_CTRLA_PRESCALER_DIV4 (TCC_CTRLA_PRESCALER_DIV4_Val << TCC_CTRLA_PRESCALER_Pos)
mbed_official 579:53297373a894 74 #define TCC_CTRLA_PRESCALER_DIV8 (TCC_CTRLA_PRESCALER_DIV8_Val << TCC_CTRLA_PRESCALER_Pos)
mbed_official 579:53297373a894 75 #define TCC_CTRLA_PRESCALER_DIV16 (TCC_CTRLA_PRESCALER_DIV16_Val << TCC_CTRLA_PRESCALER_Pos)
mbed_official 579:53297373a894 76 #define TCC_CTRLA_PRESCALER_DIV64 (TCC_CTRLA_PRESCALER_DIV64_Val << TCC_CTRLA_PRESCALER_Pos)
mbed_official 579:53297373a894 77 #define TCC_CTRLA_PRESCALER_DIV256 (TCC_CTRLA_PRESCALER_DIV256_Val << TCC_CTRLA_PRESCALER_Pos)
mbed_official 579:53297373a894 78 #define TCC_CTRLA_PRESCALER_DIV1024 (TCC_CTRLA_PRESCALER_DIV1024_Val << TCC_CTRLA_PRESCALER_Pos)
mbed_official 579:53297373a894 79 #define TCC_CTRLA_RUNSTDBY_Pos 11 /**< \brief (TCC_CTRLA) Run in Standby */
mbed_official 579:53297373a894 80 #define TCC_CTRLA_RUNSTDBY (0x1ul << TCC_CTRLA_RUNSTDBY_Pos)
mbed_official 579:53297373a894 81 #define TCC_CTRLA_PRESCSYNC_Pos 12 /**< \brief (TCC_CTRLA) Prescaler and Counter Synchronization Selection */
mbed_official 579:53297373a894 82 #define TCC_CTRLA_PRESCSYNC_Msk (0x3ul << TCC_CTRLA_PRESCSYNC_Pos)
mbed_official 579:53297373a894 83 #define TCC_CTRLA_PRESCSYNC(value) ((TCC_CTRLA_PRESCSYNC_Msk & ((value) << TCC_CTRLA_PRESCSYNC_Pos)))
mbed_official 579:53297373a894 84 #define TCC_CTRLA_PRESCSYNC_GCLK_Val 0x0ul /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK */
mbed_official 579:53297373a894 85 #define TCC_CTRLA_PRESCSYNC_PRESC_Val 0x1ul /**< \brief (TCC_CTRLA) Reload or reset counter on next prescaler clock */
mbed_official 579:53297373a894 86 #define TCC_CTRLA_PRESCSYNC_RESYNC_Val 0x2ul /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK and reset prescaler counter */
mbed_official 579:53297373a894 87 #define TCC_CTRLA_PRESCSYNC_GCLK (TCC_CTRLA_PRESCSYNC_GCLK_Val << TCC_CTRLA_PRESCSYNC_Pos)
mbed_official 579:53297373a894 88 #define TCC_CTRLA_PRESCSYNC_PRESC (TCC_CTRLA_PRESCSYNC_PRESC_Val << TCC_CTRLA_PRESCSYNC_Pos)
mbed_official 579:53297373a894 89 #define TCC_CTRLA_PRESCSYNC_RESYNC (TCC_CTRLA_PRESCSYNC_RESYNC_Val << TCC_CTRLA_PRESCSYNC_Pos)
mbed_official 579:53297373a894 90 #define TCC_CTRLA_ALOCK_Pos 14 /**< \brief (TCC_CTRLA) Auto Lock */
mbed_official 579:53297373a894 91 #define TCC_CTRLA_ALOCK (0x1ul << TCC_CTRLA_ALOCK_Pos)
mbed_official 579:53297373a894 92 #define TCC_CTRLA_CPTEN0_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel 0 Enable */
mbed_official 579:53297373a894 93 #define TCC_CTRLA_CPTEN0 (1 << TCC_CTRLA_CPTEN0_Pos)
mbed_official 579:53297373a894 94 #define TCC_CTRLA_CPTEN1_Pos 25 /**< \brief (TCC_CTRLA) Capture Channel 1 Enable */
mbed_official 579:53297373a894 95 #define TCC_CTRLA_CPTEN1 (1 << TCC_CTRLA_CPTEN1_Pos)
mbed_official 579:53297373a894 96 #define TCC_CTRLA_CPTEN2_Pos 26 /**< \brief (TCC_CTRLA) Capture Channel 2 Enable */
mbed_official 579:53297373a894 97 #define TCC_CTRLA_CPTEN2 (1 << TCC_CTRLA_CPTEN2_Pos)
mbed_official 579:53297373a894 98 #define TCC_CTRLA_CPTEN3_Pos 27 /**< \brief (TCC_CTRLA) Capture Channel 3 Enable */
mbed_official 579:53297373a894 99 #define TCC_CTRLA_CPTEN3 (1 << TCC_CTRLA_CPTEN3_Pos)
mbed_official 579:53297373a894 100 #define TCC_CTRLA_CPTEN_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel x Enable */
mbed_official 579:53297373a894 101 #define TCC_CTRLA_CPTEN_Msk (0xFul << TCC_CTRLA_CPTEN_Pos)
mbed_official 579:53297373a894 102 #define TCC_CTRLA_CPTEN(value) ((TCC_CTRLA_CPTEN_Msk & ((value) << TCC_CTRLA_CPTEN_Pos)))
mbed_official 579:53297373a894 103 #define TCC_CTRLA_MASK 0x0F007F63ul /**< \brief (TCC_CTRLA) MASK Register */
mbed_official 579:53297373a894 104
mbed_official 579:53297373a894 105 /* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W 8) Control B Clear -------- */
mbed_official 579:53297373a894 106 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 107 typedef union {
mbed_official 579:53297373a894 108 struct {
mbed_official 579:53297373a894 109 uint8_t DIR:1; /*!< bit: 0 Counter Direction */
mbed_official 579:53297373a894 110 uint8_t LUPD:1; /*!< bit: 1 Lock Update */
mbed_official 579:53297373a894 111 uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
mbed_official 579:53297373a894 112 uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
mbed_official 579:53297373a894 113 uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
mbed_official 579:53297373a894 114 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 115 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 116 } TCC_CTRLBCLR_Type;
mbed_official 579:53297373a894 117 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 118
mbed_official 579:53297373a894 119 #define TCC_CTRLBCLR_OFFSET 0x04 /**< \brief (TCC_CTRLBCLR offset) Control B Clear */
mbed_official 579:53297373a894 120 #define TCC_CTRLBCLR_RESETVALUE 0x00ul /**< \brief (TCC_CTRLBCLR reset_value) Control B Clear */
mbed_official 579:53297373a894 121
mbed_official 579:53297373a894 122 #define TCC_CTRLBCLR_DIR_Pos 0 /**< \brief (TCC_CTRLBCLR) Counter Direction */
mbed_official 579:53297373a894 123 #define TCC_CTRLBCLR_DIR (0x1ul << TCC_CTRLBCLR_DIR_Pos)
mbed_official 579:53297373a894 124 #define TCC_CTRLBCLR_LUPD_Pos 1 /**< \brief (TCC_CTRLBCLR) Lock Update */
mbed_official 579:53297373a894 125 #define TCC_CTRLBCLR_LUPD (0x1ul << TCC_CTRLBCLR_LUPD_Pos)
mbed_official 579:53297373a894 126 #define TCC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TCC_CTRLBCLR) One-Shot */
mbed_official 579:53297373a894 127 #define TCC_CTRLBCLR_ONESHOT (0x1ul << TCC_CTRLBCLR_ONESHOT_Pos)
mbed_official 579:53297373a894 128 #define TCC_CTRLBCLR_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBCLR) Ramp Index Command */
mbed_official 579:53297373a894 129 #define TCC_CTRLBCLR_IDXCMD_Msk (0x3ul << TCC_CTRLBCLR_IDXCMD_Pos)
mbed_official 579:53297373a894 130 #define TCC_CTRLBCLR_IDXCMD(value) ((TCC_CTRLBCLR_IDXCMD_Msk & ((value) << TCC_CTRLBCLR_IDXCMD_Pos)))
mbed_official 579:53297373a894 131 #define TCC_CTRLBCLR_IDXCMD_DISABLE_Val 0x0ul /**< \brief (TCC_CTRLBCLR) Command disabled: Index toggles between cycles A and B */
mbed_official 579:53297373a894 132 #define TCC_CTRLBCLR_IDXCMD_SET_Val 0x1ul /**< \brief (TCC_CTRLBCLR) Set index: cycle B will be forced in the next cycle */
mbed_official 579:53297373a894 133 #define TCC_CTRLBCLR_IDXCMD_CLEAR_Val 0x2ul /**< \brief (TCC_CTRLBCLR) Clear index: cycle A will be forced in the next cycle */
mbed_official 579:53297373a894 134 #define TCC_CTRLBCLR_IDXCMD_HOLD_Val 0x3ul /**< \brief (TCC_CTRLBCLR) Hold index: the next cycle will be the same as the current cycle */
mbed_official 579:53297373a894 135 #define TCC_CTRLBCLR_IDXCMD_DISABLE (TCC_CTRLBCLR_IDXCMD_DISABLE_Val << TCC_CTRLBCLR_IDXCMD_Pos)
mbed_official 579:53297373a894 136 #define TCC_CTRLBCLR_IDXCMD_SET (TCC_CTRLBCLR_IDXCMD_SET_Val << TCC_CTRLBCLR_IDXCMD_Pos)
mbed_official 579:53297373a894 137 #define TCC_CTRLBCLR_IDXCMD_CLEAR (TCC_CTRLBCLR_IDXCMD_CLEAR_Val << TCC_CTRLBCLR_IDXCMD_Pos)
mbed_official 579:53297373a894 138 #define TCC_CTRLBCLR_IDXCMD_HOLD (TCC_CTRLBCLR_IDXCMD_HOLD_Val << TCC_CTRLBCLR_IDXCMD_Pos)
mbed_official 579:53297373a894 139 #define TCC_CTRLBCLR_CMD_Pos 5 /**< \brief (TCC_CTRLBCLR) TCC Command */
mbed_official 579:53297373a894 140 #define TCC_CTRLBCLR_CMD_Msk (0x7ul << TCC_CTRLBCLR_CMD_Pos)
mbed_official 579:53297373a894 141 #define TCC_CTRLBCLR_CMD(value) ((TCC_CTRLBCLR_CMD_Msk & ((value) << TCC_CTRLBCLR_CMD_Pos)))
mbed_official 579:53297373a894 142 #define TCC_CTRLBCLR_CMD_NONE_Val 0x0ul /**< \brief (TCC_CTRLBCLR) No action */
mbed_official 579:53297373a894 143 #define TCC_CTRLBCLR_CMD_RETRIGGER_Val 0x1ul /**< \brief (TCC_CTRLBCLR) Clear start, restart or retrigger */
mbed_official 579:53297373a894 144 #define TCC_CTRLBCLR_CMD_STOP_Val 0x2ul /**< \brief (TCC_CTRLBCLR) Force stop */
mbed_official 579:53297373a894 145 #define TCC_CTRLBCLR_CMD_UPDATE_Val 0x3ul /**< \brief (TCC_CTRLBCLR) Force update of double buffered registers */
mbed_official 579:53297373a894 146 #define TCC_CTRLBCLR_CMD_READSYNC_Val 0x4ul /**< \brief (TCC_CTRLBCLR) Force COUNT read synchronization */
mbed_official 579:53297373a894 147 #define TCC_CTRLBCLR_CMD_NONE (TCC_CTRLBCLR_CMD_NONE_Val << TCC_CTRLBCLR_CMD_Pos)
mbed_official 579:53297373a894 148 #define TCC_CTRLBCLR_CMD_RETRIGGER (TCC_CTRLBCLR_CMD_RETRIGGER_Val << TCC_CTRLBCLR_CMD_Pos)
mbed_official 579:53297373a894 149 #define TCC_CTRLBCLR_CMD_STOP (TCC_CTRLBCLR_CMD_STOP_Val << TCC_CTRLBCLR_CMD_Pos)
mbed_official 579:53297373a894 150 #define TCC_CTRLBCLR_CMD_UPDATE (TCC_CTRLBCLR_CMD_UPDATE_Val << TCC_CTRLBCLR_CMD_Pos)
mbed_official 579:53297373a894 151 #define TCC_CTRLBCLR_CMD_READSYNC (TCC_CTRLBCLR_CMD_READSYNC_Val << TCC_CTRLBCLR_CMD_Pos)
mbed_official 579:53297373a894 152 #define TCC_CTRLBCLR_MASK 0xFFul /**< \brief (TCC_CTRLBCLR) MASK Register */
mbed_official 579:53297373a894 153
mbed_official 579:53297373a894 154 /* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W 8) Control B Set -------- */
mbed_official 579:53297373a894 155 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 156 typedef union {
mbed_official 579:53297373a894 157 struct {
mbed_official 579:53297373a894 158 uint8_t DIR:1; /*!< bit: 0 Counter Direction */
mbed_official 579:53297373a894 159 uint8_t LUPD:1; /*!< bit: 1 Lock Update */
mbed_official 579:53297373a894 160 uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
mbed_official 579:53297373a894 161 uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
mbed_official 579:53297373a894 162 uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
mbed_official 579:53297373a894 163 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 164 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 165 } TCC_CTRLBSET_Type;
mbed_official 579:53297373a894 166 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 167
mbed_official 579:53297373a894 168 #define TCC_CTRLBSET_OFFSET 0x05 /**< \brief (TCC_CTRLBSET offset) Control B Set */
mbed_official 579:53297373a894 169 #define TCC_CTRLBSET_RESETVALUE 0x00ul /**< \brief (TCC_CTRLBSET reset_value) Control B Set */
mbed_official 579:53297373a894 170
mbed_official 579:53297373a894 171 #define TCC_CTRLBSET_DIR_Pos 0 /**< \brief (TCC_CTRLBSET) Counter Direction */
mbed_official 579:53297373a894 172 #define TCC_CTRLBSET_DIR (0x1ul << TCC_CTRLBSET_DIR_Pos)
mbed_official 579:53297373a894 173 #define TCC_CTRLBSET_LUPD_Pos 1 /**< \brief (TCC_CTRLBSET) Lock Update */
mbed_official 579:53297373a894 174 #define TCC_CTRLBSET_LUPD (0x1ul << TCC_CTRLBSET_LUPD_Pos)
mbed_official 579:53297373a894 175 #define TCC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TCC_CTRLBSET) One-Shot */
mbed_official 579:53297373a894 176 #define TCC_CTRLBSET_ONESHOT (0x1ul << TCC_CTRLBSET_ONESHOT_Pos)
mbed_official 579:53297373a894 177 #define TCC_CTRLBSET_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBSET) Ramp Index Command */
mbed_official 579:53297373a894 178 #define TCC_CTRLBSET_IDXCMD_Msk (0x3ul << TCC_CTRLBSET_IDXCMD_Pos)
mbed_official 579:53297373a894 179 #define TCC_CTRLBSET_IDXCMD(value) ((TCC_CTRLBSET_IDXCMD_Msk & ((value) << TCC_CTRLBSET_IDXCMD_Pos)))
mbed_official 579:53297373a894 180 #define TCC_CTRLBSET_IDXCMD_DISABLE_Val 0x0ul /**< \brief (TCC_CTRLBSET) Command disabled: Index toggles between cycles A and B */
mbed_official 579:53297373a894 181 #define TCC_CTRLBSET_IDXCMD_SET_Val 0x1ul /**< \brief (TCC_CTRLBSET) Set index: cycle B will be forced in the next cycle */
mbed_official 579:53297373a894 182 #define TCC_CTRLBSET_IDXCMD_CLEAR_Val 0x2ul /**< \brief (TCC_CTRLBSET) Clear index: cycle A will be forced in the next cycle */
mbed_official 579:53297373a894 183 #define TCC_CTRLBSET_IDXCMD_HOLD_Val 0x3ul /**< \brief (TCC_CTRLBSET) Hold index: the next cycle will be the same as the current cycle */
mbed_official 579:53297373a894 184 #define TCC_CTRLBSET_IDXCMD_DISABLE (TCC_CTRLBSET_IDXCMD_DISABLE_Val << TCC_CTRLBSET_IDXCMD_Pos)
mbed_official 579:53297373a894 185 #define TCC_CTRLBSET_IDXCMD_SET (TCC_CTRLBSET_IDXCMD_SET_Val << TCC_CTRLBSET_IDXCMD_Pos)
mbed_official 579:53297373a894 186 #define TCC_CTRLBSET_IDXCMD_CLEAR (TCC_CTRLBSET_IDXCMD_CLEAR_Val << TCC_CTRLBSET_IDXCMD_Pos)
mbed_official 579:53297373a894 187 #define TCC_CTRLBSET_IDXCMD_HOLD (TCC_CTRLBSET_IDXCMD_HOLD_Val << TCC_CTRLBSET_IDXCMD_Pos)
mbed_official 579:53297373a894 188 #define TCC_CTRLBSET_CMD_Pos 5 /**< \brief (TCC_CTRLBSET) TCC Command */
mbed_official 579:53297373a894 189 #define TCC_CTRLBSET_CMD_Msk (0x7ul << TCC_CTRLBSET_CMD_Pos)
mbed_official 579:53297373a894 190 #define TCC_CTRLBSET_CMD(value) ((TCC_CTRLBSET_CMD_Msk & ((value) << TCC_CTRLBSET_CMD_Pos)))
mbed_official 579:53297373a894 191 #define TCC_CTRLBSET_CMD_NONE_Val 0x0ul /**< \brief (TCC_CTRLBSET) No action */
mbed_official 579:53297373a894 192 #define TCC_CTRLBSET_CMD_RETRIGGER_Val 0x1ul /**< \brief (TCC_CTRLBSET) Clear start, restart or retrigger */
mbed_official 579:53297373a894 193 #define TCC_CTRLBSET_CMD_STOP_Val 0x2ul /**< \brief (TCC_CTRLBSET) Force stop */
mbed_official 579:53297373a894 194 #define TCC_CTRLBSET_CMD_UPDATE_Val 0x3ul /**< \brief (TCC_CTRLBSET) Force update of double buffered registers */
mbed_official 579:53297373a894 195 #define TCC_CTRLBSET_CMD_READSYNC_Val 0x4ul /**< \brief (TCC_CTRLBSET) Force COUNT read synchronization */
mbed_official 579:53297373a894 196 #define TCC_CTRLBSET_CMD_NONE (TCC_CTRLBSET_CMD_NONE_Val << TCC_CTRLBSET_CMD_Pos)
mbed_official 579:53297373a894 197 #define TCC_CTRLBSET_CMD_RETRIGGER (TCC_CTRLBSET_CMD_RETRIGGER_Val << TCC_CTRLBSET_CMD_Pos)
mbed_official 579:53297373a894 198 #define TCC_CTRLBSET_CMD_STOP (TCC_CTRLBSET_CMD_STOP_Val << TCC_CTRLBSET_CMD_Pos)
mbed_official 579:53297373a894 199 #define TCC_CTRLBSET_CMD_UPDATE (TCC_CTRLBSET_CMD_UPDATE_Val << TCC_CTRLBSET_CMD_Pos)
mbed_official 579:53297373a894 200 #define TCC_CTRLBSET_CMD_READSYNC (TCC_CTRLBSET_CMD_READSYNC_Val << TCC_CTRLBSET_CMD_Pos)
mbed_official 579:53297373a894 201 #define TCC_CTRLBSET_MASK 0xFFul /**< \brief (TCC_CTRLBSET) MASK Register */
mbed_official 579:53297373a894 202
mbed_official 579:53297373a894 203 /* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/ 32) Synchronization Busy -------- */
mbed_official 579:53297373a894 204 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 205 typedef union {
mbed_official 579:53297373a894 206 struct {
mbed_official 579:53297373a894 207 uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */
mbed_official 579:53297373a894 208 uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */
mbed_official 579:53297373a894 209 uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */
mbed_official 579:53297373a894 210 uint32_t STATUS:1; /*!< bit: 3 Status Busy */
mbed_official 579:53297373a894 211 uint32_t COUNT:1; /*!< bit: 4 Count Busy */
mbed_official 579:53297373a894 212 uint32_t PATT:1; /*!< bit: 5 Pattern Busy */
mbed_official 579:53297373a894 213 uint32_t WAVE:1; /*!< bit: 6 Wave Busy */
mbed_official 579:53297373a894 214 uint32_t PER:1; /*!< bit: 7 Period busy */
mbed_official 579:53297373a894 215 uint32_t CC0:1; /*!< bit: 8 Compare Channel 0 Busy */
mbed_official 579:53297373a894 216 uint32_t CC1:1; /*!< bit: 9 Compare Channel 1 Busy */
mbed_official 579:53297373a894 217 uint32_t CC2:1; /*!< bit: 10 Compare Channel 2 Busy */
mbed_official 579:53297373a894 218 uint32_t CC3:1; /*!< bit: 11 Compare Channel 3 Busy */
mbed_official 579:53297373a894 219 uint32_t :4; /*!< bit: 12..15 Reserved */
mbed_official 579:53297373a894 220 uint32_t PATTB:1; /*!< bit: 16 Pattern Buffer Busy */
mbed_official 579:53297373a894 221 uint32_t WAVEB:1; /*!< bit: 17 Wave Buffer Busy */
mbed_official 579:53297373a894 222 uint32_t PERB:1; /*!< bit: 18 Period Buffer Busy */
mbed_official 579:53297373a894 223 uint32_t CCB0:1; /*!< bit: 19 Compare Channel Buffer 0 Busy */
mbed_official 579:53297373a894 224 uint32_t CCB1:1; /*!< bit: 20 Compare Channel Buffer 1 Busy */
mbed_official 579:53297373a894 225 uint32_t CCB2:1; /*!< bit: 21 Compare Channel Buffer 2 Busy */
mbed_official 579:53297373a894 226 uint32_t CCB3:1; /*!< bit: 22 Compare Channel Buffer 3 Busy */
mbed_official 579:53297373a894 227 uint32_t :9; /*!< bit: 23..31 Reserved */
mbed_official 579:53297373a894 228 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 229 struct {
mbed_official 579:53297373a894 230 uint32_t :8; /*!< bit: 0.. 7 Reserved */
mbed_official 579:53297373a894 231 uint32_t CC:4; /*!< bit: 8..11 Compare Channel x Busy */
mbed_official 579:53297373a894 232 uint32_t :7; /*!< bit: 12..18 Reserved */
mbed_official 579:53297373a894 233 uint32_t CCB:4; /*!< bit: 19..22 Compare Channel Buffer x Busy */
mbed_official 579:53297373a894 234 uint32_t :9; /*!< bit: 23..31 Reserved */
mbed_official 579:53297373a894 235 } vec; /*!< Structure used for vec access */
mbed_official 579:53297373a894 236 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 237 } TCC_SYNCBUSY_Type;
mbed_official 579:53297373a894 238 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 239
mbed_official 579:53297373a894 240 #define TCC_SYNCBUSY_OFFSET 0x08 /**< \brief (TCC_SYNCBUSY offset) Synchronization Busy */
mbed_official 579:53297373a894 241 #define TCC_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (TCC_SYNCBUSY reset_value) Synchronization Busy */
mbed_official 579:53297373a894 242
mbed_official 579:53297373a894 243 #define TCC_SYNCBUSY_SWRST_Pos 0 /**< \brief (TCC_SYNCBUSY) Swrst Busy */
mbed_official 579:53297373a894 244 #define TCC_SYNCBUSY_SWRST (0x1ul << TCC_SYNCBUSY_SWRST_Pos)
mbed_official 579:53297373a894 245 #define TCC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (TCC_SYNCBUSY) Enable Busy */
mbed_official 579:53297373a894 246 #define TCC_SYNCBUSY_ENABLE (0x1ul << TCC_SYNCBUSY_ENABLE_Pos)
mbed_official 579:53297373a894 247 #define TCC_SYNCBUSY_CTRLB_Pos 2 /**< \brief (TCC_SYNCBUSY) Ctrlb Busy */
mbed_official 579:53297373a894 248 #define TCC_SYNCBUSY_CTRLB (0x1ul << TCC_SYNCBUSY_CTRLB_Pos)
mbed_official 579:53297373a894 249 #define TCC_SYNCBUSY_STATUS_Pos 3 /**< \brief (TCC_SYNCBUSY) Status Busy */
mbed_official 579:53297373a894 250 #define TCC_SYNCBUSY_STATUS (0x1ul << TCC_SYNCBUSY_STATUS_Pos)
mbed_official 579:53297373a894 251 #define TCC_SYNCBUSY_COUNT_Pos 4 /**< \brief (TCC_SYNCBUSY) Count Busy */
mbed_official 579:53297373a894 252 #define TCC_SYNCBUSY_COUNT (0x1ul << TCC_SYNCBUSY_COUNT_Pos)
mbed_official 579:53297373a894 253 #define TCC_SYNCBUSY_PATT_Pos 5 /**< \brief (TCC_SYNCBUSY) Pattern Busy */
mbed_official 579:53297373a894 254 #define TCC_SYNCBUSY_PATT (0x1ul << TCC_SYNCBUSY_PATT_Pos)
mbed_official 579:53297373a894 255 #define TCC_SYNCBUSY_WAVE_Pos 6 /**< \brief (TCC_SYNCBUSY) Wave Busy */
mbed_official 579:53297373a894 256 #define TCC_SYNCBUSY_WAVE (0x1ul << TCC_SYNCBUSY_WAVE_Pos)
mbed_official 579:53297373a894 257 #define TCC_SYNCBUSY_PER_Pos 7 /**< \brief (TCC_SYNCBUSY) Period busy */
mbed_official 579:53297373a894 258 #define TCC_SYNCBUSY_PER (0x1ul << TCC_SYNCBUSY_PER_Pos)
mbed_official 579:53297373a894 259 #define TCC_SYNCBUSY_CC0_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel 0 Busy */
mbed_official 579:53297373a894 260 #define TCC_SYNCBUSY_CC0 (1 << TCC_SYNCBUSY_CC0_Pos)
mbed_official 579:53297373a894 261 #define TCC_SYNCBUSY_CC1_Pos 9 /**< \brief (TCC_SYNCBUSY) Compare Channel 1 Busy */
mbed_official 579:53297373a894 262 #define TCC_SYNCBUSY_CC1 (1 << TCC_SYNCBUSY_CC1_Pos)
mbed_official 579:53297373a894 263 #define TCC_SYNCBUSY_CC2_Pos 10 /**< \brief (TCC_SYNCBUSY) Compare Channel 2 Busy */
mbed_official 579:53297373a894 264 #define TCC_SYNCBUSY_CC2 (1 << TCC_SYNCBUSY_CC2_Pos)
mbed_official 579:53297373a894 265 #define TCC_SYNCBUSY_CC3_Pos 11 /**< \brief (TCC_SYNCBUSY) Compare Channel 3 Busy */
mbed_official 579:53297373a894 266 #define TCC_SYNCBUSY_CC3 (1 << TCC_SYNCBUSY_CC3_Pos)
mbed_official 579:53297373a894 267 #define TCC_SYNCBUSY_CC_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel x Busy */
mbed_official 579:53297373a894 268 #define TCC_SYNCBUSY_CC_Msk (0xFul << TCC_SYNCBUSY_CC_Pos)
mbed_official 579:53297373a894 269 #define TCC_SYNCBUSY_CC(value) ((TCC_SYNCBUSY_CC_Msk & ((value) << TCC_SYNCBUSY_CC_Pos)))
mbed_official 579:53297373a894 270 #define TCC_SYNCBUSY_PATTB_Pos 16 /**< \brief (TCC_SYNCBUSY) Pattern Buffer Busy */
mbed_official 579:53297373a894 271 #define TCC_SYNCBUSY_PATTB (0x1ul << TCC_SYNCBUSY_PATTB_Pos)
mbed_official 579:53297373a894 272 #define TCC_SYNCBUSY_WAVEB_Pos 17 /**< \brief (TCC_SYNCBUSY) Wave Buffer Busy */
mbed_official 579:53297373a894 273 #define TCC_SYNCBUSY_WAVEB (0x1ul << TCC_SYNCBUSY_WAVEB_Pos)
mbed_official 579:53297373a894 274 #define TCC_SYNCBUSY_PERB_Pos 18 /**< \brief (TCC_SYNCBUSY) Period Buffer Busy */
mbed_official 579:53297373a894 275 #define TCC_SYNCBUSY_PERB (0x1ul << TCC_SYNCBUSY_PERB_Pos)
mbed_official 579:53297373a894 276 #define TCC_SYNCBUSY_CCB0_Pos 19 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 0 Busy */
mbed_official 579:53297373a894 277 #define TCC_SYNCBUSY_CCB0 (1 << TCC_SYNCBUSY_CCB0_Pos)
mbed_official 579:53297373a894 278 #define TCC_SYNCBUSY_CCB1_Pos 20 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 1 Busy */
mbed_official 579:53297373a894 279 #define TCC_SYNCBUSY_CCB1 (1 << TCC_SYNCBUSY_CCB1_Pos)
mbed_official 579:53297373a894 280 #define TCC_SYNCBUSY_CCB2_Pos 21 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 2 Busy */
mbed_official 579:53297373a894 281 #define TCC_SYNCBUSY_CCB2 (1 << TCC_SYNCBUSY_CCB2_Pos)
mbed_official 579:53297373a894 282 #define TCC_SYNCBUSY_CCB3_Pos 22 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 3 Busy */
mbed_official 579:53297373a894 283 #define TCC_SYNCBUSY_CCB3 (1 << TCC_SYNCBUSY_CCB3_Pos)
mbed_official 579:53297373a894 284 #define TCC_SYNCBUSY_CCB_Pos 19 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer x Busy */
mbed_official 579:53297373a894 285 #define TCC_SYNCBUSY_CCB_Msk (0xFul << TCC_SYNCBUSY_CCB_Pos)
mbed_official 579:53297373a894 286 #define TCC_SYNCBUSY_CCB(value) ((TCC_SYNCBUSY_CCB_Msk & ((value) << TCC_SYNCBUSY_CCB_Pos)))
mbed_official 579:53297373a894 287 #define TCC_SYNCBUSY_MASK 0x007F0FFFul /**< \brief (TCC_SYNCBUSY) MASK Register */
mbed_official 579:53297373a894 288
mbed_official 579:53297373a894 289 /* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */
mbed_official 579:53297373a894 290 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 291 typedef union {
mbed_official 579:53297373a894 292 struct {
mbed_official 579:53297373a894 293 uint32_t SRC:2; /*!< bit: 0.. 1 Fault A Source */
mbed_official 579:53297373a894 294 uint32_t :1; /*!< bit: 2 Reserved */
mbed_official 579:53297373a894 295 uint32_t KEEP:1; /*!< bit: 3 Fault A Keeper */
mbed_official 579:53297373a894 296 uint32_t QUAL:1; /*!< bit: 4 Fault A Qualification */
mbed_official 579:53297373a894 297 uint32_t BLANK:2; /*!< bit: 5.. 6 Fault A Blanking Mode */
mbed_official 579:53297373a894 298 uint32_t RESTART:1; /*!< bit: 7 Fault A Restart */
mbed_official 579:53297373a894 299 uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */
mbed_official 579:53297373a894 300 uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */
mbed_official 579:53297373a894 301 uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */
mbed_official 579:53297373a894 302 uint32_t :1; /*!< bit: 15 Reserved */
mbed_official 579:53297373a894 303 uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */
mbed_official 579:53297373a894 304 uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */
mbed_official 579:53297373a894 305 uint32_t :4; /*!< bit: 28..31 Reserved */
mbed_official 579:53297373a894 306 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 307 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 308 } TCC_FCTRLA_Type;
mbed_official 579:53297373a894 309 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 310
mbed_official 579:53297373a894 311 #define TCC_FCTRLA_OFFSET 0x0C /**< \brief (TCC_FCTRLA offset) Recoverable Fault A Configuration */
mbed_official 579:53297373a894 312 #define TCC_FCTRLA_RESETVALUE 0x00000000ul /**< \brief (TCC_FCTRLA reset_value) Recoverable Fault A Configuration */
mbed_official 579:53297373a894 313
mbed_official 579:53297373a894 314 #define TCC_FCTRLA_SRC_Pos 0 /**< \brief (TCC_FCTRLA) Fault A Source */
mbed_official 579:53297373a894 315 #define TCC_FCTRLA_SRC_Msk (0x3ul << TCC_FCTRLA_SRC_Pos)
mbed_official 579:53297373a894 316 #define TCC_FCTRLA_SRC(value) ((TCC_FCTRLA_SRC_Msk & ((value) << TCC_FCTRLA_SRC_Pos)))
mbed_official 579:53297373a894 317 #define TCC_FCTRLA_SRC_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) Fault input disabled */
mbed_official 579:53297373a894 318 #define TCC_FCTRLA_SRC_ENABLE_Val 0x1ul /**< \brief (TCC_FCTRLA) MCEx (x=0,1) event input */
mbed_official 579:53297373a894 319 #define TCC_FCTRLA_SRC_INVERT_Val 0x2ul /**< \brief (TCC_FCTRLA) Inverted MCEx (x=0,1) event input */
mbed_official 579:53297373a894 320 #define TCC_FCTRLA_SRC_ALTFAULT_Val 0x3ul /**< \brief (TCC_FCTRLA) Alternate fault (A or B) state at the end of the previous period */
mbed_official 579:53297373a894 321 #define TCC_FCTRLA_SRC_DISABLE (TCC_FCTRLA_SRC_DISABLE_Val << TCC_FCTRLA_SRC_Pos)
mbed_official 579:53297373a894 322 #define TCC_FCTRLA_SRC_ENABLE (TCC_FCTRLA_SRC_ENABLE_Val << TCC_FCTRLA_SRC_Pos)
mbed_official 579:53297373a894 323 #define TCC_FCTRLA_SRC_INVERT (TCC_FCTRLA_SRC_INVERT_Val << TCC_FCTRLA_SRC_Pos)
mbed_official 579:53297373a894 324 #define TCC_FCTRLA_SRC_ALTFAULT (TCC_FCTRLA_SRC_ALTFAULT_Val << TCC_FCTRLA_SRC_Pos)
mbed_official 579:53297373a894 325 #define TCC_FCTRLA_KEEP_Pos 3 /**< \brief (TCC_FCTRLA) Fault A Keeper */
mbed_official 579:53297373a894 326 #define TCC_FCTRLA_KEEP (0x1ul << TCC_FCTRLA_KEEP_Pos)
mbed_official 579:53297373a894 327 #define TCC_FCTRLA_QUAL_Pos 4 /**< \brief (TCC_FCTRLA) Fault A Qualification */
mbed_official 579:53297373a894 328 #define TCC_FCTRLA_QUAL (0x1ul << TCC_FCTRLA_QUAL_Pos)
mbed_official 579:53297373a894 329 #define TCC_FCTRLA_BLANK_Pos 5 /**< \brief (TCC_FCTRLA) Fault A Blanking Mode */
mbed_official 579:53297373a894 330 #define TCC_FCTRLA_BLANK_Msk (0x3ul << TCC_FCTRLA_BLANK_Pos)
mbed_official 579:53297373a894 331 #define TCC_FCTRLA_BLANK(value) ((TCC_FCTRLA_BLANK_Msk & ((value) << TCC_FCTRLA_BLANK_Pos)))
mbed_official 579:53297373a894 332 #define TCC_FCTRLA_BLANK_NONE_Val 0x0ul /**< \brief (TCC_FCTRLA) No blanking applied */
mbed_official 579:53297373a894 333 #define TCC_FCTRLA_BLANK_RISE_Val 0x1ul /**< \brief (TCC_FCTRLA) Blanking applied from rising edge of the output waveform */
mbed_official 579:53297373a894 334 #define TCC_FCTRLA_BLANK_FALL_Val 0x2ul /**< \brief (TCC_FCTRLA) Blanking applied from falling edge of the output waveform */
mbed_official 579:53297373a894 335 #define TCC_FCTRLA_BLANK_BOTH_Val 0x3ul /**< \brief (TCC_FCTRLA) Blanking applied from each toggle of the output waveform */
mbed_official 579:53297373a894 336 #define TCC_FCTRLA_BLANK_NONE (TCC_FCTRLA_BLANK_NONE_Val << TCC_FCTRLA_BLANK_Pos)
mbed_official 579:53297373a894 337 #define TCC_FCTRLA_BLANK_RISE (TCC_FCTRLA_BLANK_RISE_Val << TCC_FCTRLA_BLANK_Pos)
mbed_official 579:53297373a894 338 #define TCC_FCTRLA_BLANK_FALL (TCC_FCTRLA_BLANK_FALL_Val << TCC_FCTRLA_BLANK_Pos)
mbed_official 579:53297373a894 339 #define TCC_FCTRLA_BLANK_BOTH (TCC_FCTRLA_BLANK_BOTH_Val << TCC_FCTRLA_BLANK_Pos)
mbed_official 579:53297373a894 340 #define TCC_FCTRLA_RESTART_Pos 7 /**< \brief (TCC_FCTRLA) Fault A Restart */
mbed_official 579:53297373a894 341 #define TCC_FCTRLA_RESTART (0x1ul << TCC_FCTRLA_RESTART_Pos)
mbed_official 579:53297373a894 342 #define TCC_FCTRLA_HALT_Pos 8 /**< \brief (TCC_FCTRLA) Fault A Halt Mode */
mbed_official 579:53297373a894 343 #define TCC_FCTRLA_HALT_Msk (0x3ul << TCC_FCTRLA_HALT_Pos)
mbed_official 579:53297373a894 344 #define TCC_FCTRLA_HALT(value) ((TCC_FCTRLA_HALT_Msk & ((value) << TCC_FCTRLA_HALT_Pos)))
mbed_official 579:53297373a894 345 #define TCC_FCTRLA_HALT_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) Halt action disabled */
mbed_official 579:53297373a894 346 #define TCC_FCTRLA_HALT_HW_Val 0x1ul /**< \brief (TCC_FCTRLA) Hardware halt action */
mbed_official 579:53297373a894 347 #define TCC_FCTRLA_HALT_SW_Val 0x2ul /**< \brief (TCC_FCTRLA) Software halt action */
mbed_official 579:53297373a894 348 #define TCC_FCTRLA_HALT_NR_Val 0x3ul /**< \brief (TCC_FCTRLA) Non-recoverable fault */
mbed_official 579:53297373a894 349 #define TCC_FCTRLA_HALT_DISABLE (TCC_FCTRLA_HALT_DISABLE_Val << TCC_FCTRLA_HALT_Pos)
mbed_official 579:53297373a894 350 #define TCC_FCTRLA_HALT_HW (TCC_FCTRLA_HALT_HW_Val << TCC_FCTRLA_HALT_Pos)
mbed_official 579:53297373a894 351 #define TCC_FCTRLA_HALT_SW (TCC_FCTRLA_HALT_SW_Val << TCC_FCTRLA_HALT_Pos)
mbed_official 579:53297373a894 352 #define TCC_FCTRLA_HALT_NR (TCC_FCTRLA_HALT_NR_Val << TCC_FCTRLA_HALT_Pos)
mbed_official 579:53297373a894 353 #define TCC_FCTRLA_CHSEL_Pos 10 /**< \brief (TCC_FCTRLA) Fault A Capture Channel */
mbed_official 579:53297373a894 354 #define TCC_FCTRLA_CHSEL_Msk (0x3ul << TCC_FCTRLA_CHSEL_Pos)
mbed_official 579:53297373a894 355 #define TCC_FCTRLA_CHSEL(value) ((TCC_FCTRLA_CHSEL_Msk & ((value) << TCC_FCTRLA_CHSEL_Pos)))
mbed_official 579:53297373a894 356 #define TCC_FCTRLA_CHSEL_CC0_Val 0x0ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 0 */
mbed_official 579:53297373a894 357 #define TCC_FCTRLA_CHSEL_CC1_Val 0x1ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 1 */
mbed_official 579:53297373a894 358 #define TCC_FCTRLA_CHSEL_CC2_Val 0x2ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 2 */
mbed_official 579:53297373a894 359 #define TCC_FCTRLA_CHSEL_CC3_Val 0x3ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 3 */
mbed_official 579:53297373a894 360 #define TCC_FCTRLA_CHSEL_CC0 (TCC_FCTRLA_CHSEL_CC0_Val << TCC_FCTRLA_CHSEL_Pos)
mbed_official 579:53297373a894 361 #define TCC_FCTRLA_CHSEL_CC1 (TCC_FCTRLA_CHSEL_CC1_Val << TCC_FCTRLA_CHSEL_Pos)
mbed_official 579:53297373a894 362 #define TCC_FCTRLA_CHSEL_CC2 (TCC_FCTRLA_CHSEL_CC2_Val << TCC_FCTRLA_CHSEL_Pos)
mbed_official 579:53297373a894 363 #define TCC_FCTRLA_CHSEL_CC3 (TCC_FCTRLA_CHSEL_CC3_Val << TCC_FCTRLA_CHSEL_Pos)
mbed_official 579:53297373a894 364 #define TCC_FCTRLA_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLA) Fault A Capture Action */
mbed_official 579:53297373a894 365 #define TCC_FCTRLA_CAPTURE_Msk (0x7ul << TCC_FCTRLA_CAPTURE_Pos)
mbed_official 579:53297373a894 366 #define TCC_FCTRLA_CAPTURE(value) ((TCC_FCTRLA_CAPTURE_Msk & ((value) << TCC_FCTRLA_CAPTURE_Pos)))
mbed_official 579:53297373a894 367 #define TCC_FCTRLA_CAPTURE_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) No capture */
mbed_official 579:53297373a894 368 #define TCC_FCTRLA_CAPTURE_CAPT_Val 0x1ul /**< \brief (TCC_FCTRLA) Capture on fault */
mbed_official 579:53297373a894 369 #define TCC_FCTRLA_CAPTURE_CAPTMIN_Val 0x2ul /**< \brief (TCC_FCTRLA) Minimum capture */
mbed_official 579:53297373a894 370 #define TCC_FCTRLA_CAPTURE_CAPTMAX_Val 0x3ul /**< \brief (TCC_FCTRLA) Maximum capture */
mbed_official 579:53297373a894 371 #define TCC_FCTRLA_CAPTURE_LOCMIN_Val 0x4ul /**< \brief (TCC_FCTRLA) Minimum local detection */
mbed_official 579:53297373a894 372 #define TCC_FCTRLA_CAPTURE_LOCMAX_Val 0x5ul /**< \brief (TCC_FCTRLA) Maximum local detection */
mbed_official 579:53297373a894 373 #define TCC_FCTRLA_CAPTURE_DERIV0_Val 0x6ul /**< \brief (TCC_FCTRLA) Minimum and maximum local detection */
mbed_official 579:53297373a894 374 #define TCC_FCTRLA_CAPTURE_DISABLE (TCC_FCTRLA_CAPTURE_DISABLE_Val << TCC_FCTRLA_CAPTURE_Pos)
mbed_official 579:53297373a894 375 #define TCC_FCTRLA_CAPTURE_CAPT (TCC_FCTRLA_CAPTURE_CAPT_Val << TCC_FCTRLA_CAPTURE_Pos)
mbed_official 579:53297373a894 376 #define TCC_FCTRLA_CAPTURE_CAPTMIN (TCC_FCTRLA_CAPTURE_CAPTMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
mbed_official 579:53297373a894 377 #define TCC_FCTRLA_CAPTURE_CAPTMAX (TCC_FCTRLA_CAPTURE_CAPTMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
mbed_official 579:53297373a894 378 #define TCC_FCTRLA_CAPTURE_LOCMIN (TCC_FCTRLA_CAPTURE_LOCMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
mbed_official 579:53297373a894 379 #define TCC_FCTRLA_CAPTURE_LOCMAX (TCC_FCTRLA_CAPTURE_LOCMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
mbed_official 579:53297373a894 380 #define TCC_FCTRLA_CAPTURE_DERIV0 (TCC_FCTRLA_CAPTURE_DERIV0_Val << TCC_FCTRLA_CAPTURE_Pos)
mbed_official 579:53297373a894 381 #define TCC_FCTRLA_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLA) Fault A Blanking Time */
mbed_official 579:53297373a894 382 #define TCC_FCTRLA_BLANKVAL_Msk (0xFFul << TCC_FCTRLA_BLANKVAL_Pos)
mbed_official 579:53297373a894 383 #define TCC_FCTRLA_BLANKVAL(value) ((TCC_FCTRLA_BLANKVAL_Msk & ((value) << TCC_FCTRLA_BLANKVAL_Pos)))
mbed_official 579:53297373a894 384 #define TCC_FCTRLA_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLA) Fault A Filter Value */
mbed_official 579:53297373a894 385 #define TCC_FCTRLA_FILTERVAL_Msk (0xFul << TCC_FCTRLA_FILTERVAL_Pos)
mbed_official 579:53297373a894 386 #define TCC_FCTRLA_FILTERVAL(value) ((TCC_FCTRLA_FILTERVAL_Msk & ((value) << TCC_FCTRLA_FILTERVAL_Pos)))
mbed_official 579:53297373a894 387 #define TCC_FCTRLA_MASK 0x0FFF7FFBul /**< \brief (TCC_FCTRLA) MASK Register */
mbed_official 579:53297373a894 388
mbed_official 579:53297373a894 389 /* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */
mbed_official 579:53297373a894 390 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 391 typedef union {
mbed_official 579:53297373a894 392 struct {
mbed_official 579:53297373a894 393 uint32_t SRC:2; /*!< bit: 0.. 1 Fault B Source */
mbed_official 579:53297373a894 394 uint32_t :1; /*!< bit: 2 Reserved */
mbed_official 579:53297373a894 395 uint32_t KEEP:1; /*!< bit: 3 Fault B Keeper */
mbed_official 579:53297373a894 396 uint32_t QUAL:1; /*!< bit: 4 Fault B Qualification */
mbed_official 579:53297373a894 397 uint32_t BLANK:2; /*!< bit: 5.. 6 Fault B Blanking Mode */
mbed_official 579:53297373a894 398 uint32_t RESTART:1; /*!< bit: 7 Fault B Restart */
mbed_official 579:53297373a894 399 uint32_t HALT:2; /*!< bit: 8.. 9 Fault B Halt Mode */
mbed_official 579:53297373a894 400 uint32_t CHSEL:2; /*!< bit: 10..11 Fault B Capture Channel */
mbed_official 579:53297373a894 401 uint32_t CAPTURE:3; /*!< bit: 12..14 Fault B Capture Action */
mbed_official 579:53297373a894 402 uint32_t :1; /*!< bit: 15 Reserved */
mbed_official 579:53297373a894 403 uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault B Blanking Time */
mbed_official 579:53297373a894 404 uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault B Filter Value */
mbed_official 579:53297373a894 405 uint32_t :4; /*!< bit: 28..31 Reserved */
mbed_official 579:53297373a894 406 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 407 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 408 } TCC_FCTRLB_Type;
mbed_official 579:53297373a894 409 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 410
mbed_official 579:53297373a894 411 #define TCC_FCTRLB_OFFSET 0x10 /**< \brief (TCC_FCTRLB offset) Recoverable Fault B Configuration */
mbed_official 579:53297373a894 412 #define TCC_FCTRLB_RESETVALUE 0x00000000ul /**< \brief (TCC_FCTRLB reset_value) Recoverable Fault B Configuration */
mbed_official 579:53297373a894 413
mbed_official 579:53297373a894 414 #define TCC_FCTRLB_SRC_Pos 0 /**< \brief (TCC_FCTRLB) Fault B Source */
mbed_official 579:53297373a894 415 #define TCC_FCTRLB_SRC_Msk (0x3ul << TCC_FCTRLB_SRC_Pos)
mbed_official 579:53297373a894 416 #define TCC_FCTRLB_SRC(value) ((TCC_FCTRLB_SRC_Msk & ((value) << TCC_FCTRLB_SRC_Pos)))
mbed_official 579:53297373a894 417 #define TCC_FCTRLB_SRC_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) Fault input disabled */
mbed_official 579:53297373a894 418 #define TCC_FCTRLB_SRC_ENABLE_Val 0x1ul /**< \brief (TCC_FCTRLB) MCEx (x=0,1) event input */
mbed_official 579:53297373a894 419 #define TCC_FCTRLB_SRC_INVERT_Val 0x2ul /**< \brief (TCC_FCTRLB) Inverted MCEx (x=0,1) event input */
mbed_official 579:53297373a894 420 #define TCC_FCTRLB_SRC_ALTFAULT_Val 0x3ul /**< \brief (TCC_FCTRLB) Alternate fault (A or B) state at the end of the previous period */
mbed_official 579:53297373a894 421 #define TCC_FCTRLB_SRC_DISABLE (TCC_FCTRLB_SRC_DISABLE_Val << TCC_FCTRLB_SRC_Pos)
mbed_official 579:53297373a894 422 #define TCC_FCTRLB_SRC_ENABLE (TCC_FCTRLB_SRC_ENABLE_Val << TCC_FCTRLB_SRC_Pos)
mbed_official 579:53297373a894 423 #define TCC_FCTRLB_SRC_INVERT (TCC_FCTRLB_SRC_INVERT_Val << TCC_FCTRLB_SRC_Pos)
mbed_official 579:53297373a894 424 #define TCC_FCTRLB_SRC_ALTFAULT (TCC_FCTRLB_SRC_ALTFAULT_Val << TCC_FCTRLB_SRC_Pos)
mbed_official 579:53297373a894 425 #define TCC_FCTRLB_KEEP_Pos 3 /**< \brief (TCC_FCTRLB) Fault B Keeper */
mbed_official 579:53297373a894 426 #define TCC_FCTRLB_KEEP (0x1ul << TCC_FCTRLB_KEEP_Pos)
mbed_official 579:53297373a894 427 #define TCC_FCTRLB_QUAL_Pos 4 /**< \brief (TCC_FCTRLB) Fault B Qualification */
mbed_official 579:53297373a894 428 #define TCC_FCTRLB_QUAL (0x1ul << TCC_FCTRLB_QUAL_Pos)
mbed_official 579:53297373a894 429 #define TCC_FCTRLB_BLANK_Pos 5 /**< \brief (TCC_FCTRLB) Fault B Blanking Mode */
mbed_official 579:53297373a894 430 #define TCC_FCTRLB_BLANK_Msk (0x3ul << TCC_FCTRLB_BLANK_Pos)
mbed_official 579:53297373a894 431 #define TCC_FCTRLB_BLANK(value) ((TCC_FCTRLB_BLANK_Msk & ((value) << TCC_FCTRLB_BLANK_Pos)))
mbed_official 579:53297373a894 432 #define TCC_FCTRLB_BLANK_NONE_Val 0x0ul /**< \brief (TCC_FCTRLB) No blanking applied */
mbed_official 579:53297373a894 433 #define TCC_FCTRLB_BLANK_RISE_Val 0x1ul /**< \brief (TCC_FCTRLB) Blanking applied from rising edge of the output waveform */
mbed_official 579:53297373a894 434 #define TCC_FCTRLB_BLANK_FALL_Val 0x2ul /**< \brief (TCC_FCTRLB) Blanking applied from falling edge of the output waveform */
mbed_official 579:53297373a894 435 #define TCC_FCTRLB_BLANK_BOTH_Val 0x3ul /**< \brief (TCC_FCTRLB) Blanking applied from each toggle of the output waveform */
mbed_official 579:53297373a894 436 #define TCC_FCTRLB_BLANK_NONE (TCC_FCTRLB_BLANK_NONE_Val << TCC_FCTRLB_BLANK_Pos)
mbed_official 579:53297373a894 437 #define TCC_FCTRLB_BLANK_RISE (TCC_FCTRLB_BLANK_RISE_Val << TCC_FCTRLB_BLANK_Pos)
mbed_official 579:53297373a894 438 #define TCC_FCTRLB_BLANK_FALL (TCC_FCTRLB_BLANK_FALL_Val << TCC_FCTRLB_BLANK_Pos)
mbed_official 579:53297373a894 439 #define TCC_FCTRLB_BLANK_BOTH (TCC_FCTRLB_BLANK_BOTH_Val << TCC_FCTRLB_BLANK_Pos)
mbed_official 579:53297373a894 440 #define TCC_FCTRLB_RESTART_Pos 7 /**< \brief (TCC_FCTRLB) Fault B Restart */
mbed_official 579:53297373a894 441 #define TCC_FCTRLB_RESTART (0x1ul << TCC_FCTRLB_RESTART_Pos)
mbed_official 579:53297373a894 442 #define TCC_FCTRLB_HALT_Pos 8 /**< \brief (TCC_FCTRLB) Fault B Halt Mode */
mbed_official 579:53297373a894 443 #define TCC_FCTRLB_HALT_Msk (0x3ul << TCC_FCTRLB_HALT_Pos)
mbed_official 579:53297373a894 444 #define TCC_FCTRLB_HALT(value) ((TCC_FCTRLB_HALT_Msk & ((value) << TCC_FCTRLB_HALT_Pos)))
mbed_official 579:53297373a894 445 #define TCC_FCTRLB_HALT_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) Halt action disabled */
mbed_official 579:53297373a894 446 #define TCC_FCTRLB_HALT_HW_Val 0x1ul /**< \brief (TCC_FCTRLB) Hardware halt action */
mbed_official 579:53297373a894 447 #define TCC_FCTRLB_HALT_SW_Val 0x2ul /**< \brief (TCC_FCTRLB) Software halt action */
mbed_official 579:53297373a894 448 #define TCC_FCTRLB_HALT_NR_Val 0x3ul /**< \brief (TCC_FCTRLB) Non-recoverable fault */
mbed_official 579:53297373a894 449 #define TCC_FCTRLB_HALT_DISABLE (TCC_FCTRLB_HALT_DISABLE_Val << TCC_FCTRLB_HALT_Pos)
mbed_official 579:53297373a894 450 #define TCC_FCTRLB_HALT_HW (TCC_FCTRLB_HALT_HW_Val << TCC_FCTRLB_HALT_Pos)
mbed_official 579:53297373a894 451 #define TCC_FCTRLB_HALT_SW (TCC_FCTRLB_HALT_SW_Val << TCC_FCTRLB_HALT_Pos)
mbed_official 579:53297373a894 452 #define TCC_FCTRLB_HALT_NR (TCC_FCTRLB_HALT_NR_Val << TCC_FCTRLB_HALT_Pos)
mbed_official 579:53297373a894 453 #define TCC_FCTRLB_CHSEL_Pos 10 /**< \brief (TCC_FCTRLB) Fault B Capture Channel */
mbed_official 579:53297373a894 454 #define TCC_FCTRLB_CHSEL_Msk (0x3ul << TCC_FCTRLB_CHSEL_Pos)
mbed_official 579:53297373a894 455 #define TCC_FCTRLB_CHSEL(value) ((TCC_FCTRLB_CHSEL_Msk & ((value) << TCC_FCTRLB_CHSEL_Pos)))
mbed_official 579:53297373a894 456 #define TCC_FCTRLB_CHSEL_CC0_Val 0x0ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 0 */
mbed_official 579:53297373a894 457 #define TCC_FCTRLB_CHSEL_CC1_Val 0x1ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 1 */
mbed_official 579:53297373a894 458 #define TCC_FCTRLB_CHSEL_CC2_Val 0x2ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 2 */
mbed_official 579:53297373a894 459 #define TCC_FCTRLB_CHSEL_CC3_Val 0x3ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 3 */
mbed_official 579:53297373a894 460 #define TCC_FCTRLB_CHSEL_CC0 (TCC_FCTRLB_CHSEL_CC0_Val << TCC_FCTRLB_CHSEL_Pos)
mbed_official 579:53297373a894 461 #define TCC_FCTRLB_CHSEL_CC1 (TCC_FCTRLB_CHSEL_CC1_Val << TCC_FCTRLB_CHSEL_Pos)
mbed_official 579:53297373a894 462 #define TCC_FCTRLB_CHSEL_CC2 (TCC_FCTRLB_CHSEL_CC2_Val << TCC_FCTRLB_CHSEL_Pos)
mbed_official 579:53297373a894 463 #define TCC_FCTRLB_CHSEL_CC3 (TCC_FCTRLB_CHSEL_CC3_Val << TCC_FCTRLB_CHSEL_Pos)
mbed_official 579:53297373a894 464 #define TCC_FCTRLB_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLB) Fault B Capture Action */
mbed_official 579:53297373a894 465 #define TCC_FCTRLB_CAPTURE_Msk (0x7ul << TCC_FCTRLB_CAPTURE_Pos)
mbed_official 579:53297373a894 466 #define TCC_FCTRLB_CAPTURE(value) ((TCC_FCTRLB_CAPTURE_Msk & ((value) << TCC_FCTRLB_CAPTURE_Pos)))
mbed_official 579:53297373a894 467 #define TCC_FCTRLB_CAPTURE_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) No capture */
mbed_official 579:53297373a894 468 #define TCC_FCTRLB_CAPTURE_CAPT_Val 0x1ul /**< \brief (TCC_FCTRLB) Capture on fault */
mbed_official 579:53297373a894 469 #define TCC_FCTRLB_CAPTURE_CAPTMIN_Val 0x2ul /**< \brief (TCC_FCTRLB) Minimum capture */
mbed_official 579:53297373a894 470 #define TCC_FCTRLB_CAPTURE_CAPTMAX_Val 0x3ul /**< \brief (TCC_FCTRLB) Maximum capture */
mbed_official 579:53297373a894 471 #define TCC_FCTRLB_CAPTURE_LOCMIN_Val 0x4ul /**< \brief (TCC_FCTRLB) Minimum local detection */
mbed_official 579:53297373a894 472 #define TCC_FCTRLB_CAPTURE_LOCMAX_Val 0x5ul /**< \brief (TCC_FCTRLB) Maximum local detection */
mbed_official 579:53297373a894 473 #define TCC_FCTRLB_CAPTURE_DERIV0_Val 0x6ul /**< \brief (TCC_FCTRLB) Minimum and maximum local detection */
mbed_official 579:53297373a894 474 #define TCC_FCTRLB_CAPTURE_DISABLE (TCC_FCTRLB_CAPTURE_DISABLE_Val << TCC_FCTRLB_CAPTURE_Pos)
mbed_official 579:53297373a894 475 #define TCC_FCTRLB_CAPTURE_CAPT (TCC_FCTRLB_CAPTURE_CAPT_Val << TCC_FCTRLB_CAPTURE_Pos)
mbed_official 579:53297373a894 476 #define TCC_FCTRLB_CAPTURE_CAPTMIN (TCC_FCTRLB_CAPTURE_CAPTMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
mbed_official 579:53297373a894 477 #define TCC_FCTRLB_CAPTURE_CAPTMAX (TCC_FCTRLB_CAPTURE_CAPTMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
mbed_official 579:53297373a894 478 #define TCC_FCTRLB_CAPTURE_LOCMIN (TCC_FCTRLB_CAPTURE_LOCMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
mbed_official 579:53297373a894 479 #define TCC_FCTRLB_CAPTURE_LOCMAX (TCC_FCTRLB_CAPTURE_LOCMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
mbed_official 579:53297373a894 480 #define TCC_FCTRLB_CAPTURE_DERIV0 (TCC_FCTRLB_CAPTURE_DERIV0_Val << TCC_FCTRLB_CAPTURE_Pos)
mbed_official 579:53297373a894 481 #define TCC_FCTRLB_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLB) Fault B Blanking Time */
mbed_official 579:53297373a894 482 #define TCC_FCTRLB_BLANKVAL_Msk (0xFFul << TCC_FCTRLB_BLANKVAL_Pos)
mbed_official 579:53297373a894 483 #define TCC_FCTRLB_BLANKVAL(value) ((TCC_FCTRLB_BLANKVAL_Msk & ((value) << TCC_FCTRLB_BLANKVAL_Pos)))
mbed_official 579:53297373a894 484 #define TCC_FCTRLB_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLB) Fault B Filter Value */
mbed_official 579:53297373a894 485 #define TCC_FCTRLB_FILTERVAL_Msk (0xFul << TCC_FCTRLB_FILTERVAL_Pos)
mbed_official 579:53297373a894 486 #define TCC_FCTRLB_FILTERVAL(value) ((TCC_FCTRLB_FILTERVAL_Msk & ((value) << TCC_FCTRLB_FILTERVAL_Pos)))
mbed_official 579:53297373a894 487 #define TCC_FCTRLB_MASK 0x0FFF7FFBul /**< \brief (TCC_FCTRLB) MASK Register */
mbed_official 579:53297373a894 488
mbed_official 579:53297373a894 489 /* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */
mbed_official 579:53297373a894 490 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 491 typedef union {
mbed_official 579:53297373a894 492 struct {
mbed_official 579:53297373a894 493 uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */
mbed_official 579:53297373a894 494 uint32_t :6; /*!< bit: 2.. 7 Reserved */
mbed_official 579:53297373a894 495 uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */
mbed_official 579:53297373a894 496 uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */
mbed_official 579:53297373a894 497 uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */
mbed_official 579:53297373a894 498 uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */
mbed_official 579:53297373a894 499 uint32_t :4; /*!< bit: 12..15 Reserved */
mbed_official 579:53297373a894 500 uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */
mbed_official 579:53297373a894 501 uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */
mbed_official 579:53297373a894 502 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 503 struct {
mbed_official 579:53297373a894 504 uint32_t :8; /*!< bit: 0.. 7 Reserved */
mbed_official 579:53297373a894 505 uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */
mbed_official 579:53297373a894 506 uint32_t :20; /*!< bit: 12..31 Reserved */
mbed_official 579:53297373a894 507 } vec; /*!< Structure used for vec access */
mbed_official 579:53297373a894 508 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 509 } TCC_WEXCTRL_Type;
mbed_official 579:53297373a894 510 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 511
mbed_official 579:53297373a894 512 #define TCC_WEXCTRL_OFFSET 0x14 /**< \brief (TCC_WEXCTRL offset) Waveform Extension Configuration */
mbed_official 579:53297373a894 513 #define TCC_WEXCTRL_RESETVALUE 0x00000000ul /**< \brief (TCC_WEXCTRL reset_value) Waveform Extension Configuration */
mbed_official 579:53297373a894 514
mbed_official 579:53297373a894 515 #define TCC_WEXCTRL_OTMX_Pos 0 /**< \brief (TCC_WEXCTRL) Output Matrix */
mbed_official 579:53297373a894 516 #define TCC_WEXCTRL_OTMX_Msk (0x3ul << TCC_WEXCTRL_OTMX_Pos)
mbed_official 579:53297373a894 517 #define TCC_WEXCTRL_OTMX(value) ((TCC_WEXCTRL_OTMX_Msk & ((value) << TCC_WEXCTRL_OTMX_Pos)))
mbed_official 579:53297373a894 518 #define TCC_WEXCTRL_DTIEN0_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 0 Enable */
mbed_official 579:53297373a894 519 #define TCC_WEXCTRL_DTIEN0 (1 << TCC_WEXCTRL_DTIEN0_Pos)
mbed_official 579:53297373a894 520 #define TCC_WEXCTRL_DTIEN1_Pos 9 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 1 Enable */
mbed_official 579:53297373a894 521 #define TCC_WEXCTRL_DTIEN1 (1 << TCC_WEXCTRL_DTIEN1_Pos)
mbed_official 579:53297373a894 522 #define TCC_WEXCTRL_DTIEN2_Pos 10 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 2 Enable */
mbed_official 579:53297373a894 523 #define TCC_WEXCTRL_DTIEN2 (1 << TCC_WEXCTRL_DTIEN2_Pos)
mbed_official 579:53297373a894 524 #define TCC_WEXCTRL_DTIEN3_Pos 11 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 3 Enable */
mbed_official 579:53297373a894 525 #define TCC_WEXCTRL_DTIEN3 (1 << TCC_WEXCTRL_DTIEN3_Pos)
mbed_official 579:53297373a894 526 #define TCC_WEXCTRL_DTIEN_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator x Enable */
mbed_official 579:53297373a894 527 #define TCC_WEXCTRL_DTIEN_Msk (0xFul << TCC_WEXCTRL_DTIEN_Pos)
mbed_official 579:53297373a894 528 #define TCC_WEXCTRL_DTIEN(value) ((TCC_WEXCTRL_DTIEN_Msk & ((value) << TCC_WEXCTRL_DTIEN_Pos)))
mbed_official 579:53297373a894 529 #define TCC_WEXCTRL_DTLS_Pos 16 /**< \brief (TCC_WEXCTRL) Dead-time Low Side Outputs Value */
mbed_official 579:53297373a894 530 #define TCC_WEXCTRL_DTLS_Msk (0xFFul << TCC_WEXCTRL_DTLS_Pos)
mbed_official 579:53297373a894 531 #define TCC_WEXCTRL_DTLS(value) ((TCC_WEXCTRL_DTLS_Msk & ((value) << TCC_WEXCTRL_DTLS_Pos)))
mbed_official 579:53297373a894 532 #define TCC_WEXCTRL_DTHS_Pos 24 /**< \brief (TCC_WEXCTRL) Dead-time High Side Outputs Value */
mbed_official 579:53297373a894 533 #define TCC_WEXCTRL_DTHS_Msk (0xFFul << TCC_WEXCTRL_DTHS_Pos)
mbed_official 579:53297373a894 534 #define TCC_WEXCTRL_DTHS(value) ((TCC_WEXCTRL_DTHS_Msk & ((value) << TCC_WEXCTRL_DTHS_Pos)))
mbed_official 579:53297373a894 535 #define TCC_WEXCTRL_MASK 0xFFFF0F03ul /**< \brief (TCC_WEXCTRL) MASK Register */
mbed_official 579:53297373a894 536
mbed_official 579:53297373a894 537 /* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */
mbed_official 579:53297373a894 538 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 539 typedef union {
mbed_official 579:53297373a894 540 struct {
mbed_official 579:53297373a894 541 uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */
mbed_official 579:53297373a894 542 uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */
mbed_official 579:53297373a894 543 uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */
mbed_official 579:53297373a894 544 uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */
mbed_official 579:53297373a894 545 uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */
mbed_official 579:53297373a894 546 uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */
mbed_official 579:53297373a894 547 uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */
mbed_official 579:53297373a894 548 uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */
mbed_official 579:53297373a894 549 uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */
mbed_official 579:53297373a894 550 uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */
mbed_official 579:53297373a894 551 uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */
mbed_official 579:53297373a894 552 uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */
mbed_official 579:53297373a894 553 uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */
mbed_official 579:53297373a894 554 uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */
mbed_official 579:53297373a894 555 uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */
mbed_official 579:53297373a894 556 uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */
mbed_official 579:53297373a894 557 uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */
mbed_official 579:53297373a894 558 uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */
mbed_official 579:53297373a894 559 uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */
mbed_official 579:53297373a894 560 uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */
mbed_official 579:53297373a894 561 uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */
mbed_official 579:53297373a894 562 uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */
mbed_official 579:53297373a894 563 uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */
mbed_official 579:53297373a894 564 uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */
mbed_official 579:53297373a894 565 uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */
mbed_official 579:53297373a894 566 uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */
mbed_official 579:53297373a894 567 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 568 struct {
mbed_official 579:53297373a894 569 uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */
mbed_official 579:53297373a894 570 uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */
mbed_official 579:53297373a894 571 uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */
mbed_official 579:53297373a894 572 uint32_t :8; /*!< bit: 24..31 Reserved */
mbed_official 579:53297373a894 573 } vec; /*!< Structure used for vec access */
mbed_official 579:53297373a894 574 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 575 } TCC_DRVCTRL_Type;
mbed_official 579:53297373a894 576 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 577
mbed_official 579:53297373a894 578 #define TCC_DRVCTRL_OFFSET 0x18 /**< \brief (TCC_DRVCTRL offset) Driver Control */
mbed_official 579:53297373a894 579 #define TCC_DRVCTRL_RESETVALUE 0x00000000ul /**< \brief (TCC_DRVCTRL reset_value) Driver Control */
mbed_official 579:53297373a894 580
mbed_official 579:53297373a894 581 #define TCC_DRVCTRL_NRE0_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Enable */
mbed_official 579:53297373a894 582 #define TCC_DRVCTRL_NRE0 (1 << TCC_DRVCTRL_NRE0_Pos)
mbed_official 579:53297373a894 583 #define TCC_DRVCTRL_NRE1_Pos 1 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Enable */
mbed_official 579:53297373a894 584 #define TCC_DRVCTRL_NRE1 (1 << TCC_DRVCTRL_NRE1_Pos)
mbed_official 579:53297373a894 585 #define TCC_DRVCTRL_NRE2_Pos 2 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Enable */
mbed_official 579:53297373a894 586 #define TCC_DRVCTRL_NRE2 (1 << TCC_DRVCTRL_NRE2_Pos)
mbed_official 579:53297373a894 587 #define TCC_DRVCTRL_NRE3_Pos 3 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Enable */
mbed_official 579:53297373a894 588 #define TCC_DRVCTRL_NRE3 (1 << TCC_DRVCTRL_NRE3_Pos)
mbed_official 579:53297373a894 589 #define TCC_DRVCTRL_NRE4_Pos 4 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Enable */
mbed_official 579:53297373a894 590 #define TCC_DRVCTRL_NRE4 (1 << TCC_DRVCTRL_NRE4_Pos)
mbed_official 579:53297373a894 591 #define TCC_DRVCTRL_NRE5_Pos 5 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Enable */
mbed_official 579:53297373a894 592 #define TCC_DRVCTRL_NRE5 (1 << TCC_DRVCTRL_NRE5_Pos)
mbed_official 579:53297373a894 593 #define TCC_DRVCTRL_NRE6_Pos 6 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Enable */
mbed_official 579:53297373a894 594 #define TCC_DRVCTRL_NRE6 (1 << TCC_DRVCTRL_NRE6_Pos)
mbed_official 579:53297373a894 595 #define TCC_DRVCTRL_NRE7_Pos 7 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Enable */
mbed_official 579:53297373a894 596 #define TCC_DRVCTRL_NRE7 (1 << TCC_DRVCTRL_NRE7_Pos)
mbed_official 579:53297373a894 597 #define TCC_DRVCTRL_NRE_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Enable */
mbed_official 579:53297373a894 598 #define TCC_DRVCTRL_NRE_Msk (0xFFul << TCC_DRVCTRL_NRE_Pos)
mbed_official 579:53297373a894 599 #define TCC_DRVCTRL_NRE(value) ((TCC_DRVCTRL_NRE_Msk & ((value) << TCC_DRVCTRL_NRE_Pos)))
mbed_official 579:53297373a894 600 #define TCC_DRVCTRL_NRV0_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Value */
mbed_official 579:53297373a894 601 #define TCC_DRVCTRL_NRV0 (1 << TCC_DRVCTRL_NRV0_Pos)
mbed_official 579:53297373a894 602 #define TCC_DRVCTRL_NRV1_Pos 9 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Value */
mbed_official 579:53297373a894 603 #define TCC_DRVCTRL_NRV1 (1 << TCC_DRVCTRL_NRV1_Pos)
mbed_official 579:53297373a894 604 #define TCC_DRVCTRL_NRV2_Pos 10 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Value */
mbed_official 579:53297373a894 605 #define TCC_DRVCTRL_NRV2 (1 << TCC_DRVCTRL_NRV2_Pos)
mbed_official 579:53297373a894 606 #define TCC_DRVCTRL_NRV3_Pos 11 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Value */
mbed_official 579:53297373a894 607 #define TCC_DRVCTRL_NRV3 (1 << TCC_DRVCTRL_NRV3_Pos)
mbed_official 579:53297373a894 608 #define TCC_DRVCTRL_NRV4_Pos 12 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Value */
mbed_official 579:53297373a894 609 #define TCC_DRVCTRL_NRV4 (1 << TCC_DRVCTRL_NRV4_Pos)
mbed_official 579:53297373a894 610 #define TCC_DRVCTRL_NRV5_Pos 13 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Value */
mbed_official 579:53297373a894 611 #define TCC_DRVCTRL_NRV5 (1 << TCC_DRVCTRL_NRV5_Pos)
mbed_official 579:53297373a894 612 #define TCC_DRVCTRL_NRV6_Pos 14 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Value */
mbed_official 579:53297373a894 613 #define TCC_DRVCTRL_NRV6 (1 << TCC_DRVCTRL_NRV6_Pos)
mbed_official 579:53297373a894 614 #define TCC_DRVCTRL_NRV7_Pos 15 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Value */
mbed_official 579:53297373a894 615 #define TCC_DRVCTRL_NRV7 (1 << TCC_DRVCTRL_NRV7_Pos)
mbed_official 579:53297373a894 616 #define TCC_DRVCTRL_NRV_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Value */
mbed_official 579:53297373a894 617 #define TCC_DRVCTRL_NRV_Msk (0xFFul << TCC_DRVCTRL_NRV_Pos)
mbed_official 579:53297373a894 618 #define TCC_DRVCTRL_NRV(value) ((TCC_DRVCTRL_NRV_Msk & ((value) << TCC_DRVCTRL_NRV_Pos)))
mbed_official 579:53297373a894 619 #define TCC_DRVCTRL_INVEN0_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform 0 Inversion */
mbed_official 579:53297373a894 620 #define TCC_DRVCTRL_INVEN0 (1 << TCC_DRVCTRL_INVEN0_Pos)
mbed_official 579:53297373a894 621 #define TCC_DRVCTRL_INVEN1_Pos 17 /**< \brief (TCC_DRVCTRL) Output Waveform 1 Inversion */
mbed_official 579:53297373a894 622 #define TCC_DRVCTRL_INVEN1 (1 << TCC_DRVCTRL_INVEN1_Pos)
mbed_official 579:53297373a894 623 #define TCC_DRVCTRL_INVEN2_Pos 18 /**< \brief (TCC_DRVCTRL) Output Waveform 2 Inversion */
mbed_official 579:53297373a894 624 #define TCC_DRVCTRL_INVEN2 (1 << TCC_DRVCTRL_INVEN2_Pos)
mbed_official 579:53297373a894 625 #define TCC_DRVCTRL_INVEN3_Pos 19 /**< \brief (TCC_DRVCTRL) Output Waveform 3 Inversion */
mbed_official 579:53297373a894 626 #define TCC_DRVCTRL_INVEN3 (1 << TCC_DRVCTRL_INVEN3_Pos)
mbed_official 579:53297373a894 627 #define TCC_DRVCTRL_INVEN4_Pos 20 /**< \brief (TCC_DRVCTRL) Output Waveform 4 Inversion */
mbed_official 579:53297373a894 628 #define TCC_DRVCTRL_INVEN4 (1 << TCC_DRVCTRL_INVEN4_Pos)
mbed_official 579:53297373a894 629 #define TCC_DRVCTRL_INVEN5_Pos 21 /**< \brief (TCC_DRVCTRL) Output Waveform 5 Inversion */
mbed_official 579:53297373a894 630 #define TCC_DRVCTRL_INVEN5 (1 << TCC_DRVCTRL_INVEN5_Pos)
mbed_official 579:53297373a894 631 #define TCC_DRVCTRL_INVEN6_Pos 22 /**< \brief (TCC_DRVCTRL) Output Waveform 6 Inversion */
mbed_official 579:53297373a894 632 #define TCC_DRVCTRL_INVEN6 (1 << TCC_DRVCTRL_INVEN6_Pos)
mbed_official 579:53297373a894 633 #define TCC_DRVCTRL_INVEN7_Pos 23 /**< \brief (TCC_DRVCTRL) Output Waveform 7 Inversion */
mbed_official 579:53297373a894 634 #define TCC_DRVCTRL_INVEN7 (1 << TCC_DRVCTRL_INVEN7_Pos)
mbed_official 579:53297373a894 635 #define TCC_DRVCTRL_INVEN_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform x Inversion */
mbed_official 579:53297373a894 636 #define TCC_DRVCTRL_INVEN_Msk (0xFFul << TCC_DRVCTRL_INVEN_Pos)
mbed_official 579:53297373a894 637 #define TCC_DRVCTRL_INVEN(value) ((TCC_DRVCTRL_INVEN_Msk & ((value) << TCC_DRVCTRL_INVEN_Pos)))
mbed_official 579:53297373a894 638 #define TCC_DRVCTRL_FILTERVAL0_Pos 24 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 0 Filter Value */
mbed_official 579:53297373a894 639 #define TCC_DRVCTRL_FILTERVAL0_Msk (0xFul << TCC_DRVCTRL_FILTERVAL0_Pos)
mbed_official 579:53297373a894 640 #define TCC_DRVCTRL_FILTERVAL0(value) ((TCC_DRVCTRL_FILTERVAL0_Msk & ((value) << TCC_DRVCTRL_FILTERVAL0_Pos)))
mbed_official 579:53297373a894 641 #define TCC_DRVCTRL_FILTERVAL1_Pos 28 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 1 Filter Value */
mbed_official 579:53297373a894 642 #define TCC_DRVCTRL_FILTERVAL1_Msk (0xFul << TCC_DRVCTRL_FILTERVAL1_Pos)
mbed_official 579:53297373a894 643 #define TCC_DRVCTRL_FILTERVAL1(value) ((TCC_DRVCTRL_FILTERVAL1_Msk & ((value) << TCC_DRVCTRL_FILTERVAL1_Pos)))
mbed_official 579:53297373a894 644 #define TCC_DRVCTRL_MASK 0xFFFFFFFFul /**< \brief (TCC_DRVCTRL) MASK Register */
mbed_official 579:53297373a894 645
mbed_official 579:53297373a894 646 /* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W 8) Debug Control -------- */
mbed_official 579:53297373a894 647 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 648 typedef union {
mbed_official 579:53297373a894 649 struct {
mbed_official 579:53297373a894 650 uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */
mbed_official 579:53297373a894 651 uint8_t :1; /*!< bit: 1 Reserved */
mbed_official 579:53297373a894 652 uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */
mbed_official 579:53297373a894 653 uint8_t :5; /*!< bit: 3.. 7 Reserved */
mbed_official 579:53297373a894 654 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 655 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 656 } TCC_DBGCTRL_Type;
mbed_official 579:53297373a894 657 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 658
mbed_official 579:53297373a894 659 #define TCC_DBGCTRL_OFFSET 0x1E /**< \brief (TCC_DBGCTRL offset) Debug Control */
mbed_official 579:53297373a894 660 #define TCC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (TCC_DBGCTRL reset_value) Debug Control */
mbed_official 579:53297373a894 661
mbed_official 579:53297373a894 662 #define TCC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TCC_DBGCTRL) Debug Running Mode */
mbed_official 579:53297373a894 663 #define TCC_DBGCTRL_DBGRUN (0x1ul << TCC_DBGCTRL_DBGRUN_Pos)
mbed_official 579:53297373a894 664 #define TCC_DBGCTRL_FDDBD_Pos 2 /**< \brief (TCC_DBGCTRL) Fault Detection on Debug Break Detection */
mbed_official 579:53297373a894 665 #define TCC_DBGCTRL_FDDBD (0x1ul << TCC_DBGCTRL_FDDBD_Pos)
mbed_official 579:53297373a894 666 #define TCC_DBGCTRL_MASK 0x05ul /**< \brief (TCC_DBGCTRL) MASK Register */
mbed_official 579:53297373a894 667
mbed_official 579:53297373a894 668 /* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */
mbed_official 579:53297373a894 669 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 670 typedef union {
mbed_official 579:53297373a894 671 struct {
mbed_official 579:53297373a894 672 uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */
mbed_official 579:53297373a894 673 uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */
mbed_official 579:53297373a894 674 uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */
mbed_official 579:53297373a894 675 uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */
mbed_official 579:53297373a894 676 uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */
mbed_official 579:53297373a894 677 uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */
mbed_official 579:53297373a894 678 uint32_t :1; /*!< bit: 11 Reserved */
mbed_official 579:53297373a894 679 uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */
mbed_official 579:53297373a894 680 uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */
mbed_official 579:53297373a894 681 uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */
mbed_official 579:53297373a894 682 uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */
mbed_official 579:53297373a894 683 uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */
mbed_official 579:53297373a894 684 uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */
mbed_official 579:53297373a894 685 uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */
mbed_official 579:53297373a894 686 uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */
mbed_official 579:53297373a894 687 uint32_t :4; /*!< bit: 20..23 Reserved */
mbed_official 579:53297373a894 688 uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */
mbed_official 579:53297373a894 689 uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */
mbed_official 579:53297373a894 690 uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */
mbed_official 579:53297373a894 691 uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */
mbed_official 579:53297373a894 692 uint32_t :4; /*!< bit: 28..31 Reserved */
mbed_official 579:53297373a894 693 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 694 struct {
mbed_official 579:53297373a894 695 uint32_t :12; /*!< bit: 0..11 Reserved */
mbed_official 579:53297373a894 696 uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */
mbed_official 579:53297373a894 697 uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */
mbed_official 579:53297373a894 698 uint32_t MCEI:4; /*!< bit: 16..19 Match or Capture Channel x Event Input Enable */
mbed_official 579:53297373a894 699 uint32_t :4; /*!< bit: 20..23 Reserved */
mbed_official 579:53297373a894 700 uint32_t MCEO:4; /*!< bit: 24..27 Match or Capture Channel x Event Output Enable */
mbed_official 579:53297373a894 701 uint32_t :4; /*!< bit: 28..31 Reserved */
mbed_official 579:53297373a894 702 } vec; /*!< Structure used for vec access */
mbed_official 579:53297373a894 703 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 704 } TCC_EVCTRL_Type;
mbed_official 579:53297373a894 705 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 706
mbed_official 579:53297373a894 707 #define TCC_EVCTRL_OFFSET 0x20 /**< \brief (TCC_EVCTRL offset) Event Control */
mbed_official 579:53297373a894 708 #define TCC_EVCTRL_RESETVALUE 0x00000000ul /**< \brief (TCC_EVCTRL reset_value) Event Control */
mbed_official 579:53297373a894 709
mbed_official 579:53297373a894 710 #define TCC_EVCTRL_EVACT0_Pos 0 /**< \brief (TCC_EVCTRL) Timer/counter Input Event0 Action */
mbed_official 579:53297373a894 711 #define TCC_EVCTRL_EVACT0_Msk (0x7ul << TCC_EVCTRL_EVACT0_Pos)
mbed_official 579:53297373a894 712 #define TCC_EVCTRL_EVACT0(value) ((TCC_EVCTRL_EVACT0_Msk & ((value) << TCC_EVCTRL_EVACT0_Pos)))
mbed_official 579:53297373a894 713 #define TCC_EVCTRL_EVACT0_OFF_Val 0x0ul /**< \brief (TCC_EVCTRL) Event action disabled */
mbed_official 579:53297373a894 714 #define TCC_EVCTRL_EVACT0_RETRIGGER_Val 0x1ul /**< \brief (TCC_EVCTRL) Start, restart or re-trigger counter on event */
mbed_official 579:53297373a894 715 #define TCC_EVCTRL_EVACT0_COUNTEV_Val 0x2ul /**< \brief (TCC_EVCTRL) Count on event */
mbed_official 579:53297373a894 716 #define TCC_EVCTRL_EVACT0_START_Val 0x3ul /**< \brief (TCC_EVCTRL) Start counter on event */
mbed_official 579:53297373a894 717 #define TCC_EVCTRL_EVACT0_INC_Val 0x4ul /**< \brief (TCC_EVCTRL) Increment counter on event */
mbed_official 579:53297373a894 718 #define TCC_EVCTRL_EVACT0_COUNT_Val 0x5ul /**< \brief (TCC_EVCTRL) Count on active state of asynchronous event */
mbed_official 579:53297373a894 719 #define TCC_EVCTRL_EVACT0_FAULT_Val 0x7ul /**< \brief (TCC_EVCTRL) Non-recoverable fault */
mbed_official 579:53297373a894 720 #define TCC_EVCTRL_EVACT0_OFF (TCC_EVCTRL_EVACT0_OFF_Val << TCC_EVCTRL_EVACT0_Pos)
mbed_official 579:53297373a894 721 #define TCC_EVCTRL_EVACT0_RETRIGGER (TCC_EVCTRL_EVACT0_RETRIGGER_Val << TCC_EVCTRL_EVACT0_Pos)
mbed_official 579:53297373a894 722 #define TCC_EVCTRL_EVACT0_COUNTEV (TCC_EVCTRL_EVACT0_COUNTEV_Val << TCC_EVCTRL_EVACT0_Pos)
mbed_official 579:53297373a894 723 #define TCC_EVCTRL_EVACT0_START (TCC_EVCTRL_EVACT0_START_Val << TCC_EVCTRL_EVACT0_Pos)
mbed_official 579:53297373a894 724 #define TCC_EVCTRL_EVACT0_INC (TCC_EVCTRL_EVACT0_INC_Val << TCC_EVCTRL_EVACT0_Pos)
mbed_official 579:53297373a894 725 #define TCC_EVCTRL_EVACT0_COUNT (TCC_EVCTRL_EVACT0_COUNT_Val << TCC_EVCTRL_EVACT0_Pos)
mbed_official 579:53297373a894 726 #define TCC_EVCTRL_EVACT0_FAULT (TCC_EVCTRL_EVACT0_FAULT_Val << TCC_EVCTRL_EVACT0_Pos)
mbed_official 579:53297373a894 727 #define TCC_EVCTRL_EVACT1_Pos 3 /**< \brief (TCC_EVCTRL) Timer/counter Input Event1 Action */
mbed_official 579:53297373a894 728 #define TCC_EVCTRL_EVACT1_Msk (0x7ul << TCC_EVCTRL_EVACT1_Pos)
mbed_official 579:53297373a894 729 #define TCC_EVCTRL_EVACT1(value) ((TCC_EVCTRL_EVACT1_Msk & ((value) << TCC_EVCTRL_EVACT1_Pos)))
mbed_official 579:53297373a894 730 #define TCC_EVCTRL_EVACT1_OFF_Val 0x0ul /**< \brief (TCC_EVCTRL) Event action disabled */
mbed_official 579:53297373a894 731 #define TCC_EVCTRL_EVACT1_RETRIGGER_Val 0x1ul /**< \brief (TCC_EVCTRL) Re-trigger counter on event */
mbed_official 579:53297373a894 732 #define TCC_EVCTRL_EVACT1_DIR_Val 0x2ul /**< \brief (TCC_EVCTRL) Direction control */
mbed_official 579:53297373a894 733 #define TCC_EVCTRL_EVACT1_STOP_Val 0x3ul /**< \brief (TCC_EVCTRL) Stop counter on event */
mbed_official 579:53297373a894 734 #define TCC_EVCTRL_EVACT1_DEC_Val 0x4ul /**< \brief (TCC_EVCTRL) Decrement counter on event */
mbed_official 579:53297373a894 735 #define TCC_EVCTRL_EVACT1_PPW_Val 0x5ul /**< \brief (TCC_EVCTRL) Period capture value in CC0 register, pulse width capture value in CC1 register */
mbed_official 579:53297373a894 736 #define TCC_EVCTRL_EVACT1_PWP_Val 0x6ul /**< \brief (TCC_EVCTRL) Period capture value in CC1 register, pulse width capture value in CC0 register */
mbed_official 579:53297373a894 737 #define TCC_EVCTRL_EVACT1_FAULT_Val 0x7ul /**< \brief (TCC_EVCTRL) Non-recoverable fault */
mbed_official 579:53297373a894 738 #define TCC_EVCTRL_EVACT1_OFF (TCC_EVCTRL_EVACT1_OFF_Val << TCC_EVCTRL_EVACT1_Pos)
mbed_official 579:53297373a894 739 #define TCC_EVCTRL_EVACT1_RETRIGGER (TCC_EVCTRL_EVACT1_RETRIGGER_Val << TCC_EVCTRL_EVACT1_Pos)
mbed_official 579:53297373a894 740 #define TCC_EVCTRL_EVACT1_DIR (TCC_EVCTRL_EVACT1_DIR_Val << TCC_EVCTRL_EVACT1_Pos)
mbed_official 579:53297373a894 741 #define TCC_EVCTRL_EVACT1_STOP (TCC_EVCTRL_EVACT1_STOP_Val << TCC_EVCTRL_EVACT1_Pos)
mbed_official 579:53297373a894 742 #define TCC_EVCTRL_EVACT1_DEC (TCC_EVCTRL_EVACT1_DEC_Val << TCC_EVCTRL_EVACT1_Pos)
mbed_official 579:53297373a894 743 #define TCC_EVCTRL_EVACT1_PPW (TCC_EVCTRL_EVACT1_PPW_Val << TCC_EVCTRL_EVACT1_Pos)
mbed_official 579:53297373a894 744 #define TCC_EVCTRL_EVACT1_PWP (TCC_EVCTRL_EVACT1_PWP_Val << TCC_EVCTRL_EVACT1_Pos)
mbed_official 579:53297373a894 745 #define TCC_EVCTRL_EVACT1_FAULT (TCC_EVCTRL_EVACT1_FAULT_Val << TCC_EVCTRL_EVACT1_Pos)
mbed_official 579:53297373a894 746 #define TCC_EVCTRL_CNTSEL_Pos 6 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Mode */
mbed_official 579:53297373a894 747 #define TCC_EVCTRL_CNTSEL_Msk (0x3ul << TCC_EVCTRL_CNTSEL_Pos)
mbed_official 579:53297373a894 748 #define TCC_EVCTRL_CNTSEL(value) ((TCC_EVCTRL_CNTSEL_Msk & ((value) << TCC_EVCTRL_CNTSEL_Pos)))
mbed_official 579:53297373a894 749 #define TCC_EVCTRL_CNTSEL_START_Val 0x0ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts */
mbed_official 579:53297373a894 750 #define TCC_EVCTRL_CNTSEL_END_Val 0x1ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends */
mbed_official 579:53297373a894 751 #define TCC_EVCTRL_CNTSEL_BETWEEN_Val 0x2ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends, except for the first and last cycles */
mbed_official 579:53297373a894 752 #define TCC_EVCTRL_CNTSEL_BOUNDARY_Val 0x3ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts or a counter cycle ends */
mbed_official 579:53297373a894 753 #define TCC_EVCTRL_CNTSEL_START (TCC_EVCTRL_CNTSEL_START_Val << TCC_EVCTRL_CNTSEL_Pos)
mbed_official 579:53297373a894 754 #define TCC_EVCTRL_CNTSEL_END (TCC_EVCTRL_CNTSEL_END_Val << TCC_EVCTRL_CNTSEL_Pos)
mbed_official 579:53297373a894 755 #define TCC_EVCTRL_CNTSEL_BETWEEN (TCC_EVCTRL_CNTSEL_BETWEEN_Val << TCC_EVCTRL_CNTSEL_Pos)
mbed_official 579:53297373a894 756 #define TCC_EVCTRL_CNTSEL_BOUNDARY (TCC_EVCTRL_CNTSEL_BOUNDARY_Val << TCC_EVCTRL_CNTSEL_Pos)
mbed_official 579:53297373a894 757 #define TCC_EVCTRL_OVFEO_Pos 8 /**< \brief (TCC_EVCTRL) Overflow/Underflow Output Event Enable */
mbed_official 579:53297373a894 758 #define TCC_EVCTRL_OVFEO (0x1ul << TCC_EVCTRL_OVFEO_Pos)
mbed_official 579:53297373a894 759 #define TCC_EVCTRL_TRGEO_Pos 9 /**< \brief (TCC_EVCTRL) Retrigger Output Event Enable */
mbed_official 579:53297373a894 760 #define TCC_EVCTRL_TRGEO (0x1ul << TCC_EVCTRL_TRGEO_Pos)
mbed_official 579:53297373a894 761 #define TCC_EVCTRL_CNTEO_Pos 10 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Enable */
mbed_official 579:53297373a894 762 #define TCC_EVCTRL_CNTEO (0x1ul << TCC_EVCTRL_CNTEO_Pos)
mbed_official 579:53297373a894 763 #define TCC_EVCTRL_TCINV0_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event 0 Input Enable */
mbed_official 579:53297373a894 764 #define TCC_EVCTRL_TCINV0 (1 << TCC_EVCTRL_TCINV0_Pos)
mbed_official 579:53297373a894 765 #define TCC_EVCTRL_TCINV1_Pos 13 /**< \brief (TCC_EVCTRL) Inverted Event 1 Input Enable */
mbed_official 579:53297373a894 766 #define TCC_EVCTRL_TCINV1 (1 << TCC_EVCTRL_TCINV1_Pos)
mbed_official 579:53297373a894 767 #define TCC_EVCTRL_TCINV_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event x Input Enable */
mbed_official 579:53297373a894 768 #define TCC_EVCTRL_TCINV_Msk (0x3ul << TCC_EVCTRL_TCINV_Pos)
mbed_official 579:53297373a894 769 #define TCC_EVCTRL_TCINV(value) ((TCC_EVCTRL_TCINV_Msk & ((value) << TCC_EVCTRL_TCINV_Pos)))
mbed_official 579:53297373a894 770 #define TCC_EVCTRL_TCEI0_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event 0 Input Enable */
mbed_official 579:53297373a894 771 #define TCC_EVCTRL_TCEI0 (1 << TCC_EVCTRL_TCEI0_Pos)
mbed_official 579:53297373a894 772 #define TCC_EVCTRL_TCEI1_Pos 15 /**< \brief (TCC_EVCTRL) Timer/counter Event 1 Input Enable */
mbed_official 579:53297373a894 773 #define TCC_EVCTRL_TCEI1 (1 << TCC_EVCTRL_TCEI1_Pos)
mbed_official 579:53297373a894 774 #define TCC_EVCTRL_TCEI_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event x Input Enable */
mbed_official 579:53297373a894 775 #define TCC_EVCTRL_TCEI_Msk (0x3ul << TCC_EVCTRL_TCEI_Pos)
mbed_official 579:53297373a894 776 #define TCC_EVCTRL_TCEI(value) ((TCC_EVCTRL_TCEI_Msk & ((value) << TCC_EVCTRL_TCEI_Pos)))
mbed_official 579:53297373a894 777 #define TCC_EVCTRL_MCEI0_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Input Enable */
mbed_official 579:53297373a894 778 #define TCC_EVCTRL_MCEI0 (1 << TCC_EVCTRL_MCEI0_Pos)
mbed_official 579:53297373a894 779 #define TCC_EVCTRL_MCEI1_Pos 17 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Input Enable */
mbed_official 579:53297373a894 780 #define TCC_EVCTRL_MCEI1 (1 << TCC_EVCTRL_MCEI1_Pos)
mbed_official 579:53297373a894 781 #define TCC_EVCTRL_MCEI2_Pos 18 /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Input Enable */
mbed_official 579:53297373a894 782 #define TCC_EVCTRL_MCEI2 (1 << TCC_EVCTRL_MCEI2_Pos)
mbed_official 579:53297373a894 783 #define TCC_EVCTRL_MCEI3_Pos 19 /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Input Enable */
mbed_official 579:53297373a894 784 #define TCC_EVCTRL_MCEI3 (1 << TCC_EVCTRL_MCEI3_Pos)
mbed_official 579:53297373a894 785 #define TCC_EVCTRL_MCEI_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Input Enable */
mbed_official 579:53297373a894 786 #define TCC_EVCTRL_MCEI_Msk (0xFul << TCC_EVCTRL_MCEI_Pos)
mbed_official 579:53297373a894 787 #define TCC_EVCTRL_MCEI(value) ((TCC_EVCTRL_MCEI_Msk & ((value) << TCC_EVCTRL_MCEI_Pos)))
mbed_official 579:53297373a894 788 #define TCC_EVCTRL_MCEO0_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Output Enable */
mbed_official 579:53297373a894 789 #define TCC_EVCTRL_MCEO0 (1 << TCC_EVCTRL_MCEO0_Pos)
mbed_official 579:53297373a894 790 #define TCC_EVCTRL_MCEO1_Pos 25 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Output Enable */
mbed_official 579:53297373a894 791 #define TCC_EVCTRL_MCEO1 (1 << TCC_EVCTRL_MCEO1_Pos)
mbed_official 579:53297373a894 792 #define TCC_EVCTRL_MCEO2_Pos 26 /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Output Enable */
mbed_official 579:53297373a894 793 #define TCC_EVCTRL_MCEO2 (1 << TCC_EVCTRL_MCEO2_Pos)
mbed_official 579:53297373a894 794 #define TCC_EVCTRL_MCEO3_Pos 27 /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Output Enable */
mbed_official 579:53297373a894 795 #define TCC_EVCTRL_MCEO3 (1 << TCC_EVCTRL_MCEO3_Pos)
mbed_official 579:53297373a894 796 #define TCC_EVCTRL_MCEO_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Output Enable */
mbed_official 579:53297373a894 797 #define TCC_EVCTRL_MCEO_Msk (0xFul << TCC_EVCTRL_MCEO_Pos)
mbed_official 579:53297373a894 798 #define TCC_EVCTRL_MCEO(value) ((TCC_EVCTRL_MCEO_Msk & ((value) << TCC_EVCTRL_MCEO_Pos)))
mbed_official 579:53297373a894 799 #define TCC_EVCTRL_MASK 0x0F0FF7FFul /**< \brief (TCC_EVCTRL) MASK Register */
mbed_official 579:53297373a894 800
mbed_official 579:53297373a894 801 /* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */
mbed_official 579:53297373a894 802 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 803 typedef union {
mbed_official 579:53297373a894 804 struct {
mbed_official 579:53297373a894 805 uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
mbed_official 579:53297373a894 806 uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
mbed_official 579:53297373a894 807 uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
mbed_official 579:53297373a894 808 uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
mbed_official 579:53297373a894 809 uint32_t :7; /*!< bit: 4..10 Reserved */
mbed_official 579:53297373a894 810 uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
mbed_official 579:53297373a894 811 uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
mbed_official 579:53297373a894 812 uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
mbed_official 579:53297373a894 813 uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
mbed_official 579:53297373a894 814 uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
mbed_official 579:53297373a894 815 uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
mbed_official 579:53297373a894 816 uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
mbed_official 579:53297373a894 817 uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
mbed_official 579:53297373a894 818 uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
mbed_official 579:53297373a894 819 uint32_t :12; /*!< bit: 20..31 Reserved */
mbed_official 579:53297373a894 820 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 821 struct {
mbed_official 579:53297373a894 822 uint32_t :16; /*!< bit: 0..15 Reserved */
mbed_official 579:53297373a894 823 uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */
mbed_official 579:53297373a894 824 uint32_t :12; /*!< bit: 20..31 Reserved */
mbed_official 579:53297373a894 825 } vec; /*!< Structure used for vec access */
mbed_official 579:53297373a894 826 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 827 } TCC_INTENCLR_Type;
mbed_official 579:53297373a894 828 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 829
mbed_official 579:53297373a894 830 #define TCC_INTENCLR_OFFSET 0x24 /**< \brief (TCC_INTENCLR offset) Interrupt Enable Clear */
mbed_official 579:53297373a894 831 #define TCC_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (TCC_INTENCLR reset_value) Interrupt Enable Clear */
mbed_official 579:53297373a894 832
mbed_official 579:53297373a894 833 #define TCC_INTENCLR_OVF_Pos 0 /**< \brief (TCC_INTENCLR) Overflow Interrupt Enable */
mbed_official 579:53297373a894 834 #define TCC_INTENCLR_OVF (0x1ul << TCC_INTENCLR_OVF_Pos)
mbed_official 579:53297373a894 835 #define TCC_INTENCLR_TRG_Pos 1 /**< \brief (TCC_INTENCLR) Retrigger Interrupt Enable */
mbed_official 579:53297373a894 836 #define TCC_INTENCLR_TRG (0x1ul << TCC_INTENCLR_TRG_Pos)
mbed_official 579:53297373a894 837 #define TCC_INTENCLR_CNT_Pos 2 /**< \brief (TCC_INTENCLR) Counter Interrupt Enable */
mbed_official 579:53297373a894 838 #define TCC_INTENCLR_CNT (0x1ul << TCC_INTENCLR_CNT_Pos)
mbed_official 579:53297373a894 839 #define TCC_INTENCLR_ERR_Pos 3 /**< \brief (TCC_INTENCLR) Error Interrupt Enable */
mbed_official 579:53297373a894 840 #define TCC_INTENCLR_ERR (0x1ul << TCC_INTENCLR_ERR_Pos)
mbed_official 579:53297373a894 841 #define TCC_INTENCLR_DFS_Pos 11 /**< \brief (TCC_INTENCLR) Non-Recoverable Debug Fault Interrupt Enable */
mbed_official 579:53297373a894 842 #define TCC_INTENCLR_DFS (0x1ul << TCC_INTENCLR_DFS_Pos)
mbed_official 579:53297373a894 843 #define TCC_INTENCLR_FAULTA_Pos 12 /**< \brief (TCC_INTENCLR) Recoverable Fault A Interrupt Enable */
mbed_official 579:53297373a894 844 #define TCC_INTENCLR_FAULTA (0x1ul << TCC_INTENCLR_FAULTA_Pos)
mbed_official 579:53297373a894 845 #define TCC_INTENCLR_FAULTB_Pos 13 /**< \brief (TCC_INTENCLR) Recoverable Fault B Interrupt Enable */
mbed_official 579:53297373a894 846 #define TCC_INTENCLR_FAULTB (0x1ul << TCC_INTENCLR_FAULTB_Pos)
mbed_official 579:53297373a894 847 #define TCC_INTENCLR_FAULT0_Pos 14 /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 0 Interrupt Enable */
mbed_official 579:53297373a894 848 #define TCC_INTENCLR_FAULT0 (0x1ul << TCC_INTENCLR_FAULT0_Pos)
mbed_official 579:53297373a894 849 #define TCC_INTENCLR_FAULT1_Pos 15 /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 1 Interrupt Enable */
mbed_official 579:53297373a894 850 #define TCC_INTENCLR_FAULT1 (0x1ul << TCC_INTENCLR_FAULT1_Pos)
mbed_official 579:53297373a894 851 #define TCC_INTENCLR_MC0_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */
mbed_official 579:53297373a894 852 #define TCC_INTENCLR_MC0 (1 << TCC_INTENCLR_MC0_Pos)
mbed_official 579:53297373a894 853 #define TCC_INTENCLR_MC1_Pos 17 /**< \brief (TCC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */
mbed_official 579:53297373a894 854 #define TCC_INTENCLR_MC1 (1 << TCC_INTENCLR_MC1_Pos)
mbed_official 579:53297373a894 855 #define TCC_INTENCLR_MC2_Pos 18 /**< \brief (TCC_INTENCLR) Match or Capture Channel 2 Interrupt Enable */
mbed_official 579:53297373a894 856 #define TCC_INTENCLR_MC2 (1 << TCC_INTENCLR_MC2_Pos)
mbed_official 579:53297373a894 857 #define TCC_INTENCLR_MC3_Pos 19 /**< \brief (TCC_INTENCLR) Match or Capture Channel 3 Interrupt Enable */
mbed_official 579:53297373a894 858 #define TCC_INTENCLR_MC3 (1 << TCC_INTENCLR_MC3_Pos)
mbed_official 579:53297373a894 859 #define TCC_INTENCLR_MC_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel x Interrupt Enable */
mbed_official 579:53297373a894 860 #define TCC_INTENCLR_MC_Msk (0xFul << TCC_INTENCLR_MC_Pos)
mbed_official 579:53297373a894 861 #define TCC_INTENCLR_MC(value) ((TCC_INTENCLR_MC_Msk & ((value) << TCC_INTENCLR_MC_Pos)))
mbed_official 579:53297373a894 862 #define TCC_INTENCLR_MASK 0x000FF80Ful /**< \brief (TCC_INTENCLR) MASK Register */
mbed_official 579:53297373a894 863
mbed_official 579:53297373a894 864 /* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */
mbed_official 579:53297373a894 865 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 866 typedef union {
mbed_official 579:53297373a894 867 struct {
mbed_official 579:53297373a894 868 uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
mbed_official 579:53297373a894 869 uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
mbed_official 579:53297373a894 870 uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
mbed_official 579:53297373a894 871 uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
mbed_official 579:53297373a894 872 uint32_t :7; /*!< bit: 4..10 Reserved */
mbed_official 579:53297373a894 873 uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
mbed_official 579:53297373a894 874 uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
mbed_official 579:53297373a894 875 uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
mbed_official 579:53297373a894 876 uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
mbed_official 579:53297373a894 877 uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
mbed_official 579:53297373a894 878 uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
mbed_official 579:53297373a894 879 uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
mbed_official 579:53297373a894 880 uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
mbed_official 579:53297373a894 881 uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
mbed_official 579:53297373a894 882 uint32_t :12; /*!< bit: 20..31 Reserved */
mbed_official 579:53297373a894 883 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 884 struct {
mbed_official 579:53297373a894 885 uint32_t :16; /*!< bit: 0..15 Reserved */
mbed_official 579:53297373a894 886 uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */
mbed_official 579:53297373a894 887 uint32_t :12; /*!< bit: 20..31 Reserved */
mbed_official 579:53297373a894 888 } vec; /*!< Structure used for vec access */
mbed_official 579:53297373a894 889 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 890 } TCC_INTENSET_Type;
mbed_official 579:53297373a894 891 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 892
mbed_official 579:53297373a894 893 #define TCC_INTENSET_OFFSET 0x28 /**< \brief (TCC_INTENSET offset) Interrupt Enable Set */
mbed_official 579:53297373a894 894 #define TCC_INTENSET_RESETVALUE 0x00000000ul /**< \brief (TCC_INTENSET reset_value) Interrupt Enable Set */
mbed_official 579:53297373a894 895
mbed_official 579:53297373a894 896 #define TCC_INTENSET_OVF_Pos 0 /**< \brief (TCC_INTENSET) Overflow Interrupt Enable */
mbed_official 579:53297373a894 897 #define TCC_INTENSET_OVF (0x1ul << TCC_INTENSET_OVF_Pos)
mbed_official 579:53297373a894 898 #define TCC_INTENSET_TRG_Pos 1 /**< \brief (TCC_INTENSET) Retrigger Interrupt Enable */
mbed_official 579:53297373a894 899 #define TCC_INTENSET_TRG (0x1ul << TCC_INTENSET_TRG_Pos)
mbed_official 579:53297373a894 900 #define TCC_INTENSET_CNT_Pos 2 /**< \brief (TCC_INTENSET) Counter Interrupt Enable */
mbed_official 579:53297373a894 901 #define TCC_INTENSET_CNT (0x1ul << TCC_INTENSET_CNT_Pos)
mbed_official 579:53297373a894 902 #define TCC_INTENSET_ERR_Pos 3 /**< \brief (TCC_INTENSET) Error Interrupt Enable */
mbed_official 579:53297373a894 903 #define TCC_INTENSET_ERR (0x1ul << TCC_INTENSET_ERR_Pos)
mbed_official 579:53297373a894 904 #define TCC_INTENSET_DFS_Pos 11 /**< \brief (TCC_INTENSET) Non-Recoverable Debug Fault Interrupt Enable */
mbed_official 579:53297373a894 905 #define TCC_INTENSET_DFS (0x1ul << TCC_INTENSET_DFS_Pos)
mbed_official 579:53297373a894 906 #define TCC_INTENSET_FAULTA_Pos 12 /**< \brief (TCC_INTENSET) Recoverable Fault A Interrupt Enable */
mbed_official 579:53297373a894 907 #define TCC_INTENSET_FAULTA (0x1ul << TCC_INTENSET_FAULTA_Pos)
mbed_official 579:53297373a894 908 #define TCC_INTENSET_FAULTB_Pos 13 /**< \brief (TCC_INTENSET) Recoverable Fault B Interrupt Enable */
mbed_official 579:53297373a894 909 #define TCC_INTENSET_FAULTB (0x1ul << TCC_INTENSET_FAULTB_Pos)
mbed_official 579:53297373a894 910 #define TCC_INTENSET_FAULT0_Pos 14 /**< \brief (TCC_INTENSET) Non-Recoverable Fault 0 Interrupt Enable */
mbed_official 579:53297373a894 911 #define TCC_INTENSET_FAULT0 (0x1ul << TCC_INTENSET_FAULT0_Pos)
mbed_official 579:53297373a894 912 #define TCC_INTENSET_FAULT1_Pos 15 /**< \brief (TCC_INTENSET) Non-Recoverable Fault 1 Interrupt Enable */
mbed_official 579:53297373a894 913 #define TCC_INTENSET_FAULT1 (0x1ul << TCC_INTENSET_FAULT1_Pos)
mbed_official 579:53297373a894 914 #define TCC_INTENSET_MC0_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel 0 Interrupt Enable */
mbed_official 579:53297373a894 915 #define TCC_INTENSET_MC0 (1 << TCC_INTENSET_MC0_Pos)
mbed_official 579:53297373a894 916 #define TCC_INTENSET_MC1_Pos 17 /**< \brief (TCC_INTENSET) Match or Capture Channel 1 Interrupt Enable */
mbed_official 579:53297373a894 917 #define TCC_INTENSET_MC1 (1 << TCC_INTENSET_MC1_Pos)
mbed_official 579:53297373a894 918 #define TCC_INTENSET_MC2_Pos 18 /**< \brief (TCC_INTENSET) Match or Capture Channel 2 Interrupt Enable */
mbed_official 579:53297373a894 919 #define TCC_INTENSET_MC2 (1 << TCC_INTENSET_MC2_Pos)
mbed_official 579:53297373a894 920 #define TCC_INTENSET_MC3_Pos 19 /**< \brief (TCC_INTENSET) Match or Capture Channel 3 Interrupt Enable */
mbed_official 579:53297373a894 921 #define TCC_INTENSET_MC3 (1 << TCC_INTENSET_MC3_Pos)
mbed_official 579:53297373a894 922 #define TCC_INTENSET_MC_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel x Interrupt Enable */
mbed_official 579:53297373a894 923 #define TCC_INTENSET_MC_Msk (0xFul << TCC_INTENSET_MC_Pos)
mbed_official 579:53297373a894 924 #define TCC_INTENSET_MC(value) ((TCC_INTENSET_MC_Msk & ((value) << TCC_INTENSET_MC_Pos)))
mbed_official 579:53297373a894 925 #define TCC_INTENSET_MASK 0x000FF80Ful /**< \brief (TCC_INTENSET) MASK Register */
mbed_official 579:53297373a894 926
mbed_official 579:53297373a894 927 /* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */
mbed_official 579:53297373a894 928 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 929 typedef union {
mbed_official 579:53297373a894 930 struct {
mbed_official 579:53297373a894 931 uint32_t OVF:1; /*!< bit: 0 Overflow */
mbed_official 579:53297373a894 932 uint32_t TRG:1; /*!< bit: 1 Retrigger */
mbed_official 579:53297373a894 933 uint32_t CNT:1; /*!< bit: 2 Counter */
mbed_official 579:53297373a894 934 uint32_t ERR:1; /*!< bit: 3 Error */
mbed_official 579:53297373a894 935 uint32_t :7; /*!< bit: 4..10 Reserved */
mbed_official 579:53297373a894 936 uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */
mbed_official 579:53297373a894 937 uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */
mbed_official 579:53297373a894 938 uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */
mbed_official 579:53297373a894 939 uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */
mbed_official 579:53297373a894 940 uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */
mbed_official 579:53297373a894 941 uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */
mbed_official 579:53297373a894 942 uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */
mbed_official 579:53297373a894 943 uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */
mbed_official 579:53297373a894 944 uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */
mbed_official 579:53297373a894 945 uint32_t :12; /*!< bit: 20..31 Reserved */
mbed_official 579:53297373a894 946 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 947 struct {
mbed_official 579:53297373a894 948 uint32_t :16; /*!< bit: 0..15 Reserved */
mbed_official 579:53297373a894 949 uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */
mbed_official 579:53297373a894 950 uint32_t :12; /*!< bit: 20..31 Reserved */
mbed_official 579:53297373a894 951 } vec; /*!< Structure used for vec access */
mbed_official 579:53297373a894 952 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 953 } TCC_INTFLAG_Type;
mbed_official 579:53297373a894 954 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 955
mbed_official 579:53297373a894 956 #define TCC_INTFLAG_OFFSET 0x2C /**< \brief (TCC_INTFLAG offset) Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 957 #define TCC_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (TCC_INTFLAG reset_value) Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 958
mbed_official 579:53297373a894 959 #define TCC_INTFLAG_OVF_Pos 0 /**< \brief (TCC_INTFLAG) Overflow */
mbed_official 579:53297373a894 960 #define TCC_INTFLAG_OVF (0x1ul << TCC_INTFLAG_OVF_Pos)
mbed_official 579:53297373a894 961 #define TCC_INTFLAG_TRG_Pos 1 /**< \brief (TCC_INTFLAG) Retrigger */
mbed_official 579:53297373a894 962 #define TCC_INTFLAG_TRG (0x1ul << TCC_INTFLAG_TRG_Pos)
mbed_official 579:53297373a894 963 #define TCC_INTFLAG_CNT_Pos 2 /**< \brief (TCC_INTFLAG) Counter */
mbed_official 579:53297373a894 964 #define TCC_INTFLAG_CNT (0x1ul << TCC_INTFLAG_CNT_Pos)
mbed_official 579:53297373a894 965 #define TCC_INTFLAG_ERR_Pos 3 /**< \brief (TCC_INTFLAG) Error */
mbed_official 579:53297373a894 966 #define TCC_INTFLAG_ERR (0x1ul << TCC_INTFLAG_ERR_Pos)
mbed_official 579:53297373a894 967 #define TCC_INTFLAG_DFS_Pos 11 /**< \brief (TCC_INTFLAG) Non-Recoverable Debug Fault */
mbed_official 579:53297373a894 968 #define TCC_INTFLAG_DFS (0x1ul << TCC_INTFLAG_DFS_Pos)
mbed_official 579:53297373a894 969 #define TCC_INTFLAG_FAULTA_Pos 12 /**< \brief (TCC_INTFLAG) Recoverable Fault A */
mbed_official 579:53297373a894 970 #define TCC_INTFLAG_FAULTA (0x1ul << TCC_INTFLAG_FAULTA_Pos)
mbed_official 579:53297373a894 971 #define TCC_INTFLAG_FAULTB_Pos 13 /**< \brief (TCC_INTFLAG) Recoverable Fault B */
mbed_official 579:53297373a894 972 #define TCC_INTFLAG_FAULTB (0x1ul << TCC_INTFLAG_FAULTB_Pos)
mbed_official 579:53297373a894 973 #define TCC_INTFLAG_FAULT0_Pos 14 /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 0 */
mbed_official 579:53297373a894 974 #define TCC_INTFLAG_FAULT0 (0x1ul << TCC_INTFLAG_FAULT0_Pos)
mbed_official 579:53297373a894 975 #define TCC_INTFLAG_FAULT1_Pos 15 /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 1 */
mbed_official 579:53297373a894 976 #define TCC_INTFLAG_FAULT1 (0x1ul << TCC_INTFLAG_FAULT1_Pos)
mbed_official 579:53297373a894 977 #define TCC_INTFLAG_MC0_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture 0 */
mbed_official 579:53297373a894 978 #define TCC_INTFLAG_MC0 (1 << TCC_INTFLAG_MC0_Pos)
mbed_official 579:53297373a894 979 #define TCC_INTFLAG_MC1_Pos 17 /**< \brief (TCC_INTFLAG) Match or Capture 1 */
mbed_official 579:53297373a894 980 #define TCC_INTFLAG_MC1 (1 << TCC_INTFLAG_MC1_Pos)
mbed_official 579:53297373a894 981 #define TCC_INTFLAG_MC2_Pos 18 /**< \brief (TCC_INTFLAG) Match or Capture 2 */
mbed_official 579:53297373a894 982 #define TCC_INTFLAG_MC2 (1 << TCC_INTFLAG_MC2_Pos)
mbed_official 579:53297373a894 983 #define TCC_INTFLAG_MC3_Pos 19 /**< \brief (TCC_INTFLAG) Match or Capture 3 */
mbed_official 579:53297373a894 984 #define TCC_INTFLAG_MC3 (1 << TCC_INTFLAG_MC3_Pos)
mbed_official 579:53297373a894 985 #define TCC_INTFLAG_MC_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture x */
mbed_official 579:53297373a894 986 #define TCC_INTFLAG_MC_Msk (0xFul << TCC_INTFLAG_MC_Pos)
mbed_official 579:53297373a894 987 #define TCC_INTFLAG_MC(value) ((TCC_INTFLAG_MC_Msk & ((value) << TCC_INTFLAG_MC_Pos)))
mbed_official 579:53297373a894 988 #define TCC_INTFLAG_MASK 0x000FF80Ful /**< \brief (TCC_INTFLAG) MASK Register */
mbed_official 579:53297373a894 989
mbed_official 579:53297373a894 990 /* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */
mbed_official 579:53297373a894 991 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 992 typedef union {
mbed_official 579:53297373a894 993 struct {
mbed_official 579:53297373a894 994 uint32_t STOP:1; /*!< bit: 0 Stop */
mbed_official 579:53297373a894 995 uint32_t IDX:1; /*!< bit: 1 Ramp */
mbed_official 579:53297373a894 996 uint32_t :1; /*!< bit: 2 Reserved */
mbed_official 579:53297373a894 997 uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */
mbed_official 579:53297373a894 998 uint32_t SLAVE:1; /*!< bit: 4 Slave */
mbed_official 579:53297373a894 999 uint32_t PATTBV:1; /*!< bit: 5 Pattern Buffer Valid */
mbed_official 579:53297373a894 1000 uint32_t WAVEBV:1; /*!< bit: 6 Wave Buffer Valid */
mbed_official 579:53297373a894 1001 uint32_t PERBV:1; /*!< bit: 7 Period Buffer Valid */
mbed_official 579:53297373a894 1002 uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable Fault A Input */
mbed_official 579:53297373a894 1003 uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable Fault B Input */
mbed_official 579:53297373a894 1004 uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */
mbed_official 579:53297373a894 1005 uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */
mbed_official 579:53297373a894 1006 uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A State */
mbed_official 579:53297373a894 1007 uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B State */
mbed_official 579:53297373a894 1008 uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */
mbed_official 579:53297373a894 1009 uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */
mbed_official 579:53297373a894 1010 uint32_t CCBV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */
mbed_official 579:53297373a894 1011 uint32_t CCBV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */
mbed_official 579:53297373a894 1012 uint32_t CCBV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */
mbed_official 579:53297373a894 1013 uint32_t CCBV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */
mbed_official 579:53297373a894 1014 uint32_t :4; /*!< bit: 20..23 Reserved */
mbed_official 579:53297373a894 1015 uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */
mbed_official 579:53297373a894 1016 uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */
mbed_official 579:53297373a894 1017 uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */
mbed_official 579:53297373a894 1018 uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */
mbed_official 579:53297373a894 1019 uint32_t :4; /*!< bit: 28..31 Reserved */
mbed_official 579:53297373a894 1020 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 1021 struct {
mbed_official 579:53297373a894 1022 uint32_t :16; /*!< bit: 0..15 Reserved */
mbed_official 579:53297373a894 1023 uint32_t CCBV:4; /*!< bit: 16..19 Compare Channel x Buffer Valid */
mbed_official 579:53297373a894 1024 uint32_t :4; /*!< bit: 20..23 Reserved */
mbed_official 579:53297373a894 1025 uint32_t CMP:4; /*!< bit: 24..27 Compare Channel x Value */
mbed_official 579:53297373a894 1026 uint32_t :4; /*!< bit: 28..31 Reserved */
mbed_official 579:53297373a894 1027 } vec; /*!< Structure used for vec access */
mbed_official 579:53297373a894 1028 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 1029 } TCC_STATUS_Type;
mbed_official 579:53297373a894 1030 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 1031
mbed_official 579:53297373a894 1032 #define TCC_STATUS_OFFSET 0x30 /**< \brief (TCC_STATUS offset) Status */
mbed_official 579:53297373a894 1033 #define TCC_STATUS_RESETVALUE 0x00000001ul /**< \brief (TCC_STATUS reset_value) Status */
mbed_official 579:53297373a894 1034
mbed_official 579:53297373a894 1035 #define TCC_STATUS_STOP_Pos 0 /**< \brief (TCC_STATUS) Stop */
mbed_official 579:53297373a894 1036 #define TCC_STATUS_STOP (0x1ul << TCC_STATUS_STOP_Pos)
mbed_official 579:53297373a894 1037 #define TCC_STATUS_IDX_Pos 1 /**< \brief (TCC_STATUS) Ramp */
mbed_official 579:53297373a894 1038 #define TCC_STATUS_IDX (0x1ul << TCC_STATUS_IDX_Pos)
mbed_official 579:53297373a894 1039 #define TCC_STATUS_DFS_Pos 3 /**< \brief (TCC_STATUS) Non-Recoverable Debug Fault State */
mbed_official 579:53297373a894 1040 #define TCC_STATUS_DFS (0x1ul << TCC_STATUS_DFS_Pos)
mbed_official 579:53297373a894 1041 #define TCC_STATUS_SLAVE_Pos 4 /**< \brief (TCC_STATUS) Slave */
mbed_official 579:53297373a894 1042 #define TCC_STATUS_SLAVE (0x1ul << TCC_STATUS_SLAVE_Pos)
mbed_official 579:53297373a894 1043 #define TCC_STATUS_PATTBV_Pos 5 /**< \brief (TCC_STATUS) Pattern Buffer Valid */
mbed_official 579:53297373a894 1044 #define TCC_STATUS_PATTBV (0x1ul << TCC_STATUS_PATTBV_Pos)
mbed_official 579:53297373a894 1045 #define TCC_STATUS_WAVEBV_Pos 6 /**< \brief (TCC_STATUS) Wave Buffer Valid */
mbed_official 579:53297373a894 1046 #define TCC_STATUS_WAVEBV (0x1ul << TCC_STATUS_WAVEBV_Pos)
mbed_official 579:53297373a894 1047 #define TCC_STATUS_PERBV_Pos 7 /**< \brief (TCC_STATUS) Period Buffer Valid */
mbed_official 579:53297373a894 1048 #define TCC_STATUS_PERBV (0x1ul << TCC_STATUS_PERBV_Pos)
mbed_official 579:53297373a894 1049 #define TCC_STATUS_FAULTAIN_Pos 8 /**< \brief (TCC_STATUS) Recoverable Fault A Input */
mbed_official 579:53297373a894 1050 #define TCC_STATUS_FAULTAIN (0x1ul << TCC_STATUS_FAULTAIN_Pos)
mbed_official 579:53297373a894 1051 #define TCC_STATUS_FAULTBIN_Pos 9 /**< \brief (TCC_STATUS) Recoverable Fault B Input */
mbed_official 579:53297373a894 1052 #define TCC_STATUS_FAULTBIN (0x1ul << TCC_STATUS_FAULTBIN_Pos)
mbed_official 579:53297373a894 1053 #define TCC_STATUS_FAULT0IN_Pos 10 /**< \brief (TCC_STATUS) Non-Recoverable Fault0 Input */
mbed_official 579:53297373a894 1054 #define TCC_STATUS_FAULT0IN (0x1ul << TCC_STATUS_FAULT0IN_Pos)
mbed_official 579:53297373a894 1055 #define TCC_STATUS_FAULT1IN_Pos 11 /**< \brief (TCC_STATUS) Non-Recoverable Fault1 Input */
mbed_official 579:53297373a894 1056 #define TCC_STATUS_FAULT1IN (0x1ul << TCC_STATUS_FAULT1IN_Pos)
mbed_official 579:53297373a894 1057 #define TCC_STATUS_FAULTA_Pos 12 /**< \brief (TCC_STATUS) Recoverable Fault A State */
mbed_official 579:53297373a894 1058 #define TCC_STATUS_FAULTA (0x1ul << TCC_STATUS_FAULTA_Pos)
mbed_official 579:53297373a894 1059 #define TCC_STATUS_FAULTB_Pos 13 /**< \brief (TCC_STATUS) Recoverable Fault B State */
mbed_official 579:53297373a894 1060 #define TCC_STATUS_FAULTB (0x1ul << TCC_STATUS_FAULTB_Pos)
mbed_official 579:53297373a894 1061 #define TCC_STATUS_FAULT0_Pos 14 /**< \brief (TCC_STATUS) Non-Recoverable Fault 0 State */
mbed_official 579:53297373a894 1062 #define TCC_STATUS_FAULT0 (0x1ul << TCC_STATUS_FAULT0_Pos)
mbed_official 579:53297373a894 1063 #define TCC_STATUS_FAULT1_Pos 15 /**< \brief (TCC_STATUS) Non-Recoverable Fault 1 State */
mbed_official 579:53297373a894 1064 #define TCC_STATUS_FAULT1 (0x1ul << TCC_STATUS_FAULT1_Pos)
mbed_official 579:53297373a894 1065 #define TCC_STATUS_CCBV0_Pos 16 /**< \brief (TCC_STATUS) Compare Channel 0 Buffer Valid */
mbed_official 579:53297373a894 1066 #define TCC_STATUS_CCBV0 (1 << TCC_STATUS_CCBV0_Pos)
mbed_official 579:53297373a894 1067 #define TCC_STATUS_CCBV1_Pos 17 /**< \brief (TCC_STATUS) Compare Channel 1 Buffer Valid */
mbed_official 579:53297373a894 1068 #define TCC_STATUS_CCBV1 (1 << TCC_STATUS_CCBV1_Pos)
mbed_official 579:53297373a894 1069 #define TCC_STATUS_CCBV2_Pos 18 /**< \brief (TCC_STATUS) Compare Channel 2 Buffer Valid */
mbed_official 579:53297373a894 1070 #define TCC_STATUS_CCBV2 (1 << TCC_STATUS_CCBV2_Pos)
mbed_official 579:53297373a894 1071 #define TCC_STATUS_CCBV3_Pos 19 /**< \brief (TCC_STATUS) Compare Channel 3 Buffer Valid */
mbed_official 579:53297373a894 1072 #define TCC_STATUS_CCBV3 (1 << TCC_STATUS_CCBV3_Pos)
mbed_official 579:53297373a894 1073 #define TCC_STATUS_CCBV_Pos 16 /**< \brief (TCC_STATUS) Compare Channel x Buffer Valid */
mbed_official 579:53297373a894 1074 #define TCC_STATUS_CCBV_Msk (0xFul << TCC_STATUS_CCBV_Pos)
mbed_official 579:53297373a894 1075 #define TCC_STATUS_CCBV(value) ((TCC_STATUS_CCBV_Msk & ((value) << TCC_STATUS_CCBV_Pos)))
mbed_official 579:53297373a894 1076 #define TCC_STATUS_CMP0_Pos 24 /**< \brief (TCC_STATUS) Compare Channel 0 Value */
mbed_official 579:53297373a894 1077 #define TCC_STATUS_CMP0 (1 << TCC_STATUS_CMP0_Pos)
mbed_official 579:53297373a894 1078 #define TCC_STATUS_CMP1_Pos 25 /**< \brief (TCC_STATUS) Compare Channel 1 Value */
mbed_official 579:53297373a894 1079 #define TCC_STATUS_CMP1 (1 << TCC_STATUS_CMP1_Pos)
mbed_official 579:53297373a894 1080 #define TCC_STATUS_CMP2_Pos 26 /**< \brief (TCC_STATUS) Compare Channel 2 Value */
mbed_official 579:53297373a894 1081 #define TCC_STATUS_CMP2 (1 << TCC_STATUS_CMP2_Pos)
mbed_official 579:53297373a894 1082 #define TCC_STATUS_CMP3_Pos 27 /**< \brief (TCC_STATUS) Compare Channel 3 Value */
mbed_official 579:53297373a894 1083 #define TCC_STATUS_CMP3 (1 << TCC_STATUS_CMP3_Pos)
mbed_official 579:53297373a894 1084 #define TCC_STATUS_CMP_Pos 24 /**< \brief (TCC_STATUS) Compare Channel x Value */
mbed_official 579:53297373a894 1085 #define TCC_STATUS_CMP_Msk (0xFul << TCC_STATUS_CMP_Pos)
mbed_official 579:53297373a894 1086 #define TCC_STATUS_CMP(value) ((TCC_STATUS_CMP_Msk & ((value) << TCC_STATUS_CMP_Pos)))
mbed_official 579:53297373a894 1087 #define TCC_STATUS_MASK 0x0F0FFFFBul /**< \brief (TCC_STATUS) MASK Register */
mbed_official 579:53297373a894 1088
mbed_official 579:53297373a894 1089 /* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */
mbed_official 579:53297373a894 1090 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 1091 typedef union {
mbed_official 579:53297373a894 1092 struct { // DITH4 mode
mbed_official 579:53297373a894 1093 uint32_t :4; /*!< bit: 0.. 3 Reserved */
mbed_official 579:53297373a894 1094 uint32_t COUNT:20; /*!< bit: 4..23 Counter Value */
mbed_official 579:53297373a894 1095 uint32_t :8; /*!< bit: 24..31 Reserved */
mbed_official 579:53297373a894 1096 } DITH4; /*!< Structure used for DITH4 */
mbed_official 579:53297373a894 1097 struct { // DITH5 mode
mbed_official 579:53297373a894 1098 uint32_t :5; /*!< bit: 0.. 4 Reserved */
mbed_official 579:53297373a894 1099 uint32_t COUNT:19; /*!< bit: 5..23 Counter Value */
mbed_official 579:53297373a894 1100 uint32_t :8; /*!< bit: 24..31 Reserved */
mbed_official 579:53297373a894 1101 } DITH5; /*!< Structure used for DITH5 */
mbed_official 579:53297373a894 1102 struct { // DITH6 mode
mbed_official 579:53297373a894 1103 uint32_t :6; /*!< bit: 0.. 5 Reserved */
mbed_official 579:53297373a894 1104 uint32_t COUNT:18; /*!< bit: 6..23 Counter Value */
mbed_official 579:53297373a894 1105 uint32_t :8; /*!< bit: 24..31 Reserved */
mbed_official 579:53297373a894 1106 } DITH6; /*!< Structure used for DITH6 */
mbed_official 579:53297373a894 1107 struct {
mbed_official 579:53297373a894 1108 uint32_t COUNT:24; /*!< bit: 0..23 Counter Value */
mbed_official 579:53297373a894 1109 uint32_t :8; /*!< bit: 24..31 Reserved */
mbed_official 579:53297373a894 1110 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 1111 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 1112 } TCC_COUNT_Type;
mbed_official 579:53297373a894 1113 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 1114
mbed_official 579:53297373a894 1115 #define TCC_COUNT_OFFSET 0x34 /**< \brief (TCC_COUNT offset) Count */
mbed_official 579:53297373a894 1116 #define TCC_COUNT_RESETVALUE 0x00000000ul /**< \brief (TCC_COUNT reset_value) Count */
mbed_official 579:53297373a894 1117
mbed_official 579:53297373a894 1118 // DITH4 mode
mbed_official 579:53297373a894 1119 #define TCC_COUNT_DITH4_COUNT_Pos 4 /**< \brief (TCC_COUNT_DITH4) Counter Value */
mbed_official 579:53297373a894 1120 #define TCC_COUNT_DITH4_COUNT_Msk (0xFFFFFul << TCC_COUNT_DITH4_COUNT_Pos)
mbed_official 579:53297373a894 1121 #define TCC_COUNT_DITH4_COUNT(value) ((TCC_COUNT_DITH4_COUNT_Msk & ((value) << TCC_COUNT_DITH4_COUNT_Pos)))
mbed_official 579:53297373a894 1122 #define TCC_COUNT_DITH4_MASK 0x00FFFFF0ul /**< \brief (TCC_COUNT_DITH4) MASK Register */
mbed_official 579:53297373a894 1123
mbed_official 579:53297373a894 1124 // DITH5 mode
mbed_official 579:53297373a894 1125 #define TCC_COUNT_DITH5_COUNT_Pos 5 /**< \brief (TCC_COUNT_DITH5) Counter Value */
mbed_official 579:53297373a894 1126 #define TCC_COUNT_DITH5_COUNT_Msk (0x7FFFFul << TCC_COUNT_DITH5_COUNT_Pos)
mbed_official 579:53297373a894 1127 #define TCC_COUNT_DITH5_COUNT(value) ((TCC_COUNT_DITH5_COUNT_Msk & ((value) << TCC_COUNT_DITH5_COUNT_Pos)))
mbed_official 579:53297373a894 1128 #define TCC_COUNT_DITH5_MASK 0x00FFFFE0ul /**< \brief (TCC_COUNT_DITH5) MASK Register */
mbed_official 579:53297373a894 1129
mbed_official 579:53297373a894 1130 // DITH6 mode
mbed_official 579:53297373a894 1131 #define TCC_COUNT_DITH6_COUNT_Pos 6 /**< \brief (TCC_COUNT_DITH6) Counter Value */
mbed_official 579:53297373a894 1132 #define TCC_COUNT_DITH6_COUNT_Msk (0x3FFFFul << TCC_COUNT_DITH6_COUNT_Pos)
mbed_official 579:53297373a894 1133 #define TCC_COUNT_DITH6_COUNT(value) ((TCC_COUNT_DITH6_COUNT_Msk & ((value) << TCC_COUNT_DITH6_COUNT_Pos)))
mbed_official 579:53297373a894 1134 #define TCC_COUNT_DITH6_MASK 0x00FFFFC0ul /**< \brief (TCC_COUNT_DITH6) MASK Register */
mbed_official 579:53297373a894 1135
mbed_official 579:53297373a894 1136 #define TCC_COUNT_COUNT_Pos 0 /**< \brief (TCC_COUNT) Counter Value */
mbed_official 579:53297373a894 1137 #define TCC_COUNT_COUNT_Msk (0xFFFFFFul << TCC_COUNT_COUNT_Pos)
mbed_official 579:53297373a894 1138 #define TCC_COUNT_COUNT(value) ((TCC_COUNT_COUNT_Msk & ((value) << TCC_COUNT_COUNT_Pos)))
mbed_official 579:53297373a894 1139 #define TCC_COUNT_MASK 0x00FFFFFFul /**< \brief (TCC_COUNT) MASK Register */
mbed_official 579:53297373a894 1140
mbed_official 579:53297373a894 1141 /* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */
mbed_official 579:53297373a894 1142 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 1143 typedef union {
mbed_official 579:53297373a894 1144 struct {
mbed_official 579:53297373a894 1145 uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */
mbed_official 579:53297373a894 1146 uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */
mbed_official 579:53297373a894 1147 uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */
mbed_official 579:53297373a894 1148 uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */
mbed_official 579:53297373a894 1149 uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */
mbed_official 579:53297373a894 1150 uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */
mbed_official 579:53297373a894 1151 uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */
mbed_official 579:53297373a894 1152 uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */
mbed_official 579:53297373a894 1153 uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */
mbed_official 579:53297373a894 1154 uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */
mbed_official 579:53297373a894 1155 uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */
mbed_official 579:53297373a894 1156 uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */
mbed_official 579:53297373a894 1157 uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */
mbed_official 579:53297373a894 1158 uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */
mbed_official 579:53297373a894 1159 uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */
mbed_official 579:53297373a894 1160 uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */
mbed_official 579:53297373a894 1161 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 1162 struct {
mbed_official 579:53297373a894 1163 uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */
mbed_official 579:53297373a894 1164 uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */
mbed_official 579:53297373a894 1165 } vec; /*!< Structure used for vec access */
mbed_official 579:53297373a894 1166 uint16_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 1167 } TCC_PATT_Type;
mbed_official 579:53297373a894 1168 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 1169
mbed_official 579:53297373a894 1170 #define TCC_PATT_OFFSET 0x38 /**< \brief (TCC_PATT offset) Pattern */
mbed_official 579:53297373a894 1171 #define TCC_PATT_RESETVALUE 0x0000ul /**< \brief (TCC_PATT reset_value) Pattern */
mbed_official 579:53297373a894 1172
mbed_official 579:53297373a894 1173 #define TCC_PATT_PGE0_Pos 0 /**< \brief (TCC_PATT) Pattern Generator 0 Output Enable */
mbed_official 579:53297373a894 1174 #define TCC_PATT_PGE0 (1 << TCC_PATT_PGE0_Pos)
mbed_official 579:53297373a894 1175 #define TCC_PATT_PGE1_Pos 1 /**< \brief (TCC_PATT) Pattern Generator 1 Output Enable */
mbed_official 579:53297373a894 1176 #define TCC_PATT_PGE1 (1 << TCC_PATT_PGE1_Pos)
mbed_official 579:53297373a894 1177 #define TCC_PATT_PGE2_Pos 2 /**< \brief (TCC_PATT) Pattern Generator 2 Output Enable */
mbed_official 579:53297373a894 1178 #define TCC_PATT_PGE2 (1 << TCC_PATT_PGE2_Pos)
mbed_official 579:53297373a894 1179 #define TCC_PATT_PGE3_Pos 3 /**< \brief (TCC_PATT) Pattern Generator 3 Output Enable */
mbed_official 579:53297373a894 1180 #define TCC_PATT_PGE3 (1 << TCC_PATT_PGE3_Pos)
mbed_official 579:53297373a894 1181 #define TCC_PATT_PGE4_Pos 4 /**< \brief (TCC_PATT) Pattern Generator 4 Output Enable */
mbed_official 579:53297373a894 1182 #define TCC_PATT_PGE4 (1 << TCC_PATT_PGE4_Pos)
mbed_official 579:53297373a894 1183 #define TCC_PATT_PGE5_Pos 5 /**< \brief (TCC_PATT) Pattern Generator 5 Output Enable */
mbed_official 579:53297373a894 1184 #define TCC_PATT_PGE5 (1 << TCC_PATT_PGE5_Pos)
mbed_official 579:53297373a894 1185 #define TCC_PATT_PGE6_Pos 6 /**< \brief (TCC_PATT) Pattern Generator 6 Output Enable */
mbed_official 579:53297373a894 1186 #define TCC_PATT_PGE6 (1 << TCC_PATT_PGE6_Pos)
mbed_official 579:53297373a894 1187 #define TCC_PATT_PGE7_Pos 7 /**< \brief (TCC_PATT) Pattern Generator 7 Output Enable */
mbed_official 579:53297373a894 1188 #define TCC_PATT_PGE7 (1 << TCC_PATT_PGE7_Pos)
mbed_official 579:53297373a894 1189 #define TCC_PATT_PGE_Pos 0 /**< \brief (TCC_PATT) Pattern Generator x Output Enable */
mbed_official 579:53297373a894 1190 #define TCC_PATT_PGE_Msk (0xFFul << TCC_PATT_PGE_Pos)
mbed_official 579:53297373a894 1191 #define TCC_PATT_PGE(value) ((TCC_PATT_PGE_Msk & ((value) << TCC_PATT_PGE_Pos)))
mbed_official 579:53297373a894 1192 #define TCC_PATT_PGV0_Pos 8 /**< \brief (TCC_PATT) Pattern Generator 0 Output Value */
mbed_official 579:53297373a894 1193 #define TCC_PATT_PGV0 (1 << TCC_PATT_PGV0_Pos)
mbed_official 579:53297373a894 1194 #define TCC_PATT_PGV1_Pos 9 /**< \brief (TCC_PATT) Pattern Generator 1 Output Value */
mbed_official 579:53297373a894 1195 #define TCC_PATT_PGV1 (1 << TCC_PATT_PGV1_Pos)
mbed_official 579:53297373a894 1196 #define TCC_PATT_PGV2_Pos 10 /**< \brief (TCC_PATT) Pattern Generator 2 Output Value */
mbed_official 579:53297373a894 1197 #define TCC_PATT_PGV2 (1 << TCC_PATT_PGV2_Pos)
mbed_official 579:53297373a894 1198 #define TCC_PATT_PGV3_Pos 11 /**< \brief (TCC_PATT) Pattern Generator 3 Output Value */
mbed_official 579:53297373a894 1199 #define TCC_PATT_PGV3 (1 << TCC_PATT_PGV3_Pos)
mbed_official 579:53297373a894 1200 #define TCC_PATT_PGV4_Pos 12 /**< \brief (TCC_PATT) Pattern Generator 4 Output Value */
mbed_official 579:53297373a894 1201 #define TCC_PATT_PGV4 (1 << TCC_PATT_PGV4_Pos)
mbed_official 579:53297373a894 1202 #define TCC_PATT_PGV5_Pos 13 /**< \brief (TCC_PATT) Pattern Generator 5 Output Value */
mbed_official 579:53297373a894 1203 #define TCC_PATT_PGV5 (1 << TCC_PATT_PGV5_Pos)
mbed_official 579:53297373a894 1204 #define TCC_PATT_PGV6_Pos 14 /**< \brief (TCC_PATT) Pattern Generator 6 Output Value */
mbed_official 579:53297373a894 1205 #define TCC_PATT_PGV6 (1 << TCC_PATT_PGV6_Pos)
mbed_official 579:53297373a894 1206 #define TCC_PATT_PGV7_Pos 15 /**< \brief (TCC_PATT) Pattern Generator 7 Output Value */
mbed_official 579:53297373a894 1207 #define TCC_PATT_PGV7 (1 << TCC_PATT_PGV7_Pos)
mbed_official 579:53297373a894 1208 #define TCC_PATT_PGV_Pos 8 /**< \brief (TCC_PATT) Pattern Generator x Output Value */
mbed_official 579:53297373a894 1209 #define TCC_PATT_PGV_Msk (0xFFul << TCC_PATT_PGV_Pos)
mbed_official 579:53297373a894 1210 #define TCC_PATT_PGV(value) ((TCC_PATT_PGV_Msk & ((value) << TCC_PATT_PGV_Pos)))
mbed_official 579:53297373a894 1211 #define TCC_PATT_MASK 0xFFFFul /**< \brief (TCC_PATT) MASK Register */
mbed_official 579:53297373a894 1212
mbed_official 579:53297373a894 1213 /* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */
mbed_official 579:53297373a894 1214 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 1215 typedef union {
mbed_official 579:53297373a894 1216 struct {
mbed_official 579:53297373a894 1217 uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */
mbed_official 579:53297373a894 1218 uint32_t :1; /*!< bit: 3 Reserved */
mbed_official 579:53297373a894 1219 uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */
mbed_official 579:53297373a894 1220 uint32_t :1; /*!< bit: 6 Reserved */
mbed_official 579:53297373a894 1221 uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */
mbed_official 579:53297373a894 1222 uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */
mbed_official 579:53297373a894 1223 uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */
mbed_official 579:53297373a894 1224 uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */
mbed_official 579:53297373a894 1225 uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */
mbed_official 579:53297373a894 1226 uint32_t :4; /*!< bit: 12..15 Reserved */
mbed_official 579:53297373a894 1227 uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */
mbed_official 579:53297373a894 1228 uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */
mbed_official 579:53297373a894 1229 uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */
mbed_official 579:53297373a894 1230 uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */
mbed_official 579:53297373a894 1231 uint32_t :4; /*!< bit: 20..23 Reserved */
mbed_official 579:53297373a894 1232 uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */
mbed_official 579:53297373a894 1233 uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */
mbed_official 579:53297373a894 1234 uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */
mbed_official 579:53297373a894 1235 uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */
mbed_official 579:53297373a894 1236 uint32_t :4; /*!< bit: 28..31 Reserved */
mbed_official 579:53297373a894 1237 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 1238 struct {
mbed_official 579:53297373a894 1239 uint32_t :8; /*!< bit: 0.. 7 Reserved */
mbed_official 579:53297373a894 1240 uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */
mbed_official 579:53297373a894 1241 uint32_t :4; /*!< bit: 12..15 Reserved */
mbed_official 579:53297373a894 1242 uint32_t POL:4; /*!< bit: 16..19 Channel x Polarity */
mbed_official 579:53297373a894 1243 uint32_t :4; /*!< bit: 20..23 Reserved */
mbed_official 579:53297373a894 1244 uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */
mbed_official 579:53297373a894 1245 uint32_t :4; /*!< bit: 28..31 Reserved */
mbed_official 579:53297373a894 1246 } vec; /*!< Structure used for vec access */
mbed_official 579:53297373a894 1247 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 1248 } TCC_WAVE_Type;
mbed_official 579:53297373a894 1249 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 1250
mbed_official 579:53297373a894 1251 #define TCC_WAVE_OFFSET 0x3C /**< \brief (TCC_WAVE offset) Waveform Control */
mbed_official 579:53297373a894 1252 #define TCC_WAVE_RESETVALUE 0x00000000ul /**< \brief (TCC_WAVE reset_value) Waveform Control */
mbed_official 579:53297373a894 1253
mbed_official 579:53297373a894 1254 #define TCC_WAVE_WAVEGEN_Pos 0 /**< \brief (TCC_WAVE) Waveform Generation */
mbed_official 579:53297373a894 1255 #define TCC_WAVE_WAVEGEN_Msk (0x7ul << TCC_WAVE_WAVEGEN_Pos)
mbed_official 579:53297373a894 1256 #define TCC_WAVE_WAVEGEN(value) ((TCC_WAVE_WAVEGEN_Msk & ((value) << TCC_WAVE_WAVEGEN_Pos)))
mbed_official 579:53297373a894 1257 #define TCC_WAVE_WAVEGEN_NFRQ_Val 0x0ul /**< \brief (TCC_WAVE) Normal frequency */
mbed_official 579:53297373a894 1258 #define TCC_WAVE_WAVEGEN_MFRQ_Val 0x1ul /**< \brief (TCC_WAVE) Match frequency */
mbed_official 579:53297373a894 1259 #define TCC_WAVE_WAVEGEN_NPWM_Val 0x2ul /**< \brief (TCC_WAVE) Normal PWM */
mbed_official 579:53297373a894 1260 #define TCC_WAVE_WAVEGEN_DSCRITICAL_Val 0x4ul /**< \brief (TCC_WAVE) Dual-slope critical */
mbed_official 579:53297373a894 1261 #define TCC_WAVE_WAVEGEN_DSBOTTOM_Val 0x5ul /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO */
mbed_official 579:53297373a894 1262 #define TCC_WAVE_WAVEGEN_DSBOTH_Val 0x6ul /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */
mbed_official 579:53297373a894 1263 #define TCC_WAVE_WAVEGEN_DSTOP_Val 0x7ul /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches TOP */
mbed_official 579:53297373a894 1264 #define TCC_WAVE_WAVEGEN_NFRQ (TCC_WAVE_WAVEGEN_NFRQ_Val << TCC_WAVE_WAVEGEN_Pos)
mbed_official 579:53297373a894 1265 #define TCC_WAVE_WAVEGEN_MFRQ (TCC_WAVE_WAVEGEN_MFRQ_Val << TCC_WAVE_WAVEGEN_Pos)
mbed_official 579:53297373a894 1266 #define TCC_WAVE_WAVEGEN_NPWM (TCC_WAVE_WAVEGEN_NPWM_Val << TCC_WAVE_WAVEGEN_Pos)
mbed_official 579:53297373a894 1267 #define TCC_WAVE_WAVEGEN_DSCRITICAL (TCC_WAVE_WAVEGEN_DSCRITICAL_Val << TCC_WAVE_WAVEGEN_Pos)
mbed_official 579:53297373a894 1268 #define TCC_WAVE_WAVEGEN_DSBOTTOM (TCC_WAVE_WAVEGEN_DSBOTTOM_Val << TCC_WAVE_WAVEGEN_Pos)
mbed_official 579:53297373a894 1269 #define TCC_WAVE_WAVEGEN_DSBOTH (TCC_WAVE_WAVEGEN_DSBOTH_Val << TCC_WAVE_WAVEGEN_Pos)
mbed_official 579:53297373a894 1270 #define TCC_WAVE_WAVEGEN_DSTOP (TCC_WAVE_WAVEGEN_DSTOP_Val << TCC_WAVE_WAVEGEN_Pos)
mbed_official 579:53297373a894 1271 #define TCC_WAVE_RAMP_Pos 4 /**< \brief (TCC_WAVE) Ramp Mode */
mbed_official 579:53297373a894 1272 #define TCC_WAVE_RAMP_Msk (0x3ul << TCC_WAVE_RAMP_Pos)
mbed_official 579:53297373a894 1273 #define TCC_WAVE_RAMP(value) ((TCC_WAVE_RAMP_Msk & ((value) << TCC_WAVE_RAMP_Pos)))
mbed_official 579:53297373a894 1274 #define TCC_WAVE_RAMP_RAMP1_Val 0x0ul /**< \brief (TCC_WAVE) RAMP1 operation */
mbed_official 579:53297373a894 1275 #define TCC_WAVE_RAMP_RAMP2A_Val 0x1ul /**< \brief (TCC_WAVE) Alternative RAMP2 operation */
mbed_official 579:53297373a894 1276 #define TCC_WAVE_RAMP_RAMP2_Val 0x2ul /**< \brief (TCC_WAVE) RAMP2 operation */
mbed_official 579:53297373a894 1277 #define TCC_WAVE_RAMP_RAMP1 (TCC_WAVE_RAMP_RAMP1_Val << TCC_WAVE_RAMP_Pos)
mbed_official 579:53297373a894 1278 #define TCC_WAVE_RAMP_RAMP2A (TCC_WAVE_RAMP_RAMP2A_Val << TCC_WAVE_RAMP_Pos)
mbed_official 579:53297373a894 1279 #define TCC_WAVE_RAMP_RAMP2 (TCC_WAVE_RAMP_RAMP2_Val << TCC_WAVE_RAMP_Pos)
mbed_official 579:53297373a894 1280 #define TCC_WAVE_CIPEREN_Pos 7 /**< \brief (TCC_WAVE) Circular period Enable */
mbed_official 579:53297373a894 1281 #define TCC_WAVE_CIPEREN (0x1ul << TCC_WAVE_CIPEREN_Pos)
mbed_official 579:53297373a894 1282 #define TCC_WAVE_CICCEN0_Pos 8 /**< \brief (TCC_WAVE) Circular Channel 0 Enable */
mbed_official 579:53297373a894 1283 #define TCC_WAVE_CICCEN0 (1 << TCC_WAVE_CICCEN0_Pos)
mbed_official 579:53297373a894 1284 #define TCC_WAVE_CICCEN1_Pos 9 /**< \brief (TCC_WAVE) Circular Channel 1 Enable */
mbed_official 579:53297373a894 1285 #define TCC_WAVE_CICCEN1 (1 << TCC_WAVE_CICCEN1_Pos)
mbed_official 579:53297373a894 1286 #define TCC_WAVE_CICCEN2_Pos 10 /**< \brief (TCC_WAVE) Circular Channel 2 Enable */
mbed_official 579:53297373a894 1287 #define TCC_WAVE_CICCEN2 (1 << TCC_WAVE_CICCEN2_Pos)
mbed_official 579:53297373a894 1288 #define TCC_WAVE_CICCEN3_Pos 11 /**< \brief (TCC_WAVE) Circular Channel 3 Enable */
mbed_official 579:53297373a894 1289 #define TCC_WAVE_CICCEN3 (1 << TCC_WAVE_CICCEN3_Pos)
mbed_official 579:53297373a894 1290 #define TCC_WAVE_CICCEN_Pos 8 /**< \brief (TCC_WAVE) Circular Channel x Enable */
mbed_official 579:53297373a894 1291 #define TCC_WAVE_CICCEN_Msk (0xFul << TCC_WAVE_CICCEN_Pos)
mbed_official 579:53297373a894 1292 #define TCC_WAVE_CICCEN(value) ((TCC_WAVE_CICCEN_Msk & ((value) << TCC_WAVE_CICCEN_Pos)))
mbed_official 579:53297373a894 1293 #define TCC_WAVE_POL0_Pos 16 /**< \brief (TCC_WAVE) Channel 0 Polarity */
mbed_official 579:53297373a894 1294 #define TCC_WAVE_POL0 (1 << TCC_WAVE_POL0_Pos)
mbed_official 579:53297373a894 1295 #define TCC_WAVE_POL1_Pos 17 /**< \brief (TCC_WAVE) Channel 1 Polarity */
mbed_official 579:53297373a894 1296 #define TCC_WAVE_POL1 (1 << TCC_WAVE_POL1_Pos)
mbed_official 579:53297373a894 1297 #define TCC_WAVE_POL2_Pos 18 /**< \brief (TCC_WAVE) Channel 2 Polarity */
mbed_official 579:53297373a894 1298 #define TCC_WAVE_POL2 (1 << TCC_WAVE_POL2_Pos)
mbed_official 579:53297373a894 1299 #define TCC_WAVE_POL3_Pos 19 /**< \brief (TCC_WAVE) Channel 3 Polarity */
mbed_official 579:53297373a894 1300 #define TCC_WAVE_POL3 (1 << TCC_WAVE_POL3_Pos)
mbed_official 579:53297373a894 1301 #define TCC_WAVE_POL_Pos 16 /**< \brief (TCC_WAVE) Channel x Polarity */
mbed_official 579:53297373a894 1302 #define TCC_WAVE_POL_Msk (0xFul << TCC_WAVE_POL_Pos)
mbed_official 579:53297373a894 1303 #define TCC_WAVE_POL(value) ((TCC_WAVE_POL_Msk & ((value) << TCC_WAVE_POL_Pos)))
mbed_official 579:53297373a894 1304 #define TCC_WAVE_SWAP0_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair 0 */
mbed_official 579:53297373a894 1305 #define TCC_WAVE_SWAP0 (1 << TCC_WAVE_SWAP0_Pos)
mbed_official 579:53297373a894 1306 #define TCC_WAVE_SWAP1_Pos 25 /**< \brief (TCC_WAVE) Swap DTI Output Pair 1 */
mbed_official 579:53297373a894 1307 #define TCC_WAVE_SWAP1 (1 << TCC_WAVE_SWAP1_Pos)
mbed_official 579:53297373a894 1308 #define TCC_WAVE_SWAP2_Pos 26 /**< \brief (TCC_WAVE) Swap DTI Output Pair 2 */
mbed_official 579:53297373a894 1309 #define TCC_WAVE_SWAP2 (1 << TCC_WAVE_SWAP2_Pos)
mbed_official 579:53297373a894 1310 #define TCC_WAVE_SWAP3_Pos 27 /**< \brief (TCC_WAVE) Swap DTI Output Pair 3 */
mbed_official 579:53297373a894 1311 #define TCC_WAVE_SWAP3 (1 << TCC_WAVE_SWAP3_Pos)
mbed_official 579:53297373a894 1312 #define TCC_WAVE_SWAP_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair x */
mbed_official 579:53297373a894 1313 #define TCC_WAVE_SWAP_Msk (0xFul << TCC_WAVE_SWAP_Pos)
mbed_official 579:53297373a894 1314 #define TCC_WAVE_SWAP(value) ((TCC_WAVE_SWAP_Msk & ((value) << TCC_WAVE_SWAP_Pos)))
mbed_official 579:53297373a894 1315 #define TCC_WAVE_MASK 0x0F0F0FB7ul /**< \brief (TCC_WAVE) MASK Register */
mbed_official 579:53297373a894 1316
mbed_official 579:53297373a894 1317 /* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */
mbed_official 579:53297373a894 1318 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 1319 typedef union {
mbed_official 579:53297373a894 1320 struct { // DITH4 mode
mbed_official 579:53297373a894 1321 uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */
mbed_official 579:53297373a894 1322 uint32_t PER:20; /*!< bit: 4..23 Period Value */
mbed_official 579:53297373a894 1323 uint32_t :8; /*!< bit: 24..31 Reserved */
mbed_official 579:53297373a894 1324 } DITH4; /*!< Structure used for DITH4 */
mbed_official 579:53297373a894 1325 struct { // DITH5 mode
mbed_official 579:53297373a894 1326 uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */
mbed_official 579:53297373a894 1327 uint32_t PER:19; /*!< bit: 5..23 Period Value */
mbed_official 579:53297373a894 1328 uint32_t :8; /*!< bit: 24..31 Reserved */
mbed_official 579:53297373a894 1329 } DITH5; /*!< Structure used for DITH5 */
mbed_official 579:53297373a894 1330 struct { // DITH6 mode
mbed_official 579:53297373a894 1331 uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */
mbed_official 579:53297373a894 1332 uint32_t PER:18; /*!< bit: 6..23 Period Value */
mbed_official 579:53297373a894 1333 uint32_t :8; /*!< bit: 24..31 Reserved */
mbed_official 579:53297373a894 1334 } DITH6; /*!< Structure used for DITH6 */
mbed_official 579:53297373a894 1335 struct {
mbed_official 579:53297373a894 1336 uint32_t PER:24; /*!< bit: 0..23 Period Value */
mbed_official 579:53297373a894 1337 uint32_t :8; /*!< bit: 24..31 Reserved */
mbed_official 579:53297373a894 1338 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 1339 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 1340 } TCC_PER_Type;
mbed_official 579:53297373a894 1341 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 1342
mbed_official 579:53297373a894 1343 #define TCC_PER_OFFSET 0x40 /**< \brief (TCC_PER offset) Period */
mbed_official 579:53297373a894 1344 #define TCC_PER_RESETVALUE 0xFFFFFFFFul /**< \brief (TCC_PER reset_value) Period */
mbed_official 579:53297373a894 1345
mbed_official 579:53297373a894 1346 // DITH4 mode
mbed_official 579:53297373a894 1347 #define TCC_PER_DITH4_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH4) Dithering Cycle Number */
mbed_official 579:53297373a894 1348 #define TCC_PER_DITH4_DITHERCY_Msk (0xFul << TCC_PER_DITH4_DITHERCY_Pos)
mbed_official 579:53297373a894 1349 #define TCC_PER_DITH4_DITHERCY(value) ((TCC_PER_DITH4_DITHERCY_Msk & ((value) << TCC_PER_DITH4_DITHERCY_Pos)))
mbed_official 579:53297373a894 1350 #define TCC_PER_DITH4_PER_Pos 4 /**< \brief (TCC_PER_DITH4) Period Value */
mbed_official 579:53297373a894 1351 #define TCC_PER_DITH4_PER_Msk (0xFFFFFul << TCC_PER_DITH4_PER_Pos)
mbed_official 579:53297373a894 1352 #define TCC_PER_DITH4_PER(value) ((TCC_PER_DITH4_PER_Msk & ((value) << TCC_PER_DITH4_PER_Pos)))
mbed_official 579:53297373a894 1353 #define TCC_PER_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH4) MASK Register */
mbed_official 579:53297373a894 1354
mbed_official 579:53297373a894 1355 // DITH5 mode
mbed_official 579:53297373a894 1356 #define TCC_PER_DITH5_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH5) Dithering Cycle Number */
mbed_official 579:53297373a894 1357 #define TCC_PER_DITH5_DITHERCY_Msk (0x1Ful << TCC_PER_DITH5_DITHERCY_Pos)
mbed_official 579:53297373a894 1358 #define TCC_PER_DITH5_DITHERCY(value) ((TCC_PER_DITH5_DITHERCY_Msk & ((value) << TCC_PER_DITH5_DITHERCY_Pos)))
mbed_official 579:53297373a894 1359 #define TCC_PER_DITH5_PER_Pos 5 /**< \brief (TCC_PER_DITH5) Period Value */
mbed_official 579:53297373a894 1360 #define TCC_PER_DITH5_PER_Msk (0x7FFFFul << TCC_PER_DITH5_PER_Pos)
mbed_official 579:53297373a894 1361 #define TCC_PER_DITH5_PER(value) ((TCC_PER_DITH5_PER_Msk & ((value) << TCC_PER_DITH5_PER_Pos)))
mbed_official 579:53297373a894 1362 #define TCC_PER_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH5) MASK Register */
mbed_official 579:53297373a894 1363
mbed_official 579:53297373a894 1364 // DITH6 mode
mbed_official 579:53297373a894 1365 #define TCC_PER_DITH6_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH6) Dithering Cycle Number */
mbed_official 579:53297373a894 1366 #define TCC_PER_DITH6_DITHERCY_Msk (0x3Ful << TCC_PER_DITH6_DITHERCY_Pos)
mbed_official 579:53297373a894 1367 #define TCC_PER_DITH6_DITHERCY(value) ((TCC_PER_DITH6_DITHERCY_Msk & ((value) << TCC_PER_DITH6_DITHERCY_Pos)))
mbed_official 579:53297373a894 1368 #define TCC_PER_DITH6_PER_Pos 6 /**< \brief (TCC_PER_DITH6) Period Value */
mbed_official 579:53297373a894 1369 #define TCC_PER_DITH6_PER_Msk (0x3FFFFul << TCC_PER_DITH6_PER_Pos)
mbed_official 579:53297373a894 1370 #define TCC_PER_DITH6_PER(value) ((TCC_PER_DITH6_PER_Msk & ((value) << TCC_PER_DITH6_PER_Pos)))
mbed_official 579:53297373a894 1371 #define TCC_PER_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH6) MASK Register */
mbed_official 579:53297373a894 1372
mbed_official 579:53297373a894 1373 #define TCC_PER_PER_Pos 0 /**< \brief (TCC_PER) Period Value */
mbed_official 579:53297373a894 1374 #define TCC_PER_PER_Msk (0xFFFFFFul << TCC_PER_PER_Pos)
mbed_official 579:53297373a894 1375 #define TCC_PER_PER(value) ((TCC_PER_PER_Msk & ((value) << TCC_PER_PER_Pos)))
mbed_official 579:53297373a894 1376 #define TCC_PER_MASK 0x00FFFFFFul /**< \brief (TCC_PER) MASK Register */
mbed_official 579:53297373a894 1377
mbed_official 579:53297373a894 1378 /* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */
mbed_official 579:53297373a894 1379 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 1380 typedef union {
mbed_official 579:53297373a894 1381 struct { // DITH4 mode
mbed_official 579:53297373a894 1382 uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */
mbed_official 579:53297373a894 1383 uint32_t CC:20; /*!< bit: 4..23 Channel Compare/Capture Value */
mbed_official 579:53297373a894 1384 uint32_t :8; /*!< bit: 24..31 Reserved */
mbed_official 579:53297373a894 1385 } DITH4; /*!< Structure used for DITH4 */
mbed_official 579:53297373a894 1386 struct { // DITH5 mode
mbed_official 579:53297373a894 1387 uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */
mbed_official 579:53297373a894 1388 uint32_t CC:19; /*!< bit: 5..23 Channel Compare/Capture Value */
mbed_official 579:53297373a894 1389 uint32_t :8; /*!< bit: 24..31 Reserved */
mbed_official 579:53297373a894 1390 } DITH5; /*!< Structure used for DITH5 */
mbed_official 579:53297373a894 1391 struct { // DITH6 mode
mbed_official 579:53297373a894 1392 uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */
mbed_official 579:53297373a894 1393 uint32_t CC:18; /*!< bit: 6..23 Channel Compare/Capture Value */
mbed_official 579:53297373a894 1394 uint32_t :8; /*!< bit: 24..31 Reserved */
mbed_official 579:53297373a894 1395 } DITH6; /*!< Structure used for DITH6 */
mbed_official 579:53297373a894 1396 struct {
mbed_official 579:53297373a894 1397 uint32_t CC:24; /*!< bit: 0..23 Channel Compare/Capture Value */
mbed_official 579:53297373a894 1398 uint32_t :8; /*!< bit: 24..31 Reserved */
mbed_official 579:53297373a894 1399 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 1400 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 1401 } TCC_CC_Type;
mbed_official 579:53297373a894 1402 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 1403
mbed_official 579:53297373a894 1404 #define TCC_CC_OFFSET 0x44 /**< \brief (TCC_CC offset) Compare and Capture */
mbed_official 579:53297373a894 1405 #define TCC_CC_RESETVALUE 0x00000000ul /**< \brief (TCC_CC reset_value) Compare and Capture */
mbed_official 579:53297373a894 1406
mbed_official 579:53297373a894 1407 // DITH4 mode
mbed_official 579:53297373a894 1408 #define TCC_CC_DITH4_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH4) Dithering Cycle Number */
mbed_official 579:53297373a894 1409 #define TCC_CC_DITH4_DITHERCY_Msk (0xFul << TCC_CC_DITH4_DITHERCY_Pos)
mbed_official 579:53297373a894 1410 #define TCC_CC_DITH4_DITHERCY(value) ((TCC_CC_DITH4_DITHERCY_Msk & ((value) << TCC_CC_DITH4_DITHERCY_Pos)))
mbed_official 579:53297373a894 1411 #define TCC_CC_DITH4_CC_Pos 4 /**< \brief (TCC_CC_DITH4) Channel Compare/Capture Value */
mbed_official 579:53297373a894 1412 #define TCC_CC_DITH4_CC_Msk (0xFFFFFul << TCC_CC_DITH4_CC_Pos)
mbed_official 579:53297373a894 1413 #define TCC_CC_DITH4_CC(value) ((TCC_CC_DITH4_CC_Msk & ((value) << TCC_CC_DITH4_CC_Pos)))
mbed_official 579:53297373a894 1414 #define TCC_CC_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH4) MASK Register */
mbed_official 579:53297373a894 1415
mbed_official 579:53297373a894 1416 // DITH5 mode
mbed_official 579:53297373a894 1417 #define TCC_CC_DITH5_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH5) Dithering Cycle Number */
mbed_official 579:53297373a894 1418 #define TCC_CC_DITH5_DITHERCY_Msk (0x1Ful << TCC_CC_DITH5_DITHERCY_Pos)
mbed_official 579:53297373a894 1419 #define TCC_CC_DITH5_DITHERCY(value) ((TCC_CC_DITH5_DITHERCY_Msk & ((value) << TCC_CC_DITH5_DITHERCY_Pos)))
mbed_official 579:53297373a894 1420 #define TCC_CC_DITH5_CC_Pos 5 /**< \brief (TCC_CC_DITH5) Channel Compare/Capture Value */
mbed_official 579:53297373a894 1421 #define TCC_CC_DITH5_CC_Msk (0x7FFFFul << TCC_CC_DITH5_CC_Pos)
mbed_official 579:53297373a894 1422 #define TCC_CC_DITH5_CC(value) ((TCC_CC_DITH5_CC_Msk & ((value) << TCC_CC_DITH5_CC_Pos)))
mbed_official 579:53297373a894 1423 #define TCC_CC_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH5) MASK Register */
mbed_official 579:53297373a894 1424
mbed_official 579:53297373a894 1425 // DITH6 mode
mbed_official 579:53297373a894 1426 #define TCC_CC_DITH6_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH6) Dithering Cycle Number */
mbed_official 579:53297373a894 1427 #define TCC_CC_DITH6_DITHERCY_Msk (0x3Ful << TCC_CC_DITH6_DITHERCY_Pos)
mbed_official 579:53297373a894 1428 #define TCC_CC_DITH6_DITHERCY(value) ((TCC_CC_DITH6_DITHERCY_Msk & ((value) << TCC_CC_DITH6_DITHERCY_Pos)))
mbed_official 579:53297373a894 1429 #define TCC_CC_DITH6_CC_Pos 6 /**< \brief (TCC_CC_DITH6) Channel Compare/Capture Value */
mbed_official 579:53297373a894 1430 #define TCC_CC_DITH6_CC_Msk (0x3FFFFul << TCC_CC_DITH6_CC_Pos)
mbed_official 579:53297373a894 1431 #define TCC_CC_DITH6_CC(value) ((TCC_CC_DITH6_CC_Msk & ((value) << TCC_CC_DITH6_CC_Pos)))
mbed_official 579:53297373a894 1432 #define TCC_CC_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH6) MASK Register */
mbed_official 579:53297373a894 1433
mbed_official 579:53297373a894 1434 #define TCC_CC_CC_Pos 0 /**< \brief (TCC_CC) Channel Compare/Capture Value */
mbed_official 579:53297373a894 1435 #define TCC_CC_CC_Msk (0xFFFFFFul << TCC_CC_CC_Pos)
mbed_official 579:53297373a894 1436 #define TCC_CC_CC(value) ((TCC_CC_CC_Msk & ((value) << TCC_CC_CC_Pos)))
mbed_official 579:53297373a894 1437 #define TCC_CC_MASK 0x00FFFFFFul /**< \brief (TCC_CC) MASK Register */
mbed_official 579:53297373a894 1438
mbed_official 579:53297373a894 1439 /* -------- TCC_PATTB : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */
mbed_official 579:53297373a894 1440 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 1441 typedef union {
mbed_official 579:53297373a894 1442 struct {
mbed_official 579:53297373a894 1443 uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */
mbed_official 579:53297373a894 1444 uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */
mbed_official 579:53297373a894 1445 uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */
mbed_official 579:53297373a894 1446 uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */
mbed_official 579:53297373a894 1447 uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */
mbed_official 579:53297373a894 1448 uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */
mbed_official 579:53297373a894 1449 uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */
mbed_official 579:53297373a894 1450 uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */
mbed_official 579:53297373a894 1451 uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */
mbed_official 579:53297373a894 1452 uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */
mbed_official 579:53297373a894 1453 uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */
mbed_official 579:53297373a894 1454 uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */
mbed_official 579:53297373a894 1455 uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */
mbed_official 579:53297373a894 1456 uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */
mbed_official 579:53297373a894 1457 uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */
mbed_official 579:53297373a894 1458 uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */
mbed_official 579:53297373a894 1459 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 1460 struct {
mbed_official 579:53297373a894 1461 uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */
mbed_official 579:53297373a894 1462 uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */
mbed_official 579:53297373a894 1463 } vec; /*!< Structure used for vec access */
mbed_official 579:53297373a894 1464 uint16_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 1465 } TCC_PATTB_Type;
mbed_official 579:53297373a894 1466 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 1467
mbed_official 579:53297373a894 1468 #define TCC_PATTB_OFFSET 0x64 /**< \brief (TCC_PATTB offset) Pattern Buffer */
mbed_official 579:53297373a894 1469 #define TCC_PATTB_RESETVALUE 0x0000ul /**< \brief (TCC_PATTB reset_value) Pattern Buffer */
mbed_official 579:53297373a894 1470
mbed_official 579:53297373a894 1471 #define TCC_PATTB_PGEB0_Pos 0 /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable Buffer */
mbed_official 579:53297373a894 1472 #define TCC_PATTB_PGEB0 (1 << TCC_PATTB_PGEB0_Pos)
mbed_official 579:53297373a894 1473 #define TCC_PATTB_PGEB1_Pos 1 /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable Buffer */
mbed_official 579:53297373a894 1474 #define TCC_PATTB_PGEB1 (1 << TCC_PATTB_PGEB1_Pos)
mbed_official 579:53297373a894 1475 #define TCC_PATTB_PGEB2_Pos 2 /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable Buffer */
mbed_official 579:53297373a894 1476 #define TCC_PATTB_PGEB2 (1 << TCC_PATTB_PGEB2_Pos)
mbed_official 579:53297373a894 1477 #define TCC_PATTB_PGEB3_Pos 3 /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable Buffer */
mbed_official 579:53297373a894 1478 #define TCC_PATTB_PGEB3 (1 << TCC_PATTB_PGEB3_Pos)
mbed_official 579:53297373a894 1479 #define TCC_PATTB_PGEB4_Pos 4 /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable Buffer */
mbed_official 579:53297373a894 1480 #define TCC_PATTB_PGEB4 (1 << TCC_PATTB_PGEB4_Pos)
mbed_official 579:53297373a894 1481 #define TCC_PATTB_PGEB5_Pos 5 /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable Buffer */
mbed_official 579:53297373a894 1482 #define TCC_PATTB_PGEB5 (1 << TCC_PATTB_PGEB5_Pos)
mbed_official 579:53297373a894 1483 #define TCC_PATTB_PGEB6_Pos 6 /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable Buffer */
mbed_official 579:53297373a894 1484 #define TCC_PATTB_PGEB6 (1 << TCC_PATTB_PGEB6_Pos)
mbed_official 579:53297373a894 1485 #define TCC_PATTB_PGEB7_Pos 7 /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable Buffer */
mbed_official 579:53297373a894 1486 #define TCC_PATTB_PGEB7 (1 << TCC_PATTB_PGEB7_Pos)
mbed_official 579:53297373a894 1487 #define TCC_PATTB_PGEB_Pos 0 /**< \brief (TCC_PATTB) Pattern Generator x Output Enable Buffer */
mbed_official 579:53297373a894 1488 #define TCC_PATTB_PGEB_Msk (0xFFul << TCC_PATTB_PGEB_Pos)
mbed_official 579:53297373a894 1489 #define TCC_PATTB_PGEB(value) ((TCC_PATTB_PGEB_Msk & ((value) << TCC_PATTB_PGEB_Pos)))
mbed_official 579:53297373a894 1490 #define TCC_PATTB_PGVB0_Pos 8 /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable */
mbed_official 579:53297373a894 1491 #define TCC_PATTB_PGVB0 (1 << TCC_PATTB_PGVB0_Pos)
mbed_official 579:53297373a894 1492 #define TCC_PATTB_PGVB1_Pos 9 /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable */
mbed_official 579:53297373a894 1493 #define TCC_PATTB_PGVB1 (1 << TCC_PATTB_PGVB1_Pos)
mbed_official 579:53297373a894 1494 #define TCC_PATTB_PGVB2_Pos 10 /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable */
mbed_official 579:53297373a894 1495 #define TCC_PATTB_PGVB2 (1 << TCC_PATTB_PGVB2_Pos)
mbed_official 579:53297373a894 1496 #define TCC_PATTB_PGVB3_Pos 11 /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable */
mbed_official 579:53297373a894 1497 #define TCC_PATTB_PGVB3 (1 << TCC_PATTB_PGVB3_Pos)
mbed_official 579:53297373a894 1498 #define TCC_PATTB_PGVB4_Pos 12 /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable */
mbed_official 579:53297373a894 1499 #define TCC_PATTB_PGVB4 (1 << TCC_PATTB_PGVB4_Pos)
mbed_official 579:53297373a894 1500 #define TCC_PATTB_PGVB5_Pos 13 /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable */
mbed_official 579:53297373a894 1501 #define TCC_PATTB_PGVB5 (1 << TCC_PATTB_PGVB5_Pos)
mbed_official 579:53297373a894 1502 #define TCC_PATTB_PGVB6_Pos 14 /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable */
mbed_official 579:53297373a894 1503 #define TCC_PATTB_PGVB6 (1 << TCC_PATTB_PGVB6_Pos)
mbed_official 579:53297373a894 1504 #define TCC_PATTB_PGVB7_Pos 15 /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable */
mbed_official 579:53297373a894 1505 #define TCC_PATTB_PGVB7 (1 << TCC_PATTB_PGVB7_Pos)
mbed_official 579:53297373a894 1506 #define TCC_PATTB_PGVB_Pos 8 /**< \brief (TCC_PATTB) Pattern Generator x Output Enable */
mbed_official 579:53297373a894 1507 #define TCC_PATTB_PGVB_Msk (0xFFul << TCC_PATTB_PGVB_Pos)
mbed_official 579:53297373a894 1508 #define TCC_PATTB_PGVB(value) ((TCC_PATTB_PGVB_Msk & ((value) << TCC_PATTB_PGVB_Pos)))
mbed_official 579:53297373a894 1509 #define TCC_PATTB_MASK 0xFFFFul /**< \brief (TCC_PATTB) MASK Register */
mbed_official 579:53297373a894 1510
mbed_official 579:53297373a894 1511 /* -------- TCC_WAVEB : (TCC Offset: 0x68) (R/W 32) Waveform Control Buffer -------- */
mbed_official 579:53297373a894 1512 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 1513 typedef union {
mbed_official 579:53297373a894 1514 struct {
mbed_official 579:53297373a894 1515 uint32_t WAVEGENB:3; /*!< bit: 0.. 2 Waveform Generation Buffer */
mbed_official 579:53297373a894 1516 uint32_t :1; /*!< bit: 3 Reserved */
mbed_official 579:53297373a894 1517 uint32_t RAMPB:2; /*!< bit: 4.. 5 Ramp Mode Buffer */
mbed_official 579:53297373a894 1518 uint32_t :1; /*!< bit: 6 Reserved */
mbed_official 579:53297373a894 1519 uint32_t CIPERENB:1; /*!< bit: 7 Circular Period Enable Buffer */
mbed_official 579:53297373a894 1520 uint32_t CICCENB0:1; /*!< bit: 8 Circular Channel 0 Enable Buffer */
mbed_official 579:53297373a894 1521 uint32_t CICCENB1:1; /*!< bit: 9 Circular Channel 1 Enable Buffer */
mbed_official 579:53297373a894 1522 uint32_t CICCENB2:1; /*!< bit: 10 Circular Channel 2 Enable Buffer */
mbed_official 579:53297373a894 1523 uint32_t CICCENB3:1; /*!< bit: 11 Circular Channel 3 Enable Buffer */
mbed_official 579:53297373a894 1524 uint32_t :4; /*!< bit: 12..15 Reserved */
mbed_official 579:53297373a894 1525 uint32_t POLB0:1; /*!< bit: 16 Channel 0 Polarity Buffer */
mbed_official 579:53297373a894 1526 uint32_t POLB1:1; /*!< bit: 17 Channel 1 Polarity Buffer */
mbed_official 579:53297373a894 1527 uint32_t POLB2:1; /*!< bit: 18 Channel 2 Polarity Buffer */
mbed_official 579:53297373a894 1528 uint32_t POLB3:1; /*!< bit: 19 Channel 3 Polarity Buffer */
mbed_official 579:53297373a894 1529 uint32_t :4; /*!< bit: 20..23 Reserved */
mbed_official 579:53297373a894 1530 uint32_t SWAPB0:1; /*!< bit: 24 Swap DTI Output Pair 0 Buffer */
mbed_official 579:53297373a894 1531 uint32_t SWAPB1:1; /*!< bit: 25 Swap DTI Output Pair 1 Buffer */
mbed_official 579:53297373a894 1532 uint32_t SWAPB2:1; /*!< bit: 26 Swap DTI Output Pair 2 Buffer */
mbed_official 579:53297373a894 1533 uint32_t SWAPB3:1; /*!< bit: 27 Swap DTI Output Pair 3 Buffer */
mbed_official 579:53297373a894 1534 uint32_t :4; /*!< bit: 28..31 Reserved */
mbed_official 579:53297373a894 1535 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 1536 struct {
mbed_official 579:53297373a894 1537 uint32_t :8; /*!< bit: 0.. 7 Reserved */
mbed_official 579:53297373a894 1538 uint32_t CICCENB:4; /*!< bit: 8..11 Circular Channel x Enable Buffer */
mbed_official 579:53297373a894 1539 uint32_t :4; /*!< bit: 12..15 Reserved */
mbed_official 579:53297373a894 1540 uint32_t POLB:4; /*!< bit: 16..19 Channel x Polarity Buffer */
mbed_official 579:53297373a894 1541 uint32_t :4; /*!< bit: 20..23 Reserved */
mbed_official 579:53297373a894 1542 uint32_t SWAPB:4; /*!< bit: 24..27 Swap DTI Output Pair x Buffer */
mbed_official 579:53297373a894 1543 uint32_t :4; /*!< bit: 28..31 Reserved */
mbed_official 579:53297373a894 1544 } vec; /*!< Structure used for vec access */
mbed_official 579:53297373a894 1545 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 1546 } TCC_WAVEB_Type;
mbed_official 579:53297373a894 1547 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 1548
mbed_official 579:53297373a894 1549 #define TCC_WAVEB_OFFSET 0x68 /**< \brief (TCC_WAVEB offset) Waveform Control Buffer */
mbed_official 579:53297373a894 1550 #define TCC_WAVEB_RESETVALUE 0x00000000ul /**< \brief (TCC_WAVEB reset_value) Waveform Control Buffer */
mbed_official 579:53297373a894 1551
mbed_official 579:53297373a894 1552 #define TCC_WAVEB_WAVEGENB_Pos 0 /**< \brief (TCC_WAVEB) Waveform Generation Buffer */
mbed_official 579:53297373a894 1553 #define TCC_WAVEB_WAVEGENB_Msk (0x7ul << TCC_WAVEB_WAVEGENB_Pos)
mbed_official 579:53297373a894 1554 #define TCC_WAVEB_WAVEGENB(value) ((TCC_WAVEB_WAVEGENB_Msk & ((value) << TCC_WAVEB_WAVEGENB_Pos)))
mbed_official 579:53297373a894 1555 #define TCC_WAVEB_WAVEGENB_NFRQ_Val 0x0ul /**< \brief (TCC_WAVEB) Normal frequency */
mbed_official 579:53297373a894 1556 #define TCC_WAVEB_WAVEGENB_MFRQ_Val 0x1ul /**< \brief (TCC_WAVEB) Match frequency */
mbed_official 579:53297373a894 1557 #define TCC_WAVEB_WAVEGENB_NPWM_Val 0x2ul /**< \brief (TCC_WAVEB) Normal PWM */
mbed_official 579:53297373a894 1558 #define TCC_WAVEB_WAVEGENB_DSCRITICAL_Val 0x4ul /**< \brief (TCC_WAVEB) Dual-slope critical */
mbed_official 579:53297373a894 1559 #define TCC_WAVEB_WAVEGENB_DSBOTTOM_Val 0x5ul /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO */
mbed_official 579:53297373a894 1560 #define TCC_WAVEB_WAVEGENB_DSBOTH_Val 0x6ul /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */
mbed_official 579:53297373a894 1561 #define TCC_WAVEB_WAVEGENB_DSTOP_Val 0x7ul /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches TOP */
mbed_official 579:53297373a894 1562 #define TCC_WAVEB_WAVEGENB_NFRQ (TCC_WAVEB_WAVEGENB_NFRQ_Val << TCC_WAVEB_WAVEGENB_Pos)
mbed_official 579:53297373a894 1563 #define TCC_WAVEB_WAVEGENB_MFRQ (TCC_WAVEB_WAVEGENB_MFRQ_Val << TCC_WAVEB_WAVEGENB_Pos)
mbed_official 579:53297373a894 1564 #define TCC_WAVEB_WAVEGENB_NPWM (TCC_WAVEB_WAVEGENB_NPWM_Val << TCC_WAVEB_WAVEGENB_Pos)
mbed_official 579:53297373a894 1565 #define TCC_WAVEB_WAVEGENB_DSCRITICAL (TCC_WAVEB_WAVEGENB_DSCRITICAL_Val << TCC_WAVEB_WAVEGENB_Pos)
mbed_official 579:53297373a894 1566 #define TCC_WAVEB_WAVEGENB_DSBOTTOM (TCC_WAVEB_WAVEGENB_DSBOTTOM_Val << TCC_WAVEB_WAVEGENB_Pos)
mbed_official 579:53297373a894 1567 #define TCC_WAVEB_WAVEGENB_DSBOTH (TCC_WAVEB_WAVEGENB_DSBOTH_Val << TCC_WAVEB_WAVEGENB_Pos)
mbed_official 579:53297373a894 1568 #define TCC_WAVEB_WAVEGENB_DSTOP (TCC_WAVEB_WAVEGENB_DSTOP_Val << TCC_WAVEB_WAVEGENB_Pos)
mbed_official 579:53297373a894 1569 #define TCC_WAVEB_RAMPB_Pos 4 /**< \brief (TCC_WAVEB) Ramp Mode Buffer */
mbed_official 579:53297373a894 1570 #define TCC_WAVEB_RAMPB_Msk (0x3ul << TCC_WAVEB_RAMPB_Pos)
mbed_official 579:53297373a894 1571 #define TCC_WAVEB_RAMPB(value) ((TCC_WAVEB_RAMPB_Msk & ((value) << TCC_WAVEB_RAMPB_Pos)))
mbed_official 579:53297373a894 1572 #define TCC_WAVEB_RAMPB_RAMP1_Val 0x0ul /**< \brief (TCC_WAVEB) RAMP1 operation */
mbed_official 579:53297373a894 1573 #define TCC_WAVEB_RAMPB_RAMP2A_Val 0x1ul /**< \brief (TCC_WAVEB) Alternative RAMP2 operation */
mbed_official 579:53297373a894 1574 #define TCC_WAVEB_RAMPB_RAMP2_Val 0x2ul /**< \brief (TCC_WAVEB) RAMP2 operation */
mbed_official 579:53297373a894 1575 #define TCC_WAVEB_RAMPB_RAMP1 (TCC_WAVEB_RAMPB_RAMP1_Val << TCC_WAVEB_RAMPB_Pos)
mbed_official 579:53297373a894 1576 #define TCC_WAVEB_RAMPB_RAMP2A (TCC_WAVEB_RAMPB_RAMP2A_Val << TCC_WAVEB_RAMPB_Pos)
mbed_official 579:53297373a894 1577 #define TCC_WAVEB_RAMPB_RAMP2 (TCC_WAVEB_RAMPB_RAMP2_Val << TCC_WAVEB_RAMPB_Pos)
mbed_official 579:53297373a894 1578 #define TCC_WAVEB_CIPERENB_Pos 7 /**< \brief (TCC_WAVEB) Circular Period Enable Buffer */
mbed_official 579:53297373a894 1579 #define TCC_WAVEB_CIPERENB (0x1ul << TCC_WAVEB_CIPERENB_Pos)
mbed_official 579:53297373a894 1580 #define TCC_WAVEB_CICCENB0_Pos 8 /**< \brief (TCC_WAVEB) Circular Channel 0 Enable Buffer */
mbed_official 579:53297373a894 1581 #define TCC_WAVEB_CICCENB0 (1 << TCC_WAVEB_CICCENB0_Pos)
mbed_official 579:53297373a894 1582 #define TCC_WAVEB_CICCENB1_Pos 9 /**< \brief (TCC_WAVEB) Circular Channel 1 Enable Buffer */
mbed_official 579:53297373a894 1583 #define TCC_WAVEB_CICCENB1 (1 << TCC_WAVEB_CICCENB1_Pos)
mbed_official 579:53297373a894 1584 #define TCC_WAVEB_CICCENB2_Pos 10 /**< \brief (TCC_WAVEB) Circular Channel 2 Enable Buffer */
mbed_official 579:53297373a894 1585 #define TCC_WAVEB_CICCENB2 (1 << TCC_WAVEB_CICCENB2_Pos)
mbed_official 579:53297373a894 1586 #define TCC_WAVEB_CICCENB3_Pos 11 /**< \brief (TCC_WAVEB) Circular Channel 3 Enable Buffer */
mbed_official 579:53297373a894 1587 #define TCC_WAVEB_CICCENB3 (1 << TCC_WAVEB_CICCENB3_Pos)
mbed_official 579:53297373a894 1588 #define TCC_WAVEB_CICCENB_Pos 8 /**< \brief (TCC_WAVEB) Circular Channel x Enable Buffer */
mbed_official 579:53297373a894 1589 #define TCC_WAVEB_CICCENB_Msk (0xFul << TCC_WAVEB_CICCENB_Pos)
mbed_official 579:53297373a894 1590 #define TCC_WAVEB_CICCENB(value) ((TCC_WAVEB_CICCENB_Msk & ((value) << TCC_WAVEB_CICCENB_Pos)))
mbed_official 579:53297373a894 1591 #define TCC_WAVEB_POLB0_Pos 16 /**< \brief (TCC_WAVEB) Channel 0 Polarity Buffer */
mbed_official 579:53297373a894 1592 #define TCC_WAVEB_POLB0 (1 << TCC_WAVEB_POLB0_Pos)
mbed_official 579:53297373a894 1593 #define TCC_WAVEB_POLB1_Pos 17 /**< \brief (TCC_WAVEB) Channel 1 Polarity Buffer */
mbed_official 579:53297373a894 1594 #define TCC_WAVEB_POLB1 (1 << TCC_WAVEB_POLB1_Pos)
mbed_official 579:53297373a894 1595 #define TCC_WAVEB_POLB2_Pos 18 /**< \brief (TCC_WAVEB) Channel 2 Polarity Buffer */
mbed_official 579:53297373a894 1596 #define TCC_WAVEB_POLB2 (1 << TCC_WAVEB_POLB2_Pos)
mbed_official 579:53297373a894 1597 #define TCC_WAVEB_POLB3_Pos 19 /**< \brief (TCC_WAVEB) Channel 3 Polarity Buffer */
mbed_official 579:53297373a894 1598 #define TCC_WAVEB_POLB3 (1 << TCC_WAVEB_POLB3_Pos)
mbed_official 579:53297373a894 1599 #define TCC_WAVEB_POLB_Pos 16 /**< \brief (TCC_WAVEB) Channel x Polarity Buffer */
mbed_official 579:53297373a894 1600 #define TCC_WAVEB_POLB_Msk (0xFul << TCC_WAVEB_POLB_Pos)
mbed_official 579:53297373a894 1601 #define TCC_WAVEB_POLB(value) ((TCC_WAVEB_POLB_Msk & ((value) << TCC_WAVEB_POLB_Pos)))
mbed_official 579:53297373a894 1602 #define TCC_WAVEB_SWAPB0_Pos 24 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 0 Buffer */
mbed_official 579:53297373a894 1603 #define TCC_WAVEB_SWAPB0 (1 << TCC_WAVEB_SWAPB0_Pos)
mbed_official 579:53297373a894 1604 #define TCC_WAVEB_SWAPB1_Pos 25 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 1 Buffer */
mbed_official 579:53297373a894 1605 #define TCC_WAVEB_SWAPB1 (1 << TCC_WAVEB_SWAPB1_Pos)
mbed_official 579:53297373a894 1606 #define TCC_WAVEB_SWAPB2_Pos 26 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 2 Buffer */
mbed_official 579:53297373a894 1607 #define TCC_WAVEB_SWAPB2 (1 << TCC_WAVEB_SWAPB2_Pos)
mbed_official 579:53297373a894 1608 #define TCC_WAVEB_SWAPB3_Pos 27 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 3 Buffer */
mbed_official 579:53297373a894 1609 #define TCC_WAVEB_SWAPB3 (1 << TCC_WAVEB_SWAPB3_Pos)
mbed_official 579:53297373a894 1610 #define TCC_WAVEB_SWAPB_Pos 24 /**< \brief (TCC_WAVEB) Swap DTI Output Pair x Buffer */
mbed_official 579:53297373a894 1611 #define TCC_WAVEB_SWAPB_Msk (0xFul << TCC_WAVEB_SWAPB_Pos)
mbed_official 579:53297373a894 1612 #define TCC_WAVEB_SWAPB(value) ((TCC_WAVEB_SWAPB_Msk & ((value) << TCC_WAVEB_SWAPB_Pos)))
mbed_official 579:53297373a894 1613 #define TCC_WAVEB_MASK 0x0F0F0FB7ul /**< \brief (TCC_WAVEB) MASK Register */
mbed_official 579:53297373a894 1614
mbed_official 579:53297373a894 1615 /* -------- TCC_PERB : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */
mbed_official 579:53297373a894 1616 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 1617 typedef union {
mbed_official 579:53297373a894 1618 struct { // DITH4 mode
mbed_official 579:53297373a894 1619 uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */
mbed_official 579:53297373a894 1620 uint32_t PERB:20; /*!< bit: 4..23 Period Buffer Value */
mbed_official 579:53297373a894 1621 uint32_t :8; /*!< bit: 24..31 Reserved */
mbed_official 579:53297373a894 1622 } DITH4; /*!< Structure used for DITH4 */
mbed_official 579:53297373a894 1623 struct { // DITH5 mode
mbed_official 579:53297373a894 1624 uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */
mbed_official 579:53297373a894 1625 uint32_t PERB:19; /*!< bit: 5..23 Period Buffer Value */
mbed_official 579:53297373a894 1626 uint32_t :8; /*!< bit: 24..31 Reserved */
mbed_official 579:53297373a894 1627 } DITH5; /*!< Structure used for DITH5 */
mbed_official 579:53297373a894 1628 struct { // DITH6 mode
mbed_official 579:53297373a894 1629 uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */
mbed_official 579:53297373a894 1630 uint32_t PERB:18; /*!< bit: 6..23 Period Buffer Value */
mbed_official 579:53297373a894 1631 uint32_t :8; /*!< bit: 24..31 Reserved */
mbed_official 579:53297373a894 1632 } DITH6; /*!< Structure used for DITH6 */
mbed_official 579:53297373a894 1633 struct {
mbed_official 579:53297373a894 1634 uint32_t PERB:24; /*!< bit: 0..23 Period Buffer Value */
mbed_official 579:53297373a894 1635 uint32_t :8; /*!< bit: 24..31 Reserved */
mbed_official 579:53297373a894 1636 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 1637 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 1638 } TCC_PERB_Type;
mbed_official 579:53297373a894 1639 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 1640
mbed_official 579:53297373a894 1641 #define TCC_PERB_OFFSET 0x6C /**< \brief (TCC_PERB offset) Period Buffer */
mbed_official 579:53297373a894 1642 #define TCC_PERB_RESETVALUE 0xFFFFFFFFul /**< \brief (TCC_PERB reset_value) Period Buffer */
mbed_official 579:53297373a894 1643
mbed_official 579:53297373a894 1644 // DITH4 mode
mbed_official 579:53297373a894 1645 #define TCC_PERB_DITH4_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH4) Dithering Buffer Cycle Number */
mbed_official 579:53297373a894 1646 #define TCC_PERB_DITH4_DITHERCYB_Msk (0xFul << TCC_PERB_DITH4_DITHERCYB_Pos)
mbed_official 579:53297373a894 1647 #define TCC_PERB_DITH4_DITHERCYB(value) ((TCC_PERB_DITH4_DITHERCYB_Msk & ((value) << TCC_PERB_DITH4_DITHERCYB_Pos)))
mbed_official 579:53297373a894 1648 #define TCC_PERB_DITH4_PERB_Pos 4 /**< \brief (TCC_PERB_DITH4) Period Buffer Value */
mbed_official 579:53297373a894 1649 #define TCC_PERB_DITH4_PERB_Msk (0xFFFFFul << TCC_PERB_DITH4_PERB_Pos)
mbed_official 579:53297373a894 1650 #define TCC_PERB_DITH4_PERB(value) ((TCC_PERB_DITH4_PERB_Msk & ((value) << TCC_PERB_DITH4_PERB_Pos)))
mbed_official 579:53297373a894 1651 #define TCC_PERB_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_PERB_DITH4) MASK Register */
mbed_official 579:53297373a894 1652
mbed_official 579:53297373a894 1653 // DITH5 mode
mbed_official 579:53297373a894 1654 #define TCC_PERB_DITH5_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH5) Dithering Buffer Cycle Number */
mbed_official 579:53297373a894 1655 #define TCC_PERB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_PERB_DITH5_DITHERCYB_Pos)
mbed_official 579:53297373a894 1656 #define TCC_PERB_DITH5_DITHERCYB(value) ((TCC_PERB_DITH5_DITHERCYB_Msk & ((value) << TCC_PERB_DITH5_DITHERCYB_Pos)))
mbed_official 579:53297373a894 1657 #define TCC_PERB_DITH5_PERB_Pos 5 /**< \brief (TCC_PERB_DITH5) Period Buffer Value */
mbed_official 579:53297373a894 1658 #define TCC_PERB_DITH5_PERB_Msk (0x7FFFFul << TCC_PERB_DITH5_PERB_Pos)
mbed_official 579:53297373a894 1659 #define TCC_PERB_DITH5_PERB(value) ((TCC_PERB_DITH5_PERB_Msk & ((value) << TCC_PERB_DITH5_PERB_Pos)))
mbed_official 579:53297373a894 1660 #define TCC_PERB_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_PERB_DITH5) MASK Register */
mbed_official 579:53297373a894 1661
mbed_official 579:53297373a894 1662 // DITH6 mode
mbed_official 579:53297373a894 1663 #define TCC_PERB_DITH6_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH6) Dithering Buffer Cycle Number */
mbed_official 579:53297373a894 1664 #define TCC_PERB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_PERB_DITH6_DITHERCYB_Pos)
mbed_official 579:53297373a894 1665 #define TCC_PERB_DITH6_DITHERCYB(value) ((TCC_PERB_DITH6_DITHERCYB_Msk & ((value) << TCC_PERB_DITH6_DITHERCYB_Pos)))
mbed_official 579:53297373a894 1666 #define TCC_PERB_DITH6_PERB_Pos 6 /**< \brief (TCC_PERB_DITH6) Period Buffer Value */
mbed_official 579:53297373a894 1667 #define TCC_PERB_DITH6_PERB_Msk (0x3FFFFul << TCC_PERB_DITH6_PERB_Pos)
mbed_official 579:53297373a894 1668 #define TCC_PERB_DITH6_PERB(value) ((TCC_PERB_DITH6_PERB_Msk & ((value) << TCC_PERB_DITH6_PERB_Pos)))
mbed_official 579:53297373a894 1669 #define TCC_PERB_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_PERB_DITH6) MASK Register */
mbed_official 579:53297373a894 1670
mbed_official 579:53297373a894 1671 #define TCC_PERB_PERB_Pos 0 /**< \brief (TCC_PERB) Period Buffer Value */
mbed_official 579:53297373a894 1672 #define TCC_PERB_PERB_Msk (0xFFFFFFul << TCC_PERB_PERB_Pos)
mbed_official 579:53297373a894 1673 #define TCC_PERB_PERB(value) ((TCC_PERB_PERB_Msk & ((value) << TCC_PERB_PERB_Pos)))
mbed_official 579:53297373a894 1674 #define TCC_PERB_MASK 0x00FFFFFFul /**< \brief (TCC_PERB) MASK Register */
mbed_official 579:53297373a894 1675
mbed_official 579:53297373a894 1676 /* -------- TCC_CCB : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */
mbed_official 579:53297373a894 1677 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 1678 typedef union {
mbed_official 579:53297373a894 1679 struct { // DITH4 mode
mbed_official 579:53297373a894 1680 uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */
mbed_official 579:53297373a894 1681 uint32_t CCB:20; /*!< bit: 4..23 Channel Compare/Capture Buffer Value */
mbed_official 579:53297373a894 1682 uint32_t :8; /*!< bit: 24..31 Reserved */
mbed_official 579:53297373a894 1683 } DITH4; /*!< Structure used for DITH4 */
mbed_official 579:53297373a894 1684 struct { // DITH5 mode
mbed_official 579:53297373a894 1685 uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */
mbed_official 579:53297373a894 1686 uint32_t CCB:19; /*!< bit: 5..23 Channel Compare/Capture Buffer Value */
mbed_official 579:53297373a894 1687 uint32_t :8; /*!< bit: 24..31 Reserved */
mbed_official 579:53297373a894 1688 } DITH5; /*!< Structure used for DITH5 */
mbed_official 579:53297373a894 1689 struct { // DITH6 mode
mbed_official 579:53297373a894 1690 uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */
mbed_official 579:53297373a894 1691 uint32_t CCB:18; /*!< bit: 6..23 Channel Compare/Capture Buffer Value */
mbed_official 579:53297373a894 1692 uint32_t :8; /*!< bit: 24..31 Reserved */
mbed_official 579:53297373a894 1693 } DITH6; /*!< Structure used for DITH6 */
mbed_official 579:53297373a894 1694 struct {
mbed_official 579:53297373a894 1695 uint32_t CCB:24; /*!< bit: 0..23 Channel Compare/Capture Buffer Value */
mbed_official 579:53297373a894 1696 uint32_t :8; /*!< bit: 24..31 Reserved */
mbed_official 579:53297373a894 1697 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 1698 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 1699 } TCC_CCB_Type;
mbed_official 579:53297373a894 1700 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 1701
mbed_official 579:53297373a894 1702 #define TCC_CCB_OFFSET 0x70 /**< \brief (TCC_CCB offset) Compare and Capture Buffer */
mbed_official 579:53297373a894 1703 #define TCC_CCB_RESETVALUE 0x00000000ul /**< \brief (TCC_CCB reset_value) Compare and Capture Buffer */
mbed_official 579:53297373a894 1704
mbed_official 579:53297373a894 1705 // DITH4 mode
mbed_official 579:53297373a894 1706 #define TCC_CCB_DITH4_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH4) Dithering Buffer Cycle Number */
mbed_official 579:53297373a894 1707 #define TCC_CCB_DITH4_DITHERCYB_Msk (0xFul << TCC_CCB_DITH4_DITHERCYB_Pos)
mbed_official 579:53297373a894 1708 #define TCC_CCB_DITH4_DITHERCYB(value) ((TCC_CCB_DITH4_DITHERCYB_Msk & ((value) << TCC_CCB_DITH4_DITHERCYB_Pos)))
mbed_official 579:53297373a894 1709 #define TCC_CCB_DITH4_CCB_Pos 4 /**< \brief (TCC_CCB_DITH4) Channel Compare/Capture Buffer Value */
mbed_official 579:53297373a894 1710 #define TCC_CCB_DITH4_CCB_Msk (0xFFFFFul << TCC_CCB_DITH4_CCB_Pos)
mbed_official 579:53297373a894 1711 #define TCC_CCB_DITH4_CCB(value) ((TCC_CCB_DITH4_CCB_Msk & ((value) << TCC_CCB_DITH4_CCB_Pos)))
mbed_official 579:53297373a894 1712 #define TCC_CCB_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_CCB_DITH4) MASK Register */
mbed_official 579:53297373a894 1713
mbed_official 579:53297373a894 1714 // DITH5 mode
mbed_official 579:53297373a894 1715 #define TCC_CCB_DITH5_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH5) Dithering Buffer Cycle Number */
mbed_official 579:53297373a894 1716 #define TCC_CCB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_CCB_DITH5_DITHERCYB_Pos)
mbed_official 579:53297373a894 1717 #define TCC_CCB_DITH5_DITHERCYB(value) ((TCC_CCB_DITH5_DITHERCYB_Msk & ((value) << TCC_CCB_DITH5_DITHERCYB_Pos)))
mbed_official 579:53297373a894 1718 #define TCC_CCB_DITH5_CCB_Pos 5 /**< \brief (TCC_CCB_DITH5) Channel Compare/Capture Buffer Value */
mbed_official 579:53297373a894 1719 #define TCC_CCB_DITH5_CCB_Msk (0x7FFFFul << TCC_CCB_DITH5_CCB_Pos)
mbed_official 579:53297373a894 1720 #define TCC_CCB_DITH5_CCB(value) ((TCC_CCB_DITH5_CCB_Msk & ((value) << TCC_CCB_DITH5_CCB_Pos)))
mbed_official 579:53297373a894 1721 #define TCC_CCB_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_CCB_DITH5) MASK Register */
mbed_official 579:53297373a894 1722
mbed_official 579:53297373a894 1723 // DITH6 mode
mbed_official 579:53297373a894 1724 #define TCC_CCB_DITH6_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH6) Dithering Buffer Cycle Number */
mbed_official 579:53297373a894 1725 #define TCC_CCB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_CCB_DITH6_DITHERCYB_Pos)
mbed_official 579:53297373a894 1726 #define TCC_CCB_DITH6_DITHERCYB(value) ((TCC_CCB_DITH6_DITHERCYB_Msk & ((value) << TCC_CCB_DITH6_DITHERCYB_Pos)))
mbed_official 579:53297373a894 1727 #define TCC_CCB_DITH6_CCB_Pos 6 /**< \brief (TCC_CCB_DITH6) Channel Compare/Capture Buffer Value */
mbed_official 579:53297373a894 1728 #define TCC_CCB_DITH6_CCB_Msk (0x3FFFFul << TCC_CCB_DITH6_CCB_Pos)
mbed_official 579:53297373a894 1729 #define TCC_CCB_DITH6_CCB(value) ((TCC_CCB_DITH6_CCB_Msk & ((value) << TCC_CCB_DITH6_CCB_Pos)))
mbed_official 579:53297373a894 1730 #define TCC_CCB_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_CCB_DITH6) MASK Register */
mbed_official 579:53297373a894 1731
mbed_official 579:53297373a894 1732 #define TCC_CCB_CCB_Pos 0 /**< \brief (TCC_CCB) Channel Compare/Capture Buffer Value */
mbed_official 579:53297373a894 1733 #define TCC_CCB_CCB_Msk (0xFFFFFFul << TCC_CCB_CCB_Pos)
mbed_official 579:53297373a894 1734 #define TCC_CCB_CCB(value) ((TCC_CCB_CCB_Msk & ((value) << TCC_CCB_CCB_Pos)))
mbed_official 579:53297373a894 1735 #define TCC_CCB_MASK 0x00FFFFFFul /**< \brief (TCC_CCB) MASK Register */
mbed_official 579:53297373a894 1736
mbed_official 579:53297373a894 1737 /** \brief TCC hardware registers */
mbed_official 579:53297373a894 1738 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 1739 typedef struct {
mbed_official 579:53297373a894 1740 __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
mbed_official 579:53297373a894 1741 __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
mbed_official 579:53297373a894 1742 __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
mbed_official 579:53297373a894 1743 RoReg8 Reserved1[0x2];
mbed_official 579:53297373a894 1744 __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */
mbed_official 579:53297373a894 1745 __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */
mbed_official 579:53297373a894 1746 __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */
mbed_official 579:53297373a894 1747 __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */
mbed_official 579:53297373a894 1748 __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */
mbed_official 579:53297373a894 1749 RoReg8 Reserved2[0x2];
mbed_official 579:53297373a894 1750 __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */
mbed_official 579:53297373a894 1751 RoReg8 Reserved3[0x1];
mbed_official 579:53297373a894 1752 __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */
mbed_official 579:53297373a894 1753 __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */
mbed_official 579:53297373a894 1754 __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */
mbed_official 579:53297373a894 1755 __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 1756 __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */
mbed_official 579:53297373a894 1757 __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */
mbed_official 579:53297373a894 1758 __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */
mbed_official 579:53297373a894 1759 RoReg8 Reserved4[0x2];
mbed_official 579:53297373a894 1760 __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */
mbed_official 579:53297373a894 1761 __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */
mbed_official 579:53297373a894 1762 __IO TCC_CC_Type CC[4]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */
mbed_official 579:53297373a894 1763 RoReg8 Reserved5[0x10];
mbed_official 579:53297373a894 1764 __IO TCC_PATTB_Type PATTB; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */
mbed_official 579:53297373a894 1765 RoReg8 Reserved6[0x2];
mbed_official 579:53297373a894 1766 __IO TCC_WAVEB_Type WAVEB; /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */
mbed_official 579:53297373a894 1767 __IO TCC_PERB_Type PERB; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */
mbed_official 579:53297373a894 1768 __IO TCC_CCB_Type CCB[4]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */
mbed_official 579:53297373a894 1769 } Tcc;
mbed_official 579:53297373a894 1770 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 1771
mbed_official 579:53297373a894 1772 /*@}*/
mbed_official 579:53297373a894 1773
mbed_official 579:53297373a894 1774 #endif /* _SAMD21_TCC_COMPONENT_ */