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targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_sysctrl.h@592:a274ee790e56, 2015-07-17 (annotated)

Committer:
mbed_official
Date:
Fri Jul 17 09:15:10 2015 +0100
Revision:
592:a274ee790e56
Parent:
579:53297373a894 
Synchronized with git revision e7144f83a8d75df80c4877936b6ffe552b0be9e6



Full URL: https://github.com/mbedmicro/mbed/commit/e7144f83a8d75df80c4877936b6ffe552b0be9e6/



More API implementation for SAMR21

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UserRevisionLine numberNew contents of line
mbed_official 579:53297373a894 1 #ifndef _SAMD21_SYSCTRL_COMPONENT_
mbed_official 579:53297373a894 2 #define _SAMD21_SYSCTRL_COMPONENT_
mbed_official 579:53297373a894 3
mbed_official 579:53297373a894 4 /* ========================================================================== */
mbed_official 579:53297373a894 5 /** SOFTWARE API DEFINITION FOR SYSCTRL */
mbed_official 579:53297373a894 6 /* ========================================================================== */
mbed_official 579:53297373a894 7 /** \addtogroup SAMD21_SYSCTRL System Control */
mbed_official 579:53297373a894 8 /*@{*/
mbed_official 579:53297373a894 9
mbed_official 579:53297373a894 10 #define SYSCTRL_U2100
mbed_official 579:53297373a894 11 #define REV_SYSCTRL 0x201
mbed_official 579:53297373a894 12
mbed_official 579:53297373a894 13 /* -------- SYSCTRL_INTENCLR : (SYSCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
mbed_official 579:53297373a894 14 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 15 typedef union {
mbed_official 579:53297373a894 16 struct {
mbed_official 579:53297373a894 17 uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
mbed_official 579:53297373a894 18 uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */
mbed_official 579:53297373a894 19 uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */
mbed_official 579:53297373a894 20 uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */
mbed_official 579:53297373a894 21 uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */
mbed_official 579:53297373a894 22 uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */
mbed_official 579:53297373a894 23 uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */
mbed_official 579:53297373a894 24 uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */
mbed_official 579:53297373a894 25 uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */
mbed_official 579:53297373a894 26 uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */
mbed_official 579:53297373a894 27 uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */
mbed_official 579:53297373a894 28 uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */
mbed_official 579:53297373a894 29 uint32_t :3; /*!< bit: 12..14 Reserved */
mbed_official 579:53297373a894 30 uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */
mbed_official 579:53297373a894 31 uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */
mbed_official 579:53297373a894 32 uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */
mbed_official 579:53297373a894 33 uint32_t :14; /*!< bit: 18..31 Reserved */
mbed_official 579:53297373a894 34 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 35 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 36 } SYSCTRL_INTENCLR_Type;
mbed_official 579:53297373a894 37 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 38
mbed_official 579:53297373a894 39 #define SYSCTRL_INTENCLR_OFFSET 0x00 /**< \brief (SYSCTRL_INTENCLR offset) Interrupt Enable Clear */
mbed_official 579:53297373a894 40 #define SYSCTRL_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_INTENCLR reset_value) Interrupt Enable Clear */
mbed_official 579:53297373a894 41
mbed_official 579:53297373a894 42 #define SYSCTRL_INTENCLR_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_INTENCLR) XOSC Ready Interrupt Enable */
mbed_official 579:53297373a894 43 #define SYSCTRL_INTENCLR_XOSCRDY (0x1ul << SYSCTRL_INTENCLR_XOSCRDY_Pos)
mbed_official 579:53297373a894 44 #define SYSCTRL_INTENCLR_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_INTENCLR) XOSC32K Ready Interrupt Enable */
mbed_official 579:53297373a894 45 #define SYSCTRL_INTENCLR_XOSC32KRDY (0x1ul << SYSCTRL_INTENCLR_XOSC32KRDY_Pos)
mbed_official 579:53297373a894 46 #define SYSCTRL_INTENCLR_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_INTENCLR) OSC32K Ready Interrupt Enable */
mbed_official 579:53297373a894 47 #define SYSCTRL_INTENCLR_OSC32KRDY (0x1ul << SYSCTRL_INTENCLR_OSC32KRDY_Pos)
mbed_official 579:53297373a894 48 #define SYSCTRL_INTENCLR_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_INTENCLR) OSC8M Ready Interrupt Enable */
mbed_official 579:53297373a894 49 #define SYSCTRL_INTENCLR_OSC8MRDY (0x1ul << SYSCTRL_INTENCLR_OSC8MRDY_Pos)
mbed_official 579:53297373a894 50 #define SYSCTRL_INTENCLR_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_INTENCLR) DFLL Ready Interrupt Enable */
mbed_official 579:53297373a894 51 #define SYSCTRL_INTENCLR_DFLLRDY (0x1ul << SYSCTRL_INTENCLR_DFLLRDY_Pos)
mbed_official 579:53297373a894 52 #define SYSCTRL_INTENCLR_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_INTENCLR) DFLL Out Of Bounds Interrupt Enable */
mbed_official 579:53297373a894 53 #define SYSCTRL_INTENCLR_DFLLOOB (0x1ul << SYSCTRL_INTENCLR_DFLLOOB_Pos)
mbed_official 579:53297373a894 54 #define SYSCTRL_INTENCLR_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_INTENCLR) DFLL Lock Fine Interrupt Enable */
mbed_official 579:53297373a894 55 #define SYSCTRL_INTENCLR_DFLLLCKF (0x1ul << SYSCTRL_INTENCLR_DFLLLCKF_Pos)
mbed_official 579:53297373a894 56 #define SYSCTRL_INTENCLR_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_INTENCLR) DFLL Lock Coarse Interrupt Enable */
mbed_official 579:53297373a894 57 #define SYSCTRL_INTENCLR_DFLLLCKC (0x1ul << SYSCTRL_INTENCLR_DFLLLCKC_Pos)
mbed_official 579:53297373a894 58 #define SYSCTRL_INTENCLR_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_INTENCLR) DFLL Reference Clock Stopped Interrupt Enable */
mbed_official 579:53297373a894 59 #define SYSCTRL_INTENCLR_DFLLRCS (0x1ul << SYSCTRL_INTENCLR_DFLLRCS_Pos)
mbed_official 579:53297373a894 60 #define SYSCTRL_INTENCLR_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_INTENCLR) BOD33 Ready Interrupt Enable */
mbed_official 579:53297373a894 61 #define SYSCTRL_INTENCLR_BOD33RDY (0x1ul << SYSCTRL_INTENCLR_BOD33RDY_Pos)
mbed_official 579:53297373a894 62 #define SYSCTRL_INTENCLR_BOD33DET_Pos 10 /**< \brief (SYSCTRL_INTENCLR) BOD33 Detection Interrupt Enable */
mbed_official 579:53297373a894 63 #define SYSCTRL_INTENCLR_BOD33DET (0x1ul << SYSCTRL_INTENCLR_BOD33DET_Pos)
mbed_official 579:53297373a894 64 #define SYSCTRL_INTENCLR_B33SRDY_Pos 11 /**< \brief (SYSCTRL_INTENCLR) BOD33 Synchronization Ready Interrupt Enable */
mbed_official 579:53297373a894 65 #define SYSCTRL_INTENCLR_B33SRDY (0x1ul << SYSCTRL_INTENCLR_B33SRDY_Pos)
mbed_official 579:53297373a894 66 #define SYSCTRL_INTENCLR_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Rise Interrupt Enable */
mbed_official 579:53297373a894 67 #define SYSCTRL_INTENCLR_DPLLLCKR (0x1ul << SYSCTRL_INTENCLR_DPLLLCKR_Pos)
mbed_official 579:53297373a894 68 #define SYSCTRL_INTENCLR_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Fall Interrupt Enable */
mbed_official 579:53297373a894 69 #define SYSCTRL_INTENCLR_DPLLLCKF (0x1ul << SYSCTRL_INTENCLR_DPLLLCKF_Pos)
mbed_official 579:53297373a894 70 #define SYSCTRL_INTENCLR_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Timeout Interrupt Enable */
mbed_official 579:53297373a894 71 #define SYSCTRL_INTENCLR_DPLLLTO (0x1ul << SYSCTRL_INTENCLR_DPLLLTO_Pos)
mbed_official 579:53297373a894 72 #define SYSCTRL_INTENCLR_MASK 0x00038FFFul /**< \brief (SYSCTRL_INTENCLR) MASK Register */
mbed_official 579:53297373a894 73
mbed_official 579:53297373a894 74 /* -------- SYSCTRL_INTENSET : (SYSCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
mbed_official 579:53297373a894 75 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 76 typedef union {
mbed_official 579:53297373a894 77 struct {
mbed_official 579:53297373a894 78 uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
mbed_official 579:53297373a894 79 uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */
mbed_official 579:53297373a894 80 uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */
mbed_official 579:53297373a894 81 uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */
mbed_official 579:53297373a894 82 uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */
mbed_official 579:53297373a894 83 uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */
mbed_official 579:53297373a894 84 uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */
mbed_official 579:53297373a894 85 uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */
mbed_official 579:53297373a894 86 uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */
mbed_official 579:53297373a894 87 uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */
mbed_official 579:53297373a894 88 uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */
mbed_official 579:53297373a894 89 uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */
mbed_official 579:53297373a894 90 uint32_t :3; /*!< bit: 12..14 Reserved */
mbed_official 579:53297373a894 91 uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */
mbed_official 579:53297373a894 92 uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */
mbed_official 579:53297373a894 93 uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */
mbed_official 579:53297373a894 94 uint32_t :14; /*!< bit: 18..31 Reserved */
mbed_official 579:53297373a894 95 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 96 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 97 } SYSCTRL_INTENSET_Type;
mbed_official 579:53297373a894 98 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 99
mbed_official 579:53297373a894 100 #define SYSCTRL_INTENSET_OFFSET 0x04 /**< \brief (SYSCTRL_INTENSET offset) Interrupt Enable Set */
mbed_official 579:53297373a894 101 #define SYSCTRL_INTENSET_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_INTENSET reset_value) Interrupt Enable Set */
mbed_official 579:53297373a894 102
mbed_official 579:53297373a894 103 #define SYSCTRL_INTENSET_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_INTENSET) XOSC Ready Interrupt Enable */
mbed_official 579:53297373a894 104 #define SYSCTRL_INTENSET_XOSCRDY (0x1ul << SYSCTRL_INTENSET_XOSCRDY_Pos)
mbed_official 579:53297373a894 105 #define SYSCTRL_INTENSET_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_INTENSET) XOSC32K Ready Interrupt Enable */
mbed_official 579:53297373a894 106 #define SYSCTRL_INTENSET_XOSC32KRDY (0x1ul << SYSCTRL_INTENSET_XOSC32KRDY_Pos)
mbed_official 579:53297373a894 107 #define SYSCTRL_INTENSET_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_INTENSET) OSC32K Ready Interrupt Enable */
mbed_official 579:53297373a894 108 #define SYSCTRL_INTENSET_OSC32KRDY (0x1ul << SYSCTRL_INTENSET_OSC32KRDY_Pos)
mbed_official 579:53297373a894 109 #define SYSCTRL_INTENSET_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_INTENSET) OSC8M Ready Interrupt Enable */
mbed_official 579:53297373a894 110 #define SYSCTRL_INTENSET_OSC8MRDY (0x1ul << SYSCTRL_INTENSET_OSC8MRDY_Pos)
mbed_official 579:53297373a894 111 #define SYSCTRL_INTENSET_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_INTENSET) DFLL Ready Interrupt Enable */
mbed_official 579:53297373a894 112 #define SYSCTRL_INTENSET_DFLLRDY (0x1ul << SYSCTRL_INTENSET_DFLLRDY_Pos)
mbed_official 579:53297373a894 113 #define SYSCTRL_INTENSET_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_INTENSET) DFLL Out Of Bounds Interrupt Enable */
mbed_official 579:53297373a894 114 #define SYSCTRL_INTENSET_DFLLOOB (0x1ul << SYSCTRL_INTENSET_DFLLOOB_Pos)
mbed_official 579:53297373a894 115 #define SYSCTRL_INTENSET_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_INTENSET) DFLL Lock Fine Interrupt Enable */
mbed_official 579:53297373a894 116 #define SYSCTRL_INTENSET_DFLLLCKF (0x1ul << SYSCTRL_INTENSET_DFLLLCKF_Pos)
mbed_official 579:53297373a894 117 #define SYSCTRL_INTENSET_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_INTENSET) DFLL Lock Coarse Interrupt Enable */
mbed_official 579:53297373a894 118 #define SYSCTRL_INTENSET_DFLLLCKC (0x1ul << SYSCTRL_INTENSET_DFLLLCKC_Pos)
mbed_official 579:53297373a894 119 #define SYSCTRL_INTENSET_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_INTENSET) DFLL Reference Clock Stopped Interrupt Enable */
mbed_official 579:53297373a894 120 #define SYSCTRL_INTENSET_DFLLRCS (0x1ul << SYSCTRL_INTENSET_DFLLRCS_Pos)
mbed_official 579:53297373a894 121 #define SYSCTRL_INTENSET_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_INTENSET) BOD33 Ready Interrupt Enable */
mbed_official 579:53297373a894 122 #define SYSCTRL_INTENSET_BOD33RDY (0x1ul << SYSCTRL_INTENSET_BOD33RDY_Pos)
mbed_official 579:53297373a894 123 #define SYSCTRL_INTENSET_BOD33DET_Pos 10 /**< \brief (SYSCTRL_INTENSET) BOD33 Detection Interrupt Enable */
mbed_official 579:53297373a894 124 #define SYSCTRL_INTENSET_BOD33DET (0x1ul << SYSCTRL_INTENSET_BOD33DET_Pos)
mbed_official 579:53297373a894 125 #define SYSCTRL_INTENSET_B33SRDY_Pos 11 /**< \brief (SYSCTRL_INTENSET) BOD33 Synchronization Ready Interrupt Enable */
mbed_official 579:53297373a894 126 #define SYSCTRL_INTENSET_B33SRDY (0x1ul << SYSCTRL_INTENSET_B33SRDY_Pos)
mbed_official 579:53297373a894 127 #define SYSCTRL_INTENSET_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_INTENSET) DPLL Lock Rise Interrupt Enable */
mbed_official 579:53297373a894 128 #define SYSCTRL_INTENSET_DPLLLCKR (0x1ul << SYSCTRL_INTENSET_DPLLLCKR_Pos)
mbed_official 579:53297373a894 129 #define SYSCTRL_INTENSET_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_INTENSET) DPLL Lock Fall Interrupt Enable */
mbed_official 579:53297373a894 130 #define SYSCTRL_INTENSET_DPLLLCKF (0x1ul << SYSCTRL_INTENSET_DPLLLCKF_Pos)
mbed_official 579:53297373a894 131 #define SYSCTRL_INTENSET_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_INTENSET) DPLL Lock Timeout Interrupt Enable */
mbed_official 579:53297373a894 132 #define SYSCTRL_INTENSET_DPLLLTO (0x1ul << SYSCTRL_INTENSET_DPLLLTO_Pos)
mbed_official 579:53297373a894 133 #define SYSCTRL_INTENSET_MASK 0x00038FFFul /**< \brief (SYSCTRL_INTENSET) MASK Register */
mbed_official 579:53297373a894 134
mbed_official 579:53297373a894 135 /* -------- SYSCTRL_INTFLAG : (SYSCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
mbed_official 579:53297373a894 136 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 137 typedef union {
mbed_official 579:53297373a894 138 struct {
mbed_official 579:53297373a894 139 uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
mbed_official 579:53297373a894 140 uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
mbed_official 579:53297373a894 141 uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
mbed_official 579:53297373a894 142 uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
mbed_official 579:53297373a894 143 uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
mbed_official 579:53297373a894 144 uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
mbed_official 579:53297373a894 145 uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
mbed_official 579:53297373a894 146 uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
mbed_official 579:53297373a894 147 uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
mbed_official 579:53297373a894 148 uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
mbed_official 579:53297373a894 149 uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
mbed_official 579:53297373a894 150 uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
mbed_official 579:53297373a894 151 uint32_t :3; /*!< bit: 12..14 Reserved */
mbed_official 579:53297373a894 152 uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
mbed_official 579:53297373a894 153 uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
mbed_official 579:53297373a894 154 uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
mbed_official 579:53297373a894 155 uint32_t :14; /*!< bit: 18..31 Reserved */
mbed_official 579:53297373a894 156 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 157 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 158 } SYSCTRL_INTFLAG_Type;
mbed_official 579:53297373a894 159 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 160
mbed_official 579:53297373a894 161 #define SYSCTRL_INTFLAG_OFFSET 0x08 /**< \brief (SYSCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 162 #define SYSCTRL_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 163
mbed_official 579:53297373a894 164 #define SYSCTRL_INTFLAG_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_INTFLAG) XOSC Ready */
mbed_official 579:53297373a894 165 #define SYSCTRL_INTFLAG_XOSCRDY (0x1ul << SYSCTRL_INTFLAG_XOSCRDY_Pos)
mbed_official 579:53297373a894 166 #define SYSCTRL_INTFLAG_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_INTFLAG) XOSC32K Ready */
mbed_official 579:53297373a894 167 #define SYSCTRL_INTFLAG_XOSC32KRDY (0x1ul << SYSCTRL_INTFLAG_XOSC32KRDY_Pos)
mbed_official 579:53297373a894 168 #define SYSCTRL_INTFLAG_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_INTFLAG) OSC32K Ready */
mbed_official 579:53297373a894 169 #define SYSCTRL_INTFLAG_OSC32KRDY (0x1ul << SYSCTRL_INTFLAG_OSC32KRDY_Pos)
mbed_official 579:53297373a894 170 #define SYSCTRL_INTFLAG_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_INTFLAG) OSC8M Ready */
mbed_official 579:53297373a894 171 #define SYSCTRL_INTFLAG_OSC8MRDY (0x1ul << SYSCTRL_INTFLAG_OSC8MRDY_Pos)
mbed_official 579:53297373a894 172 #define SYSCTRL_INTFLAG_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_INTFLAG) DFLL Ready */
mbed_official 579:53297373a894 173 #define SYSCTRL_INTFLAG_DFLLRDY (0x1ul << SYSCTRL_INTFLAG_DFLLRDY_Pos)
mbed_official 579:53297373a894 174 #define SYSCTRL_INTFLAG_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_INTFLAG) DFLL Out Of Bounds */
mbed_official 579:53297373a894 175 #define SYSCTRL_INTFLAG_DFLLOOB (0x1ul << SYSCTRL_INTFLAG_DFLLOOB_Pos)
mbed_official 579:53297373a894 176 #define SYSCTRL_INTFLAG_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_INTFLAG) DFLL Lock Fine */
mbed_official 579:53297373a894 177 #define SYSCTRL_INTFLAG_DFLLLCKF (0x1ul << SYSCTRL_INTFLAG_DFLLLCKF_Pos)
mbed_official 579:53297373a894 178 #define SYSCTRL_INTFLAG_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_INTFLAG) DFLL Lock Coarse */
mbed_official 579:53297373a894 179 #define SYSCTRL_INTFLAG_DFLLLCKC (0x1ul << SYSCTRL_INTFLAG_DFLLLCKC_Pos)
mbed_official 579:53297373a894 180 #define SYSCTRL_INTFLAG_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_INTFLAG) DFLL Reference Clock Stopped */
mbed_official 579:53297373a894 181 #define SYSCTRL_INTFLAG_DFLLRCS (0x1ul << SYSCTRL_INTFLAG_DFLLRCS_Pos)
mbed_official 579:53297373a894 182 #define SYSCTRL_INTFLAG_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_INTFLAG) BOD33 Ready */
mbed_official 579:53297373a894 183 #define SYSCTRL_INTFLAG_BOD33RDY (0x1ul << SYSCTRL_INTFLAG_BOD33RDY_Pos)
mbed_official 579:53297373a894 184 #define SYSCTRL_INTFLAG_BOD33DET_Pos 10 /**< \brief (SYSCTRL_INTFLAG) BOD33 Detection */
mbed_official 579:53297373a894 185 #define SYSCTRL_INTFLAG_BOD33DET (0x1ul << SYSCTRL_INTFLAG_BOD33DET_Pos)
mbed_official 579:53297373a894 186 #define SYSCTRL_INTFLAG_B33SRDY_Pos 11 /**< \brief (SYSCTRL_INTFLAG) BOD33 Synchronization Ready */
mbed_official 579:53297373a894 187 #define SYSCTRL_INTFLAG_B33SRDY (0x1ul << SYSCTRL_INTFLAG_B33SRDY_Pos)
mbed_official 579:53297373a894 188 #define SYSCTRL_INTFLAG_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Rise */
mbed_official 579:53297373a894 189 #define SYSCTRL_INTFLAG_DPLLLCKR (0x1ul << SYSCTRL_INTFLAG_DPLLLCKR_Pos)
mbed_official 579:53297373a894 190 #define SYSCTRL_INTFLAG_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Fall */
mbed_official 579:53297373a894 191 #define SYSCTRL_INTFLAG_DPLLLCKF (0x1ul << SYSCTRL_INTFLAG_DPLLLCKF_Pos)
mbed_official 579:53297373a894 192 #define SYSCTRL_INTFLAG_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Timeout */
mbed_official 579:53297373a894 193 #define SYSCTRL_INTFLAG_DPLLLTO (0x1ul << SYSCTRL_INTFLAG_DPLLLTO_Pos)
mbed_official 579:53297373a894 194 #define SYSCTRL_INTFLAG_MASK 0x00038FFFul /**< \brief (SYSCTRL_INTFLAG) MASK Register */
mbed_official 579:53297373a894 195
mbed_official 579:53297373a894 196 /* -------- SYSCTRL_PCLKSR : (SYSCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */
mbed_official 579:53297373a894 197 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 198 typedef union {
mbed_official 579:53297373a894 199 struct {
mbed_official 579:53297373a894 200 uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
mbed_official 579:53297373a894 201 uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
mbed_official 579:53297373a894 202 uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
mbed_official 579:53297373a894 203 uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
mbed_official 579:53297373a894 204 uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
mbed_official 579:53297373a894 205 uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
mbed_official 579:53297373a894 206 uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
mbed_official 579:53297373a894 207 uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
mbed_official 579:53297373a894 208 uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
mbed_official 579:53297373a894 209 uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
mbed_official 579:53297373a894 210 uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
mbed_official 579:53297373a894 211 uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
mbed_official 579:53297373a894 212 uint32_t :3; /*!< bit: 12..14 Reserved */
mbed_official 579:53297373a894 213 uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
mbed_official 579:53297373a894 214 uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
mbed_official 579:53297373a894 215 uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
mbed_official 579:53297373a894 216 uint32_t :14; /*!< bit: 18..31 Reserved */
mbed_official 579:53297373a894 217 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 218 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 219 } SYSCTRL_PCLKSR_Type;
mbed_official 579:53297373a894 220 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 221
mbed_official 579:53297373a894 222 #define SYSCTRL_PCLKSR_OFFSET 0x0C /**< \brief (SYSCTRL_PCLKSR offset) Power and Clocks Status */
mbed_official 579:53297373a894 223 #define SYSCTRL_PCLKSR_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_PCLKSR reset_value) Power and Clocks Status */
mbed_official 579:53297373a894 224
mbed_official 579:53297373a894 225 #define SYSCTRL_PCLKSR_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_PCLKSR) XOSC Ready */
mbed_official 579:53297373a894 226 #define SYSCTRL_PCLKSR_XOSCRDY (0x1ul << SYSCTRL_PCLKSR_XOSCRDY_Pos)
mbed_official 579:53297373a894 227 #define SYSCTRL_PCLKSR_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_PCLKSR) XOSC32K Ready */
mbed_official 579:53297373a894 228 #define SYSCTRL_PCLKSR_XOSC32KRDY (0x1ul << SYSCTRL_PCLKSR_XOSC32KRDY_Pos)
mbed_official 579:53297373a894 229 #define SYSCTRL_PCLKSR_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_PCLKSR) OSC32K Ready */
mbed_official 579:53297373a894 230 #define SYSCTRL_PCLKSR_OSC32KRDY (0x1ul << SYSCTRL_PCLKSR_OSC32KRDY_Pos)
mbed_official 579:53297373a894 231 #define SYSCTRL_PCLKSR_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_PCLKSR) OSC8M Ready */
mbed_official 579:53297373a894 232 #define SYSCTRL_PCLKSR_OSC8MRDY (0x1ul << SYSCTRL_PCLKSR_OSC8MRDY_Pos)
mbed_official 579:53297373a894 233 #define SYSCTRL_PCLKSR_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_PCLKSR) DFLL Ready */
mbed_official 579:53297373a894 234 #define SYSCTRL_PCLKSR_DFLLRDY (0x1ul << SYSCTRL_PCLKSR_DFLLRDY_Pos)
mbed_official 579:53297373a894 235 #define SYSCTRL_PCLKSR_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_PCLKSR) DFLL Out Of Bounds */
mbed_official 579:53297373a894 236 #define SYSCTRL_PCLKSR_DFLLOOB (0x1ul << SYSCTRL_PCLKSR_DFLLOOB_Pos)
mbed_official 579:53297373a894 237 #define SYSCTRL_PCLKSR_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_PCLKSR) DFLL Lock Fine */
mbed_official 579:53297373a894 238 #define SYSCTRL_PCLKSR_DFLLLCKF (0x1ul << SYSCTRL_PCLKSR_DFLLLCKF_Pos)
mbed_official 579:53297373a894 239 #define SYSCTRL_PCLKSR_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_PCLKSR) DFLL Lock Coarse */
mbed_official 579:53297373a894 240 #define SYSCTRL_PCLKSR_DFLLLCKC (0x1ul << SYSCTRL_PCLKSR_DFLLLCKC_Pos)
mbed_official 579:53297373a894 241 #define SYSCTRL_PCLKSR_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_PCLKSR) DFLL Reference Clock Stopped */
mbed_official 579:53297373a894 242 #define SYSCTRL_PCLKSR_DFLLRCS (0x1ul << SYSCTRL_PCLKSR_DFLLRCS_Pos)
mbed_official 579:53297373a894 243 #define SYSCTRL_PCLKSR_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_PCLKSR) BOD33 Ready */
mbed_official 579:53297373a894 244 #define SYSCTRL_PCLKSR_BOD33RDY (0x1ul << SYSCTRL_PCLKSR_BOD33RDY_Pos)
mbed_official 579:53297373a894 245 #define SYSCTRL_PCLKSR_BOD33DET_Pos 10 /**< \brief (SYSCTRL_PCLKSR) BOD33 Detection */
mbed_official 579:53297373a894 246 #define SYSCTRL_PCLKSR_BOD33DET (0x1ul << SYSCTRL_PCLKSR_BOD33DET_Pos)
mbed_official 579:53297373a894 247 #define SYSCTRL_PCLKSR_B33SRDY_Pos 11 /**< \brief (SYSCTRL_PCLKSR) BOD33 Synchronization Ready */
mbed_official 579:53297373a894 248 #define SYSCTRL_PCLKSR_B33SRDY (0x1ul << SYSCTRL_PCLKSR_B33SRDY_Pos)
mbed_official 579:53297373a894 249 #define SYSCTRL_PCLKSR_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Rise */
mbed_official 579:53297373a894 250 #define SYSCTRL_PCLKSR_DPLLLCKR (0x1ul << SYSCTRL_PCLKSR_DPLLLCKR_Pos)
mbed_official 579:53297373a894 251 #define SYSCTRL_PCLKSR_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Fall */
mbed_official 579:53297373a894 252 #define SYSCTRL_PCLKSR_DPLLLCKF (0x1ul << SYSCTRL_PCLKSR_DPLLLCKF_Pos)
mbed_official 579:53297373a894 253 #define SYSCTRL_PCLKSR_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Timeout */
mbed_official 579:53297373a894 254 #define SYSCTRL_PCLKSR_DPLLLTO (0x1ul << SYSCTRL_PCLKSR_DPLLLTO_Pos)
mbed_official 579:53297373a894 255 #define SYSCTRL_PCLKSR_MASK 0x00038FFFul /**< \brief (SYSCTRL_PCLKSR) MASK Register */
mbed_official 579:53297373a894 256
mbed_official 579:53297373a894 257 /* -------- SYSCTRL_XOSC : (SYSCTRL Offset: 0x10) (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control -------- */
mbed_official 579:53297373a894 258 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 259 typedef union {
mbed_official 579:53297373a894 260 struct {
mbed_official 579:53297373a894 261 uint16_t :1; /*!< bit: 0 Reserved */
mbed_official 579:53297373a894 262 uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
mbed_official 579:53297373a894 263 uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
mbed_official 579:53297373a894 264 uint16_t :3; /*!< bit: 3.. 5 Reserved */
mbed_official 579:53297373a894 265 uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
mbed_official 579:53297373a894 266 uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
mbed_official 579:53297373a894 267 uint16_t GAIN:3; /*!< bit: 8..10 Oscillator Gain */
mbed_official 579:53297373a894 268 uint16_t AMPGC:1; /*!< bit: 11 Automatic Amplitude Gain Control */
mbed_official 579:53297373a894 269 uint16_t STARTUP:4; /*!< bit: 12..15 Start-Up Time */
mbed_official 579:53297373a894 270 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 271 uint16_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 272 } SYSCTRL_XOSC_Type;
mbed_official 579:53297373a894 273 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 274
mbed_official 579:53297373a894 275 #define SYSCTRL_XOSC_OFFSET 0x10 /**< \brief (SYSCTRL_XOSC offset) External Multipurpose Crystal Oscillator (XOSC) Control */
mbed_official 579:53297373a894 276 #define SYSCTRL_XOSC_RESETVALUE 0x0080ul /**< \brief (SYSCTRL_XOSC reset_value) External Multipurpose Crystal Oscillator (XOSC) Control */
mbed_official 579:53297373a894 277
mbed_official 579:53297373a894 278 #define SYSCTRL_XOSC_ENABLE_Pos 1 /**< \brief (SYSCTRL_XOSC) Oscillator Enable */
mbed_official 579:53297373a894 279 #define SYSCTRL_XOSC_ENABLE (0x1ul << SYSCTRL_XOSC_ENABLE_Pos)
mbed_official 579:53297373a894 280 #define SYSCTRL_XOSC_XTALEN_Pos 2 /**< \brief (SYSCTRL_XOSC) Crystal Oscillator Enable */
mbed_official 579:53297373a894 281 #define SYSCTRL_XOSC_XTALEN (0x1ul << SYSCTRL_XOSC_XTALEN_Pos)
mbed_official 579:53297373a894 282 #define SYSCTRL_XOSC_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_XOSC) Run in Standby */
mbed_official 579:53297373a894 283 #define SYSCTRL_XOSC_RUNSTDBY (0x1ul << SYSCTRL_XOSC_RUNSTDBY_Pos)
mbed_official 579:53297373a894 284 #define SYSCTRL_XOSC_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_XOSC) On Demand Control */
mbed_official 579:53297373a894 285 #define SYSCTRL_XOSC_ONDEMAND (0x1ul << SYSCTRL_XOSC_ONDEMAND_Pos)
mbed_official 579:53297373a894 286 #define SYSCTRL_XOSC_GAIN_Pos 8 /**< \brief (SYSCTRL_XOSC) Oscillator Gain */
mbed_official 579:53297373a894 287 #define SYSCTRL_XOSC_GAIN_Msk (0x7ul << SYSCTRL_XOSC_GAIN_Pos)
mbed_official 579:53297373a894 288 #define SYSCTRL_XOSC_GAIN(value) ((SYSCTRL_XOSC_GAIN_Msk & ((value) << SYSCTRL_XOSC_GAIN_Pos)))
mbed_official 579:53297373a894 289 #define SYSCTRL_XOSC_GAIN_0_Val 0x0ul /**< \brief (SYSCTRL_XOSC) 2MHz */
mbed_official 579:53297373a894 290 #define SYSCTRL_XOSC_GAIN_1_Val 0x1ul /**< \brief (SYSCTRL_XOSC) 4MHz */
mbed_official 579:53297373a894 291 #define SYSCTRL_XOSC_GAIN_2_Val 0x2ul /**< \brief (SYSCTRL_XOSC) 8MHz */
mbed_official 579:53297373a894 292 #define SYSCTRL_XOSC_GAIN_3_Val 0x3ul /**< \brief (SYSCTRL_XOSC) 16MHz */
mbed_official 579:53297373a894 293 #define SYSCTRL_XOSC_GAIN_4_Val 0x4ul /**< \brief (SYSCTRL_XOSC) 30MHz */
mbed_official 579:53297373a894 294 #define SYSCTRL_XOSC_GAIN_0 (SYSCTRL_XOSC_GAIN_0_Val << SYSCTRL_XOSC_GAIN_Pos)
mbed_official 579:53297373a894 295 #define SYSCTRL_XOSC_GAIN_1 (SYSCTRL_XOSC_GAIN_1_Val << SYSCTRL_XOSC_GAIN_Pos)
mbed_official 579:53297373a894 296 #define SYSCTRL_XOSC_GAIN_2 (SYSCTRL_XOSC_GAIN_2_Val << SYSCTRL_XOSC_GAIN_Pos)
mbed_official 579:53297373a894 297 #define SYSCTRL_XOSC_GAIN_3 (SYSCTRL_XOSC_GAIN_3_Val << SYSCTRL_XOSC_GAIN_Pos)
mbed_official 579:53297373a894 298 #define SYSCTRL_XOSC_GAIN_4 (SYSCTRL_XOSC_GAIN_4_Val << SYSCTRL_XOSC_GAIN_Pos)
mbed_official 579:53297373a894 299 #define SYSCTRL_XOSC_AMPGC_Pos 11 /**< \brief (SYSCTRL_XOSC) Automatic Amplitude Gain Control */
mbed_official 579:53297373a894 300 #define SYSCTRL_XOSC_AMPGC (0x1ul << SYSCTRL_XOSC_AMPGC_Pos)
mbed_official 579:53297373a894 301 #define SYSCTRL_XOSC_STARTUP_Pos 12 /**< \brief (SYSCTRL_XOSC) Start-Up Time */
mbed_official 579:53297373a894 302 #define SYSCTRL_XOSC_STARTUP_Msk (0xFul << SYSCTRL_XOSC_STARTUP_Pos)
mbed_official 579:53297373a894 303 #define SYSCTRL_XOSC_STARTUP(value) ((SYSCTRL_XOSC_STARTUP_Msk & ((value) << SYSCTRL_XOSC_STARTUP_Pos)))
mbed_official 579:53297373a894 304 #define SYSCTRL_XOSC_MASK 0xFFC6ul /**< \brief (SYSCTRL_XOSC) MASK Register */
mbed_official 579:53297373a894 305
mbed_official 579:53297373a894 306 /* -------- SYSCTRL_XOSC32K : (SYSCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */
mbed_official 579:53297373a894 307 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 308 typedef union {
mbed_official 579:53297373a894 309 struct {
mbed_official 579:53297373a894 310 uint16_t :1; /*!< bit: 0 Reserved */
mbed_official 579:53297373a894 311 uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
mbed_official 579:53297373a894 312 uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
mbed_official 579:53297373a894 313 uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */
mbed_official 579:53297373a894 314 uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */
mbed_official 579:53297373a894 315 uint16_t AAMPEN:1; /*!< bit: 5 Automatic Amplitude Control Enable */
mbed_official 579:53297373a894 316 uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
mbed_official 579:53297373a894 317 uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
mbed_official 579:53297373a894 318 uint16_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
mbed_official 579:53297373a894 319 uint16_t :1; /*!< bit: 11 Reserved */
mbed_official 579:53297373a894 320 uint16_t WRTLOCK:1; /*!< bit: 12 Write Lock */
mbed_official 579:53297373a894 321 uint16_t :3; /*!< bit: 13..15 Reserved */
mbed_official 579:53297373a894 322 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 323 uint16_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 324 } SYSCTRL_XOSC32K_Type;
mbed_official 579:53297373a894 325 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 326
mbed_official 579:53297373a894 327 #define SYSCTRL_XOSC32K_OFFSET 0x14 /**< \brief (SYSCTRL_XOSC32K offset) 32kHz External Crystal Oscillator (XOSC32K) Control */
mbed_official 579:53297373a894 328 #define SYSCTRL_XOSC32K_RESETVALUE 0x0080ul /**< \brief (SYSCTRL_XOSC32K reset_value) 32kHz External Crystal Oscillator (XOSC32K) Control */
mbed_official 579:53297373a894 329
mbed_official 579:53297373a894 330 #define SYSCTRL_XOSC32K_ENABLE_Pos 1 /**< \brief (SYSCTRL_XOSC32K) Oscillator Enable */
mbed_official 579:53297373a894 331 #define SYSCTRL_XOSC32K_ENABLE (0x1ul << SYSCTRL_XOSC32K_ENABLE_Pos)
mbed_official 579:53297373a894 332 #define SYSCTRL_XOSC32K_XTALEN_Pos 2 /**< \brief (SYSCTRL_XOSC32K) Crystal Oscillator Enable */
mbed_official 579:53297373a894 333 #define SYSCTRL_XOSC32K_XTALEN (0x1ul << SYSCTRL_XOSC32K_XTALEN_Pos)
mbed_official 579:53297373a894 334 #define SYSCTRL_XOSC32K_EN32K_Pos 3 /**< \brief (SYSCTRL_XOSC32K) 32kHz Output Enable */
mbed_official 579:53297373a894 335 #define SYSCTRL_XOSC32K_EN32K (0x1ul << SYSCTRL_XOSC32K_EN32K_Pos)
mbed_official 579:53297373a894 336 #define SYSCTRL_XOSC32K_EN1K_Pos 4 /**< \brief (SYSCTRL_XOSC32K) 1kHz Output Enable */
mbed_official 579:53297373a894 337 #define SYSCTRL_XOSC32K_EN1K (0x1ul << SYSCTRL_XOSC32K_EN1K_Pos)
mbed_official 579:53297373a894 338 #define SYSCTRL_XOSC32K_AAMPEN_Pos 5 /**< \brief (SYSCTRL_XOSC32K) Automatic Amplitude Control Enable */
mbed_official 579:53297373a894 339 #define SYSCTRL_XOSC32K_AAMPEN (0x1ul << SYSCTRL_XOSC32K_AAMPEN_Pos)
mbed_official 579:53297373a894 340 #define SYSCTRL_XOSC32K_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_XOSC32K) Run in Standby */
mbed_official 579:53297373a894 341 #define SYSCTRL_XOSC32K_RUNSTDBY (0x1ul << SYSCTRL_XOSC32K_RUNSTDBY_Pos)
mbed_official 579:53297373a894 342 #define SYSCTRL_XOSC32K_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_XOSC32K) On Demand Control */
mbed_official 579:53297373a894 343 #define SYSCTRL_XOSC32K_ONDEMAND (0x1ul << SYSCTRL_XOSC32K_ONDEMAND_Pos)
mbed_official 579:53297373a894 344 #define SYSCTRL_XOSC32K_STARTUP_Pos 8 /**< \brief (SYSCTRL_XOSC32K) Oscillator Start-Up Time */
mbed_official 579:53297373a894 345 #define SYSCTRL_XOSC32K_STARTUP_Msk (0x7ul << SYSCTRL_XOSC32K_STARTUP_Pos)
mbed_official 579:53297373a894 346 #define SYSCTRL_XOSC32K_STARTUP(value) ((SYSCTRL_XOSC32K_STARTUP_Msk & ((value) << SYSCTRL_XOSC32K_STARTUP_Pos)))
mbed_official 579:53297373a894 347 #define SYSCTRL_XOSC32K_WRTLOCK_Pos 12 /**< \brief (SYSCTRL_XOSC32K) Write Lock */
mbed_official 579:53297373a894 348 #define SYSCTRL_XOSC32K_WRTLOCK (0x1ul << SYSCTRL_XOSC32K_WRTLOCK_Pos)
mbed_official 579:53297373a894 349 #define SYSCTRL_XOSC32K_MASK 0x17FEul /**< \brief (SYSCTRL_XOSC32K) MASK Register */
mbed_official 579:53297373a894 350
mbed_official 579:53297373a894 351 /* -------- SYSCTRL_OSC32K : (SYSCTRL Offset: 0x18) (R/W 32) 32kHz Internal Oscillator (OSC32K) Control -------- */
mbed_official 579:53297373a894 352 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 353 typedef union {
mbed_official 579:53297373a894 354 struct {
mbed_official 579:53297373a894 355 uint32_t :1; /*!< bit: 0 Reserved */
mbed_official 579:53297373a894 356 uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
mbed_official 579:53297373a894 357 uint32_t EN32K:1; /*!< bit: 2 32kHz Output Enable */
mbed_official 579:53297373a894 358 uint32_t EN1K:1; /*!< bit: 3 1kHz Output Enable */
mbed_official 579:53297373a894 359 uint32_t :2; /*!< bit: 4.. 5 Reserved */
mbed_official 579:53297373a894 360 uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
mbed_official 579:53297373a894 361 uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
mbed_official 579:53297373a894 362 uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
mbed_official 579:53297373a894 363 uint32_t :1; /*!< bit: 11 Reserved */
mbed_official 579:53297373a894 364 uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */
mbed_official 579:53297373a894 365 uint32_t :3; /*!< bit: 13..15 Reserved */
mbed_official 579:53297373a894 366 uint32_t CALIB:7; /*!< bit: 16..22 Oscillator Calibration */
mbed_official 579:53297373a894 367 uint32_t :9; /*!< bit: 23..31 Reserved */
mbed_official 579:53297373a894 368 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 369 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 370 } SYSCTRL_OSC32K_Type;
mbed_official 579:53297373a894 371 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 372
mbed_official 579:53297373a894 373 #define SYSCTRL_OSC32K_OFFSET 0x18 /**< \brief (SYSCTRL_OSC32K offset) 32kHz Internal Oscillator (OSC32K) Control */
mbed_official 579:53297373a894 374 #define SYSCTRL_OSC32K_RESETVALUE 0x003F0080ul /**< \brief (SYSCTRL_OSC32K reset_value) 32kHz Internal Oscillator (OSC32K) Control */
mbed_official 579:53297373a894 375
mbed_official 579:53297373a894 376 #define SYSCTRL_OSC32K_ENABLE_Pos 1 /**< \brief (SYSCTRL_OSC32K) Oscillator Enable */
mbed_official 579:53297373a894 377 #define SYSCTRL_OSC32K_ENABLE (0x1ul << SYSCTRL_OSC32K_ENABLE_Pos)
mbed_official 579:53297373a894 378 #define SYSCTRL_OSC32K_EN32K_Pos 2 /**< \brief (SYSCTRL_OSC32K) 32kHz Output Enable */
mbed_official 579:53297373a894 379 #define SYSCTRL_OSC32K_EN32K (0x1ul << SYSCTRL_OSC32K_EN32K_Pos)
mbed_official 579:53297373a894 380 #define SYSCTRL_OSC32K_EN1K_Pos 3 /**< \brief (SYSCTRL_OSC32K) 1kHz Output Enable */
mbed_official 579:53297373a894 381 #define SYSCTRL_OSC32K_EN1K (0x1ul << SYSCTRL_OSC32K_EN1K_Pos)
mbed_official 579:53297373a894 382 #define SYSCTRL_OSC32K_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_OSC32K) Run in Standby */
mbed_official 579:53297373a894 383 #define SYSCTRL_OSC32K_RUNSTDBY (0x1ul << SYSCTRL_OSC32K_RUNSTDBY_Pos)
mbed_official 579:53297373a894 384 #define SYSCTRL_OSC32K_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_OSC32K) On Demand Control */
mbed_official 579:53297373a894 385 #define SYSCTRL_OSC32K_ONDEMAND (0x1ul << SYSCTRL_OSC32K_ONDEMAND_Pos)
mbed_official 579:53297373a894 386 #define SYSCTRL_OSC32K_STARTUP_Pos 8 /**< \brief (SYSCTRL_OSC32K) Oscillator Start-Up Time */
mbed_official 579:53297373a894 387 #define SYSCTRL_OSC32K_STARTUP_Msk (0x7ul << SYSCTRL_OSC32K_STARTUP_Pos)
mbed_official 579:53297373a894 388 #define SYSCTRL_OSC32K_STARTUP(value) ((SYSCTRL_OSC32K_STARTUP_Msk & ((value) << SYSCTRL_OSC32K_STARTUP_Pos)))
mbed_official 579:53297373a894 389 #define SYSCTRL_OSC32K_WRTLOCK_Pos 12 /**< \brief (SYSCTRL_OSC32K) Write Lock */
mbed_official 579:53297373a894 390 #define SYSCTRL_OSC32K_WRTLOCK (0x1ul << SYSCTRL_OSC32K_WRTLOCK_Pos)
mbed_official 579:53297373a894 391 #define SYSCTRL_OSC32K_CALIB_Pos 16 /**< \brief (SYSCTRL_OSC32K) Oscillator Calibration */
mbed_official 579:53297373a894 392 #define SYSCTRL_OSC32K_CALIB_Msk (0x7Ful << SYSCTRL_OSC32K_CALIB_Pos)
mbed_official 579:53297373a894 393 #define SYSCTRL_OSC32K_CALIB(value) ((SYSCTRL_OSC32K_CALIB_Msk & ((value) << SYSCTRL_OSC32K_CALIB_Pos)))
mbed_official 579:53297373a894 394 #define SYSCTRL_OSC32K_MASK 0x007F17CEul /**< \brief (SYSCTRL_OSC32K) MASK Register */
mbed_official 579:53297373a894 395
mbed_official 579:53297373a894 396 /* -------- SYSCTRL_OSCULP32K : (SYSCTRL Offset: 0x1C) (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */
mbed_official 579:53297373a894 397 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 398 typedef union {
mbed_official 579:53297373a894 399 struct {
mbed_official 579:53297373a894 400 uint8_t CALIB:5; /*!< bit: 0.. 4 Oscillator Calibration */
mbed_official 579:53297373a894 401 uint8_t :2; /*!< bit: 5.. 6 Reserved */
mbed_official 579:53297373a894 402 uint8_t WRTLOCK:1; /*!< bit: 7 Write Lock */
mbed_official 579:53297373a894 403 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 404 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 405 } SYSCTRL_OSCULP32K_Type;
mbed_official 579:53297373a894 406 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 407
mbed_official 579:53297373a894 408 #define SYSCTRL_OSCULP32K_OFFSET 0x1C /**< \brief (SYSCTRL_OSCULP32K offset) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
mbed_official 579:53297373a894 409 #define SYSCTRL_OSCULP32K_RESETVALUE 0x1Ful /**< \brief (SYSCTRL_OSCULP32K reset_value) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
mbed_official 579:53297373a894 410
mbed_official 579:53297373a894 411 #define SYSCTRL_OSCULP32K_CALIB_Pos 0 /**< \brief (SYSCTRL_OSCULP32K) Oscillator Calibration */
mbed_official 579:53297373a894 412 #define SYSCTRL_OSCULP32K_CALIB_Msk (0x1Ful << SYSCTRL_OSCULP32K_CALIB_Pos)
mbed_official 579:53297373a894 413 #define SYSCTRL_OSCULP32K_CALIB(value) ((SYSCTRL_OSCULP32K_CALIB_Msk & ((value) << SYSCTRL_OSCULP32K_CALIB_Pos)))
mbed_official 579:53297373a894 414 #define SYSCTRL_OSCULP32K_WRTLOCK_Pos 7 /**< \brief (SYSCTRL_OSCULP32K) Write Lock */
mbed_official 579:53297373a894 415 #define SYSCTRL_OSCULP32K_WRTLOCK (0x1ul << SYSCTRL_OSCULP32K_WRTLOCK_Pos)
mbed_official 579:53297373a894 416 #define SYSCTRL_OSCULP32K_MASK 0x9Ful /**< \brief (SYSCTRL_OSCULP32K) MASK Register */
mbed_official 579:53297373a894 417
mbed_official 579:53297373a894 418 /* -------- SYSCTRL_OSC8M : (SYSCTRL Offset: 0x20) (R/W 32) 8MHz Internal Oscillator (OSC8M) Control -------- */
mbed_official 579:53297373a894 419 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 420 typedef union {
mbed_official 579:53297373a894 421 struct {
mbed_official 579:53297373a894 422 uint32_t :1; /*!< bit: 0 Reserved */
mbed_official 579:53297373a894 423 uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
mbed_official 579:53297373a894 424 uint32_t :4; /*!< bit: 2.. 5 Reserved */
mbed_official 579:53297373a894 425 uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
mbed_official 579:53297373a894 426 uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
mbed_official 579:53297373a894 427 uint32_t PRESC:2; /*!< bit: 8.. 9 Oscillator Prescaler */
mbed_official 579:53297373a894 428 uint32_t :6; /*!< bit: 10..15 Reserved */
mbed_official 579:53297373a894 429 uint32_t CALIB:12; /*!< bit: 16..27 Oscillator Calibration */
mbed_official 579:53297373a894 430 uint32_t :2; /*!< bit: 28..29 Reserved */
mbed_official 579:53297373a894 431 uint32_t FRANGE:2; /*!< bit: 30..31 Oscillator Frequency Range */
mbed_official 579:53297373a894 432 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 433 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 434 } SYSCTRL_OSC8M_Type;
mbed_official 579:53297373a894 435 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 436
mbed_official 579:53297373a894 437 #define SYSCTRL_OSC8M_OFFSET 0x20 /**< \brief (SYSCTRL_OSC8M offset) 8MHz Internal Oscillator (OSC8M) Control */
mbed_official 579:53297373a894 438 #define SYSCTRL_OSC8M_RESETVALUE 0x87070382ul /**< \brief (SYSCTRL_OSC8M reset_value) 8MHz Internal Oscillator (OSC8M) Control */
mbed_official 579:53297373a894 439
mbed_official 579:53297373a894 440 #define SYSCTRL_OSC8M_ENABLE_Pos 1 /**< \brief (SYSCTRL_OSC8M) Oscillator Enable */
mbed_official 579:53297373a894 441 #define SYSCTRL_OSC8M_ENABLE (0x1ul << SYSCTRL_OSC8M_ENABLE_Pos)
mbed_official 579:53297373a894 442 #define SYSCTRL_OSC8M_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_OSC8M) Run in Standby */
mbed_official 579:53297373a894 443 #define SYSCTRL_OSC8M_RUNSTDBY (0x1ul << SYSCTRL_OSC8M_RUNSTDBY_Pos)
mbed_official 579:53297373a894 444 #define SYSCTRL_OSC8M_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_OSC8M) On Demand Control */
mbed_official 579:53297373a894 445 #define SYSCTRL_OSC8M_ONDEMAND (0x1ul << SYSCTRL_OSC8M_ONDEMAND_Pos)
mbed_official 579:53297373a894 446 #define SYSCTRL_OSC8M_PRESC_Pos 8 /**< \brief (SYSCTRL_OSC8M) Oscillator Prescaler */
mbed_official 579:53297373a894 447 #define SYSCTRL_OSC8M_PRESC_Msk (0x3ul << SYSCTRL_OSC8M_PRESC_Pos)
mbed_official 579:53297373a894 448 #define SYSCTRL_OSC8M_PRESC(value) ((SYSCTRL_OSC8M_PRESC_Msk & ((value) << SYSCTRL_OSC8M_PRESC_Pos)))
mbed_official 579:53297373a894 449 #define SYSCTRL_OSC8M_PRESC_0_Val 0x0ul /**< \brief (SYSCTRL_OSC8M) 1 */
mbed_official 579:53297373a894 450 #define SYSCTRL_OSC8M_PRESC_1_Val 0x1ul /**< \brief (SYSCTRL_OSC8M) 2 */
mbed_official 579:53297373a894 451 #define SYSCTRL_OSC8M_PRESC_2_Val 0x2ul /**< \brief (SYSCTRL_OSC8M) 4 */
mbed_official 579:53297373a894 452 #define SYSCTRL_OSC8M_PRESC_3_Val 0x3ul /**< \brief (SYSCTRL_OSC8M) 8 */
mbed_official 579:53297373a894 453 #define SYSCTRL_OSC8M_PRESC_0 (SYSCTRL_OSC8M_PRESC_0_Val << SYSCTRL_OSC8M_PRESC_Pos)
mbed_official 579:53297373a894 454 #define SYSCTRL_OSC8M_PRESC_1 (SYSCTRL_OSC8M_PRESC_1_Val << SYSCTRL_OSC8M_PRESC_Pos)
mbed_official 579:53297373a894 455 #define SYSCTRL_OSC8M_PRESC_2 (SYSCTRL_OSC8M_PRESC_2_Val << SYSCTRL_OSC8M_PRESC_Pos)
mbed_official 579:53297373a894 456 #define SYSCTRL_OSC8M_PRESC_3 (SYSCTRL_OSC8M_PRESC_3_Val << SYSCTRL_OSC8M_PRESC_Pos)
mbed_official 579:53297373a894 457 #define SYSCTRL_OSC8M_CALIB_Pos 16 /**< \brief (SYSCTRL_OSC8M) Oscillator Calibration */
mbed_official 579:53297373a894 458 #define SYSCTRL_OSC8M_CALIB_Msk (0xFFFul << SYSCTRL_OSC8M_CALIB_Pos)
mbed_official 579:53297373a894 459 #define SYSCTRL_OSC8M_CALIB(value) ((SYSCTRL_OSC8M_CALIB_Msk & ((value) << SYSCTRL_OSC8M_CALIB_Pos)))
mbed_official 579:53297373a894 460 #define SYSCTRL_OSC8M_FRANGE_Pos 30 /**< \brief (SYSCTRL_OSC8M) Oscillator Frequency Range */
mbed_official 579:53297373a894 461 #define SYSCTRL_OSC8M_FRANGE_Msk (0x3ul << SYSCTRL_OSC8M_FRANGE_Pos)
mbed_official 579:53297373a894 462 #define SYSCTRL_OSC8M_FRANGE(value) ((SYSCTRL_OSC8M_FRANGE_Msk & ((value) << SYSCTRL_OSC8M_FRANGE_Pos)))
mbed_official 579:53297373a894 463 #define SYSCTRL_OSC8M_FRANGE_0_Val 0x0ul /**< \brief (SYSCTRL_OSC8M) 4 to 6MHz */
mbed_official 579:53297373a894 464 #define SYSCTRL_OSC8M_FRANGE_1_Val 0x1ul /**< \brief (SYSCTRL_OSC8M) 6 to 8MHz */
mbed_official 579:53297373a894 465 #define SYSCTRL_OSC8M_FRANGE_2_Val 0x2ul /**< \brief (SYSCTRL_OSC8M) 8 to 11MHz */
mbed_official 579:53297373a894 466 #define SYSCTRL_OSC8M_FRANGE_3_Val 0x3ul /**< \brief (SYSCTRL_OSC8M) 11 to 15MHz */
mbed_official 579:53297373a894 467 #define SYSCTRL_OSC8M_FRANGE_0 (SYSCTRL_OSC8M_FRANGE_0_Val << SYSCTRL_OSC8M_FRANGE_Pos)
mbed_official 579:53297373a894 468 #define SYSCTRL_OSC8M_FRANGE_1 (SYSCTRL_OSC8M_FRANGE_1_Val << SYSCTRL_OSC8M_FRANGE_Pos)
mbed_official 579:53297373a894 469 #define SYSCTRL_OSC8M_FRANGE_2 (SYSCTRL_OSC8M_FRANGE_2_Val << SYSCTRL_OSC8M_FRANGE_Pos)
mbed_official 579:53297373a894 470 #define SYSCTRL_OSC8M_FRANGE_3 (SYSCTRL_OSC8M_FRANGE_3_Val << SYSCTRL_OSC8M_FRANGE_Pos)
mbed_official 579:53297373a894 471 #define SYSCTRL_OSC8M_MASK 0xCFFF03C2ul /**< \brief (SYSCTRL_OSC8M) MASK Register */
mbed_official 579:53297373a894 472
mbed_official 579:53297373a894 473 /* -------- SYSCTRL_DFLLCTRL : (SYSCTRL Offset: 0x24) (R/W 16) DFLL48M Control -------- */
mbed_official 579:53297373a894 474 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 475 typedef union {
mbed_official 579:53297373a894 476 struct {
mbed_official 579:53297373a894 477 uint16_t :1; /*!< bit: 0 Reserved */
mbed_official 579:53297373a894 478 uint16_t ENABLE:1; /*!< bit: 1 DFLL Enable */
mbed_official 579:53297373a894 479 uint16_t MODE:1; /*!< bit: 2 Operating Mode Selection */
mbed_official 579:53297373a894 480 uint16_t STABLE:1; /*!< bit: 3 Stable DFLL Frequency */
mbed_official 579:53297373a894 481 uint16_t LLAW:1; /*!< bit: 4 Lose Lock After Wake */
mbed_official 579:53297373a894 482 uint16_t USBCRM:1; /*!< bit: 5 USB Clock Recovery Mode */
mbed_official 579:53297373a894 483 uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
mbed_official 579:53297373a894 484 uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
mbed_official 579:53297373a894 485 uint16_t CCDIS:1; /*!< bit: 8 Chill Cycle Disable */
mbed_official 579:53297373a894 486 uint16_t QLDIS:1; /*!< bit: 9 Quick Lock Disable */
mbed_official 579:53297373a894 487 uint16_t BPLCKC:1; /*!< bit: 10 Bypass Coarse Lock */
mbed_official 579:53297373a894 488 uint16_t WAITLOCK:1; /*!< bit: 11 Wait Lock */
mbed_official 579:53297373a894 489 uint16_t :4; /*!< bit: 12..15 Reserved */
mbed_official 579:53297373a894 490 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 491 uint16_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 492 } SYSCTRL_DFLLCTRL_Type;
mbed_official 579:53297373a894 493 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 494
mbed_official 579:53297373a894 495 #define SYSCTRL_DFLLCTRL_OFFSET 0x24 /**< \brief (SYSCTRL_DFLLCTRL offset) DFLL48M Control */
mbed_official 579:53297373a894 496 #define SYSCTRL_DFLLCTRL_RESETVALUE 0x0080ul /**< \brief (SYSCTRL_DFLLCTRL reset_value) DFLL48M Control */
mbed_official 579:53297373a894 497
mbed_official 579:53297373a894 498 #define SYSCTRL_DFLLCTRL_ENABLE_Pos 1 /**< \brief (SYSCTRL_DFLLCTRL) DFLL Enable */
mbed_official 579:53297373a894 499 #define SYSCTRL_DFLLCTRL_ENABLE (0x1ul << SYSCTRL_DFLLCTRL_ENABLE_Pos)
mbed_official 579:53297373a894 500 #define SYSCTRL_DFLLCTRL_MODE_Pos 2 /**< \brief (SYSCTRL_DFLLCTRL) Operating Mode Selection */
mbed_official 579:53297373a894 501 #define SYSCTRL_DFLLCTRL_MODE (0x1ul << SYSCTRL_DFLLCTRL_MODE_Pos)
mbed_official 579:53297373a894 502 #define SYSCTRL_DFLLCTRL_STABLE_Pos 3 /**< \brief (SYSCTRL_DFLLCTRL) Stable DFLL Frequency */
mbed_official 579:53297373a894 503 #define SYSCTRL_DFLLCTRL_STABLE (0x1ul << SYSCTRL_DFLLCTRL_STABLE_Pos)
mbed_official 579:53297373a894 504 #define SYSCTRL_DFLLCTRL_LLAW_Pos 4 /**< \brief (SYSCTRL_DFLLCTRL) Lose Lock After Wake */
mbed_official 579:53297373a894 505 #define SYSCTRL_DFLLCTRL_LLAW (0x1ul << SYSCTRL_DFLLCTRL_LLAW_Pos)
mbed_official 579:53297373a894 506 #define SYSCTRL_DFLLCTRL_USBCRM_Pos 5 /**< \brief (SYSCTRL_DFLLCTRL) USB Clock Recovery Mode */
mbed_official 579:53297373a894 507 #define SYSCTRL_DFLLCTRL_USBCRM (0x1ul << SYSCTRL_DFLLCTRL_USBCRM_Pos)
mbed_official 579:53297373a894 508 #define SYSCTRL_DFLLCTRL_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_DFLLCTRL) Run in Standby */
mbed_official 579:53297373a894 509 #define SYSCTRL_DFLLCTRL_RUNSTDBY (0x1ul << SYSCTRL_DFLLCTRL_RUNSTDBY_Pos)
mbed_official 579:53297373a894 510 #define SYSCTRL_DFLLCTRL_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_DFLLCTRL) On Demand Control */
mbed_official 579:53297373a894 511 #define SYSCTRL_DFLLCTRL_ONDEMAND (0x1ul << SYSCTRL_DFLLCTRL_ONDEMAND_Pos)
mbed_official 579:53297373a894 512 #define SYSCTRL_DFLLCTRL_CCDIS_Pos 8 /**< \brief (SYSCTRL_DFLLCTRL) Chill Cycle Disable */
mbed_official 579:53297373a894 513 #define SYSCTRL_DFLLCTRL_CCDIS (0x1ul << SYSCTRL_DFLLCTRL_CCDIS_Pos)
mbed_official 579:53297373a894 514 #define SYSCTRL_DFLLCTRL_QLDIS_Pos 9 /**< \brief (SYSCTRL_DFLLCTRL) Quick Lock Disable */
mbed_official 579:53297373a894 515 #define SYSCTRL_DFLLCTRL_QLDIS (0x1ul << SYSCTRL_DFLLCTRL_QLDIS_Pos)
mbed_official 579:53297373a894 516 #define SYSCTRL_DFLLCTRL_BPLCKC_Pos 10 /**< \brief (SYSCTRL_DFLLCTRL) Bypass Coarse Lock */
mbed_official 579:53297373a894 517 #define SYSCTRL_DFLLCTRL_BPLCKC (0x1ul << SYSCTRL_DFLLCTRL_BPLCKC_Pos)
mbed_official 579:53297373a894 518 #define SYSCTRL_DFLLCTRL_WAITLOCK_Pos 11 /**< \brief (SYSCTRL_DFLLCTRL) Wait Lock */
mbed_official 579:53297373a894 519 #define SYSCTRL_DFLLCTRL_WAITLOCK (0x1ul << SYSCTRL_DFLLCTRL_WAITLOCK_Pos)
mbed_official 579:53297373a894 520 #define SYSCTRL_DFLLCTRL_MASK 0x0FFEul /**< \brief (SYSCTRL_DFLLCTRL) MASK Register */
mbed_official 579:53297373a894 521
mbed_official 579:53297373a894 522 /* -------- SYSCTRL_DFLLVAL : (SYSCTRL Offset: 0x28) (R/W 32) DFLL48M Value -------- */
mbed_official 579:53297373a894 523 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 524 typedef union {
mbed_official 579:53297373a894 525 struct {
mbed_official 579:53297373a894 526 uint32_t FINE:10; /*!< bit: 0.. 9 Fine Value */
mbed_official 579:53297373a894 527 uint32_t COARSE:6; /*!< bit: 10..15 Coarse Value */
mbed_official 579:53297373a894 528 uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */
mbed_official 579:53297373a894 529 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 530 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 531 } SYSCTRL_DFLLVAL_Type;
mbed_official 579:53297373a894 532 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 533
mbed_official 579:53297373a894 534 #define SYSCTRL_DFLLVAL_OFFSET 0x28 /**< \brief (SYSCTRL_DFLLVAL offset) DFLL48M Value */
mbed_official 579:53297373a894 535 #define SYSCTRL_DFLLVAL_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_DFLLVAL reset_value) DFLL48M Value */
mbed_official 579:53297373a894 536
mbed_official 579:53297373a894 537 #define SYSCTRL_DFLLVAL_FINE_Pos 0 /**< \brief (SYSCTRL_DFLLVAL) Fine Value */
mbed_official 579:53297373a894 538 #define SYSCTRL_DFLLVAL_FINE_Msk (0x3FFul << SYSCTRL_DFLLVAL_FINE_Pos)
mbed_official 579:53297373a894 539 #define SYSCTRL_DFLLVAL_FINE(value) ((SYSCTRL_DFLLVAL_FINE_Msk & ((value) << SYSCTRL_DFLLVAL_FINE_Pos)))
mbed_official 579:53297373a894 540 #define SYSCTRL_DFLLVAL_COARSE_Pos 10 /**< \brief (SYSCTRL_DFLLVAL) Coarse Value */
mbed_official 579:53297373a894 541 #define SYSCTRL_DFLLVAL_COARSE_Msk (0x3Ful << SYSCTRL_DFLLVAL_COARSE_Pos)
mbed_official 579:53297373a894 542 #define SYSCTRL_DFLLVAL_COARSE(value) ((SYSCTRL_DFLLVAL_COARSE_Msk & ((value) << SYSCTRL_DFLLVAL_COARSE_Pos)))
mbed_official 579:53297373a894 543 #define SYSCTRL_DFLLVAL_DIFF_Pos 16 /**< \brief (SYSCTRL_DFLLVAL) Multiplication Ratio Difference */
mbed_official 579:53297373a894 544 #define SYSCTRL_DFLLVAL_DIFF_Msk (0xFFFFul << SYSCTRL_DFLLVAL_DIFF_Pos)
mbed_official 579:53297373a894 545 #define SYSCTRL_DFLLVAL_DIFF(value) ((SYSCTRL_DFLLVAL_DIFF_Msk & ((value) << SYSCTRL_DFLLVAL_DIFF_Pos)))
mbed_official 579:53297373a894 546 #define SYSCTRL_DFLLVAL_MASK 0xFFFFFFFFul /**< \brief (SYSCTRL_DFLLVAL) MASK Register */
mbed_official 579:53297373a894 547
mbed_official 579:53297373a894 548 /* -------- SYSCTRL_DFLLMUL : (SYSCTRL Offset: 0x2C) (R/W 32) DFLL48M Multiplier -------- */
mbed_official 579:53297373a894 549 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 550 typedef union {
mbed_official 579:53297373a894 551 struct {
mbed_official 579:53297373a894 552 uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */
mbed_official 579:53297373a894 553 uint32_t FSTEP:10; /*!< bit: 16..25 Fine Maximum Step */
mbed_official 579:53297373a894 554 uint32_t CSTEP:6; /*!< bit: 26..31 Coarse Maximum Step */
mbed_official 579:53297373a894 555 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 556 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 557 } SYSCTRL_DFLLMUL_Type;
mbed_official 579:53297373a894 558 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 559
mbed_official 579:53297373a894 560 #define SYSCTRL_DFLLMUL_OFFSET 0x2C /**< \brief (SYSCTRL_DFLLMUL offset) DFLL48M Multiplier */
mbed_official 579:53297373a894 561 #define SYSCTRL_DFLLMUL_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_DFLLMUL reset_value) DFLL48M Multiplier */
mbed_official 579:53297373a894 562
mbed_official 579:53297373a894 563 #define SYSCTRL_DFLLMUL_MUL_Pos 0 /**< \brief (SYSCTRL_DFLLMUL) DFLL Multiply Factor */
mbed_official 579:53297373a894 564 #define SYSCTRL_DFLLMUL_MUL_Msk (0xFFFFul << SYSCTRL_DFLLMUL_MUL_Pos)
mbed_official 579:53297373a894 565 #define SYSCTRL_DFLLMUL_MUL(value) ((SYSCTRL_DFLLMUL_MUL_Msk & ((value) << SYSCTRL_DFLLMUL_MUL_Pos)))
mbed_official 579:53297373a894 566 #define SYSCTRL_DFLLMUL_FSTEP_Pos 16 /**< \brief (SYSCTRL_DFLLMUL) Fine Maximum Step */
mbed_official 579:53297373a894 567 #define SYSCTRL_DFLLMUL_FSTEP_Msk (0x3FFul << SYSCTRL_DFLLMUL_FSTEP_Pos)
mbed_official 579:53297373a894 568 #define SYSCTRL_DFLLMUL_FSTEP(value) ((SYSCTRL_DFLLMUL_FSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_FSTEP_Pos)))
mbed_official 579:53297373a894 569 #define SYSCTRL_DFLLMUL_CSTEP_Pos 26 /**< \brief (SYSCTRL_DFLLMUL) Coarse Maximum Step */
mbed_official 579:53297373a894 570 #define SYSCTRL_DFLLMUL_CSTEP_Msk (0x3Ful << SYSCTRL_DFLLMUL_CSTEP_Pos)
mbed_official 579:53297373a894 571 #define SYSCTRL_DFLLMUL_CSTEP(value) ((SYSCTRL_DFLLMUL_CSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_CSTEP_Pos)))
mbed_official 579:53297373a894 572 #define SYSCTRL_DFLLMUL_MASK 0xFFFFFFFFul /**< \brief (SYSCTRL_DFLLMUL) MASK Register */
mbed_official 579:53297373a894 573
mbed_official 579:53297373a894 574 /* -------- SYSCTRL_DFLLSYNC : (SYSCTRL Offset: 0x30) (R/W 8) DFLL48M Synchronization -------- */
mbed_official 579:53297373a894 575 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 576 typedef union {
mbed_official 579:53297373a894 577 struct {
mbed_official 579:53297373a894 578 uint8_t :7; /*!< bit: 0.. 6 Reserved */
mbed_official 579:53297373a894 579 uint8_t READREQ:1; /*!< bit: 7 Read Request */
mbed_official 579:53297373a894 580 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 581 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 582 } SYSCTRL_DFLLSYNC_Type;
mbed_official 579:53297373a894 583 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 584
mbed_official 579:53297373a894 585 #define SYSCTRL_DFLLSYNC_OFFSET 0x30 /**< \brief (SYSCTRL_DFLLSYNC offset) DFLL48M Synchronization */
mbed_official 579:53297373a894 586 #define SYSCTRL_DFLLSYNC_RESETVALUE 0x00ul /**< \brief (SYSCTRL_DFLLSYNC reset_value) DFLL48M Synchronization */
mbed_official 579:53297373a894 587
mbed_official 579:53297373a894 588 #define SYSCTRL_DFLLSYNC_READREQ_Pos 7 /**< \brief (SYSCTRL_DFLLSYNC) Read Request */
mbed_official 579:53297373a894 589 #define SYSCTRL_DFLLSYNC_READREQ (0x1ul << SYSCTRL_DFLLSYNC_READREQ_Pos)
mbed_official 579:53297373a894 590 #define SYSCTRL_DFLLSYNC_MASK 0x80ul /**< \brief (SYSCTRL_DFLLSYNC) MASK Register */
mbed_official 579:53297373a894 591
mbed_official 579:53297373a894 592 /* -------- SYSCTRL_BOD33 : (SYSCTRL Offset: 0x34) (R/W 32) 3.3V Brown-Out Detector (BOD33) Control -------- */
mbed_official 579:53297373a894 593 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 594 typedef union {
mbed_official 579:53297373a894 595 struct {
mbed_official 579:53297373a894 596 uint32_t :1; /*!< bit: 0 Reserved */
mbed_official 579:53297373a894 597 uint32_t ENABLE:1; /*!< bit: 1 Enable */
mbed_official 579:53297373a894 598 uint32_t HYST:1; /*!< bit: 2 Hysteresis */
mbed_official 579:53297373a894 599 uint32_t ACTION:2; /*!< bit: 3.. 4 BOD33 Action */
mbed_official 579:53297373a894 600 uint32_t :1; /*!< bit: 5 Reserved */
mbed_official 579:53297373a894 601 uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
mbed_official 579:53297373a894 602 uint32_t :1; /*!< bit: 7 Reserved */
mbed_official 579:53297373a894 603 uint32_t MODE:1; /*!< bit: 8 Operation Mode */
mbed_official 579:53297373a894 604 uint32_t CEN:1; /*!< bit: 9 Clock Enable */
mbed_official 579:53297373a894 605 uint32_t :2; /*!< bit: 10..11 Reserved */
mbed_official 579:53297373a894 606 uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */
mbed_official 579:53297373a894 607 uint32_t LEVEL:6; /*!< bit: 16..21 BOD33 Threshold Level */
mbed_official 579:53297373a894 608 uint32_t :10; /*!< bit: 22..31 Reserved */
mbed_official 579:53297373a894 609 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 610 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 611 } SYSCTRL_BOD33_Type;
mbed_official 579:53297373a894 612 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 613
mbed_official 579:53297373a894 614 #define SYSCTRL_BOD33_OFFSET 0x34 /**< \brief (SYSCTRL_BOD33 offset) 3.3V Brown-Out Detector (BOD33) Control */
mbed_official 579:53297373a894 615 #define SYSCTRL_BOD33_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_BOD33 reset_value) 3.3V Brown-Out Detector (BOD33) Control */
mbed_official 579:53297373a894 616
mbed_official 579:53297373a894 617 #define SYSCTRL_BOD33_ENABLE_Pos 1 /**< \brief (SYSCTRL_BOD33) Enable */
mbed_official 579:53297373a894 618 #define SYSCTRL_BOD33_ENABLE (0x1ul << SYSCTRL_BOD33_ENABLE_Pos)
mbed_official 579:53297373a894 619 #define SYSCTRL_BOD33_HYST_Pos 2 /**< \brief (SYSCTRL_BOD33) Hysteresis */
mbed_official 579:53297373a894 620 #define SYSCTRL_BOD33_HYST (0x1ul << SYSCTRL_BOD33_HYST_Pos)
mbed_official 579:53297373a894 621 #define SYSCTRL_BOD33_ACTION_Pos 3 /**< \brief (SYSCTRL_BOD33) BOD33 Action */
mbed_official 579:53297373a894 622 #define SYSCTRL_BOD33_ACTION_Msk (0x3ul << SYSCTRL_BOD33_ACTION_Pos)
mbed_official 579:53297373a894 623 #define SYSCTRL_BOD33_ACTION(value) ((SYSCTRL_BOD33_ACTION_Msk & ((value) << SYSCTRL_BOD33_ACTION_Pos)))
mbed_official 579:53297373a894 624 #define SYSCTRL_BOD33_ACTION_NONE_Val 0x0ul /**< \brief (SYSCTRL_BOD33) No action */
mbed_official 579:53297373a894 625 #define SYSCTRL_BOD33_ACTION_RESET_Val 0x1ul /**< \brief (SYSCTRL_BOD33) The BOD33 generates a reset */
mbed_official 579:53297373a894 626 #define SYSCTRL_BOD33_ACTION_INTERRUPT_Val 0x2ul /**< \brief (SYSCTRL_BOD33) The BOD33 generates an interrupt */
mbed_official 579:53297373a894 627 #define SYSCTRL_BOD33_ACTION_NONE (SYSCTRL_BOD33_ACTION_NONE_Val << SYSCTRL_BOD33_ACTION_Pos)
mbed_official 579:53297373a894 628 #define SYSCTRL_BOD33_ACTION_RESET (SYSCTRL_BOD33_ACTION_RESET_Val << SYSCTRL_BOD33_ACTION_Pos)
mbed_official 579:53297373a894 629 #define SYSCTRL_BOD33_ACTION_INTERRUPT (SYSCTRL_BOD33_ACTION_INTERRUPT_Val << SYSCTRL_BOD33_ACTION_Pos)
mbed_official 579:53297373a894 630 #define SYSCTRL_BOD33_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_BOD33) Run in Standby */
mbed_official 579:53297373a894 631 #define SYSCTRL_BOD33_RUNSTDBY (0x1ul << SYSCTRL_BOD33_RUNSTDBY_Pos)
mbed_official 579:53297373a894 632 #define SYSCTRL_BOD33_MODE_Pos 8 /**< \brief (SYSCTRL_BOD33) Operation Mode */
mbed_official 579:53297373a894 633 #define SYSCTRL_BOD33_MODE (0x1ul << SYSCTRL_BOD33_MODE_Pos)
mbed_official 579:53297373a894 634 #define SYSCTRL_BOD33_CEN_Pos 9 /**< \brief (SYSCTRL_BOD33) Clock Enable */
mbed_official 579:53297373a894 635 #define SYSCTRL_BOD33_CEN (0x1ul << SYSCTRL_BOD33_CEN_Pos)
mbed_official 579:53297373a894 636 #define SYSCTRL_BOD33_PSEL_Pos 12 /**< \brief (SYSCTRL_BOD33) Prescaler Select */
mbed_official 579:53297373a894 637 #define SYSCTRL_BOD33_PSEL_Msk (0xFul << SYSCTRL_BOD33_PSEL_Pos)
mbed_official 579:53297373a894 638 #define SYSCTRL_BOD33_PSEL(value) ((SYSCTRL_BOD33_PSEL_Msk & ((value) << SYSCTRL_BOD33_PSEL_Pos)))
mbed_official 579:53297373a894 639 #define SYSCTRL_BOD33_PSEL_DIV2_Val 0x0ul /**< \brief (SYSCTRL_BOD33) Divide clock by 2 */
mbed_official 579:53297373a894 640 #define SYSCTRL_BOD33_PSEL_DIV4_Val 0x1ul /**< \brief (SYSCTRL_BOD33) Divide clock by 4 */
mbed_official 579:53297373a894 641 #define SYSCTRL_BOD33_PSEL_DIV8_Val 0x2ul /**< \brief (SYSCTRL_BOD33) Divide clock by 8 */
mbed_official 579:53297373a894 642 #define SYSCTRL_BOD33_PSEL_DIV16_Val 0x3ul /**< \brief (SYSCTRL_BOD33) Divide clock by 16 */
mbed_official 579:53297373a894 643 #define SYSCTRL_BOD33_PSEL_DIV32_Val 0x4ul /**< \brief (SYSCTRL_BOD33) Divide clock by 32 */
mbed_official 579:53297373a894 644 #define SYSCTRL_BOD33_PSEL_DIV64_Val 0x5ul /**< \brief (SYSCTRL_BOD33) Divide clock by 64 */
mbed_official 579:53297373a894 645 #define SYSCTRL_BOD33_PSEL_DIV128_Val 0x6ul /**< \brief (SYSCTRL_BOD33) Divide clock by 128 */
mbed_official 579:53297373a894 646 #define SYSCTRL_BOD33_PSEL_DIV256_Val 0x7ul /**< \brief (SYSCTRL_BOD33) Divide clock by 256 */
mbed_official 579:53297373a894 647 #define SYSCTRL_BOD33_PSEL_DIV512_Val 0x8ul /**< \brief (SYSCTRL_BOD33) Divide clock by 512 */
mbed_official 579:53297373a894 648 #define SYSCTRL_BOD33_PSEL_DIV1K_Val 0x9ul /**< \brief (SYSCTRL_BOD33) Divide clock by 1024 */
mbed_official 579:53297373a894 649 #define SYSCTRL_BOD33_PSEL_DIV2K_Val 0xAul /**< \brief (SYSCTRL_BOD33) Divide clock by 2048 */
mbed_official 579:53297373a894 650 #define SYSCTRL_BOD33_PSEL_DIV4K_Val 0xBul /**< \brief (SYSCTRL_BOD33) Divide clock by 4096 */
mbed_official 579:53297373a894 651 #define SYSCTRL_BOD33_PSEL_DIV8K_Val 0xCul /**< \brief (SYSCTRL_BOD33) Divide clock by 8192 */
mbed_official 579:53297373a894 652 #define SYSCTRL_BOD33_PSEL_DIV16K_Val 0xDul /**< \brief (SYSCTRL_BOD33) Divide clock by 16384 */
mbed_official 579:53297373a894 653 #define SYSCTRL_BOD33_PSEL_DIV32K_Val 0xEul /**< \brief (SYSCTRL_BOD33) Divide clock by 32768 */
mbed_official 579:53297373a894 654 #define SYSCTRL_BOD33_PSEL_DIV64K_Val 0xFul /**< \brief (SYSCTRL_BOD33) Divide clock by 65536 */
mbed_official 579:53297373a894 655 #define SYSCTRL_BOD33_PSEL_DIV2 (SYSCTRL_BOD33_PSEL_DIV2_Val << SYSCTRL_BOD33_PSEL_Pos)
mbed_official 579:53297373a894 656 #define SYSCTRL_BOD33_PSEL_DIV4 (SYSCTRL_BOD33_PSEL_DIV4_Val << SYSCTRL_BOD33_PSEL_Pos)
mbed_official 579:53297373a894 657 #define SYSCTRL_BOD33_PSEL_DIV8 (SYSCTRL_BOD33_PSEL_DIV8_Val << SYSCTRL_BOD33_PSEL_Pos)
mbed_official 579:53297373a894 658 #define SYSCTRL_BOD33_PSEL_DIV16 (SYSCTRL_BOD33_PSEL_DIV16_Val << SYSCTRL_BOD33_PSEL_Pos)
mbed_official 579:53297373a894 659 #define SYSCTRL_BOD33_PSEL_DIV32 (SYSCTRL_BOD33_PSEL_DIV32_Val << SYSCTRL_BOD33_PSEL_Pos)
mbed_official 579:53297373a894 660 #define SYSCTRL_BOD33_PSEL_DIV64 (SYSCTRL_BOD33_PSEL_DIV64_Val << SYSCTRL_BOD33_PSEL_Pos)
mbed_official 579:53297373a894 661 #define SYSCTRL_BOD33_PSEL_DIV128 (SYSCTRL_BOD33_PSEL_DIV128_Val << SYSCTRL_BOD33_PSEL_Pos)
mbed_official 579:53297373a894 662 #define SYSCTRL_BOD33_PSEL_DIV256 (SYSCTRL_BOD33_PSEL_DIV256_Val << SYSCTRL_BOD33_PSEL_Pos)
mbed_official 579:53297373a894 663 #define SYSCTRL_BOD33_PSEL_DIV512 (SYSCTRL_BOD33_PSEL_DIV512_Val << SYSCTRL_BOD33_PSEL_Pos)
mbed_official 579:53297373a894 664 #define SYSCTRL_BOD33_PSEL_DIV1K (SYSCTRL_BOD33_PSEL_DIV1K_Val << SYSCTRL_BOD33_PSEL_Pos)
mbed_official 579:53297373a894 665 #define SYSCTRL_BOD33_PSEL_DIV2K (SYSCTRL_BOD33_PSEL_DIV2K_Val << SYSCTRL_BOD33_PSEL_Pos)
mbed_official 579:53297373a894 666 #define SYSCTRL_BOD33_PSEL_DIV4K (SYSCTRL_BOD33_PSEL_DIV4K_Val << SYSCTRL_BOD33_PSEL_Pos)
mbed_official 579:53297373a894 667 #define SYSCTRL_BOD33_PSEL_DIV8K (SYSCTRL_BOD33_PSEL_DIV8K_Val << SYSCTRL_BOD33_PSEL_Pos)
mbed_official 579:53297373a894 668 #define SYSCTRL_BOD33_PSEL_DIV16K (SYSCTRL_BOD33_PSEL_DIV16K_Val << SYSCTRL_BOD33_PSEL_Pos)
mbed_official 579:53297373a894 669 #define SYSCTRL_BOD33_PSEL_DIV32K (SYSCTRL_BOD33_PSEL_DIV32K_Val << SYSCTRL_BOD33_PSEL_Pos)
mbed_official 579:53297373a894 670 #define SYSCTRL_BOD33_PSEL_DIV64K (SYSCTRL_BOD33_PSEL_DIV64K_Val << SYSCTRL_BOD33_PSEL_Pos)
mbed_official 579:53297373a894 671 #define SYSCTRL_BOD33_LEVEL_Pos 16 /**< \brief (SYSCTRL_BOD33) BOD33 Threshold Level */
mbed_official 579:53297373a894 672 #define SYSCTRL_BOD33_LEVEL_Msk (0x3Ful << SYSCTRL_BOD33_LEVEL_Pos)
mbed_official 579:53297373a894 673 #define SYSCTRL_BOD33_LEVEL(value) ((SYSCTRL_BOD33_LEVEL_Msk & ((value) << SYSCTRL_BOD33_LEVEL_Pos)))
mbed_official 579:53297373a894 674 #define SYSCTRL_BOD33_MASK 0x003FF35Eul /**< \brief (SYSCTRL_BOD33) MASK Register */
mbed_official 579:53297373a894 675
mbed_official 579:53297373a894 676 /* -------- SYSCTRL_VREG : (SYSCTRL Offset: 0x3C) (R/W 16) Voltage Regulator System (VREG) Control -------- */
mbed_official 579:53297373a894 677 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 678 typedef union {
mbed_official 579:53297373a894 679 struct {
mbed_official 579:53297373a894 680 uint16_t :6; /*!< bit: 0.. 5 Reserved */
mbed_official 579:53297373a894 681 uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
mbed_official 579:53297373a894 682 uint16_t :6; /*!< bit: 7..12 Reserved */
mbed_official 579:53297373a894 683 uint16_t FORCELDO:1; /*!< bit: 13 Force LDO Voltage Regulator */
mbed_official 579:53297373a894 684 uint16_t :2; /*!< bit: 14..15 Reserved */
mbed_official 579:53297373a894 685 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 686 uint16_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 687 } SYSCTRL_VREG_Type;
mbed_official 579:53297373a894 688 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 689
mbed_official 579:53297373a894 690 #define SYSCTRL_VREG_OFFSET 0x3C /**< \brief (SYSCTRL_VREG offset) Voltage Regulator System (VREG) Control */
mbed_official 579:53297373a894 691 #define SYSCTRL_VREG_RESETVALUE 0x0000ul /**< \brief (SYSCTRL_VREG reset_value) Voltage Regulator System (VREG) Control */
mbed_official 579:53297373a894 692
mbed_official 579:53297373a894 693 #define SYSCTRL_VREG_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_VREG) Run in Standby */
mbed_official 579:53297373a894 694 #define SYSCTRL_VREG_RUNSTDBY (0x1ul << SYSCTRL_VREG_RUNSTDBY_Pos)
mbed_official 579:53297373a894 695 #define SYSCTRL_VREG_FORCELDO_Pos 13 /**< \brief (SYSCTRL_VREG) Force LDO Voltage Regulator */
mbed_official 579:53297373a894 696 #define SYSCTRL_VREG_FORCELDO (0x1ul << SYSCTRL_VREG_FORCELDO_Pos)
mbed_official 579:53297373a894 697 #define SYSCTRL_VREG_MASK 0x2040ul /**< \brief (SYSCTRL_VREG) MASK Register */
mbed_official 579:53297373a894 698
mbed_official 579:53297373a894 699 /* -------- SYSCTRL_VREF : (SYSCTRL Offset: 0x40) (R/W 32) Voltage References System (VREF) Control -------- */
mbed_official 579:53297373a894 700 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 701 typedef union {
mbed_official 579:53297373a894 702 struct {
mbed_official 579:53297373a894 703 uint32_t :1; /*!< bit: 0 Reserved */
mbed_official 579:53297373a894 704 uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Enable */
mbed_official 579:53297373a894 705 uint32_t BGOUTEN:1; /*!< bit: 2 Bandgap Output Enable */
mbed_official 579:53297373a894 706 uint32_t :13; /*!< bit: 3..15 Reserved */
mbed_official 579:53297373a894 707 uint32_t CALIB:11; /*!< bit: 16..26 Bandgap Voltage Generator Calibration */
mbed_official 579:53297373a894 708 uint32_t :5; /*!< bit: 27..31 Reserved */
mbed_official 579:53297373a894 709 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 710 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 711 } SYSCTRL_VREF_Type;
mbed_official 579:53297373a894 712 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 713
mbed_official 579:53297373a894 714 #define SYSCTRL_VREF_OFFSET 0x40 /**< \brief (SYSCTRL_VREF offset) Voltage References System (VREF) Control */
mbed_official 579:53297373a894 715 #define SYSCTRL_VREF_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_VREF reset_value) Voltage References System (VREF) Control */
mbed_official 579:53297373a894 716
mbed_official 579:53297373a894 717 #define SYSCTRL_VREF_TSEN_Pos 1 /**< \brief (SYSCTRL_VREF) Temperature Sensor Enable */
mbed_official 579:53297373a894 718 #define SYSCTRL_VREF_TSEN (0x1ul << SYSCTRL_VREF_TSEN_Pos)
mbed_official 579:53297373a894 719 #define SYSCTRL_VREF_BGOUTEN_Pos 2 /**< \brief (SYSCTRL_VREF) Bandgap Output Enable */
mbed_official 579:53297373a894 720 #define SYSCTRL_VREF_BGOUTEN (0x1ul << SYSCTRL_VREF_BGOUTEN_Pos)
mbed_official 579:53297373a894 721 #define SYSCTRL_VREF_CALIB_Pos 16 /**< \brief (SYSCTRL_VREF) Bandgap Voltage Generator Calibration */
mbed_official 579:53297373a894 722 #define SYSCTRL_VREF_CALIB_Msk (0x7FFul << SYSCTRL_VREF_CALIB_Pos)
mbed_official 579:53297373a894 723 #define SYSCTRL_VREF_CALIB(value) ((SYSCTRL_VREF_CALIB_Msk & ((value) << SYSCTRL_VREF_CALIB_Pos)))
mbed_official 579:53297373a894 724 #define SYSCTRL_VREF_MASK 0x07FF0006ul /**< \brief (SYSCTRL_VREF) MASK Register */
mbed_official 579:53297373a894 725
mbed_official 579:53297373a894 726 /* -------- SYSCTRL_DPLLCTRLA : (SYSCTRL Offset: 0x44) (R/W 8) DPLL Control A -------- */
mbed_official 579:53297373a894 727 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 728 typedef union {
mbed_official 579:53297373a894 729 struct {
mbed_official 579:53297373a894 730 uint8_t :1; /*!< bit: 0 Reserved */
mbed_official 579:53297373a894 731 uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable */
mbed_official 579:53297373a894 732 uint8_t :4; /*!< bit: 2.. 5 Reserved */
mbed_official 579:53297373a894 733 uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
mbed_official 579:53297373a894 734 uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Clock Activation */
mbed_official 579:53297373a894 735 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 736 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 737 } SYSCTRL_DPLLCTRLA_Type;
mbed_official 579:53297373a894 738 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 739
mbed_official 579:53297373a894 740 #define SYSCTRL_DPLLCTRLA_OFFSET 0x44 /**< \brief (SYSCTRL_DPLLCTRLA offset) DPLL Control A */
mbed_official 579:53297373a894 741 #define SYSCTRL_DPLLCTRLA_RESETVALUE 0x80ul /**< \brief (SYSCTRL_DPLLCTRLA reset_value) DPLL Control A */
mbed_official 579:53297373a894 742
mbed_official 579:53297373a894 743 #define SYSCTRL_DPLLCTRLA_ENABLE_Pos 1 /**< \brief (SYSCTRL_DPLLCTRLA) DPLL Enable */
mbed_official 579:53297373a894 744 #define SYSCTRL_DPLLCTRLA_ENABLE (0x1ul << SYSCTRL_DPLLCTRLA_ENABLE_Pos)
mbed_official 579:53297373a894 745 #define SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_DPLLCTRLA) Run in Standby */
mbed_official 579:53297373a894 746 #define SYSCTRL_DPLLCTRLA_RUNSTDBY (0x1ul << SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos)
mbed_official 579:53297373a894 747 #define SYSCTRL_DPLLCTRLA_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_DPLLCTRLA) On Demand Clock Activation */
mbed_official 579:53297373a894 748 #define SYSCTRL_DPLLCTRLA_ONDEMAND (0x1ul << SYSCTRL_DPLLCTRLA_ONDEMAND_Pos)
mbed_official 579:53297373a894 749 #define SYSCTRL_DPLLCTRLA_MASK 0xC2ul /**< \brief (SYSCTRL_DPLLCTRLA) MASK Register */
mbed_official 579:53297373a894 750
mbed_official 579:53297373a894 751 /* -------- SYSCTRL_DPLLRATIO : (SYSCTRL Offset: 0x48) (R/W 32) DPLL Ratio Control -------- */
mbed_official 579:53297373a894 752 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 753 typedef union {
mbed_official 579:53297373a894 754 struct {
mbed_official 579:53297373a894 755 uint32_t LDR:12; /*!< bit: 0..11 Loop Divider Ratio */
mbed_official 579:53297373a894 756 uint32_t :4; /*!< bit: 12..15 Reserved */
mbed_official 579:53297373a894 757 uint32_t LDRFRAC:4; /*!< bit: 16..19 Loop Divider Ratio Fractional Part */
mbed_official 579:53297373a894 758 uint32_t :12; /*!< bit: 20..31 Reserved */
mbed_official 579:53297373a894 759 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 760 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 761 } SYSCTRL_DPLLRATIO_Type;
mbed_official 579:53297373a894 762 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 763
mbed_official 579:53297373a894 764 #define SYSCTRL_DPLLRATIO_OFFSET 0x48 /**< \brief (SYSCTRL_DPLLRATIO offset) DPLL Ratio Control */
mbed_official 579:53297373a894 765 #define SYSCTRL_DPLLRATIO_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_DPLLRATIO reset_value) DPLL Ratio Control */
mbed_official 579:53297373a894 766
mbed_official 579:53297373a894 767 #define SYSCTRL_DPLLRATIO_LDR_Pos 0 /**< \brief (SYSCTRL_DPLLRATIO) Loop Divider Ratio */
mbed_official 579:53297373a894 768 #define SYSCTRL_DPLLRATIO_LDR_Msk (0xFFFul << SYSCTRL_DPLLRATIO_LDR_Pos)
mbed_official 579:53297373a894 769 #define SYSCTRL_DPLLRATIO_LDR(value) ((SYSCTRL_DPLLRATIO_LDR_Msk & ((value) << SYSCTRL_DPLLRATIO_LDR_Pos)))
mbed_official 579:53297373a894 770 #define SYSCTRL_DPLLRATIO_LDRFRAC_Pos 16 /**< \brief (SYSCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part */
mbed_official 579:53297373a894 771 #define SYSCTRL_DPLLRATIO_LDRFRAC_Msk (0xFul << SYSCTRL_DPLLRATIO_LDRFRAC_Pos)
mbed_official 579:53297373a894 772 #define SYSCTRL_DPLLRATIO_LDRFRAC(value) ((SYSCTRL_DPLLRATIO_LDRFRAC_Msk & ((value) << SYSCTRL_DPLLRATIO_LDRFRAC_Pos)))
mbed_official 579:53297373a894 773 #define SYSCTRL_DPLLRATIO_MASK 0x000F0FFFul /**< \brief (SYSCTRL_DPLLRATIO) MASK Register */
mbed_official 579:53297373a894 774
mbed_official 579:53297373a894 775 /* -------- SYSCTRL_DPLLCTRLB : (SYSCTRL Offset: 0x4C) (R/W 32) DPLL Control B -------- */
mbed_official 579:53297373a894 776 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 777 typedef union {
mbed_official 579:53297373a894 778 struct {
mbed_official 579:53297373a894 779 uint32_t FILTER:2; /*!< bit: 0.. 1 Proportional Integral Filter Selection */
mbed_official 579:53297373a894 780 uint32_t LPEN:1; /*!< bit: 2 Low-Power Enable */
mbed_official 579:53297373a894 781 uint32_t WUF:1; /*!< bit: 3 Wake Up Fast */
mbed_official 579:53297373a894 782 uint32_t REFCLK:2; /*!< bit: 4.. 5 Reference Clock Selection */
mbed_official 579:53297373a894 783 uint32_t :2; /*!< bit: 6.. 7 Reserved */
mbed_official 579:53297373a894 784 uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */
mbed_official 579:53297373a894 785 uint32_t :1; /*!< bit: 11 Reserved */
mbed_official 579:53297373a894 786 uint32_t LBYPASS:1; /*!< bit: 12 Lock Bypass */
mbed_official 579:53297373a894 787 uint32_t :3; /*!< bit: 13..15 Reserved */
mbed_official 579:53297373a894 788 uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */
mbed_official 579:53297373a894 789 uint32_t :5; /*!< bit: 27..31 Reserved */
mbed_official 579:53297373a894 790 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 791 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 792 } SYSCTRL_DPLLCTRLB_Type;
mbed_official 579:53297373a894 793 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 794
mbed_official 579:53297373a894 795 #define SYSCTRL_DPLLCTRLB_OFFSET 0x4C /**< \brief (SYSCTRL_DPLLCTRLB offset) DPLL Control B */
mbed_official 579:53297373a894 796 #define SYSCTRL_DPLLCTRLB_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_DPLLCTRLB reset_value) DPLL Control B */
mbed_official 579:53297373a894 797
mbed_official 579:53297373a894 798 #define SYSCTRL_DPLLCTRLB_FILTER_Pos 0 /**< \brief (SYSCTRL_DPLLCTRLB) Proportional Integral Filter Selection */
mbed_official 579:53297373a894 799 #define SYSCTRL_DPLLCTRLB_FILTER_Msk (0x3ul << SYSCTRL_DPLLCTRLB_FILTER_Pos)
mbed_official 579:53297373a894 800 #define SYSCTRL_DPLLCTRLB_FILTER(value) ((SYSCTRL_DPLLCTRLB_FILTER_Msk & ((value) << SYSCTRL_DPLLCTRLB_FILTER_Pos)))
mbed_official 579:53297373a894 801 #define SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val 0x0ul /**< \brief (SYSCTRL_DPLLCTRLB) Default filter mode */
mbed_official 579:53297373a894 802 #define SYSCTRL_DPLLCTRLB_FILTER_LBFILT_Val 0x1ul /**< \brief (SYSCTRL_DPLLCTRLB) Low bandwidth filter */
mbed_official 579:53297373a894 803 #define SYSCTRL_DPLLCTRLB_FILTER_HBFILT_Val 0x2ul /**< \brief (SYSCTRL_DPLLCTRLB) High bandwidth filter */
mbed_official 579:53297373a894 804 #define SYSCTRL_DPLLCTRLB_FILTER_HDFILT_Val 0x3ul /**< \brief (SYSCTRL_DPLLCTRLB) High damping filter */
mbed_official 579:53297373a894 805 #define SYSCTRL_DPLLCTRLB_FILTER_DEFAULT (SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
mbed_official 579:53297373a894 806 #define SYSCTRL_DPLLCTRLB_FILTER_LBFILT (SYSCTRL_DPLLCTRLB_FILTER_LBFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
mbed_official 579:53297373a894 807 #define SYSCTRL_DPLLCTRLB_FILTER_HBFILT (SYSCTRL_DPLLCTRLB_FILTER_HBFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
mbed_official 579:53297373a894 808 #define SYSCTRL_DPLLCTRLB_FILTER_HDFILT (SYSCTRL_DPLLCTRLB_FILTER_HDFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
mbed_official 579:53297373a894 809 #define SYSCTRL_DPLLCTRLB_LPEN_Pos 2 /**< \brief (SYSCTRL_DPLLCTRLB) Low-Power Enable */
mbed_official 579:53297373a894 810 #define SYSCTRL_DPLLCTRLB_LPEN (0x1ul << SYSCTRL_DPLLCTRLB_LPEN_Pos)
mbed_official 579:53297373a894 811 #define SYSCTRL_DPLLCTRLB_WUF_Pos 3 /**< \brief (SYSCTRL_DPLLCTRLB) Wake Up Fast */
mbed_official 579:53297373a894 812 #define SYSCTRL_DPLLCTRLB_WUF (0x1ul << SYSCTRL_DPLLCTRLB_WUF_Pos)
mbed_official 579:53297373a894 813 #define SYSCTRL_DPLLCTRLB_REFCLK_Pos 4 /**< \brief (SYSCTRL_DPLLCTRLB) Reference Clock Selection */
mbed_official 579:53297373a894 814 #define SYSCTRL_DPLLCTRLB_REFCLK_Msk (0x3ul << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
mbed_official 579:53297373a894 815 #define SYSCTRL_DPLLCTRLB_REFCLK(value) ((SYSCTRL_DPLLCTRLB_REFCLK_Msk & ((value) << SYSCTRL_DPLLCTRLB_REFCLK_Pos)))
mbed_official 579:53297373a894 816 #define SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val 0x0ul /**< \brief (SYSCTRL_DPLLCTRLB) CLK_DPLL_REF0 clock reference */
mbed_official 579:53297373a894 817 #define SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val 0x1ul /**< \brief (SYSCTRL_DPLLCTRLB) CLK_DPLL_REF1 clock reference */
mbed_official 579:53297373a894 818 #define SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val 0x2ul /**< \brief (SYSCTRL_DPLLCTRLB) GCLK_DPLL clock reference */
mbed_official 579:53297373a894 819 #define SYSCTRL_DPLLCTRLB_REFCLK_REF0 (SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
mbed_official 579:53297373a894 820 #define SYSCTRL_DPLLCTRLB_REFCLK_REF1 (SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
mbed_official 579:53297373a894 821 #define SYSCTRL_DPLLCTRLB_REFCLK_GCLK (SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
mbed_official 579:53297373a894 822 #define SYSCTRL_DPLLCTRLB_LTIME_Pos 8 /**< \brief (SYSCTRL_DPLLCTRLB) Lock Time */
mbed_official 579:53297373a894 823 #define SYSCTRL_DPLLCTRLB_LTIME_Msk (0x7ul << SYSCTRL_DPLLCTRLB_LTIME_Pos)
mbed_official 579:53297373a894 824 #define SYSCTRL_DPLLCTRLB_LTIME(value) ((SYSCTRL_DPLLCTRLB_LTIME_Msk & ((value) << SYSCTRL_DPLLCTRLB_LTIME_Pos)))
mbed_official 579:53297373a894 825 #define SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val 0x0ul /**< \brief (SYSCTRL_DPLLCTRLB) No time-out */
mbed_official 579:53297373a894 826 #define SYSCTRL_DPLLCTRLB_LTIME_8MS_Val 0x4ul /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 8 ms */
mbed_official 579:53297373a894 827 #define SYSCTRL_DPLLCTRLB_LTIME_9MS_Val 0x5ul /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 9 ms */
mbed_official 579:53297373a894 828 #define SYSCTRL_DPLLCTRLB_LTIME_10MS_Val 0x6ul /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 10 ms */
mbed_official 579:53297373a894 829 #define SYSCTRL_DPLLCTRLB_LTIME_11MS_Val 0x7ul /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 11 ms */
mbed_official 579:53297373a894 830 #define SYSCTRL_DPLLCTRLB_LTIME_DEFAULT (SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
mbed_official 579:53297373a894 831 #define SYSCTRL_DPLLCTRLB_LTIME_8MS (SYSCTRL_DPLLCTRLB_LTIME_8MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
mbed_official 579:53297373a894 832 #define SYSCTRL_DPLLCTRLB_LTIME_9MS (SYSCTRL_DPLLCTRLB_LTIME_9MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
mbed_official 579:53297373a894 833 #define SYSCTRL_DPLLCTRLB_LTIME_10MS (SYSCTRL_DPLLCTRLB_LTIME_10MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
mbed_official 579:53297373a894 834 #define SYSCTRL_DPLLCTRLB_LTIME_11MS (SYSCTRL_DPLLCTRLB_LTIME_11MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
mbed_official 579:53297373a894 835 #define SYSCTRL_DPLLCTRLB_LBYPASS_Pos 12 /**< \brief (SYSCTRL_DPLLCTRLB) Lock Bypass */
mbed_official 579:53297373a894 836 #define SYSCTRL_DPLLCTRLB_LBYPASS (0x1ul << SYSCTRL_DPLLCTRLB_LBYPASS_Pos)
mbed_official 579:53297373a894 837 #define SYSCTRL_DPLLCTRLB_DIV_Pos 16 /**< \brief (SYSCTRL_DPLLCTRLB) Clock Divider */
mbed_official 579:53297373a894 838 #define SYSCTRL_DPLLCTRLB_DIV_Msk (0x7FFul << SYSCTRL_DPLLCTRLB_DIV_Pos)
mbed_official 579:53297373a894 839 #define SYSCTRL_DPLLCTRLB_DIV(value) ((SYSCTRL_DPLLCTRLB_DIV_Msk & ((value) << SYSCTRL_DPLLCTRLB_DIV_Pos)))
mbed_official 579:53297373a894 840 #define SYSCTRL_DPLLCTRLB_MASK 0x07FF173Ful /**< \brief (SYSCTRL_DPLLCTRLB) MASK Register */
mbed_official 579:53297373a894 841
mbed_official 579:53297373a894 842 /* -------- SYSCTRL_DPLLSTATUS : (SYSCTRL Offset: 0x50) (R/ 8) DPLL Status -------- */
mbed_official 579:53297373a894 843 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 844 typedef union {
mbed_official 579:53297373a894 845 struct {
mbed_official 579:53297373a894 846 uint8_t LOCK:1; /*!< bit: 0 DPLL Lock Status */
mbed_official 579:53297373a894 847 uint8_t CLKRDY:1; /*!< bit: 1 Output Clock Ready */
mbed_official 579:53297373a894 848 uint8_t ENABLE:1; /*!< bit: 2 DPLL Enable */
mbed_official 579:53297373a894 849 uint8_t DIV:1; /*!< bit: 3 Divider Enable */
mbed_official 579:53297373a894 850 uint8_t :4; /*!< bit: 4.. 7 Reserved */
mbed_official 579:53297373a894 851 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 852 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 853 } SYSCTRL_DPLLSTATUS_Type;
mbed_official 579:53297373a894 854 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 855
mbed_official 579:53297373a894 856 #define SYSCTRL_DPLLSTATUS_OFFSET 0x50 /**< \brief (SYSCTRL_DPLLSTATUS offset) DPLL Status */
mbed_official 579:53297373a894 857 #define SYSCTRL_DPLLSTATUS_RESETVALUE 0x00ul /**< \brief (SYSCTRL_DPLLSTATUS reset_value) DPLL Status */
mbed_official 579:53297373a894 858
mbed_official 579:53297373a894 859 #define SYSCTRL_DPLLSTATUS_LOCK_Pos 0 /**< \brief (SYSCTRL_DPLLSTATUS) DPLL Lock Status */
mbed_official 579:53297373a894 860 #define SYSCTRL_DPLLSTATUS_LOCK (0x1ul << SYSCTRL_DPLLSTATUS_LOCK_Pos)
mbed_official 579:53297373a894 861 #define SYSCTRL_DPLLSTATUS_CLKRDY_Pos 1 /**< \brief (SYSCTRL_DPLLSTATUS) Output Clock Ready */
mbed_official 579:53297373a894 862 #define SYSCTRL_DPLLSTATUS_CLKRDY (0x1ul << SYSCTRL_DPLLSTATUS_CLKRDY_Pos)
mbed_official 579:53297373a894 863 #define SYSCTRL_DPLLSTATUS_ENABLE_Pos 2 /**< \brief (SYSCTRL_DPLLSTATUS) DPLL Enable */
mbed_official 579:53297373a894 864 #define SYSCTRL_DPLLSTATUS_ENABLE (0x1ul << SYSCTRL_DPLLSTATUS_ENABLE_Pos)
mbed_official 579:53297373a894 865 #define SYSCTRL_DPLLSTATUS_DIV_Pos 3 /**< \brief (SYSCTRL_DPLLSTATUS) Divider Enable */
mbed_official 579:53297373a894 866 #define SYSCTRL_DPLLSTATUS_DIV (0x1ul << SYSCTRL_DPLLSTATUS_DIV_Pos)
mbed_official 579:53297373a894 867 #define SYSCTRL_DPLLSTATUS_MASK 0x0Ful /**< \brief (SYSCTRL_DPLLSTATUS) MASK Register */
mbed_official 579:53297373a894 868
mbed_official 579:53297373a894 869 /** \brief SYSCTRL hardware registers */
mbed_official 579:53297373a894 870 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 871 typedef struct {
mbed_official 579:53297373a894 872 __IO SYSCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
mbed_official 579:53297373a894 873 __IO SYSCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
mbed_official 579:53297373a894 874 __IO SYSCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 875 __I SYSCTRL_PCLKSR_Type PCLKSR; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */
mbed_official 579:53297373a894 876 __IO SYSCTRL_XOSC_Type XOSC; /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */
mbed_official 579:53297373a894 877 RoReg8 Reserved1[0x2];
mbed_official 579:53297373a894 878 __IO SYSCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */
mbed_official 579:53297373a894 879 RoReg8 Reserved2[0x2];
mbed_official 579:53297373a894 880 __IO SYSCTRL_OSC32K_Type OSC32K; /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */
mbed_official 579:53297373a894 881 __IO SYSCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
mbed_official 579:53297373a894 882 RoReg8 Reserved3[0x3];
mbed_official 579:53297373a894 883 __IO SYSCTRL_OSC8M_Type OSC8M; /**< \brief Offset: 0x20 (R/W 32) 8MHz Internal Oscillator (OSC8M) Control */
mbed_official 579:53297373a894 884 __IO SYSCTRL_DFLLCTRL_Type DFLLCTRL; /**< \brief Offset: 0x24 (R/W 16) DFLL48M Control */
mbed_official 579:53297373a894 885 RoReg8 Reserved4[0x2];
mbed_official 579:53297373a894 886 __IO SYSCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x28 (R/W 32) DFLL48M Value */
mbed_official 579:53297373a894 887 __IO SYSCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x2C (R/W 32) DFLL48M Multiplier */
mbed_official 579:53297373a894 888 __IO SYSCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x30 (R/W 8) DFLL48M Synchronization */
mbed_official 579:53297373a894 889 RoReg8 Reserved5[0x3];
mbed_official 579:53297373a894 890 __IO SYSCTRL_BOD33_Type BOD33; /**< \brief Offset: 0x34 (R/W 32) 3.3V Brown-Out Detector (BOD33) Control */
mbed_official 579:53297373a894 891 RoReg8 Reserved6[0x4];
mbed_official 579:53297373a894 892 __IO SYSCTRL_VREG_Type VREG; /**< \brief Offset: 0x3C (R/W 16) Voltage Regulator System (VREG) Control */
mbed_official 579:53297373a894 893 RoReg8 Reserved7[0x2];
mbed_official 579:53297373a894 894 __IO SYSCTRL_VREF_Type VREF; /**< \brief Offset: 0x40 (R/W 32) Voltage References System (VREF) Control */
mbed_official 579:53297373a894 895 __IO SYSCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x44 (R/W 8) DPLL Control A */
mbed_official 579:53297373a894 896 RoReg8 Reserved8[0x3];
mbed_official 579:53297373a894 897 __IO SYSCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x48 (R/W 32) DPLL Ratio Control */
mbed_official 579:53297373a894 898 __IO SYSCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x4C (R/W 32) DPLL Control B */
mbed_official 579:53297373a894 899 __I SYSCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x50 (R/ 8) DPLL Status */
mbed_official 579:53297373a894 900 } Sysctrl;
mbed_official 579:53297373a894 901 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 902
mbed_official 579:53297373a894 903 /*@}*/
mbed_official 579:53297373a894 904
mbed_official 579:53297373a894 905 #endif /* _SAMD21_SYSCTRL_COMPONENT_ */