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targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_sercom.h@592:a274ee790e56, 2015-07-17 (annotated)
- Committer:
- mbed_official
- Date:
- Fri Jul 17 09:15:10 2015 +0100
- Revision:
- 592:a274ee790e56
- Parent:
- 579:53297373a894
Synchronized with git revision e7144f83a8d75df80c4877936b6ffe552b0be9e6
Full URL: https://github.com/mbedmicro/mbed/commit/e7144f83a8d75df80c4877936b6ffe552b0be9e6/
More API implementation for SAMR21
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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mbed_official | 579:53297373a894 | 1 | #ifndef _SAMD21_SERCOM_COMPONENT_ |
mbed_official | 579:53297373a894 | 2 | #define _SAMD21_SERCOM_COMPONENT_ |
mbed_official | 579:53297373a894 | 3 | |
mbed_official | 579:53297373a894 | 4 | /* ========================================================================== */ |
mbed_official | 579:53297373a894 | 5 | /** SOFTWARE API DEFINITION FOR SERCOM */ |
mbed_official | 579:53297373a894 | 6 | /* ========================================================================== */ |
mbed_official | 579:53297373a894 | 7 | /** \addtogroup SAMD21_SERCOM Serial Communication Interface */ |
mbed_official | 579:53297373a894 | 8 | /*@{*/ |
mbed_official | 579:53297373a894 | 9 | |
mbed_official | 579:53297373a894 | 10 | #define SERCOM_U2201 |
mbed_official | 579:53297373a894 | 11 | #define REV_SERCOM 0x200 |
mbed_official | 579:53297373a894 | 12 | |
mbed_official | 579:53297373a894 | 13 | /* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM I2CM Control A -------- */ |
mbed_official | 579:53297373a894 | 14 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 15 | typedef union { |
mbed_official | 579:53297373a894 | 16 | struct { |
mbed_official | 579:53297373a894 | 17 | uint32_t SWRST:1; /*!< bit: 0 Software Reset */ |
mbed_official | 579:53297373a894 | 18 | uint32_t ENABLE:1; /*!< bit: 1 Enable */ |
mbed_official | 579:53297373a894 | 19 | uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ |
mbed_official | 579:53297373a894 | 20 | uint32_t :2; /*!< bit: 5.. 6 Reserved */ |
mbed_official | 579:53297373a894 | 21 | uint32_t RUNSTDBY:1; /*!< bit: 7 Run in Standby */ |
mbed_official | 579:53297373a894 | 22 | uint32_t :8; /*!< bit: 8..15 Reserved */ |
mbed_official | 579:53297373a894 | 23 | uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */ |
mbed_official | 579:53297373a894 | 24 | uint32_t :3; /*!< bit: 17..19 Reserved */ |
mbed_official | 579:53297373a894 | 25 | uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */ |
mbed_official | 579:53297373a894 | 26 | uint32_t MEXTTOEN:1; /*!< bit: 22 Master SCL Low Extend Timeout */ |
mbed_official | 579:53297373a894 | 27 | uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */ |
mbed_official | 579:53297373a894 | 28 | uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */ |
mbed_official | 579:53297373a894 | 29 | uint32_t :1; /*!< bit: 26 Reserved */ |
mbed_official | 579:53297373a894 | 30 | uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */ |
mbed_official | 579:53297373a894 | 31 | uint32_t INACTOUT:2; /*!< bit: 28..29 Inactive Time-Out */ |
mbed_official | 579:53297373a894 | 32 | uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */ |
mbed_official | 579:53297373a894 | 33 | uint32_t :1; /*!< bit: 31 Reserved */ |
mbed_official | 579:53297373a894 | 34 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 35 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 36 | } SERCOM_I2CM_CTRLA_Type; |
mbed_official | 579:53297373a894 | 37 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 38 | |
mbed_official | 579:53297373a894 | 39 | #define SERCOM_I2CM_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CM_CTRLA offset) I2CM Control A */ |
mbed_official | 579:53297373a894 | 40 | #define SERCOM_I2CM_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_CTRLA reset_value) I2CM Control A */ |
mbed_official | 579:53297373a894 | 41 | |
mbed_official | 579:53297373a894 | 42 | #define SERCOM_I2CM_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_CTRLA) Software Reset */ |
mbed_official | 579:53297373a894 | 43 | #define SERCOM_I2CM_CTRLA_SWRST (0x1ul << SERCOM_I2CM_CTRLA_SWRST_Pos) |
mbed_official | 579:53297373a894 | 44 | #define SERCOM_I2CM_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_CTRLA) Enable */ |
mbed_official | 579:53297373a894 | 45 | #define SERCOM_I2CM_CTRLA_ENABLE (0x1ul << SERCOM_I2CM_CTRLA_ENABLE_Pos) |
mbed_official | 579:53297373a894 | 46 | #define SERCOM_I2CM_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CM_CTRLA) Operating Mode */ |
mbed_official | 579:53297373a894 | 47 | #define SERCOM_I2CM_CTRLA_MODE_Msk (0x7ul << SERCOM_I2CM_CTRLA_MODE_Pos) |
mbed_official | 579:53297373a894 | 48 | #define SERCOM_I2CM_CTRLA_MODE(value) ((SERCOM_I2CM_CTRLA_MODE_Msk & ((value) << SERCOM_I2CM_CTRLA_MODE_Pos))) |
mbed_official | 579:53297373a894 | 49 | #define SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_I2CM_CTRLA) USART mode with external clock */ |
mbed_official | 579:53297373a894 | 50 | #define SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_I2CM_CTRLA) USART mode with internal clock */ |
mbed_official | 579:53297373a894 | 51 | #define SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with external clock */ |
mbed_official | 579:53297373a894 | 52 | #define SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with internal clock */ |
mbed_official | 579:53297373a894 | 53 | #define SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with external clock */ |
mbed_official | 579:53297373a894 | 54 | #define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with internal clock */ |
mbed_official | 579:53297373a894 | 55 | #define SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK (SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos) |
mbed_official | 579:53297373a894 | 56 | #define SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK (SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos) |
mbed_official | 579:53297373a894 | 57 | #define SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE (SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos) |
mbed_official | 579:53297373a894 | 58 | #define SERCOM_I2CM_CTRLA_MODE_SPI_MASTER (SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos) |
mbed_official | 579:53297373a894 | 59 | #define SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE (SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos) |
mbed_official | 579:53297373a894 | 60 | #define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos) |
mbed_official | 579:53297373a894 | 61 | #define SERCOM_I2CM_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CM_CTRLA) Run in Standby */ |
mbed_official | 579:53297373a894 | 62 | #define SERCOM_I2CM_CTRLA_RUNSTDBY (0x1ul << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos) |
mbed_official | 579:53297373a894 | 63 | #define SERCOM_I2CM_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CM_CTRLA) Pin Usage */ |
mbed_official | 579:53297373a894 | 64 | #define SERCOM_I2CM_CTRLA_PINOUT (0x1ul << SERCOM_I2CM_CTRLA_PINOUT_Pos) |
mbed_official | 579:53297373a894 | 65 | #define SERCOM_I2CM_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CM_CTRLA) SDA Hold Time */ |
mbed_official | 579:53297373a894 | 66 | #define SERCOM_I2CM_CTRLA_SDAHOLD_Msk (0x3ul << SERCOM_I2CM_CTRLA_SDAHOLD_Pos) |
mbed_official | 579:53297373a894 | 67 | #define SERCOM_I2CM_CTRLA_SDAHOLD(value) ((SERCOM_I2CM_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos))) |
mbed_official | 579:53297373a894 | 68 | #define SERCOM_I2CM_CTRLA_MEXTTOEN_Pos 22 /**< \brief (SERCOM_I2CM_CTRLA) Master SCL Low Extend Timeout */ |
mbed_official | 579:53297373a894 | 69 | #define SERCOM_I2CM_CTRLA_MEXTTOEN (0x1ul << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos) |
mbed_official | 579:53297373a894 | 70 | #define SERCOM_I2CM_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CM_CTRLA) Slave SCL Low Extend Timeout */ |
mbed_official | 579:53297373a894 | 71 | #define SERCOM_I2CM_CTRLA_SEXTTOEN (0x1ul << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos) |
mbed_official | 579:53297373a894 | 72 | #define SERCOM_I2CM_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CM_CTRLA) Transfer Speed */ |
mbed_official | 579:53297373a894 | 73 | #define SERCOM_I2CM_CTRLA_SPEED_Msk (0x3ul << SERCOM_I2CM_CTRLA_SPEED_Pos) |
mbed_official | 579:53297373a894 | 74 | #define SERCOM_I2CM_CTRLA_SPEED(value) ((SERCOM_I2CM_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CM_CTRLA_SPEED_Pos))) |
mbed_official | 579:53297373a894 | 75 | #define SERCOM_I2CM_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CM_CTRLA) SCL Clock Stretch Mode */ |
mbed_official | 579:53297373a894 | 76 | #define SERCOM_I2CM_CTRLA_SCLSM (0x1ul << SERCOM_I2CM_CTRLA_SCLSM_Pos) |
mbed_official | 579:53297373a894 | 77 | #define SERCOM_I2CM_CTRLA_INACTOUT_Pos 28 /**< \brief (SERCOM_I2CM_CTRLA) Inactive Time-Out */ |
mbed_official | 579:53297373a894 | 78 | #define SERCOM_I2CM_CTRLA_INACTOUT_Msk (0x3ul << SERCOM_I2CM_CTRLA_INACTOUT_Pos) |
mbed_official | 579:53297373a894 | 79 | #define SERCOM_I2CM_CTRLA_INACTOUT(value) ((SERCOM_I2CM_CTRLA_INACTOUT_Msk & ((value) << SERCOM_I2CM_CTRLA_INACTOUT_Pos))) |
mbed_official | 579:53297373a894 | 80 | #define SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CM_CTRLA) SCL Low Timeout Enable */ |
mbed_official | 579:53297373a894 | 81 | #define SERCOM_I2CM_CTRLA_LOWTOUTEN (0x1ul << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos) |
mbed_official | 579:53297373a894 | 82 | #define SERCOM_I2CM_CTRLA_MASK 0x7BF1009Ful /**< \brief (SERCOM_I2CM_CTRLA) MASK Register */ |
mbed_official | 579:53297373a894 | 83 | |
mbed_official | 579:53297373a894 | 84 | /* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS I2CS Control A -------- */ |
mbed_official | 579:53297373a894 | 85 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 86 | typedef union { |
mbed_official | 579:53297373a894 | 87 | struct { |
mbed_official | 579:53297373a894 | 88 | uint32_t SWRST:1; /*!< bit: 0 Software Reset */ |
mbed_official | 579:53297373a894 | 89 | uint32_t ENABLE:1; /*!< bit: 1 Enable */ |
mbed_official | 579:53297373a894 | 90 | uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ |
mbed_official | 579:53297373a894 | 91 | uint32_t :2; /*!< bit: 5.. 6 Reserved */ |
mbed_official | 579:53297373a894 | 92 | uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ |
mbed_official | 579:53297373a894 | 93 | uint32_t :8; /*!< bit: 8..15 Reserved */ |
mbed_official | 579:53297373a894 | 94 | uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */ |
mbed_official | 579:53297373a894 | 95 | uint32_t :3; /*!< bit: 17..19 Reserved */ |
mbed_official | 579:53297373a894 | 96 | uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */ |
mbed_official | 579:53297373a894 | 97 | uint32_t :1; /*!< bit: 22 Reserved */ |
mbed_official | 579:53297373a894 | 98 | uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */ |
mbed_official | 579:53297373a894 | 99 | uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */ |
mbed_official | 579:53297373a894 | 100 | uint32_t :1; /*!< bit: 26 Reserved */ |
mbed_official | 579:53297373a894 | 101 | uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */ |
mbed_official | 579:53297373a894 | 102 | uint32_t :2; /*!< bit: 28..29 Reserved */ |
mbed_official | 579:53297373a894 | 103 | uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */ |
mbed_official | 579:53297373a894 | 104 | uint32_t :1; /*!< bit: 31 Reserved */ |
mbed_official | 579:53297373a894 | 105 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 106 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 107 | } SERCOM_I2CS_CTRLA_Type; |
mbed_official | 579:53297373a894 | 108 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 109 | |
mbed_official | 579:53297373a894 | 110 | #define SERCOM_I2CS_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CS_CTRLA offset) I2CS Control A */ |
mbed_official | 579:53297373a894 | 111 | #define SERCOM_I2CS_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_CTRLA reset_value) I2CS Control A */ |
mbed_official | 579:53297373a894 | 112 | |
mbed_official | 579:53297373a894 | 113 | #define SERCOM_I2CS_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_CTRLA) Software Reset */ |
mbed_official | 579:53297373a894 | 114 | #define SERCOM_I2CS_CTRLA_SWRST (0x1ul << SERCOM_I2CS_CTRLA_SWRST_Pos) |
mbed_official | 579:53297373a894 | 115 | #define SERCOM_I2CS_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_CTRLA) Enable */ |
mbed_official | 579:53297373a894 | 116 | #define SERCOM_I2CS_CTRLA_ENABLE (0x1ul << SERCOM_I2CS_CTRLA_ENABLE_Pos) |
mbed_official | 579:53297373a894 | 117 | #define SERCOM_I2CS_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CS_CTRLA) Operating Mode */ |
mbed_official | 579:53297373a894 | 118 | #define SERCOM_I2CS_CTRLA_MODE_Msk (0x7ul << SERCOM_I2CS_CTRLA_MODE_Pos) |
mbed_official | 579:53297373a894 | 119 | #define SERCOM_I2CS_CTRLA_MODE(value) ((SERCOM_I2CS_CTRLA_MODE_Msk & ((value) << SERCOM_I2CS_CTRLA_MODE_Pos))) |
mbed_official | 579:53297373a894 | 120 | #define SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_I2CS_CTRLA) USART mode with external clock */ |
mbed_official | 579:53297373a894 | 121 | #define SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_I2CS_CTRLA) USART mode with internal clock */ |
mbed_official | 579:53297373a894 | 122 | #define SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with external clock */ |
mbed_official | 579:53297373a894 | 123 | #define SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with internal clock */ |
mbed_official | 579:53297373a894 | 124 | #define SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with external clock */ |
mbed_official | 579:53297373a894 | 125 | #define SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with internal clock */ |
mbed_official | 579:53297373a894 | 126 | #define SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK (SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos) |
mbed_official | 579:53297373a894 | 127 | #define SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK (SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos) |
mbed_official | 579:53297373a894 | 128 | #define SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE (SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos) |
mbed_official | 579:53297373a894 | 129 | #define SERCOM_I2CS_CTRLA_MODE_SPI_MASTER (SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos) |
mbed_official | 579:53297373a894 | 130 | #define SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE (SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos) |
mbed_official | 579:53297373a894 | 131 | #define SERCOM_I2CS_CTRLA_MODE_I2C_MASTER (SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos) |
mbed_official | 579:53297373a894 | 132 | #define SERCOM_I2CS_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CS_CTRLA) Run during Standby */ |
mbed_official | 579:53297373a894 | 133 | #define SERCOM_I2CS_CTRLA_RUNSTDBY (0x1ul << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos) |
mbed_official | 579:53297373a894 | 134 | #define SERCOM_I2CS_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CS_CTRLA) Pin Usage */ |
mbed_official | 579:53297373a894 | 135 | #define SERCOM_I2CS_CTRLA_PINOUT (0x1ul << SERCOM_I2CS_CTRLA_PINOUT_Pos) |
mbed_official | 579:53297373a894 | 136 | #define SERCOM_I2CS_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CS_CTRLA) SDA Hold Time */ |
mbed_official | 579:53297373a894 | 137 | #define SERCOM_I2CS_CTRLA_SDAHOLD_Msk (0x3ul << SERCOM_I2CS_CTRLA_SDAHOLD_Pos) |
mbed_official | 579:53297373a894 | 138 | #define SERCOM_I2CS_CTRLA_SDAHOLD(value) ((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))) |
mbed_official | 579:53297373a894 | 139 | #define SERCOM_I2CS_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CS_CTRLA) Slave SCL Low Extend Timeout */ |
mbed_official | 579:53297373a894 | 140 | #define SERCOM_I2CS_CTRLA_SEXTTOEN (0x1ul << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos) |
mbed_official | 579:53297373a894 | 141 | #define SERCOM_I2CS_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CS_CTRLA) Transfer Speed */ |
mbed_official | 579:53297373a894 | 142 | #define SERCOM_I2CS_CTRLA_SPEED_Msk (0x3ul << SERCOM_I2CS_CTRLA_SPEED_Pos) |
mbed_official | 579:53297373a894 | 143 | #define SERCOM_I2CS_CTRLA_SPEED(value) ((SERCOM_I2CS_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CS_CTRLA_SPEED_Pos))) |
mbed_official | 579:53297373a894 | 144 | #define SERCOM_I2CS_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CS_CTRLA) SCL Clock Stretch Mode */ |
mbed_official | 579:53297373a894 | 145 | #define SERCOM_I2CS_CTRLA_SCLSM (0x1ul << SERCOM_I2CS_CTRLA_SCLSM_Pos) |
mbed_official | 579:53297373a894 | 146 | #define SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CS_CTRLA) SCL Low Timeout Enable */ |
mbed_official | 579:53297373a894 | 147 | #define SERCOM_I2CS_CTRLA_LOWTOUTEN (0x1ul << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos) |
mbed_official | 579:53297373a894 | 148 | #define SERCOM_I2CS_CTRLA_MASK 0x4BB1009Ful /**< \brief (SERCOM_I2CS_CTRLA) MASK Register */ |
mbed_official | 579:53297373a894 | 149 | |
mbed_official | 579:53297373a894 | 150 | /* -------- SERCOM_SPI_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPI SPI Control A -------- */ |
mbed_official | 579:53297373a894 | 151 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 152 | typedef union { |
mbed_official | 579:53297373a894 | 153 | struct { |
mbed_official | 579:53297373a894 | 154 | uint32_t SWRST:1; /*!< bit: 0 Software Reset */ |
mbed_official | 579:53297373a894 | 155 | uint32_t ENABLE:1; /*!< bit: 1 Enable */ |
mbed_official | 579:53297373a894 | 156 | uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ |
mbed_official | 579:53297373a894 | 157 | uint32_t :2; /*!< bit: 5.. 6 Reserved */ |
mbed_official | 579:53297373a894 | 158 | uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ |
mbed_official | 579:53297373a894 | 159 | uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */ |
mbed_official | 579:53297373a894 | 160 | uint32_t :7; /*!< bit: 9..15 Reserved */ |
mbed_official | 579:53297373a894 | 161 | uint32_t DOPO:2; /*!< bit: 16..17 Data Out Pinout */ |
mbed_official | 579:53297373a894 | 162 | uint32_t :2; /*!< bit: 18..19 Reserved */ |
mbed_official | 579:53297373a894 | 163 | uint32_t DIPO:2; /*!< bit: 20..21 Data In Pinout */ |
mbed_official | 579:53297373a894 | 164 | uint32_t :2; /*!< bit: 22..23 Reserved */ |
mbed_official | 579:53297373a894 | 165 | uint32_t FORM:4; /*!< bit: 24..27 Frame Format */ |
mbed_official | 579:53297373a894 | 166 | uint32_t CPHA:1; /*!< bit: 28 Clock Phase */ |
mbed_official | 579:53297373a894 | 167 | uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */ |
mbed_official | 579:53297373a894 | 168 | uint32_t DORD:1; /*!< bit: 30 Data Order */ |
mbed_official | 579:53297373a894 | 169 | uint32_t :1; /*!< bit: 31 Reserved */ |
mbed_official | 579:53297373a894 | 170 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 171 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 172 | } SERCOM_SPI_CTRLA_Type; |
mbed_official | 579:53297373a894 | 173 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 174 | |
mbed_official | 579:53297373a894 | 175 | #define SERCOM_SPI_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_SPI_CTRLA offset) SPI Control A */ |
mbed_official | 579:53297373a894 | 176 | #define SERCOM_SPI_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_CTRLA reset_value) SPI Control A */ |
mbed_official | 579:53297373a894 | 177 | |
mbed_official | 579:53297373a894 | 178 | #define SERCOM_SPI_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_SPI_CTRLA) Software Reset */ |
mbed_official | 579:53297373a894 | 179 | #define SERCOM_SPI_CTRLA_SWRST (0x1ul << SERCOM_SPI_CTRLA_SWRST_Pos) |
mbed_official | 579:53297373a894 | 180 | #define SERCOM_SPI_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_CTRLA) Enable */ |
mbed_official | 579:53297373a894 | 181 | #define SERCOM_SPI_CTRLA_ENABLE (0x1ul << SERCOM_SPI_CTRLA_ENABLE_Pos) |
mbed_official | 579:53297373a894 | 182 | #define SERCOM_SPI_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_SPI_CTRLA) Operating Mode */ |
mbed_official | 579:53297373a894 | 183 | #define SERCOM_SPI_CTRLA_MODE_Msk (0x7ul << SERCOM_SPI_CTRLA_MODE_Pos) |
mbed_official | 579:53297373a894 | 184 | #define SERCOM_SPI_CTRLA_MODE(value) ((SERCOM_SPI_CTRLA_MODE_Msk & ((value) << SERCOM_SPI_CTRLA_MODE_Pos))) |
mbed_official | 579:53297373a894 | 185 | #define SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_SPI_CTRLA) USART mode with external clock */ |
mbed_official | 579:53297373a894 | 186 | #define SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_SPI_CTRLA) USART mode with internal clock */ |
mbed_official | 579:53297373a894 | 187 | #define SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_SPI_CTRLA) SPI mode with external clock */ |
mbed_official | 579:53297373a894 | 188 | #define SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_SPI_CTRLA) SPI mode with internal clock */ |
mbed_official | 579:53297373a894 | 189 | #define SERCOM_SPI_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_SPI_CTRLA) I2C mode with external clock */ |
mbed_official | 579:53297373a894 | 190 | #define SERCOM_SPI_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_SPI_CTRLA) I2C mode with internal clock */ |
mbed_official | 579:53297373a894 | 191 | #define SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK (SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_SPI_CTRLA_MODE_Pos) |
mbed_official | 579:53297373a894 | 192 | #define SERCOM_SPI_CTRLA_MODE_USART_INT_CLK (SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_SPI_CTRLA_MODE_Pos) |
mbed_official | 579:53297373a894 | 193 | #define SERCOM_SPI_CTRLA_MODE_SPI_SLAVE (SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_SPI_CTRLA_MODE_Pos) |
mbed_official | 579:53297373a894 | 194 | #define SERCOM_SPI_CTRLA_MODE_SPI_MASTER (SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val << SERCOM_SPI_CTRLA_MODE_Pos) |
mbed_official | 579:53297373a894 | 195 | #define SERCOM_SPI_CTRLA_MODE_I2C_SLAVE (SERCOM_SPI_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_SPI_CTRLA_MODE_Pos) |
mbed_official | 579:53297373a894 | 196 | #define SERCOM_SPI_CTRLA_MODE_I2C_MASTER (SERCOM_SPI_CTRLA_MODE_I2C_MASTER_Val << SERCOM_SPI_CTRLA_MODE_Pos) |
mbed_official | 579:53297373a894 | 197 | #define SERCOM_SPI_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_SPI_CTRLA) Run during Standby */ |
mbed_official | 579:53297373a894 | 198 | #define SERCOM_SPI_CTRLA_RUNSTDBY (0x1ul << SERCOM_SPI_CTRLA_RUNSTDBY_Pos) |
mbed_official | 579:53297373a894 | 199 | #define SERCOM_SPI_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_SPI_CTRLA) Immediate Buffer Overflow Notification */ |
mbed_official | 579:53297373a894 | 200 | #define SERCOM_SPI_CTRLA_IBON (0x1ul << SERCOM_SPI_CTRLA_IBON_Pos) |
mbed_official | 579:53297373a894 | 201 | #define SERCOM_SPI_CTRLA_DOPO_Pos 16 /**< \brief (SERCOM_SPI_CTRLA) Data Out Pinout */ |
mbed_official | 579:53297373a894 | 202 | #define SERCOM_SPI_CTRLA_DOPO_Msk (0x3ul << SERCOM_SPI_CTRLA_DOPO_Pos) |
mbed_official | 579:53297373a894 | 203 | #define SERCOM_SPI_CTRLA_DOPO(value) ((SERCOM_SPI_CTRLA_DOPO_Msk & ((value) << SERCOM_SPI_CTRLA_DOPO_Pos))) |
mbed_official | 579:53297373a894 | 204 | #define SERCOM_SPI_CTRLA_DIPO_Pos 20 /**< \brief (SERCOM_SPI_CTRLA) Data In Pinout */ |
mbed_official | 579:53297373a894 | 205 | #define SERCOM_SPI_CTRLA_DIPO_Msk (0x3ul << SERCOM_SPI_CTRLA_DIPO_Pos) |
mbed_official | 579:53297373a894 | 206 | #define SERCOM_SPI_CTRLA_DIPO(value) ((SERCOM_SPI_CTRLA_DIPO_Msk & ((value) << SERCOM_SPI_CTRLA_DIPO_Pos))) |
mbed_official | 579:53297373a894 | 207 | #define SERCOM_SPI_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_SPI_CTRLA) Frame Format */ |
mbed_official | 579:53297373a894 | 208 | #define SERCOM_SPI_CTRLA_FORM_Msk (0xFul << SERCOM_SPI_CTRLA_FORM_Pos) |
mbed_official | 579:53297373a894 | 209 | #define SERCOM_SPI_CTRLA_FORM(value) ((SERCOM_SPI_CTRLA_FORM_Msk & ((value) << SERCOM_SPI_CTRLA_FORM_Pos))) |
mbed_official | 579:53297373a894 | 210 | #define SERCOM_SPI_CTRLA_CPHA_Pos 28 /**< \brief (SERCOM_SPI_CTRLA) Clock Phase */ |
mbed_official | 579:53297373a894 | 211 | #define SERCOM_SPI_CTRLA_CPHA (0x1ul << SERCOM_SPI_CTRLA_CPHA_Pos) |
mbed_official | 579:53297373a894 | 212 | #define SERCOM_SPI_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_SPI_CTRLA) Clock Polarity */ |
mbed_official | 579:53297373a894 | 213 | #define SERCOM_SPI_CTRLA_CPOL (0x1ul << SERCOM_SPI_CTRLA_CPOL_Pos) |
mbed_official | 579:53297373a894 | 214 | #define SERCOM_SPI_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_SPI_CTRLA) Data Order */ |
mbed_official | 579:53297373a894 | 215 | #define SERCOM_SPI_CTRLA_DORD (0x1ul << SERCOM_SPI_CTRLA_DORD_Pos) |
mbed_official | 579:53297373a894 | 216 | #define SERCOM_SPI_CTRLA_MASK 0x7F33019Ful /**< \brief (SERCOM_SPI_CTRLA) MASK Register */ |
mbed_official | 579:53297373a894 | 217 | |
mbed_official | 579:53297373a894 | 218 | /* -------- SERCOM_USART_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART USART Control A -------- */ |
mbed_official | 579:53297373a894 | 219 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 220 | typedef union { |
mbed_official | 579:53297373a894 | 221 | struct { |
mbed_official | 579:53297373a894 | 222 | uint32_t SWRST:1; /*!< bit: 0 Software Reset */ |
mbed_official | 579:53297373a894 | 223 | uint32_t ENABLE:1; /*!< bit: 1 Enable */ |
mbed_official | 579:53297373a894 | 224 | uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ |
mbed_official | 579:53297373a894 | 225 | uint32_t :2; /*!< bit: 5.. 6 Reserved */ |
mbed_official | 579:53297373a894 | 226 | uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ |
mbed_official | 579:53297373a894 | 227 | uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */ |
mbed_official | 579:53297373a894 | 228 | uint32_t :4; /*!< bit: 9..12 Reserved */ |
mbed_official | 579:53297373a894 | 229 | uint32_t SAMPR:3; /*!< bit: 13..15 Sample */ |
mbed_official | 579:53297373a894 | 230 | uint32_t TXPO:2; /*!< bit: 16..17 Transmit Data Pinout */ |
mbed_official | 579:53297373a894 | 231 | uint32_t :2; /*!< bit: 18..19 Reserved */ |
mbed_official | 579:53297373a894 | 232 | uint32_t RXPO:2; /*!< bit: 20..21 Receive Data Pinout */ |
mbed_official | 579:53297373a894 | 233 | uint32_t SAMPA:2; /*!< bit: 22..23 Sample Adjustment */ |
mbed_official | 579:53297373a894 | 234 | uint32_t FORM:4; /*!< bit: 24..27 Frame Format */ |
mbed_official | 579:53297373a894 | 235 | uint32_t CMODE:1; /*!< bit: 28 Communication Mode */ |
mbed_official | 579:53297373a894 | 236 | uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */ |
mbed_official | 579:53297373a894 | 237 | uint32_t DORD:1; /*!< bit: 30 Data Order */ |
mbed_official | 579:53297373a894 | 238 | uint32_t :1; /*!< bit: 31 Reserved */ |
mbed_official | 579:53297373a894 | 239 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 240 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 241 | } SERCOM_USART_CTRLA_Type; |
mbed_official | 579:53297373a894 | 242 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 243 | |
mbed_official | 579:53297373a894 | 244 | #define SERCOM_USART_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_USART_CTRLA offset) USART Control A */ |
mbed_official | 579:53297373a894 | 245 | #define SERCOM_USART_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_CTRLA reset_value) USART Control A */ |
mbed_official | 579:53297373a894 | 246 | |
mbed_official | 579:53297373a894 | 247 | #define SERCOM_USART_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_USART_CTRLA) Software Reset */ |
mbed_official | 579:53297373a894 | 248 | #define SERCOM_USART_CTRLA_SWRST (0x1ul << SERCOM_USART_CTRLA_SWRST_Pos) |
mbed_official | 579:53297373a894 | 249 | #define SERCOM_USART_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_USART_CTRLA) Enable */ |
mbed_official | 579:53297373a894 | 250 | #define SERCOM_USART_CTRLA_ENABLE (0x1ul << SERCOM_USART_CTRLA_ENABLE_Pos) |
mbed_official | 579:53297373a894 | 251 | #define SERCOM_USART_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_USART_CTRLA) Operating Mode */ |
mbed_official | 579:53297373a894 | 252 | #define SERCOM_USART_CTRLA_MODE_Msk (0x7ul << SERCOM_USART_CTRLA_MODE_Pos) |
mbed_official | 579:53297373a894 | 253 | #define SERCOM_USART_CTRLA_MODE(value) ((SERCOM_USART_CTRLA_MODE_Msk & ((value) << SERCOM_USART_CTRLA_MODE_Pos))) |
mbed_official | 579:53297373a894 | 254 | #define SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_USART_CTRLA) USART mode with external clock */ |
mbed_official | 579:53297373a894 | 255 | #define SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_USART_CTRLA) USART mode with internal clock */ |
mbed_official | 579:53297373a894 | 256 | #define SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_USART_CTRLA) SPI mode with external clock */ |
mbed_official | 579:53297373a894 | 257 | #define SERCOM_USART_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_USART_CTRLA) SPI mode with internal clock */ |
mbed_official | 579:53297373a894 | 258 | #define SERCOM_USART_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_USART_CTRLA) I2C mode with external clock */ |
mbed_official | 579:53297373a894 | 259 | #define SERCOM_USART_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_USART_CTRLA) I2C mode with internal clock */ |
mbed_official | 579:53297373a894 | 260 | #define SERCOM_USART_CTRLA_MODE_USART_EXT_CLK (SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_USART_CTRLA_MODE_Pos) |
mbed_official | 579:53297373a894 | 261 | #define SERCOM_USART_CTRLA_MODE_USART_INT_CLK (SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_USART_CTRLA_MODE_Pos) |
mbed_official | 579:53297373a894 | 262 | #define SERCOM_USART_CTRLA_MODE_SPI_SLAVE (SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_USART_CTRLA_MODE_Pos) |
mbed_official | 579:53297373a894 | 263 | #define SERCOM_USART_CTRLA_MODE_SPI_MASTER (SERCOM_USART_CTRLA_MODE_SPI_MASTER_Val << SERCOM_USART_CTRLA_MODE_Pos) |
mbed_official | 579:53297373a894 | 264 | #define SERCOM_USART_CTRLA_MODE_I2C_SLAVE (SERCOM_USART_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_USART_CTRLA_MODE_Pos) |
mbed_official | 579:53297373a894 | 265 | #define SERCOM_USART_CTRLA_MODE_I2C_MASTER (SERCOM_USART_CTRLA_MODE_I2C_MASTER_Val << SERCOM_USART_CTRLA_MODE_Pos) |
mbed_official | 579:53297373a894 | 266 | #define SERCOM_USART_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_USART_CTRLA) Run during Standby */ |
mbed_official | 579:53297373a894 | 267 | #define SERCOM_USART_CTRLA_RUNSTDBY (0x1ul << SERCOM_USART_CTRLA_RUNSTDBY_Pos) |
mbed_official | 579:53297373a894 | 268 | #define SERCOM_USART_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_USART_CTRLA) Immediate Buffer Overflow Notification */ |
mbed_official | 579:53297373a894 | 269 | #define SERCOM_USART_CTRLA_IBON (0x1ul << SERCOM_USART_CTRLA_IBON_Pos) |
mbed_official | 579:53297373a894 | 270 | #define SERCOM_USART_CTRLA_SAMPR_Pos 13 /**< \brief (SERCOM_USART_CTRLA) Sample */ |
mbed_official | 579:53297373a894 | 271 | #define SERCOM_USART_CTRLA_SAMPR_Msk (0x7ul << SERCOM_USART_CTRLA_SAMPR_Pos) |
mbed_official | 579:53297373a894 | 272 | #define SERCOM_USART_CTRLA_SAMPR(value) ((SERCOM_USART_CTRLA_SAMPR_Msk & ((value) << SERCOM_USART_CTRLA_SAMPR_Pos))) |
mbed_official | 579:53297373a894 | 273 | #define SERCOM_USART_CTRLA_TXPO_Pos 16 /**< \brief (SERCOM_USART_CTRLA) Transmit Data Pinout */ |
mbed_official | 579:53297373a894 | 274 | #define SERCOM_USART_CTRLA_TXPO_Msk (0x3ul << SERCOM_USART_CTRLA_TXPO_Pos) |
mbed_official | 579:53297373a894 | 275 | #define SERCOM_USART_CTRLA_TXPO(value) ((SERCOM_USART_CTRLA_TXPO_Msk & ((value) << SERCOM_USART_CTRLA_TXPO_Pos))) |
mbed_official | 579:53297373a894 | 276 | #define SERCOM_USART_CTRLA_RXPO_Pos 20 /**< \brief (SERCOM_USART_CTRLA) Receive Data Pinout */ |
mbed_official | 579:53297373a894 | 277 | #define SERCOM_USART_CTRLA_RXPO_Msk (0x3ul << SERCOM_USART_CTRLA_RXPO_Pos) |
mbed_official | 579:53297373a894 | 278 | #define SERCOM_USART_CTRLA_RXPO(value) ((SERCOM_USART_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_CTRLA_RXPO_Pos))) |
mbed_official | 579:53297373a894 | 279 | #define SERCOM_USART_CTRLA_SAMPA_Pos 22 /**< \brief (SERCOM_USART_CTRLA) Sample Adjustment */ |
mbed_official | 579:53297373a894 | 280 | #define SERCOM_USART_CTRLA_SAMPA_Msk (0x3ul << SERCOM_USART_CTRLA_SAMPA_Pos) |
mbed_official | 579:53297373a894 | 281 | #define SERCOM_USART_CTRLA_SAMPA(value) ((SERCOM_USART_CTRLA_SAMPA_Msk & ((value) << SERCOM_USART_CTRLA_SAMPA_Pos))) |
mbed_official | 579:53297373a894 | 282 | #define SERCOM_USART_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_USART_CTRLA) Frame Format */ |
mbed_official | 579:53297373a894 | 283 | #define SERCOM_USART_CTRLA_FORM_Msk (0xFul << SERCOM_USART_CTRLA_FORM_Pos) |
mbed_official | 579:53297373a894 | 284 | #define SERCOM_USART_CTRLA_FORM(value) ((SERCOM_USART_CTRLA_FORM_Msk & ((value) << SERCOM_USART_CTRLA_FORM_Pos))) |
mbed_official | 579:53297373a894 | 285 | #define SERCOM_USART_CTRLA_CMODE_Pos 28 /**< \brief (SERCOM_USART_CTRLA) Communication Mode */ |
mbed_official | 579:53297373a894 | 286 | #define SERCOM_USART_CTRLA_CMODE (0x1ul << SERCOM_USART_CTRLA_CMODE_Pos) |
mbed_official | 579:53297373a894 | 287 | #define SERCOM_USART_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_USART_CTRLA) Clock Polarity */ |
mbed_official | 579:53297373a894 | 288 | #define SERCOM_USART_CTRLA_CPOL (0x1ul << SERCOM_USART_CTRLA_CPOL_Pos) |
mbed_official | 579:53297373a894 | 289 | #define SERCOM_USART_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_USART_CTRLA) Data Order */ |
mbed_official | 579:53297373a894 | 290 | #define SERCOM_USART_CTRLA_DORD (0x1ul << SERCOM_USART_CTRLA_DORD_Pos) |
mbed_official | 579:53297373a894 | 291 | #define SERCOM_USART_CTRLA_MASK 0x7FF3E19Ful /**< \brief (SERCOM_USART_CTRLA) MASK Register */ |
mbed_official | 579:53297373a894 | 292 | |
mbed_official | 579:53297373a894 | 293 | /* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM I2CM Control B -------- */ |
mbed_official | 579:53297373a894 | 294 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 295 | typedef union { |
mbed_official | 579:53297373a894 | 296 | struct { |
mbed_official | 579:53297373a894 | 297 | uint32_t :8; /*!< bit: 0.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 298 | uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */ |
mbed_official | 579:53297373a894 | 299 | uint32_t QCEN:1; /*!< bit: 9 Quick Command Enable */ |
mbed_official | 579:53297373a894 | 300 | uint32_t :6; /*!< bit: 10..15 Reserved */ |
mbed_official | 579:53297373a894 | 301 | uint32_t CMD:2; /*!< bit: 16..17 Command */ |
mbed_official | 579:53297373a894 | 302 | uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */ |
mbed_official | 579:53297373a894 | 303 | uint32_t :13; /*!< bit: 19..31 Reserved */ |
mbed_official | 579:53297373a894 | 304 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 305 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 306 | } SERCOM_I2CM_CTRLB_Type; |
mbed_official | 579:53297373a894 | 307 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 308 | |
mbed_official | 579:53297373a894 | 309 | #define SERCOM_I2CM_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CM_CTRLB offset) I2CM Control B */ |
mbed_official | 579:53297373a894 | 310 | #define SERCOM_I2CM_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_CTRLB reset_value) I2CM Control B */ |
mbed_official | 579:53297373a894 | 311 | |
mbed_official | 579:53297373a894 | 312 | #define SERCOM_I2CM_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CM_CTRLB) Smart Mode Enable */ |
mbed_official | 579:53297373a894 | 313 | #define SERCOM_I2CM_CTRLB_SMEN (0x1ul << SERCOM_I2CM_CTRLB_SMEN_Pos) |
mbed_official | 579:53297373a894 | 314 | #define SERCOM_I2CM_CTRLB_QCEN_Pos 9 /**< \brief (SERCOM_I2CM_CTRLB) Quick Command Enable */ |
mbed_official | 579:53297373a894 | 315 | #define SERCOM_I2CM_CTRLB_QCEN (0x1ul << SERCOM_I2CM_CTRLB_QCEN_Pos) |
mbed_official | 579:53297373a894 | 316 | #define SERCOM_I2CM_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CM_CTRLB) Command */ |
mbed_official | 579:53297373a894 | 317 | #define SERCOM_I2CM_CTRLB_CMD_Msk (0x3ul << SERCOM_I2CM_CTRLB_CMD_Pos) |
mbed_official | 579:53297373a894 | 318 | #define SERCOM_I2CM_CTRLB_CMD(value) ((SERCOM_I2CM_CTRLB_CMD_Msk & ((value) << SERCOM_I2CM_CTRLB_CMD_Pos))) |
mbed_official | 579:53297373a894 | 319 | #define SERCOM_I2CM_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CM_CTRLB) Acknowledge Action */ |
mbed_official | 579:53297373a894 | 320 | #define SERCOM_I2CM_CTRLB_ACKACT (0x1ul << SERCOM_I2CM_CTRLB_ACKACT_Pos) |
mbed_official | 579:53297373a894 | 321 | #define SERCOM_I2CM_CTRLB_MASK 0x00070300ul /**< \brief (SERCOM_I2CM_CTRLB) MASK Register */ |
mbed_official | 579:53297373a894 | 322 | |
mbed_official | 579:53297373a894 | 323 | /* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS I2CS Control B -------- */ |
mbed_official | 579:53297373a894 | 324 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 325 | typedef union { |
mbed_official | 579:53297373a894 | 326 | struct { |
mbed_official | 579:53297373a894 | 327 | uint32_t :8; /*!< bit: 0.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 328 | uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */ |
mbed_official | 579:53297373a894 | 329 | uint32_t GCMD:1; /*!< bit: 9 PMBus Group Command */ |
mbed_official | 579:53297373a894 | 330 | uint32_t AACKEN:1; /*!< bit: 10 Automatic Address Acknowledge */ |
mbed_official | 579:53297373a894 | 331 | uint32_t :3; /*!< bit: 11..13 Reserved */ |
mbed_official | 579:53297373a894 | 332 | uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */ |
mbed_official | 579:53297373a894 | 333 | uint32_t CMD:2; /*!< bit: 16..17 Command */ |
mbed_official | 579:53297373a894 | 334 | uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */ |
mbed_official | 579:53297373a894 | 335 | uint32_t :13; /*!< bit: 19..31 Reserved */ |
mbed_official | 579:53297373a894 | 336 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 337 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 338 | } SERCOM_I2CS_CTRLB_Type; |
mbed_official | 579:53297373a894 | 339 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 340 | |
mbed_official | 579:53297373a894 | 341 | #define SERCOM_I2CS_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CS_CTRLB offset) I2CS Control B */ |
mbed_official | 579:53297373a894 | 342 | #define SERCOM_I2CS_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_CTRLB reset_value) I2CS Control B */ |
mbed_official | 579:53297373a894 | 343 | |
mbed_official | 579:53297373a894 | 344 | #define SERCOM_I2CS_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CS_CTRLB) Smart Mode Enable */ |
mbed_official | 579:53297373a894 | 345 | #define SERCOM_I2CS_CTRLB_SMEN (0x1ul << SERCOM_I2CS_CTRLB_SMEN_Pos) |
mbed_official | 579:53297373a894 | 346 | #define SERCOM_I2CS_CTRLB_GCMD_Pos 9 /**< \brief (SERCOM_I2CS_CTRLB) PMBus Group Command */ |
mbed_official | 579:53297373a894 | 347 | #define SERCOM_I2CS_CTRLB_GCMD (0x1ul << SERCOM_I2CS_CTRLB_GCMD_Pos) |
mbed_official | 579:53297373a894 | 348 | #define SERCOM_I2CS_CTRLB_AACKEN_Pos 10 /**< \brief (SERCOM_I2CS_CTRLB) Automatic Address Acknowledge */ |
mbed_official | 579:53297373a894 | 349 | #define SERCOM_I2CS_CTRLB_AACKEN (0x1ul << SERCOM_I2CS_CTRLB_AACKEN_Pos) |
mbed_official | 579:53297373a894 | 350 | #define SERCOM_I2CS_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_I2CS_CTRLB) Address Mode */ |
mbed_official | 579:53297373a894 | 351 | #define SERCOM_I2CS_CTRLB_AMODE_Msk (0x3ul << SERCOM_I2CS_CTRLB_AMODE_Pos) |
mbed_official | 579:53297373a894 | 352 | #define SERCOM_I2CS_CTRLB_AMODE(value) ((SERCOM_I2CS_CTRLB_AMODE_Msk & ((value) << SERCOM_I2CS_CTRLB_AMODE_Pos))) |
mbed_official | 579:53297373a894 | 353 | #define SERCOM_I2CS_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CS_CTRLB) Command */ |
mbed_official | 579:53297373a894 | 354 | #define SERCOM_I2CS_CTRLB_CMD_Msk (0x3ul << SERCOM_I2CS_CTRLB_CMD_Pos) |
mbed_official | 579:53297373a894 | 355 | #define SERCOM_I2CS_CTRLB_CMD(value) ((SERCOM_I2CS_CTRLB_CMD_Msk & ((value) << SERCOM_I2CS_CTRLB_CMD_Pos))) |
mbed_official | 579:53297373a894 | 356 | #define SERCOM_I2CS_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CS_CTRLB) Acknowledge Action */ |
mbed_official | 579:53297373a894 | 357 | #define SERCOM_I2CS_CTRLB_ACKACT (0x1ul << SERCOM_I2CS_CTRLB_ACKACT_Pos) |
mbed_official | 579:53297373a894 | 358 | #define SERCOM_I2CS_CTRLB_MASK 0x0007C700ul /**< \brief (SERCOM_I2CS_CTRLB) MASK Register */ |
mbed_official | 579:53297373a894 | 359 | |
mbed_official | 579:53297373a894 | 360 | /* -------- SERCOM_SPI_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPI SPI Control B -------- */ |
mbed_official | 579:53297373a894 | 361 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 362 | typedef union { |
mbed_official | 579:53297373a894 | 363 | struct { |
mbed_official | 579:53297373a894 | 364 | uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */ |
mbed_official | 579:53297373a894 | 365 | uint32_t :3; /*!< bit: 3.. 5 Reserved */ |
mbed_official | 579:53297373a894 | 366 | uint32_t PLOADEN:1; /*!< bit: 6 Data Preload Enable */ |
mbed_official | 579:53297373a894 | 367 | uint32_t :2; /*!< bit: 7.. 8 Reserved */ |
mbed_official | 579:53297373a894 | 368 | uint32_t SSDE:1; /*!< bit: 9 Slave Select Low Detect Enable */ |
mbed_official | 579:53297373a894 | 369 | uint32_t :3; /*!< bit: 10..12 Reserved */ |
mbed_official | 579:53297373a894 | 370 | uint32_t MSSEN:1; /*!< bit: 13 Master Slave Select Enable */ |
mbed_official | 579:53297373a894 | 371 | uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */ |
mbed_official | 579:53297373a894 | 372 | uint32_t :1; /*!< bit: 16 Reserved */ |
mbed_official | 579:53297373a894 | 373 | uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */ |
mbed_official | 579:53297373a894 | 374 | uint32_t :14; /*!< bit: 18..31 Reserved */ |
mbed_official | 579:53297373a894 | 375 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 376 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 377 | } SERCOM_SPI_CTRLB_Type; |
mbed_official | 579:53297373a894 | 378 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 379 | |
mbed_official | 579:53297373a894 | 380 | #define SERCOM_SPI_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_SPI_CTRLB offset) SPI Control B */ |
mbed_official | 579:53297373a894 | 381 | #define SERCOM_SPI_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_CTRLB reset_value) SPI Control B */ |
mbed_official | 579:53297373a894 | 382 | |
mbed_official | 579:53297373a894 | 383 | #define SERCOM_SPI_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_SPI_CTRLB) Character Size */ |
mbed_official | 579:53297373a894 | 384 | #define SERCOM_SPI_CTRLB_CHSIZE_Msk (0x7ul << SERCOM_SPI_CTRLB_CHSIZE_Pos) |
mbed_official | 579:53297373a894 | 385 | #define SERCOM_SPI_CTRLB_CHSIZE(value) ((SERCOM_SPI_CTRLB_CHSIZE_Msk & ((value) << SERCOM_SPI_CTRLB_CHSIZE_Pos))) |
mbed_official | 579:53297373a894 | 386 | #define SERCOM_SPI_CTRLB_PLOADEN_Pos 6 /**< \brief (SERCOM_SPI_CTRLB) Data Preload Enable */ |
mbed_official | 579:53297373a894 | 387 | #define SERCOM_SPI_CTRLB_PLOADEN (0x1ul << SERCOM_SPI_CTRLB_PLOADEN_Pos) |
mbed_official | 579:53297373a894 | 388 | #define SERCOM_SPI_CTRLB_SSDE_Pos 9 /**< \brief (SERCOM_SPI_CTRLB) Slave Select Low Detect Enable */ |
mbed_official | 579:53297373a894 | 389 | #define SERCOM_SPI_CTRLB_SSDE (0x1ul << SERCOM_SPI_CTRLB_SSDE_Pos) |
mbed_official | 579:53297373a894 | 390 | #define SERCOM_SPI_CTRLB_MSSEN_Pos 13 /**< \brief (SERCOM_SPI_CTRLB) Master Slave Select Enable */ |
mbed_official | 579:53297373a894 | 391 | #define SERCOM_SPI_CTRLB_MSSEN (0x1ul << SERCOM_SPI_CTRLB_MSSEN_Pos) |
mbed_official | 579:53297373a894 | 392 | #define SERCOM_SPI_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_SPI_CTRLB) Address Mode */ |
mbed_official | 579:53297373a894 | 393 | #define SERCOM_SPI_CTRLB_AMODE_Msk (0x3ul << SERCOM_SPI_CTRLB_AMODE_Pos) |
mbed_official | 579:53297373a894 | 394 | #define SERCOM_SPI_CTRLB_AMODE(value) ((SERCOM_SPI_CTRLB_AMODE_Msk & ((value) << SERCOM_SPI_CTRLB_AMODE_Pos))) |
mbed_official | 579:53297373a894 | 395 | #define SERCOM_SPI_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_SPI_CTRLB) Receiver Enable */ |
mbed_official | 579:53297373a894 | 396 | #define SERCOM_SPI_CTRLB_RXEN (0x1ul << SERCOM_SPI_CTRLB_RXEN_Pos) |
mbed_official | 579:53297373a894 | 397 | #define SERCOM_SPI_CTRLB_MASK 0x0002E247ul /**< \brief (SERCOM_SPI_CTRLB) MASK Register */ |
mbed_official | 579:53297373a894 | 398 | |
mbed_official | 579:53297373a894 | 399 | /* -------- SERCOM_USART_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART USART Control B -------- */ |
mbed_official | 579:53297373a894 | 400 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 401 | typedef union { |
mbed_official | 579:53297373a894 | 402 | struct { |
mbed_official | 579:53297373a894 | 403 | uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */ |
mbed_official | 579:53297373a894 | 404 | uint32_t :3; /*!< bit: 3.. 5 Reserved */ |
mbed_official | 579:53297373a894 | 405 | uint32_t SBMODE:1; /*!< bit: 6 Stop Bit Mode */ |
mbed_official | 579:53297373a894 | 406 | uint32_t :1; /*!< bit: 7 Reserved */ |
mbed_official | 579:53297373a894 | 407 | uint32_t COLDEN:1; /*!< bit: 8 Collision Detection Enable */ |
mbed_official | 579:53297373a894 | 408 | uint32_t SFDE:1; /*!< bit: 9 Start of Frame Detection Enable */ |
mbed_official | 579:53297373a894 | 409 | uint32_t ENC:1; /*!< bit: 10 Encoding Format */ |
mbed_official | 579:53297373a894 | 410 | uint32_t :2; /*!< bit: 11..12 Reserved */ |
mbed_official | 579:53297373a894 | 411 | uint32_t PMODE:1; /*!< bit: 13 Parity Mode */ |
mbed_official | 579:53297373a894 | 412 | uint32_t :2; /*!< bit: 14..15 Reserved */ |
mbed_official | 579:53297373a894 | 413 | uint32_t TXEN:1; /*!< bit: 16 Transmitter Enable */ |
mbed_official | 579:53297373a894 | 414 | uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */ |
mbed_official | 579:53297373a894 | 415 | uint32_t :14; /*!< bit: 18..31 Reserved */ |
mbed_official | 579:53297373a894 | 416 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 417 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 418 | } SERCOM_USART_CTRLB_Type; |
mbed_official | 579:53297373a894 | 419 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 420 | |
mbed_official | 579:53297373a894 | 421 | #define SERCOM_USART_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_USART_CTRLB offset) USART Control B */ |
mbed_official | 579:53297373a894 | 422 | #define SERCOM_USART_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_CTRLB reset_value) USART Control B */ |
mbed_official | 579:53297373a894 | 423 | |
mbed_official | 579:53297373a894 | 424 | #define SERCOM_USART_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_USART_CTRLB) Character Size */ |
mbed_official | 579:53297373a894 | 425 | #define SERCOM_USART_CTRLB_CHSIZE_Msk (0x7ul << SERCOM_USART_CTRLB_CHSIZE_Pos) |
mbed_official | 579:53297373a894 | 426 | #define SERCOM_USART_CTRLB_CHSIZE(value) ((SERCOM_USART_CTRLB_CHSIZE_Msk & ((value) << SERCOM_USART_CTRLB_CHSIZE_Pos))) |
mbed_official | 579:53297373a894 | 427 | #define SERCOM_USART_CTRLB_SBMODE_Pos 6 /**< \brief (SERCOM_USART_CTRLB) Stop Bit Mode */ |
mbed_official | 579:53297373a894 | 428 | #define SERCOM_USART_CTRLB_SBMODE (0x1ul << SERCOM_USART_CTRLB_SBMODE_Pos) |
mbed_official | 579:53297373a894 | 429 | #define SERCOM_USART_CTRLB_COLDEN_Pos 8 /**< \brief (SERCOM_USART_CTRLB) Collision Detection Enable */ |
mbed_official | 579:53297373a894 | 430 | #define SERCOM_USART_CTRLB_COLDEN (0x1ul << SERCOM_USART_CTRLB_COLDEN_Pos) |
mbed_official | 579:53297373a894 | 431 | #define SERCOM_USART_CTRLB_SFDE_Pos 9 /**< \brief (SERCOM_USART_CTRLB) Start of Frame Detection Enable */ |
mbed_official | 579:53297373a894 | 432 | #define SERCOM_USART_CTRLB_SFDE (0x1ul << SERCOM_USART_CTRLB_SFDE_Pos) |
mbed_official | 579:53297373a894 | 433 | #define SERCOM_USART_CTRLB_ENC_Pos 10 /**< \brief (SERCOM_USART_CTRLB) Encoding Format */ |
mbed_official | 579:53297373a894 | 434 | #define SERCOM_USART_CTRLB_ENC (0x1ul << SERCOM_USART_CTRLB_ENC_Pos) |
mbed_official | 579:53297373a894 | 435 | #define SERCOM_USART_CTRLB_PMODE_Pos 13 /**< \brief (SERCOM_USART_CTRLB) Parity Mode */ |
mbed_official | 579:53297373a894 | 436 | #define SERCOM_USART_CTRLB_PMODE (0x1ul << SERCOM_USART_CTRLB_PMODE_Pos) |
mbed_official | 579:53297373a894 | 437 | #define SERCOM_USART_CTRLB_TXEN_Pos 16 /**< \brief (SERCOM_USART_CTRLB) Transmitter Enable */ |
mbed_official | 579:53297373a894 | 438 | #define SERCOM_USART_CTRLB_TXEN (0x1ul << SERCOM_USART_CTRLB_TXEN_Pos) |
mbed_official | 579:53297373a894 | 439 | #define SERCOM_USART_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_USART_CTRLB) Receiver Enable */ |
mbed_official | 579:53297373a894 | 440 | #define SERCOM_USART_CTRLB_RXEN (0x1ul << SERCOM_USART_CTRLB_RXEN_Pos) |
mbed_official | 579:53297373a894 | 441 | #define SERCOM_USART_CTRLB_MASK 0x00032747ul /**< \brief (SERCOM_USART_CTRLB) MASK Register */ |
mbed_official | 579:53297373a894 | 442 | |
mbed_official | 579:53297373a894 | 443 | /* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0C) (R/W 32) I2CM I2CM Baud Rate -------- */ |
mbed_official | 579:53297373a894 | 444 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 445 | typedef union { |
mbed_official | 579:53297373a894 | 446 | struct { |
mbed_official | 579:53297373a894 | 447 | uint32_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */ |
mbed_official | 579:53297373a894 | 448 | uint32_t BAUDLOW:8; /*!< bit: 8..15 Baud Rate Value Low */ |
mbed_official | 579:53297373a894 | 449 | uint32_t HSBAUD:8; /*!< bit: 16..23 High Speed Baud Rate Value */ |
mbed_official | 579:53297373a894 | 450 | uint32_t HSBAUDLOW:8; /*!< bit: 24..31 High Speed Baud Rate Value Low */ |
mbed_official | 579:53297373a894 | 451 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 452 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 453 | } SERCOM_I2CM_BAUD_Type; |
mbed_official | 579:53297373a894 | 454 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 455 | |
mbed_official | 579:53297373a894 | 456 | #define SERCOM_I2CM_BAUD_OFFSET 0x0C /**< \brief (SERCOM_I2CM_BAUD offset) I2CM Baud Rate */ |
mbed_official | 579:53297373a894 | 457 | #define SERCOM_I2CM_BAUD_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_BAUD reset_value) I2CM Baud Rate */ |
mbed_official | 579:53297373a894 | 458 | |
mbed_official | 579:53297373a894 | 459 | #define SERCOM_I2CM_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value */ |
mbed_official | 579:53297373a894 | 460 | #define SERCOM_I2CM_BAUD_BAUD_Msk (0xFFul << SERCOM_I2CM_BAUD_BAUD_Pos) |
mbed_official | 579:53297373a894 | 461 | #define SERCOM_I2CM_BAUD_BAUD(value) ((SERCOM_I2CM_BAUD_BAUD_Msk & ((value) << SERCOM_I2CM_BAUD_BAUD_Pos))) |
mbed_official | 579:53297373a894 | 462 | #define SERCOM_I2CM_BAUD_BAUDLOW_Pos 8 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value Low */ |
mbed_official | 579:53297373a894 | 463 | #define SERCOM_I2CM_BAUD_BAUDLOW_Msk (0xFFul << SERCOM_I2CM_BAUD_BAUDLOW_Pos) |
mbed_official | 579:53297373a894 | 464 | #define SERCOM_I2CM_BAUD_BAUDLOW(value) ((SERCOM_I2CM_BAUD_BAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_BAUDLOW_Pos))) |
mbed_official | 579:53297373a894 | 465 | #define SERCOM_I2CM_BAUD_HSBAUD_Pos 16 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value */ |
mbed_official | 579:53297373a894 | 466 | #define SERCOM_I2CM_BAUD_HSBAUD_Msk (0xFFul << SERCOM_I2CM_BAUD_HSBAUD_Pos) |
mbed_official | 579:53297373a894 | 467 | #define SERCOM_I2CM_BAUD_HSBAUD(value) ((SERCOM_I2CM_BAUD_HSBAUD_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUD_Pos))) |
mbed_official | 579:53297373a894 | 468 | #define SERCOM_I2CM_BAUD_HSBAUDLOW_Pos 24 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Low */ |
mbed_official | 579:53297373a894 | 469 | #define SERCOM_I2CM_BAUD_HSBAUDLOW_Msk (0xFFul << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos) |
mbed_official | 579:53297373a894 | 470 | #define SERCOM_I2CM_BAUD_HSBAUDLOW(value) ((SERCOM_I2CM_BAUD_HSBAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos))) |
mbed_official | 579:53297373a894 | 471 | #define SERCOM_I2CM_BAUD_MASK 0xFFFFFFFFul /**< \brief (SERCOM_I2CM_BAUD) MASK Register */ |
mbed_official | 579:53297373a894 | 472 | |
mbed_official | 579:53297373a894 | 473 | /* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0C) (R/W 8) SPI SPI Baud Rate -------- */ |
mbed_official | 579:53297373a894 | 474 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 475 | typedef union { |
mbed_official | 579:53297373a894 | 476 | struct { |
mbed_official | 579:53297373a894 | 477 | uint8_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */ |
mbed_official | 579:53297373a894 | 478 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 479 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 480 | } SERCOM_SPI_BAUD_Type; |
mbed_official | 579:53297373a894 | 481 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 482 | |
mbed_official | 579:53297373a894 | 483 | #define SERCOM_SPI_BAUD_OFFSET 0x0C /**< \brief (SERCOM_SPI_BAUD offset) SPI Baud Rate */ |
mbed_official | 579:53297373a894 | 484 | #define SERCOM_SPI_BAUD_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_BAUD reset_value) SPI Baud Rate */ |
mbed_official | 579:53297373a894 | 485 | |
mbed_official | 579:53297373a894 | 486 | #define SERCOM_SPI_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_SPI_BAUD) Baud Rate Value */ |
mbed_official | 579:53297373a894 | 487 | #define SERCOM_SPI_BAUD_BAUD_Msk (0xFFul << SERCOM_SPI_BAUD_BAUD_Pos) |
mbed_official | 579:53297373a894 | 488 | #define SERCOM_SPI_BAUD_BAUD(value) ((SERCOM_SPI_BAUD_BAUD_Msk & ((value) << SERCOM_SPI_BAUD_BAUD_Pos))) |
mbed_official | 579:53297373a894 | 489 | #define SERCOM_SPI_BAUD_MASK 0xFFul /**< \brief (SERCOM_SPI_BAUD) MASK Register */ |
mbed_official | 579:53297373a894 | 490 | |
mbed_official | 579:53297373a894 | 491 | /* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART USART Baud Rate -------- */ |
mbed_official | 579:53297373a894 | 492 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 493 | typedef union { |
mbed_official | 579:53297373a894 | 494 | struct { |
mbed_official | 579:53297373a894 | 495 | uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */ |
mbed_official | 579:53297373a894 | 496 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 497 | struct { // FRAC mode |
mbed_official | 579:53297373a894 | 498 | uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */ |
mbed_official | 579:53297373a894 | 499 | uint16_t FP:3; /*!< bit: 13..15 Fractional Part */ |
mbed_official | 579:53297373a894 | 500 | } FRAC; /*!< Structure used for FRAC */ |
mbed_official | 579:53297373a894 | 501 | struct { // FRACFP mode |
mbed_official | 579:53297373a894 | 502 | uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */ |
mbed_official | 579:53297373a894 | 503 | uint16_t FP:3; /*!< bit: 13..15 Fractional Part */ |
mbed_official | 579:53297373a894 | 504 | } FRACFP; /*!< Structure used for FRACFP */ |
mbed_official | 579:53297373a894 | 505 | struct { // USARTFP mode |
mbed_official | 579:53297373a894 | 506 | uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */ |
mbed_official | 579:53297373a894 | 507 | } USARTFP; /*!< Structure used for USARTFP */ |
mbed_official | 579:53297373a894 | 508 | uint16_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 509 | } SERCOM_USART_BAUD_Type; |
mbed_official | 579:53297373a894 | 510 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 511 | |
mbed_official | 579:53297373a894 | 512 | #define SERCOM_USART_BAUD_OFFSET 0x0C /**< \brief (SERCOM_USART_BAUD offset) USART Baud Rate */ |
mbed_official | 579:53297373a894 | 513 | #define SERCOM_USART_BAUD_RESETVALUE 0x0000ul /**< \brief (SERCOM_USART_BAUD reset_value) USART Baud Rate */ |
mbed_official | 579:53297373a894 | 514 | |
mbed_official | 579:53297373a894 | 515 | #define SERCOM_USART_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD) Baud Rate Value */ |
mbed_official | 579:53297373a894 | 516 | #define SERCOM_USART_BAUD_BAUD_Msk (0xFFFFul << SERCOM_USART_BAUD_BAUD_Pos) |
mbed_official | 579:53297373a894 | 517 | #define SERCOM_USART_BAUD_BAUD(value) ((SERCOM_USART_BAUD_BAUD_Msk & ((value) << SERCOM_USART_BAUD_BAUD_Pos))) |
mbed_official | 579:53297373a894 | 518 | #define SERCOM_USART_BAUD_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD) MASK Register */ |
mbed_official | 579:53297373a894 | 519 | |
mbed_official | 579:53297373a894 | 520 | // FRAC mode |
mbed_official | 579:53297373a894 | 521 | #define SERCOM_USART_BAUD_FRAC_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRAC) Baud Rate Value */ |
mbed_official | 579:53297373a894 | 522 | #define SERCOM_USART_BAUD_FRAC_BAUD_Msk (0x1FFFul << SERCOM_USART_BAUD_FRAC_BAUD_Pos) |
mbed_official | 579:53297373a894 | 523 | #define SERCOM_USART_BAUD_FRAC_BAUD(value) ((SERCOM_USART_BAUD_FRAC_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRAC_BAUD_Pos))) |
mbed_official | 579:53297373a894 | 524 | #define SERCOM_USART_BAUD_FRAC_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRAC) Fractional Part */ |
mbed_official | 579:53297373a894 | 525 | #define SERCOM_USART_BAUD_FRAC_FP_Msk (0x7ul << SERCOM_USART_BAUD_FRAC_FP_Pos) |
mbed_official | 579:53297373a894 | 526 | #define SERCOM_USART_BAUD_FRAC_FP(value) ((SERCOM_USART_BAUD_FRAC_FP_Msk & ((value) << SERCOM_USART_BAUD_FRAC_FP_Pos))) |
mbed_official | 579:53297373a894 | 527 | #define SERCOM_USART_BAUD_FRAC_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD_FRAC) MASK Register */ |
mbed_official | 579:53297373a894 | 528 | |
mbed_official | 579:53297373a894 | 529 | // FRACFP mode |
mbed_official | 579:53297373a894 | 530 | #define SERCOM_USART_BAUD_FRACFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRACFP) Baud Rate Value */ |
mbed_official | 579:53297373a894 | 531 | #define SERCOM_USART_BAUD_FRACFP_BAUD_Msk (0x1FFFul << SERCOM_USART_BAUD_FRACFP_BAUD_Pos) |
mbed_official | 579:53297373a894 | 532 | #define SERCOM_USART_BAUD_FRACFP_BAUD(value) ((SERCOM_USART_BAUD_FRACFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos))) |
mbed_official | 579:53297373a894 | 533 | #define SERCOM_USART_BAUD_FRACFP_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRACFP) Fractional Part */ |
mbed_official | 579:53297373a894 | 534 | #define SERCOM_USART_BAUD_FRACFP_FP_Msk (0x7ul << SERCOM_USART_BAUD_FRACFP_FP_Pos) |
mbed_official | 579:53297373a894 | 535 | #define SERCOM_USART_BAUD_FRACFP_FP(value) ((SERCOM_USART_BAUD_FRACFP_FP_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_FP_Pos))) |
mbed_official | 579:53297373a894 | 536 | #define SERCOM_USART_BAUD_FRACFP_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD_FRACFP) MASK Register */ |
mbed_official | 579:53297373a894 | 537 | |
mbed_official | 579:53297373a894 | 538 | // USARTFP mode |
mbed_official | 579:53297373a894 | 539 | #define SERCOM_USART_BAUD_USARTFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_USARTFP) Baud Rate Value */ |
mbed_official | 579:53297373a894 | 540 | #define SERCOM_USART_BAUD_USARTFP_BAUD_Msk (0xFFFFul << SERCOM_USART_BAUD_USARTFP_BAUD_Pos) |
mbed_official | 579:53297373a894 | 541 | #define SERCOM_USART_BAUD_USARTFP_BAUD(value) ((SERCOM_USART_BAUD_USARTFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos))) |
mbed_official | 579:53297373a894 | 542 | #define SERCOM_USART_BAUD_USARTFP_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD_USARTFP) MASK Register */ |
mbed_official | 579:53297373a894 | 543 | |
mbed_official | 579:53297373a894 | 544 | /* -------- SERCOM_USART_RXPL : (SERCOM Offset: 0x0E) (R/W 8) USART USART Receive Pulse Length -------- */ |
mbed_official | 579:53297373a894 | 545 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 546 | typedef union { |
mbed_official | 579:53297373a894 | 547 | struct { |
mbed_official | 579:53297373a894 | 548 | uint8_t RXPL:8; /*!< bit: 0.. 7 Receive Pulse Length */ |
mbed_official | 579:53297373a894 | 549 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 550 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 551 | } SERCOM_USART_RXPL_Type; |
mbed_official | 579:53297373a894 | 552 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 553 | |
mbed_official | 579:53297373a894 | 554 | #define SERCOM_USART_RXPL_OFFSET 0x0E /**< \brief (SERCOM_USART_RXPL offset) USART Receive Pulse Length */ |
mbed_official | 579:53297373a894 | 555 | #define SERCOM_USART_RXPL_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_RXPL reset_value) USART Receive Pulse Length */ |
mbed_official | 579:53297373a894 | 556 | |
mbed_official | 579:53297373a894 | 557 | #define SERCOM_USART_RXPL_RXPL_Pos 0 /**< \brief (SERCOM_USART_RXPL) Receive Pulse Length */ |
mbed_official | 579:53297373a894 | 558 | #define SERCOM_USART_RXPL_RXPL_Msk (0xFFul << SERCOM_USART_RXPL_RXPL_Pos) |
mbed_official | 579:53297373a894 | 559 | #define SERCOM_USART_RXPL_RXPL(value) ((SERCOM_USART_RXPL_RXPL_Msk & ((value) << SERCOM_USART_RXPL_RXPL_Pos))) |
mbed_official | 579:53297373a894 | 560 | #define SERCOM_USART_RXPL_MASK 0xFFul /**< \brief (SERCOM_USART_RXPL) MASK Register */ |
mbed_official | 579:53297373a894 | 561 | |
mbed_official | 579:53297373a894 | 562 | /* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CM I2CM Interrupt Enable Clear -------- */ |
mbed_official | 579:53297373a894 | 563 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 564 | typedef union { |
mbed_official | 579:53297373a894 | 565 | struct { |
mbed_official | 579:53297373a894 | 566 | uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Disable */ |
mbed_official | 579:53297373a894 | 567 | uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Disable */ |
mbed_official | 579:53297373a894 | 568 | uint8_t :5; /*!< bit: 2.. 6 Reserved */ |
mbed_official | 579:53297373a894 | 569 | uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ |
mbed_official | 579:53297373a894 | 570 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 571 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 572 | } SERCOM_I2CM_INTENCLR_Type; |
mbed_official | 579:53297373a894 | 573 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 574 | |
mbed_official | 579:53297373a894 | 575 | #define SERCOM_I2CM_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CM_INTENCLR offset) I2CM Interrupt Enable Clear */ |
mbed_official | 579:53297373a894 | 576 | #define SERCOM_I2CM_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_INTENCLR reset_value) I2CM Interrupt Enable Clear */ |
mbed_official | 579:53297373a894 | 577 | |
mbed_official | 579:53297373a894 | 578 | #define SERCOM_I2CM_INTENCLR_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENCLR) Master On Bus Interrupt Disable */ |
mbed_official | 579:53297373a894 | 579 | #define SERCOM_I2CM_INTENCLR_MB (0x1ul << SERCOM_I2CM_INTENCLR_MB_Pos) |
mbed_official | 579:53297373a894 | 580 | #define SERCOM_I2CM_INTENCLR_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENCLR) Slave On Bus Interrupt Disable */ |
mbed_official | 579:53297373a894 | 581 | #define SERCOM_I2CM_INTENCLR_SB (0x1ul << SERCOM_I2CM_INTENCLR_SB_Pos) |
mbed_official | 579:53297373a894 | 582 | #define SERCOM_I2CM_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENCLR) Combined Error Interrupt Disable */ |
mbed_official | 579:53297373a894 | 583 | #define SERCOM_I2CM_INTENCLR_ERROR (0x1ul << SERCOM_I2CM_INTENCLR_ERROR_Pos) |
mbed_official | 579:53297373a894 | 584 | #define SERCOM_I2CM_INTENCLR_MASK 0x83ul /**< \brief (SERCOM_I2CM_INTENCLR) MASK Register */ |
mbed_official | 579:53297373a894 | 585 | |
mbed_official | 579:53297373a894 | 586 | /* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CS I2CS Interrupt Enable Clear -------- */ |
mbed_official | 579:53297373a894 | 587 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 588 | typedef union { |
mbed_official | 579:53297373a894 | 589 | struct { |
mbed_official | 579:53297373a894 | 590 | uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Disable */ |
mbed_official | 579:53297373a894 | 591 | uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Disable */ |
mbed_official | 579:53297373a894 | 592 | uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Disable */ |
mbed_official | 579:53297373a894 | 593 | uint8_t :4; /*!< bit: 3.. 6 Reserved */ |
mbed_official | 579:53297373a894 | 594 | uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ |
mbed_official | 579:53297373a894 | 595 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 596 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 597 | } SERCOM_I2CS_INTENCLR_Type; |
mbed_official | 579:53297373a894 | 598 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 599 | |
mbed_official | 579:53297373a894 | 600 | #define SERCOM_I2CS_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CS_INTENCLR offset) I2CS Interrupt Enable Clear */ |
mbed_official | 579:53297373a894 | 601 | #define SERCOM_I2CS_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_INTENCLR reset_value) I2CS Interrupt Enable Clear */ |
mbed_official | 579:53297373a894 | 602 | |
mbed_official | 579:53297373a894 | 603 | #define SERCOM_I2CS_INTENCLR_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENCLR) Stop Received Interrupt Disable */ |
mbed_official | 579:53297373a894 | 604 | #define SERCOM_I2CS_INTENCLR_PREC (0x1ul << SERCOM_I2CS_INTENCLR_PREC_Pos) |
mbed_official | 579:53297373a894 | 605 | #define SERCOM_I2CS_INTENCLR_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENCLR) Address Match Interrupt Disable */ |
mbed_official | 579:53297373a894 | 606 | #define SERCOM_I2CS_INTENCLR_AMATCH (0x1ul << SERCOM_I2CS_INTENCLR_AMATCH_Pos) |
mbed_official | 579:53297373a894 | 607 | #define SERCOM_I2CS_INTENCLR_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENCLR) Data Interrupt Disable */ |
mbed_official | 579:53297373a894 | 608 | #define SERCOM_I2CS_INTENCLR_DRDY (0x1ul << SERCOM_I2CS_INTENCLR_DRDY_Pos) |
mbed_official | 579:53297373a894 | 609 | #define SERCOM_I2CS_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENCLR) Combined Error Interrupt Disable */ |
mbed_official | 579:53297373a894 | 610 | #define SERCOM_I2CS_INTENCLR_ERROR (0x1ul << SERCOM_I2CS_INTENCLR_ERROR_Pos) |
mbed_official | 579:53297373a894 | 611 | #define SERCOM_I2CS_INTENCLR_MASK 0x87ul /**< \brief (SERCOM_I2CS_INTENCLR) MASK Register */ |
mbed_official | 579:53297373a894 | 612 | |
mbed_official | 579:53297373a894 | 613 | /* -------- SERCOM_SPI_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) SPI SPI Interrupt Enable Clear -------- */ |
mbed_official | 579:53297373a894 | 614 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 615 | typedef union { |
mbed_official | 579:53297373a894 | 616 | struct { |
mbed_official | 579:53297373a894 | 617 | uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */ |
mbed_official | 579:53297373a894 | 618 | uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */ |
mbed_official | 579:53297373a894 | 619 | uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */ |
mbed_official | 579:53297373a894 | 620 | uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Disable */ |
mbed_official | 579:53297373a894 | 621 | uint8_t :3; /*!< bit: 4.. 6 Reserved */ |
mbed_official | 579:53297373a894 | 622 | uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ |
mbed_official | 579:53297373a894 | 623 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 624 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 625 | } SERCOM_SPI_INTENCLR_Type; |
mbed_official | 579:53297373a894 | 626 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 627 | |
mbed_official | 579:53297373a894 | 628 | #define SERCOM_SPI_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_SPI_INTENCLR offset) SPI Interrupt Enable Clear */ |
mbed_official | 579:53297373a894 | 629 | #define SERCOM_SPI_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_INTENCLR reset_value) SPI Interrupt Enable Clear */ |
mbed_official | 579:53297373a894 | 630 | |
mbed_official | 579:53297373a894 | 631 | #define SERCOM_SPI_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENCLR) Data Register Empty Interrupt Disable */ |
mbed_official | 579:53297373a894 | 632 | #define SERCOM_SPI_INTENCLR_DRE (0x1ul << SERCOM_SPI_INTENCLR_DRE_Pos) |
mbed_official | 579:53297373a894 | 633 | #define SERCOM_SPI_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENCLR) Transmit Complete Interrupt Disable */ |
mbed_official | 579:53297373a894 | 634 | #define SERCOM_SPI_INTENCLR_TXC (0x1ul << SERCOM_SPI_INTENCLR_TXC_Pos) |
mbed_official | 579:53297373a894 | 635 | #define SERCOM_SPI_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENCLR) Receive Complete Interrupt Disable */ |
mbed_official | 579:53297373a894 | 636 | #define SERCOM_SPI_INTENCLR_RXC (0x1ul << SERCOM_SPI_INTENCLR_RXC_Pos) |
mbed_official | 579:53297373a894 | 637 | #define SERCOM_SPI_INTENCLR_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENCLR) Slave Select Low Interrupt Disable */ |
mbed_official | 579:53297373a894 | 638 | #define SERCOM_SPI_INTENCLR_SSL (0x1ul << SERCOM_SPI_INTENCLR_SSL_Pos) |
mbed_official | 579:53297373a894 | 639 | #define SERCOM_SPI_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENCLR) Combined Error Interrupt Disable */ |
mbed_official | 579:53297373a894 | 640 | #define SERCOM_SPI_INTENCLR_ERROR (0x1ul << SERCOM_SPI_INTENCLR_ERROR_Pos) |
mbed_official | 579:53297373a894 | 641 | #define SERCOM_SPI_INTENCLR_MASK 0x8Ful /**< \brief (SERCOM_SPI_INTENCLR) MASK Register */ |
mbed_official | 579:53297373a894 | 642 | |
mbed_official | 579:53297373a894 | 643 | /* -------- SERCOM_USART_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) USART USART Interrupt Enable Clear -------- */ |
mbed_official | 579:53297373a894 | 644 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 645 | typedef union { |
mbed_official | 579:53297373a894 | 646 | struct { |
mbed_official | 579:53297373a894 | 647 | uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */ |
mbed_official | 579:53297373a894 | 648 | uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */ |
mbed_official | 579:53297373a894 | 649 | uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */ |
mbed_official | 579:53297373a894 | 650 | uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Disable */ |
mbed_official | 579:53297373a894 | 651 | uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Disable */ |
mbed_official | 579:53297373a894 | 652 | uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Disable */ |
mbed_official | 579:53297373a894 | 653 | uint8_t :1; /*!< bit: 6 Reserved */ |
mbed_official | 579:53297373a894 | 654 | uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ |
mbed_official | 579:53297373a894 | 655 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 656 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 657 | } SERCOM_USART_INTENCLR_Type; |
mbed_official | 579:53297373a894 | 658 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 659 | |
mbed_official | 579:53297373a894 | 660 | #define SERCOM_USART_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_USART_INTENCLR offset) USART Interrupt Enable Clear */ |
mbed_official | 579:53297373a894 | 661 | #define SERCOM_USART_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_INTENCLR reset_value) USART Interrupt Enable Clear */ |
mbed_official | 579:53297373a894 | 662 | |
mbed_official | 579:53297373a894 | 663 | #define SERCOM_USART_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENCLR) Data Register Empty Interrupt Disable */ |
mbed_official | 579:53297373a894 | 664 | #define SERCOM_USART_INTENCLR_DRE (0x1ul << SERCOM_USART_INTENCLR_DRE_Pos) |
mbed_official | 579:53297373a894 | 665 | #define SERCOM_USART_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENCLR) Transmit Complete Interrupt Disable */ |
mbed_official | 579:53297373a894 | 666 | #define SERCOM_USART_INTENCLR_TXC (0x1ul << SERCOM_USART_INTENCLR_TXC_Pos) |
mbed_official | 579:53297373a894 | 667 | #define SERCOM_USART_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENCLR) Receive Complete Interrupt Disable */ |
mbed_official | 579:53297373a894 | 668 | #define SERCOM_USART_INTENCLR_RXC (0x1ul << SERCOM_USART_INTENCLR_RXC_Pos) |
mbed_official | 579:53297373a894 | 669 | #define SERCOM_USART_INTENCLR_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENCLR) Receive Start Interrupt Disable */ |
mbed_official | 579:53297373a894 | 670 | #define SERCOM_USART_INTENCLR_RXS (0x1ul << SERCOM_USART_INTENCLR_RXS_Pos) |
mbed_official | 579:53297373a894 | 671 | #define SERCOM_USART_INTENCLR_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENCLR) Clear To Send Input Change Interrupt Disable */ |
mbed_official | 579:53297373a894 | 672 | #define SERCOM_USART_INTENCLR_CTSIC (0x1ul << SERCOM_USART_INTENCLR_CTSIC_Pos) |
mbed_official | 579:53297373a894 | 673 | #define SERCOM_USART_INTENCLR_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENCLR) Break Received Interrupt Disable */ |
mbed_official | 579:53297373a894 | 674 | #define SERCOM_USART_INTENCLR_RXBRK (0x1ul << SERCOM_USART_INTENCLR_RXBRK_Pos) |
mbed_official | 579:53297373a894 | 675 | #define SERCOM_USART_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENCLR) Combined Error Interrupt Disable */ |
mbed_official | 579:53297373a894 | 676 | #define SERCOM_USART_INTENCLR_ERROR (0x1ul << SERCOM_USART_INTENCLR_ERROR_Pos) |
mbed_official | 579:53297373a894 | 677 | #define SERCOM_USART_INTENCLR_MASK 0xBFul /**< \brief (SERCOM_USART_INTENCLR) MASK Register */ |
mbed_official | 579:53297373a894 | 678 | |
mbed_official | 579:53297373a894 | 679 | /* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CM I2CM Interrupt Enable Set -------- */ |
mbed_official | 579:53297373a894 | 680 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 681 | typedef union { |
mbed_official | 579:53297373a894 | 682 | struct { |
mbed_official | 579:53297373a894 | 683 | uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Enable */ |
mbed_official | 579:53297373a894 | 684 | uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Enable */ |
mbed_official | 579:53297373a894 | 685 | uint8_t :5; /*!< bit: 2.. 6 Reserved */ |
mbed_official | 579:53297373a894 | 686 | uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ |
mbed_official | 579:53297373a894 | 687 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 688 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 689 | } SERCOM_I2CM_INTENSET_Type; |
mbed_official | 579:53297373a894 | 690 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 691 | |
mbed_official | 579:53297373a894 | 692 | #define SERCOM_I2CM_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CM_INTENSET offset) I2CM Interrupt Enable Set */ |
mbed_official | 579:53297373a894 | 693 | #define SERCOM_I2CM_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_INTENSET reset_value) I2CM Interrupt Enable Set */ |
mbed_official | 579:53297373a894 | 694 | |
mbed_official | 579:53297373a894 | 695 | #define SERCOM_I2CM_INTENSET_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENSET) Master On Bus Interrupt Enable */ |
mbed_official | 579:53297373a894 | 696 | #define SERCOM_I2CM_INTENSET_MB (0x1ul << SERCOM_I2CM_INTENSET_MB_Pos) |
mbed_official | 579:53297373a894 | 697 | #define SERCOM_I2CM_INTENSET_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENSET) Slave On Bus Interrupt Enable */ |
mbed_official | 579:53297373a894 | 698 | #define SERCOM_I2CM_INTENSET_SB (0x1ul << SERCOM_I2CM_INTENSET_SB_Pos) |
mbed_official | 579:53297373a894 | 699 | #define SERCOM_I2CM_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENSET) Combined Error Interrupt Enable */ |
mbed_official | 579:53297373a894 | 700 | #define SERCOM_I2CM_INTENSET_ERROR (0x1ul << SERCOM_I2CM_INTENSET_ERROR_Pos) |
mbed_official | 579:53297373a894 | 701 | #define SERCOM_I2CM_INTENSET_MASK 0x83ul /**< \brief (SERCOM_I2CM_INTENSET) MASK Register */ |
mbed_official | 579:53297373a894 | 702 | |
mbed_official | 579:53297373a894 | 703 | /* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CS I2CS Interrupt Enable Set -------- */ |
mbed_official | 579:53297373a894 | 704 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 705 | typedef union { |
mbed_official | 579:53297373a894 | 706 | struct { |
mbed_official | 579:53297373a894 | 707 | uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Enable */ |
mbed_official | 579:53297373a894 | 708 | uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Enable */ |
mbed_official | 579:53297373a894 | 709 | uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Enable */ |
mbed_official | 579:53297373a894 | 710 | uint8_t :4; /*!< bit: 3.. 6 Reserved */ |
mbed_official | 579:53297373a894 | 711 | uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ |
mbed_official | 579:53297373a894 | 712 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 713 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 714 | } SERCOM_I2CS_INTENSET_Type; |
mbed_official | 579:53297373a894 | 715 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 716 | |
mbed_official | 579:53297373a894 | 717 | #define SERCOM_I2CS_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CS_INTENSET offset) I2CS Interrupt Enable Set */ |
mbed_official | 579:53297373a894 | 718 | #define SERCOM_I2CS_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_INTENSET reset_value) I2CS Interrupt Enable Set */ |
mbed_official | 579:53297373a894 | 719 | |
mbed_official | 579:53297373a894 | 720 | #define SERCOM_I2CS_INTENSET_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENSET) Stop Received Interrupt Enable */ |
mbed_official | 579:53297373a894 | 721 | #define SERCOM_I2CS_INTENSET_PREC (0x1ul << SERCOM_I2CS_INTENSET_PREC_Pos) |
mbed_official | 579:53297373a894 | 722 | #define SERCOM_I2CS_INTENSET_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENSET) Address Match Interrupt Enable */ |
mbed_official | 579:53297373a894 | 723 | #define SERCOM_I2CS_INTENSET_AMATCH (0x1ul << SERCOM_I2CS_INTENSET_AMATCH_Pos) |
mbed_official | 579:53297373a894 | 724 | #define SERCOM_I2CS_INTENSET_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENSET) Data Interrupt Enable */ |
mbed_official | 579:53297373a894 | 725 | #define SERCOM_I2CS_INTENSET_DRDY (0x1ul << SERCOM_I2CS_INTENSET_DRDY_Pos) |
mbed_official | 579:53297373a894 | 726 | #define SERCOM_I2CS_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENSET) Combined Error Interrupt Enable */ |
mbed_official | 579:53297373a894 | 727 | #define SERCOM_I2CS_INTENSET_ERROR (0x1ul << SERCOM_I2CS_INTENSET_ERROR_Pos) |
mbed_official | 579:53297373a894 | 728 | #define SERCOM_I2CS_INTENSET_MASK 0x87ul /**< \brief (SERCOM_I2CS_INTENSET) MASK Register */ |
mbed_official | 579:53297373a894 | 729 | |
mbed_official | 579:53297373a894 | 730 | /* -------- SERCOM_SPI_INTENSET : (SERCOM Offset: 0x16) (R/W 8) SPI SPI Interrupt Enable Set -------- */ |
mbed_official | 579:53297373a894 | 731 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 732 | typedef union { |
mbed_official | 579:53297373a894 | 733 | struct { |
mbed_official | 579:53297373a894 | 734 | uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */ |
mbed_official | 579:53297373a894 | 735 | uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */ |
mbed_official | 579:53297373a894 | 736 | uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */ |
mbed_official | 579:53297373a894 | 737 | uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Enable */ |
mbed_official | 579:53297373a894 | 738 | uint8_t :3; /*!< bit: 4.. 6 Reserved */ |
mbed_official | 579:53297373a894 | 739 | uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ |
mbed_official | 579:53297373a894 | 740 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 741 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 742 | } SERCOM_SPI_INTENSET_Type; |
mbed_official | 579:53297373a894 | 743 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 744 | |
mbed_official | 579:53297373a894 | 745 | #define SERCOM_SPI_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_SPI_INTENSET offset) SPI Interrupt Enable Set */ |
mbed_official | 579:53297373a894 | 746 | #define SERCOM_SPI_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_INTENSET reset_value) SPI Interrupt Enable Set */ |
mbed_official | 579:53297373a894 | 747 | |
mbed_official | 579:53297373a894 | 748 | #define SERCOM_SPI_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENSET) Data Register Empty Interrupt Enable */ |
mbed_official | 579:53297373a894 | 749 | #define SERCOM_SPI_INTENSET_DRE (0x1ul << SERCOM_SPI_INTENSET_DRE_Pos) |
mbed_official | 579:53297373a894 | 750 | #define SERCOM_SPI_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENSET) Transmit Complete Interrupt Enable */ |
mbed_official | 579:53297373a894 | 751 | #define SERCOM_SPI_INTENSET_TXC (0x1ul << SERCOM_SPI_INTENSET_TXC_Pos) |
mbed_official | 579:53297373a894 | 752 | #define SERCOM_SPI_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENSET) Receive Complete Interrupt Enable */ |
mbed_official | 579:53297373a894 | 753 | #define SERCOM_SPI_INTENSET_RXC (0x1ul << SERCOM_SPI_INTENSET_RXC_Pos) |
mbed_official | 579:53297373a894 | 754 | #define SERCOM_SPI_INTENSET_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENSET) Slave Select Low Interrupt Enable */ |
mbed_official | 579:53297373a894 | 755 | #define SERCOM_SPI_INTENSET_SSL (0x1ul << SERCOM_SPI_INTENSET_SSL_Pos) |
mbed_official | 579:53297373a894 | 756 | #define SERCOM_SPI_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENSET) Combined Error Interrupt Enable */ |
mbed_official | 579:53297373a894 | 757 | #define SERCOM_SPI_INTENSET_ERROR (0x1ul << SERCOM_SPI_INTENSET_ERROR_Pos) |
mbed_official | 579:53297373a894 | 758 | #define SERCOM_SPI_INTENSET_MASK 0x8Ful /**< \brief (SERCOM_SPI_INTENSET) MASK Register */ |
mbed_official | 579:53297373a894 | 759 | |
mbed_official | 579:53297373a894 | 760 | /* -------- SERCOM_USART_INTENSET : (SERCOM Offset: 0x16) (R/W 8) USART USART Interrupt Enable Set -------- */ |
mbed_official | 579:53297373a894 | 761 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 762 | typedef union { |
mbed_official | 579:53297373a894 | 763 | struct { |
mbed_official | 579:53297373a894 | 764 | uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */ |
mbed_official | 579:53297373a894 | 765 | uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */ |
mbed_official | 579:53297373a894 | 766 | uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */ |
mbed_official | 579:53297373a894 | 767 | uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Enable */ |
mbed_official | 579:53297373a894 | 768 | uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Enable */ |
mbed_official | 579:53297373a894 | 769 | uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Enable */ |
mbed_official | 579:53297373a894 | 770 | uint8_t :1; /*!< bit: 6 Reserved */ |
mbed_official | 579:53297373a894 | 771 | uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ |
mbed_official | 579:53297373a894 | 772 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 773 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 774 | } SERCOM_USART_INTENSET_Type; |
mbed_official | 579:53297373a894 | 775 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 776 | |
mbed_official | 579:53297373a894 | 777 | #define SERCOM_USART_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_USART_INTENSET offset) USART Interrupt Enable Set */ |
mbed_official | 579:53297373a894 | 778 | #define SERCOM_USART_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_INTENSET reset_value) USART Interrupt Enable Set */ |
mbed_official | 579:53297373a894 | 779 | |
mbed_official | 579:53297373a894 | 780 | #define SERCOM_USART_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENSET) Data Register Empty Interrupt Enable */ |
mbed_official | 579:53297373a894 | 781 | #define SERCOM_USART_INTENSET_DRE (0x1ul << SERCOM_USART_INTENSET_DRE_Pos) |
mbed_official | 579:53297373a894 | 782 | #define SERCOM_USART_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENSET) Transmit Complete Interrupt Enable */ |
mbed_official | 579:53297373a894 | 783 | #define SERCOM_USART_INTENSET_TXC (0x1ul << SERCOM_USART_INTENSET_TXC_Pos) |
mbed_official | 579:53297373a894 | 784 | #define SERCOM_USART_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENSET) Receive Complete Interrupt Enable */ |
mbed_official | 579:53297373a894 | 785 | #define SERCOM_USART_INTENSET_RXC (0x1ul << SERCOM_USART_INTENSET_RXC_Pos) |
mbed_official | 579:53297373a894 | 786 | #define SERCOM_USART_INTENSET_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENSET) Receive Start Interrupt Enable */ |
mbed_official | 579:53297373a894 | 787 | #define SERCOM_USART_INTENSET_RXS (0x1ul << SERCOM_USART_INTENSET_RXS_Pos) |
mbed_official | 579:53297373a894 | 788 | #define SERCOM_USART_INTENSET_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENSET) Clear To Send Input Change Interrupt Enable */ |
mbed_official | 579:53297373a894 | 789 | #define SERCOM_USART_INTENSET_CTSIC (0x1ul << SERCOM_USART_INTENSET_CTSIC_Pos) |
mbed_official | 579:53297373a894 | 790 | #define SERCOM_USART_INTENSET_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENSET) Break Received Interrupt Enable */ |
mbed_official | 579:53297373a894 | 791 | #define SERCOM_USART_INTENSET_RXBRK (0x1ul << SERCOM_USART_INTENSET_RXBRK_Pos) |
mbed_official | 579:53297373a894 | 792 | #define SERCOM_USART_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENSET) Combined Error Interrupt Enable */ |
mbed_official | 579:53297373a894 | 793 | #define SERCOM_USART_INTENSET_ERROR (0x1ul << SERCOM_USART_INTENSET_ERROR_Pos) |
mbed_official | 579:53297373a894 | 794 | #define SERCOM_USART_INTENSET_MASK 0xBFul /**< \brief (SERCOM_USART_INTENSET) MASK Register */ |
mbed_official | 579:53297373a894 | 795 | |
mbed_official | 579:53297373a894 | 796 | /* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CM I2CM Interrupt Flag Status and Clear -------- */ |
mbed_official | 579:53297373a894 | 797 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 798 | typedef union { |
mbed_official | 579:53297373a894 | 799 | struct { |
mbed_official | 579:53297373a894 | 800 | uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt */ |
mbed_official | 579:53297373a894 | 801 | uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt */ |
mbed_official | 579:53297373a894 | 802 | uint8_t :5; /*!< bit: 2.. 6 Reserved */ |
mbed_official | 579:53297373a894 | 803 | uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ |
mbed_official | 579:53297373a894 | 804 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 805 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 806 | } SERCOM_I2CM_INTFLAG_Type; |
mbed_official | 579:53297373a894 | 807 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 808 | |
mbed_official | 579:53297373a894 | 809 | #define SERCOM_I2CM_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CM_INTFLAG offset) I2CM Interrupt Flag Status and Clear */ |
mbed_official | 579:53297373a894 | 810 | #define SERCOM_I2CM_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_INTFLAG reset_value) I2CM Interrupt Flag Status and Clear */ |
mbed_official | 579:53297373a894 | 811 | |
mbed_official | 579:53297373a894 | 812 | #define SERCOM_I2CM_INTFLAG_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTFLAG) Master On Bus Interrupt */ |
mbed_official | 579:53297373a894 | 813 | #define SERCOM_I2CM_INTFLAG_MB (0x1ul << SERCOM_I2CM_INTFLAG_MB_Pos) |
mbed_official | 579:53297373a894 | 814 | #define SERCOM_I2CM_INTFLAG_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTFLAG) Slave On Bus Interrupt */ |
mbed_official | 579:53297373a894 | 815 | #define SERCOM_I2CM_INTFLAG_SB (0x1ul << SERCOM_I2CM_INTFLAG_SB_Pos) |
mbed_official | 579:53297373a894 | 816 | #define SERCOM_I2CM_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTFLAG) Combined Error Interrupt */ |
mbed_official | 579:53297373a894 | 817 | #define SERCOM_I2CM_INTFLAG_ERROR (0x1ul << SERCOM_I2CM_INTFLAG_ERROR_Pos) |
mbed_official | 579:53297373a894 | 818 | #define SERCOM_I2CM_INTFLAG_MASK 0x83ul /**< \brief (SERCOM_I2CM_INTFLAG) MASK Register */ |
mbed_official | 579:53297373a894 | 819 | |
mbed_official | 579:53297373a894 | 820 | /* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CS I2CS Interrupt Flag Status and Clear -------- */ |
mbed_official | 579:53297373a894 | 821 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 822 | typedef union { |
mbed_official | 579:53297373a894 | 823 | struct { |
mbed_official | 579:53297373a894 | 824 | uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt */ |
mbed_official | 579:53297373a894 | 825 | uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt */ |
mbed_official | 579:53297373a894 | 826 | uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */ |
mbed_official | 579:53297373a894 | 827 | uint8_t :4; /*!< bit: 3.. 6 Reserved */ |
mbed_official | 579:53297373a894 | 828 | uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ |
mbed_official | 579:53297373a894 | 829 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 830 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 831 | } SERCOM_I2CS_INTFLAG_Type; |
mbed_official | 579:53297373a894 | 832 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 833 | |
mbed_official | 579:53297373a894 | 834 | #define SERCOM_I2CS_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CS_INTFLAG offset) I2CS Interrupt Flag Status and Clear */ |
mbed_official | 579:53297373a894 | 835 | #define SERCOM_I2CS_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_INTFLAG reset_value) I2CS Interrupt Flag Status and Clear */ |
mbed_official | 579:53297373a894 | 836 | |
mbed_official | 579:53297373a894 | 837 | #define SERCOM_I2CS_INTFLAG_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTFLAG) Stop Received Interrupt */ |
mbed_official | 579:53297373a894 | 838 | #define SERCOM_I2CS_INTFLAG_PREC (0x1ul << SERCOM_I2CS_INTFLAG_PREC_Pos) |
mbed_official | 579:53297373a894 | 839 | #define SERCOM_I2CS_INTFLAG_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTFLAG) Address Match Interrupt */ |
mbed_official | 579:53297373a894 | 840 | #define SERCOM_I2CS_INTFLAG_AMATCH (0x1ul << SERCOM_I2CS_INTFLAG_AMATCH_Pos) |
mbed_official | 579:53297373a894 | 841 | #define SERCOM_I2CS_INTFLAG_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTFLAG) Data Interrupt */ |
mbed_official | 579:53297373a894 | 842 | #define SERCOM_I2CS_INTFLAG_DRDY (0x1ul << SERCOM_I2CS_INTFLAG_DRDY_Pos) |
mbed_official | 579:53297373a894 | 843 | #define SERCOM_I2CS_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTFLAG) Combined Error Interrupt */ |
mbed_official | 579:53297373a894 | 844 | #define SERCOM_I2CS_INTFLAG_ERROR (0x1ul << SERCOM_I2CS_INTFLAG_ERROR_Pos) |
mbed_official | 579:53297373a894 | 845 | #define SERCOM_I2CS_INTFLAG_MASK 0x87ul /**< \brief (SERCOM_I2CS_INTFLAG) MASK Register */ |
mbed_official | 579:53297373a894 | 846 | |
mbed_official | 579:53297373a894 | 847 | /* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) SPI SPI Interrupt Flag Status and Clear -------- */ |
mbed_official | 579:53297373a894 | 848 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 849 | typedef union { |
mbed_official | 579:53297373a894 | 850 | struct { |
mbed_official | 579:53297373a894 | 851 | uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */ |
mbed_official | 579:53297373a894 | 852 | uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */ |
mbed_official | 579:53297373a894 | 853 | uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */ |
mbed_official | 579:53297373a894 | 854 | uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Flag */ |
mbed_official | 579:53297373a894 | 855 | uint8_t :3; /*!< bit: 4.. 6 Reserved */ |
mbed_official | 579:53297373a894 | 856 | uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ |
mbed_official | 579:53297373a894 | 857 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 858 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 859 | } SERCOM_SPI_INTFLAG_Type; |
mbed_official | 579:53297373a894 | 860 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 861 | |
mbed_official | 579:53297373a894 | 862 | #define SERCOM_SPI_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_SPI_INTFLAG offset) SPI Interrupt Flag Status and Clear */ |
mbed_official | 579:53297373a894 | 863 | #define SERCOM_SPI_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_INTFLAG reset_value) SPI Interrupt Flag Status and Clear */ |
mbed_official | 579:53297373a894 | 864 | |
mbed_official | 579:53297373a894 | 865 | #define SERCOM_SPI_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTFLAG) Data Register Empty Interrupt */ |
mbed_official | 579:53297373a894 | 866 | #define SERCOM_SPI_INTFLAG_DRE (0x1ul << SERCOM_SPI_INTFLAG_DRE_Pos) |
mbed_official | 579:53297373a894 | 867 | #define SERCOM_SPI_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTFLAG) Transmit Complete Interrupt */ |
mbed_official | 579:53297373a894 | 868 | #define SERCOM_SPI_INTFLAG_TXC (0x1ul << SERCOM_SPI_INTFLAG_TXC_Pos) |
mbed_official | 579:53297373a894 | 869 | #define SERCOM_SPI_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTFLAG) Receive Complete Interrupt */ |
mbed_official | 579:53297373a894 | 870 | #define SERCOM_SPI_INTFLAG_RXC (0x1ul << SERCOM_SPI_INTFLAG_RXC_Pos) |
mbed_official | 579:53297373a894 | 871 | #define SERCOM_SPI_INTFLAG_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTFLAG) Slave Select Low Interrupt Flag */ |
mbed_official | 579:53297373a894 | 872 | #define SERCOM_SPI_INTFLAG_SSL (0x1ul << SERCOM_SPI_INTFLAG_SSL_Pos) |
mbed_official | 579:53297373a894 | 873 | #define SERCOM_SPI_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTFLAG) Combined Error Interrupt */ |
mbed_official | 579:53297373a894 | 874 | #define SERCOM_SPI_INTFLAG_ERROR (0x1ul << SERCOM_SPI_INTFLAG_ERROR_Pos) |
mbed_official | 579:53297373a894 | 875 | #define SERCOM_SPI_INTFLAG_MASK 0x8Ful /**< \brief (SERCOM_SPI_INTFLAG) MASK Register */ |
mbed_official | 579:53297373a894 | 876 | |
mbed_official | 579:53297373a894 | 877 | /* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) USART USART Interrupt Flag Status and Clear -------- */ |
mbed_official | 579:53297373a894 | 878 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 879 | typedef union { |
mbed_official | 579:53297373a894 | 880 | struct { |
mbed_official | 579:53297373a894 | 881 | uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */ |
mbed_official | 579:53297373a894 | 882 | uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */ |
mbed_official | 579:53297373a894 | 883 | uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */ |
mbed_official | 579:53297373a894 | 884 | uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */ |
mbed_official | 579:53297373a894 | 885 | uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt */ |
mbed_official | 579:53297373a894 | 886 | uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt */ |
mbed_official | 579:53297373a894 | 887 | uint8_t :1; /*!< bit: 6 Reserved */ |
mbed_official | 579:53297373a894 | 888 | uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ |
mbed_official | 579:53297373a894 | 889 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 890 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 891 | } SERCOM_USART_INTFLAG_Type; |
mbed_official | 579:53297373a894 | 892 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 893 | |
mbed_official | 579:53297373a894 | 894 | #define SERCOM_USART_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_USART_INTFLAG offset) USART Interrupt Flag Status and Clear */ |
mbed_official | 579:53297373a894 | 895 | #define SERCOM_USART_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_INTFLAG reset_value) USART Interrupt Flag Status and Clear */ |
mbed_official | 579:53297373a894 | 896 | |
mbed_official | 579:53297373a894 | 897 | #define SERCOM_USART_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_USART_INTFLAG) Data Register Empty Interrupt */ |
mbed_official | 579:53297373a894 | 898 | #define SERCOM_USART_INTFLAG_DRE (0x1ul << SERCOM_USART_INTFLAG_DRE_Pos) |
mbed_official | 579:53297373a894 | 899 | #define SERCOM_USART_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_USART_INTFLAG) Transmit Complete Interrupt */ |
mbed_official | 579:53297373a894 | 900 | #define SERCOM_USART_INTFLAG_TXC (0x1ul << SERCOM_USART_INTFLAG_TXC_Pos) |
mbed_official | 579:53297373a894 | 901 | #define SERCOM_USART_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_USART_INTFLAG) Receive Complete Interrupt */ |
mbed_official | 579:53297373a894 | 902 | #define SERCOM_USART_INTFLAG_RXC (0x1ul << SERCOM_USART_INTFLAG_RXC_Pos) |
mbed_official | 579:53297373a894 | 903 | #define SERCOM_USART_INTFLAG_RXS_Pos 3 /**< \brief (SERCOM_USART_INTFLAG) Receive Start Interrupt */ |
mbed_official | 579:53297373a894 | 904 | #define SERCOM_USART_INTFLAG_RXS (0x1ul << SERCOM_USART_INTFLAG_RXS_Pos) |
mbed_official | 579:53297373a894 | 905 | #define SERCOM_USART_INTFLAG_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTFLAG) Clear To Send Input Change Interrupt */ |
mbed_official | 579:53297373a894 | 906 | #define SERCOM_USART_INTFLAG_CTSIC (0x1ul << SERCOM_USART_INTFLAG_CTSIC_Pos) |
mbed_official | 579:53297373a894 | 907 | #define SERCOM_USART_INTFLAG_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTFLAG) Break Received Interrupt */ |
mbed_official | 579:53297373a894 | 908 | #define SERCOM_USART_INTFLAG_RXBRK (0x1ul << SERCOM_USART_INTFLAG_RXBRK_Pos) |
mbed_official | 579:53297373a894 | 909 | #define SERCOM_USART_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTFLAG) Combined Error Interrupt */ |
mbed_official | 579:53297373a894 | 910 | #define SERCOM_USART_INTFLAG_ERROR (0x1ul << SERCOM_USART_INTFLAG_ERROR_Pos) |
mbed_official | 579:53297373a894 | 911 | #define SERCOM_USART_INTFLAG_MASK 0xBFul /**< \brief (SERCOM_USART_INTFLAG) MASK Register */ |
mbed_official | 579:53297373a894 | 912 | |
mbed_official | 579:53297373a894 | 913 | /* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CM I2CM Status -------- */ |
mbed_official | 579:53297373a894 | 914 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 915 | typedef union { |
mbed_official | 579:53297373a894 | 916 | struct { |
mbed_official | 579:53297373a894 | 917 | uint16_t BUSERR:1; /*!< bit: 0 Bus Error */ |
mbed_official | 579:53297373a894 | 918 | uint16_t ARBLOST:1; /*!< bit: 1 Arbitration Lost */ |
mbed_official | 579:53297373a894 | 919 | uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */ |
mbed_official | 579:53297373a894 | 920 | uint16_t :1; /*!< bit: 3 Reserved */ |
mbed_official | 579:53297373a894 | 921 | uint16_t BUSSTATE:2; /*!< bit: 4.. 5 Bus State */ |
mbed_official | 579:53297373a894 | 922 | uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */ |
mbed_official | 579:53297373a894 | 923 | uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */ |
mbed_official | 579:53297373a894 | 924 | uint16_t MEXTTOUT:1; /*!< bit: 8 Master SCL Low Extend Timeout */ |
mbed_official | 579:53297373a894 | 925 | uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */ |
mbed_official | 579:53297373a894 | 926 | uint16_t LENERR:1; /*!< bit: 10 Length Error */ |
mbed_official | 579:53297373a894 | 927 | uint16_t :5; /*!< bit: 11..15 Reserved */ |
mbed_official | 579:53297373a894 | 928 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 929 | uint16_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 930 | } SERCOM_I2CM_STATUS_Type; |
mbed_official | 579:53297373a894 | 931 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 932 | |
mbed_official | 579:53297373a894 | 933 | #define SERCOM_I2CM_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CM_STATUS offset) I2CM Status */ |
mbed_official | 579:53297373a894 | 934 | #define SERCOM_I2CM_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_I2CM_STATUS reset_value) I2CM Status */ |
mbed_official | 579:53297373a894 | 935 | |
mbed_official | 579:53297373a894 | 936 | #define SERCOM_I2CM_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CM_STATUS) Bus Error */ |
mbed_official | 579:53297373a894 | 937 | #define SERCOM_I2CM_STATUS_BUSERR (0x1ul << SERCOM_I2CM_STATUS_BUSERR_Pos) |
mbed_official | 579:53297373a894 | 938 | #define SERCOM_I2CM_STATUS_ARBLOST_Pos 1 /**< \brief (SERCOM_I2CM_STATUS) Arbitration Lost */ |
mbed_official | 579:53297373a894 | 939 | #define SERCOM_I2CM_STATUS_ARBLOST (0x1ul << SERCOM_I2CM_STATUS_ARBLOST_Pos) |
mbed_official | 579:53297373a894 | 940 | #define SERCOM_I2CM_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CM_STATUS) Received Not Acknowledge */ |
mbed_official | 579:53297373a894 | 941 | #define SERCOM_I2CM_STATUS_RXNACK (0x1ul << SERCOM_I2CM_STATUS_RXNACK_Pos) |
mbed_official | 579:53297373a894 | 942 | #define SERCOM_I2CM_STATUS_BUSSTATE_Pos 4 /**< \brief (SERCOM_I2CM_STATUS) Bus State */ |
mbed_official | 579:53297373a894 | 943 | #define SERCOM_I2CM_STATUS_BUSSTATE_Msk (0x3ul << SERCOM_I2CM_STATUS_BUSSTATE_Pos) |
mbed_official | 579:53297373a894 | 944 | #define SERCOM_I2CM_STATUS_BUSSTATE(value) ((SERCOM_I2CM_STATUS_BUSSTATE_Msk & ((value) << SERCOM_I2CM_STATUS_BUSSTATE_Pos))) |
mbed_official | 579:53297373a894 | 945 | #define SERCOM_I2CM_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CM_STATUS) SCL Low Timeout */ |
mbed_official | 579:53297373a894 | 946 | #define SERCOM_I2CM_STATUS_LOWTOUT (0x1ul << SERCOM_I2CM_STATUS_LOWTOUT_Pos) |
mbed_official | 579:53297373a894 | 947 | #define SERCOM_I2CM_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CM_STATUS) Clock Hold */ |
mbed_official | 579:53297373a894 | 948 | #define SERCOM_I2CM_STATUS_CLKHOLD (0x1ul << SERCOM_I2CM_STATUS_CLKHOLD_Pos) |
mbed_official | 579:53297373a894 | 949 | #define SERCOM_I2CM_STATUS_MEXTTOUT_Pos 8 /**< \brief (SERCOM_I2CM_STATUS) Master SCL Low Extend Timeout */ |
mbed_official | 579:53297373a894 | 950 | #define SERCOM_I2CM_STATUS_MEXTTOUT (0x1ul << SERCOM_I2CM_STATUS_MEXTTOUT_Pos) |
mbed_official | 579:53297373a894 | 951 | #define SERCOM_I2CM_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CM_STATUS) Slave SCL Low Extend Timeout */ |
mbed_official | 579:53297373a894 | 952 | #define SERCOM_I2CM_STATUS_SEXTTOUT (0x1ul << SERCOM_I2CM_STATUS_SEXTTOUT_Pos) |
mbed_official | 579:53297373a894 | 953 | #define SERCOM_I2CM_STATUS_LENERR_Pos 10 /**< \brief (SERCOM_I2CM_STATUS) Length Error */ |
mbed_official | 579:53297373a894 | 954 | #define SERCOM_I2CM_STATUS_LENERR (0x1ul << SERCOM_I2CM_STATUS_LENERR_Pos) |
mbed_official | 579:53297373a894 | 955 | #define SERCOM_I2CM_STATUS_MASK 0x07F7ul /**< \brief (SERCOM_I2CM_STATUS) MASK Register */ |
mbed_official | 579:53297373a894 | 956 | |
mbed_official | 579:53297373a894 | 957 | /* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CS I2CS Status -------- */ |
mbed_official | 579:53297373a894 | 958 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 959 | typedef union { |
mbed_official | 579:53297373a894 | 960 | struct { |
mbed_official | 579:53297373a894 | 961 | uint16_t BUSERR:1; /*!< bit: 0 Bus Error */ |
mbed_official | 579:53297373a894 | 962 | uint16_t COLL:1; /*!< bit: 1 Transmit Collision */ |
mbed_official | 579:53297373a894 | 963 | uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */ |
mbed_official | 579:53297373a894 | 964 | uint16_t DIR:1; /*!< bit: 3 Read/Write Direction */ |
mbed_official | 579:53297373a894 | 965 | uint16_t SR:1; /*!< bit: 4 Repeated Start */ |
mbed_official | 579:53297373a894 | 966 | uint16_t :1; /*!< bit: 5 Reserved */ |
mbed_official | 579:53297373a894 | 967 | uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */ |
mbed_official | 579:53297373a894 | 968 | uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */ |
mbed_official | 579:53297373a894 | 969 | uint16_t :1; /*!< bit: 8 Reserved */ |
mbed_official | 579:53297373a894 | 970 | uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */ |
mbed_official | 579:53297373a894 | 971 | uint16_t HS:1; /*!< bit: 10 High Speed */ |
mbed_official | 579:53297373a894 | 972 | uint16_t :5; /*!< bit: 11..15 Reserved */ |
mbed_official | 579:53297373a894 | 973 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 974 | uint16_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 975 | } SERCOM_I2CS_STATUS_Type; |
mbed_official | 579:53297373a894 | 976 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 977 | |
mbed_official | 579:53297373a894 | 978 | #define SERCOM_I2CS_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CS_STATUS offset) I2CS Status */ |
mbed_official | 579:53297373a894 | 979 | #define SERCOM_I2CS_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_I2CS_STATUS reset_value) I2CS Status */ |
mbed_official | 579:53297373a894 | 980 | |
mbed_official | 579:53297373a894 | 981 | #define SERCOM_I2CS_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CS_STATUS) Bus Error */ |
mbed_official | 579:53297373a894 | 982 | #define SERCOM_I2CS_STATUS_BUSERR (0x1ul << SERCOM_I2CS_STATUS_BUSERR_Pos) |
mbed_official | 579:53297373a894 | 983 | #define SERCOM_I2CS_STATUS_COLL_Pos 1 /**< \brief (SERCOM_I2CS_STATUS) Transmit Collision */ |
mbed_official | 579:53297373a894 | 984 | #define SERCOM_I2CS_STATUS_COLL (0x1ul << SERCOM_I2CS_STATUS_COLL_Pos) |
mbed_official | 579:53297373a894 | 985 | #define SERCOM_I2CS_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CS_STATUS) Received Not Acknowledge */ |
mbed_official | 579:53297373a894 | 986 | #define SERCOM_I2CS_STATUS_RXNACK (0x1ul << SERCOM_I2CS_STATUS_RXNACK_Pos) |
mbed_official | 579:53297373a894 | 987 | #define SERCOM_I2CS_STATUS_DIR_Pos 3 /**< \brief (SERCOM_I2CS_STATUS) Read/Write Direction */ |
mbed_official | 579:53297373a894 | 988 | #define SERCOM_I2CS_STATUS_DIR (0x1ul << SERCOM_I2CS_STATUS_DIR_Pos) |
mbed_official | 579:53297373a894 | 989 | #define SERCOM_I2CS_STATUS_SR_Pos 4 /**< \brief (SERCOM_I2CS_STATUS) Repeated Start */ |
mbed_official | 579:53297373a894 | 990 | #define SERCOM_I2CS_STATUS_SR (0x1ul << SERCOM_I2CS_STATUS_SR_Pos) |
mbed_official | 579:53297373a894 | 991 | #define SERCOM_I2CS_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CS_STATUS) SCL Low Timeout */ |
mbed_official | 579:53297373a894 | 992 | #define SERCOM_I2CS_STATUS_LOWTOUT (0x1ul << SERCOM_I2CS_STATUS_LOWTOUT_Pos) |
mbed_official | 579:53297373a894 | 993 | #define SERCOM_I2CS_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CS_STATUS) Clock Hold */ |
mbed_official | 579:53297373a894 | 994 | #define SERCOM_I2CS_STATUS_CLKHOLD (0x1ul << SERCOM_I2CS_STATUS_CLKHOLD_Pos) |
mbed_official | 579:53297373a894 | 995 | #define SERCOM_I2CS_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CS_STATUS) Slave SCL Low Extend Timeout */ |
mbed_official | 579:53297373a894 | 996 | #define SERCOM_I2CS_STATUS_SEXTTOUT (0x1ul << SERCOM_I2CS_STATUS_SEXTTOUT_Pos) |
mbed_official | 579:53297373a894 | 997 | #define SERCOM_I2CS_STATUS_HS_Pos 10 /**< \brief (SERCOM_I2CS_STATUS) High Speed */ |
mbed_official | 579:53297373a894 | 998 | #define SERCOM_I2CS_STATUS_HS (0x1ul << SERCOM_I2CS_STATUS_HS_Pos) |
mbed_official | 579:53297373a894 | 999 | #define SERCOM_I2CS_STATUS_MASK 0x06DFul /**< \brief (SERCOM_I2CS_STATUS) MASK Register */ |
mbed_official | 579:53297373a894 | 1000 | |
mbed_official | 579:53297373a894 | 1001 | /* -------- SERCOM_SPI_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPI SPI Status -------- */ |
mbed_official | 579:53297373a894 | 1002 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 1003 | typedef union { |
mbed_official | 579:53297373a894 | 1004 | struct { |
mbed_official | 579:53297373a894 | 1005 | uint16_t :2; /*!< bit: 0.. 1 Reserved */ |
mbed_official | 579:53297373a894 | 1006 | uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */ |
mbed_official | 579:53297373a894 | 1007 | uint16_t :13; /*!< bit: 3..15 Reserved */ |
mbed_official | 579:53297373a894 | 1008 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 1009 | uint16_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 1010 | } SERCOM_SPI_STATUS_Type; |
mbed_official | 579:53297373a894 | 1011 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 1012 | |
mbed_official | 579:53297373a894 | 1013 | #define SERCOM_SPI_STATUS_OFFSET 0x1A /**< \brief (SERCOM_SPI_STATUS offset) SPI Status */ |
mbed_official | 579:53297373a894 | 1014 | #define SERCOM_SPI_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_SPI_STATUS reset_value) SPI Status */ |
mbed_official | 579:53297373a894 | 1015 | |
mbed_official | 579:53297373a894 | 1016 | #define SERCOM_SPI_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_SPI_STATUS) Buffer Overflow */ |
mbed_official | 579:53297373a894 | 1017 | #define SERCOM_SPI_STATUS_BUFOVF (0x1ul << SERCOM_SPI_STATUS_BUFOVF_Pos) |
mbed_official | 579:53297373a894 | 1018 | #define SERCOM_SPI_STATUS_MASK 0x0004ul /**< \brief (SERCOM_SPI_STATUS) MASK Register */ |
mbed_official | 579:53297373a894 | 1019 | |
mbed_official | 579:53297373a894 | 1020 | /* -------- SERCOM_USART_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART USART Status -------- */ |
mbed_official | 579:53297373a894 | 1021 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 1022 | typedef union { |
mbed_official | 579:53297373a894 | 1023 | struct { |
mbed_official | 579:53297373a894 | 1024 | uint16_t PERR:1; /*!< bit: 0 Parity Error */ |
mbed_official | 579:53297373a894 | 1025 | uint16_t FERR:1; /*!< bit: 1 Frame Error */ |
mbed_official | 579:53297373a894 | 1026 | uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */ |
mbed_official | 579:53297373a894 | 1027 | uint16_t CTS:1; /*!< bit: 3 Clear To Send */ |
mbed_official | 579:53297373a894 | 1028 | uint16_t ISF:1; /*!< bit: 4 Inconsistent Sync Field */ |
mbed_official | 579:53297373a894 | 1029 | uint16_t COLL:1; /*!< bit: 5 Collision Detected */ |
mbed_official | 579:53297373a894 | 1030 | uint16_t :10; /*!< bit: 6..15 Reserved */ |
mbed_official | 579:53297373a894 | 1031 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 1032 | uint16_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 1033 | } SERCOM_USART_STATUS_Type; |
mbed_official | 579:53297373a894 | 1034 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 1035 | |
mbed_official | 579:53297373a894 | 1036 | #define SERCOM_USART_STATUS_OFFSET 0x1A /**< \brief (SERCOM_USART_STATUS offset) USART Status */ |
mbed_official | 579:53297373a894 | 1037 | #define SERCOM_USART_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_USART_STATUS reset_value) USART Status */ |
mbed_official | 579:53297373a894 | 1038 | |
mbed_official | 579:53297373a894 | 1039 | #define SERCOM_USART_STATUS_PERR_Pos 0 /**< \brief (SERCOM_USART_STATUS) Parity Error */ |
mbed_official | 579:53297373a894 | 1040 | #define SERCOM_USART_STATUS_PERR (0x1ul << SERCOM_USART_STATUS_PERR_Pos) |
mbed_official | 579:53297373a894 | 1041 | #define SERCOM_USART_STATUS_FERR_Pos 1 /**< \brief (SERCOM_USART_STATUS) Frame Error */ |
mbed_official | 579:53297373a894 | 1042 | #define SERCOM_USART_STATUS_FERR (0x1ul << SERCOM_USART_STATUS_FERR_Pos) |
mbed_official | 579:53297373a894 | 1043 | #define SERCOM_USART_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_USART_STATUS) Buffer Overflow */ |
mbed_official | 579:53297373a894 | 1044 | #define SERCOM_USART_STATUS_BUFOVF (0x1ul << SERCOM_USART_STATUS_BUFOVF_Pos) |
mbed_official | 579:53297373a894 | 1045 | #define SERCOM_USART_STATUS_CTS_Pos 3 /**< \brief (SERCOM_USART_STATUS) Clear To Send */ |
mbed_official | 579:53297373a894 | 1046 | #define SERCOM_USART_STATUS_CTS (0x1ul << SERCOM_USART_STATUS_CTS_Pos) |
mbed_official | 579:53297373a894 | 1047 | #define SERCOM_USART_STATUS_ISF_Pos 4 /**< \brief (SERCOM_USART_STATUS) Inconsistent Sync Field */ |
mbed_official | 579:53297373a894 | 1048 | #define SERCOM_USART_STATUS_ISF (0x1ul << SERCOM_USART_STATUS_ISF_Pos) |
mbed_official | 579:53297373a894 | 1049 | #define SERCOM_USART_STATUS_COLL_Pos 5 /**< \brief (SERCOM_USART_STATUS) Collision Detected */ |
mbed_official | 579:53297373a894 | 1050 | #define SERCOM_USART_STATUS_COLL (0x1ul << SERCOM_USART_STATUS_COLL_Pos) |
mbed_official | 579:53297373a894 | 1051 | #define SERCOM_USART_STATUS_MASK 0x003Ful /**< \brief (SERCOM_USART_STATUS) MASK Register */ |
mbed_official | 579:53297373a894 | 1052 | |
mbed_official | 579:53297373a894 | 1053 | /* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CM I2CM Syncbusy -------- */ |
mbed_official | 579:53297373a894 | 1054 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 1055 | typedef union { |
mbed_official | 579:53297373a894 | 1056 | struct { |
mbed_official | 579:53297373a894 | 1057 | uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ |
mbed_official | 579:53297373a894 | 1058 | uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ |
mbed_official | 579:53297373a894 | 1059 | uint32_t SYSOP:1; /*!< bit: 2 System Operation Synchronization Busy */ |
mbed_official | 579:53297373a894 | 1060 | uint32_t :29; /*!< bit: 3..31 Reserved */ |
mbed_official | 579:53297373a894 | 1061 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 1062 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 1063 | } SERCOM_I2CM_SYNCBUSY_Type; |
mbed_official | 579:53297373a894 | 1064 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 1065 | |
mbed_official | 579:53297373a894 | 1066 | #define SERCOM_I2CM_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CM_SYNCBUSY offset) I2CM Syncbusy */ |
mbed_official | 579:53297373a894 | 1067 | #define SERCOM_I2CM_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_SYNCBUSY reset_value) I2CM Syncbusy */ |
mbed_official | 579:53297373a894 | 1068 | |
mbed_official | 579:53297373a894 | 1069 | #define SERCOM_I2CM_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_SYNCBUSY) Software Reset Synchronization Busy */ |
mbed_official | 579:53297373a894 | 1070 | #define SERCOM_I2CM_SYNCBUSY_SWRST (0x1ul << SERCOM_I2CM_SYNCBUSY_SWRST_Pos) |
mbed_official | 579:53297373a894 | 1071 | #define SERCOM_I2CM_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_SYNCBUSY) SERCOM Enable Synchronization Busy */ |
mbed_official | 579:53297373a894 | 1072 | #define SERCOM_I2CM_SYNCBUSY_ENABLE (0x1ul << SERCOM_I2CM_SYNCBUSY_ENABLE_Pos) |
mbed_official | 579:53297373a894 | 1073 | #define SERCOM_I2CM_SYNCBUSY_SYSOP_Pos 2 /**< \brief (SERCOM_I2CM_SYNCBUSY) System Operation Synchronization Busy */ |
mbed_official | 579:53297373a894 | 1074 | #define SERCOM_I2CM_SYNCBUSY_SYSOP (0x1ul << SERCOM_I2CM_SYNCBUSY_SYSOP_Pos) |
mbed_official | 579:53297373a894 | 1075 | #define SERCOM_I2CM_SYNCBUSY_MASK 0x00000007ul /**< \brief (SERCOM_I2CM_SYNCBUSY) MASK Register */ |
mbed_official | 579:53297373a894 | 1076 | |
mbed_official | 579:53297373a894 | 1077 | /* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CS I2CS Syncbusy -------- */ |
mbed_official | 579:53297373a894 | 1078 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 1079 | typedef union { |
mbed_official | 579:53297373a894 | 1080 | struct { |
mbed_official | 579:53297373a894 | 1081 | uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ |
mbed_official | 579:53297373a894 | 1082 | uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ |
mbed_official | 579:53297373a894 | 1083 | uint32_t :30; /*!< bit: 2..31 Reserved */ |
mbed_official | 579:53297373a894 | 1084 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 1085 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 1086 | } SERCOM_I2CS_SYNCBUSY_Type; |
mbed_official | 579:53297373a894 | 1087 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 1088 | |
mbed_official | 579:53297373a894 | 1089 | #define SERCOM_I2CS_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CS_SYNCBUSY offset) I2CS Syncbusy */ |
mbed_official | 579:53297373a894 | 1090 | #define SERCOM_I2CS_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_SYNCBUSY reset_value) I2CS Syncbusy */ |
mbed_official | 579:53297373a894 | 1091 | |
mbed_official | 579:53297373a894 | 1092 | #define SERCOM_I2CS_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_SYNCBUSY) Software Reset Synchronization Busy */ |
mbed_official | 579:53297373a894 | 1093 | #define SERCOM_I2CS_SYNCBUSY_SWRST (0x1ul << SERCOM_I2CS_SYNCBUSY_SWRST_Pos) |
mbed_official | 579:53297373a894 | 1094 | #define SERCOM_I2CS_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_SYNCBUSY) SERCOM Enable Synchronization Busy */ |
mbed_official | 579:53297373a894 | 1095 | #define SERCOM_I2CS_SYNCBUSY_ENABLE (0x1ul << SERCOM_I2CS_SYNCBUSY_ENABLE_Pos) |
mbed_official | 579:53297373a894 | 1096 | #define SERCOM_I2CS_SYNCBUSY_MASK 0x00000003ul /**< \brief (SERCOM_I2CS_SYNCBUSY) MASK Register */ |
mbed_official | 579:53297373a894 | 1097 | |
mbed_official | 579:53297373a894 | 1098 | /* -------- SERCOM_SPI_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) SPI SPI Syncbusy -------- */ |
mbed_official | 579:53297373a894 | 1099 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 1100 | typedef union { |
mbed_official | 579:53297373a894 | 1101 | struct { |
mbed_official | 579:53297373a894 | 1102 | uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ |
mbed_official | 579:53297373a894 | 1103 | uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ |
mbed_official | 579:53297373a894 | 1104 | uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */ |
mbed_official | 579:53297373a894 | 1105 | uint32_t :29; /*!< bit: 3..31 Reserved */ |
mbed_official | 579:53297373a894 | 1106 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 1107 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 1108 | } SERCOM_SPI_SYNCBUSY_Type; |
mbed_official | 579:53297373a894 | 1109 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 1110 | |
mbed_official | 579:53297373a894 | 1111 | #define SERCOM_SPI_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_SPI_SYNCBUSY offset) SPI Syncbusy */ |
mbed_official | 579:53297373a894 | 1112 | #define SERCOM_SPI_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_SYNCBUSY reset_value) SPI Syncbusy */ |
mbed_official | 579:53297373a894 | 1113 | |
mbed_official | 579:53297373a894 | 1114 | #define SERCOM_SPI_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_SPI_SYNCBUSY) Software Reset Synchronization Busy */ |
mbed_official | 579:53297373a894 | 1115 | #define SERCOM_SPI_SYNCBUSY_SWRST (0x1ul << SERCOM_SPI_SYNCBUSY_SWRST_Pos) |
mbed_official | 579:53297373a894 | 1116 | #define SERCOM_SPI_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_SYNCBUSY) SERCOM Enable Synchronization Busy */ |
mbed_official | 579:53297373a894 | 1117 | #define SERCOM_SPI_SYNCBUSY_ENABLE (0x1ul << SERCOM_SPI_SYNCBUSY_ENABLE_Pos) |
mbed_official | 579:53297373a894 | 1118 | #define SERCOM_SPI_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_SPI_SYNCBUSY) CTRLB Synchronization Busy */ |
mbed_official | 579:53297373a894 | 1119 | #define SERCOM_SPI_SYNCBUSY_CTRLB (0x1ul << SERCOM_SPI_SYNCBUSY_CTRLB_Pos) |
mbed_official | 579:53297373a894 | 1120 | #define SERCOM_SPI_SYNCBUSY_MASK 0x00000007ul /**< \brief (SERCOM_SPI_SYNCBUSY) MASK Register */ |
mbed_official | 579:53297373a894 | 1121 | |
mbed_official | 579:53297373a894 | 1122 | /* -------- SERCOM_USART_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) USART USART Syncbusy -------- */ |
mbed_official | 579:53297373a894 | 1123 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 1124 | typedef union { |
mbed_official | 579:53297373a894 | 1125 | struct { |
mbed_official | 579:53297373a894 | 1126 | uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ |
mbed_official | 579:53297373a894 | 1127 | uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ |
mbed_official | 579:53297373a894 | 1128 | uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */ |
mbed_official | 579:53297373a894 | 1129 | uint32_t :29; /*!< bit: 3..31 Reserved */ |
mbed_official | 579:53297373a894 | 1130 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 1131 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 1132 | } SERCOM_USART_SYNCBUSY_Type; |
mbed_official | 579:53297373a894 | 1133 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 1134 | |
mbed_official | 579:53297373a894 | 1135 | #define SERCOM_USART_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_USART_SYNCBUSY offset) USART Syncbusy */ |
mbed_official | 579:53297373a894 | 1136 | #define SERCOM_USART_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_SYNCBUSY reset_value) USART Syncbusy */ |
mbed_official | 579:53297373a894 | 1137 | |
mbed_official | 579:53297373a894 | 1138 | #define SERCOM_USART_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_USART_SYNCBUSY) Software Reset Synchronization Busy */ |
mbed_official | 579:53297373a894 | 1139 | #define SERCOM_USART_SYNCBUSY_SWRST (0x1ul << SERCOM_USART_SYNCBUSY_SWRST_Pos) |
mbed_official | 579:53297373a894 | 1140 | #define SERCOM_USART_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_USART_SYNCBUSY) SERCOM Enable Synchronization Busy */ |
mbed_official | 579:53297373a894 | 1141 | #define SERCOM_USART_SYNCBUSY_ENABLE (0x1ul << SERCOM_USART_SYNCBUSY_ENABLE_Pos) |
mbed_official | 579:53297373a894 | 1142 | #define SERCOM_USART_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_USART_SYNCBUSY) CTRLB Synchronization Busy */ |
mbed_official | 579:53297373a894 | 1143 | #define SERCOM_USART_SYNCBUSY_CTRLB (0x1ul << SERCOM_USART_SYNCBUSY_CTRLB_Pos) |
mbed_official | 579:53297373a894 | 1144 | #define SERCOM_USART_SYNCBUSY_MASK 0x00000007ul /**< \brief (SERCOM_USART_SYNCBUSY) MASK Register */ |
mbed_official | 579:53297373a894 | 1145 | |
mbed_official | 579:53297373a894 | 1146 | /* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CM I2CM Address -------- */ |
mbed_official | 579:53297373a894 | 1147 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 1148 | typedef union { |
mbed_official | 579:53297373a894 | 1149 | struct { |
mbed_official | 579:53297373a894 | 1150 | uint32_t ADDR:11; /*!< bit: 0..10 Address Value */ |
mbed_official | 579:53297373a894 | 1151 | uint32_t :2; /*!< bit: 11..12 Reserved */ |
mbed_official | 579:53297373a894 | 1152 | uint32_t LENEN:1; /*!< bit: 13 Length Enable */ |
mbed_official | 579:53297373a894 | 1153 | uint32_t HS:1; /*!< bit: 14 High Speed Mode */ |
mbed_official | 579:53297373a894 | 1154 | uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */ |
mbed_official | 579:53297373a894 | 1155 | uint32_t LEN:8; /*!< bit: 16..23 Length */ |
mbed_official | 579:53297373a894 | 1156 | uint32_t :8; /*!< bit: 24..31 Reserved */ |
mbed_official | 579:53297373a894 | 1157 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 1158 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 1159 | } SERCOM_I2CM_ADDR_Type; |
mbed_official | 579:53297373a894 | 1160 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 1161 | |
mbed_official | 579:53297373a894 | 1162 | #define SERCOM_I2CM_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CM_ADDR offset) I2CM Address */ |
mbed_official | 579:53297373a894 | 1163 | #define SERCOM_I2CM_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_ADDR reset_value) I2CM Address */ |
mbed_official | 579:53297373a894 | 1164 | |
mbed_official | 579:53297373a894 | 1165 | #define SERCOM_I2CM_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_I2CM_ADDR) Address Value */ |
mbed_official | 579:53297373a894 | 1166 | #define SERCOM_I2CM_ADDR_ADDR_Msk (0x7FFul << SERCOM_I2CM_ADDR_ADDR_Pos) |
mbed_official | 579:53297373a894 | 1167 | #define SERCOM_I2CM_ADDR_ADDR(value) ((SERCOM_I2CM_ADDR_ADDR_Msk & ((value) << SERCOM_I2CM_ADDR_ADDR_Pos))) |
mbed_official | 579:53297373a894 | 1168 | #define SERCOM_I2CM_ADDR_LENEN_Pos 13 /**< \brief (SERCOM_I2CM_ADDR) Length Enable */ |
mbed_official | 579:53297373a894 | 1169 | #define SERCOM_I2CM_ADDR_LENEN (0x1ul << SERCOM_I2CM_ADDR_LENEN_Pos) |
mbed_official | 579:53297373a894 | 1170 | #define SERCOM_I2CM_ADDR_HS_Pos 14 /**< \brief (SERCOM_I2CM_ADDR) High Speed Mode */ |
mbed_official | 579:53297373a894 | 1171 | #define SERCOM_I2CM_ADDR_HS (0x1ul << SERCOM_I2CM_ADDR_HS_Pos) |
mbed_official | 579:53297373a894 | 1172 | #define SERCOM_I2CM_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CM_ADDR) Ten Bit Addressing Enable */ |
mbed_official | 579:53297373a894 | 1173 | #define SERCOM_I2CM_ADDR_TENBITEN (0x1ul << SERCOM_I2CM_ADDR_TENBITEN_Pos) |
mbed_official | 579:53297373a894 | 1174 | #define SERCOM_I2CM_ADDR_LEN_Pos 16 /**< \brief (SERCOM_I2CM_ADDR) Length */ |
mbed_official | 579:53297373a894 | 1175 | #define SERCOM_I2CM_ADDR_LEN_Msk (0xFFul << SERCOM_I2CM_ADDR_LEN_Pos) |
mbed_official | 579:53297373a894 | 1176 | #define SERCOM_I2CM_ADDR_LEN(value) ((SERCOM_I2CM_ADDR_LEN_Msk & ((value) << SERCOM_I2CM_ADDR_LEN_Pos))) |
mbed_official | 579:53297373a894 | 1177 | #define SERCOM_I2CM_ADDR_MASK 0x00FFE7FFul /**< \brief (SERCOM_I2CM_ADDR) MASK Register */ |
mbed_official | 579:53297373a894 | 1178 | |
mbed_official | 579:53297373a894 | 1179 | /* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS I2CS Address -------- */ |
mbed_official | 579:53297373a894 | 1180 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 1181 | typedef union { |
mbed_official | 579:53297373a894 | 1182 | struct { |
mbed_official | 579:53297373a894 | 1183 | uint32_t GENCEN:1; /*!< bit: 0 General Call Address Enable */ |
mbed_official | 579:53297373a894 | 1184 | uint32_t ADDR:10; /*!< bit: 1..10 Address Value */ |
mbed_official | 579:53297373a894 | 1185 | uint32_t :4; /*!< bit: 11..14 Reserved */ |
mbed_official | 579:53297373a894 | 1186 | uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */ |
mbed_official | 579:53297373a894 | 1187 | uint32_t :1; /*!< bit: 16 Reserved */ |
mbed_official | 579:53297373a894 | 1188 | uint32_t ADDRMASK:10; /*!< bit: 17..26 Address Mask */ |
mbed_official | 579:53297373a894 | 1189 | uint32_t :5; /*!< bit: 27..31 Reserved */ |
mbed_official | 579:53297373a894 | 1190 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 1191 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 1192 | } SERCOM_I2CS_ADDR_Type; |
mbed_official | 579:53297373a894 | 1193 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 1194 | |
mbed_official | 579:53297373a894 | 1195 | #define SERCOM_I2CS_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CS_ADDR offset) I2CS Address */ |
mbed_official | 579:53297373a894 | 1196 | #define SERCOM_I2CS_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_ADDR reset_value) I2CS Address */ |
mbed_official | 579:53297373a894 | 1197 | |
mbed_official | 579:53297373a894 | 1198 | #define SERCOM_I2CS_ADDR_GENCEN_Pos 0 /**< \brief (SERCOM_I2CS_ADDR) General Call Address Enable */ |
mbed_official | 579:53297373a894 | 1199 | #define SERCOM_I2CS_ADDR_GENCEN (0x1ul << SERCOM_I2CS_ADDR_GENCEN_Pos) |
mbed_official | 579:53297373a894 | 1200 | #define SERCOM_I2CS_ADDR_ADDR_Pos 1 /**< \brief (SERCOM_I2CS_ADDR) Address Value */ |
mbed_official | 579:53297373a894 | 1201 | #define SERCOM_I2CS_ADDR_ADDR_Msk (0x3FFul << SERCOM_I2CS_ADDR_ADDR_Pos) |
mbed_official | 579:53297373a894 | 1202 | #define SERCOM_I2CS_ADDR_ADDR(value) ((SERCOM_I2CS_ADDR_ADDR_Msk & ((value) << SERCOM_I2CS_ADDR_ADDR_Pos))) |
mbed_official | 579:53297373a894 | 1203 | #define SERCOM_I2CS_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CS_ADDR) Ten Bit Addressing Enable */ |
mbed_official | 579:53297373a894 | 1204 | #define SERCOM_I2CS_ADDR_TENBITEN (0x1ul << SERCOM_I2CS_ADDR_TENBITEN_Pos) |
mbed_official | 579:53297373a894 | 1205 | #define SERCOM_I2CS_ADDR_ADDRMASK_Pos 17 /**< \brief (SERCOM_I2CS_ADDR) Address Mask */ |
mbed_official | 579:53297373a894 | 1206 | #define SERCOM_I2CS_ADDR_ADDRMASK_Msk (0x3FFul << SERCOM_I2CS_ADDR_ADDRMASK_Pos) |
mbed_official | 579:53297373a894 | 1207 | #define SERCOM_I2CS_ADDR_ADDRMASK(value) ((SERCOM_I2CS_ADDR_ADDRMASK_Msk & ((value) << SERCOM_I2CS_ADDR_ADDRMASK_Pos))) |
mbed_official | 579:53297373a894 | 1208 | #define SERCOM_I2CS_ADDR_MASK 0x07FE87FFul /**< \brief (SERCOM_I2CS_ADDR) MASK Register */ |
mbed_official | 579:53297373a894 | 1209 | |
mbed_official | 579:53297373a894 | 1210 | /* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPI SPI Address -------- */ |
mbed_official | 579:53297373a894 | 1211 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 1212 | typedef union { |
mbed_official | 579:53297373a894 | 1213 | struct { |
mbed_official | 579:53297373a894 | 1214 | uint32_t ADDR:8; /*!< bit: 0.. 7 Address Value */ |
mbed_official | 579:53297373a894 | 1215 | uint32_t :8; /*!< bit: 8..15 Reserved */ |
mbed_official | 579:53297373a894 | 1216 | uint32_t ADDRMASK:8; /*!< bit: 16..23 Address Mask */ |
mbed_official | 579:53297373a894 | 1217 | uint32_t :8; /*!< bit: 24..31 Reserved */ |
mbed_official | 579:53297373a894 | 1218 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 1219 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 1220 | } SERCOM_SPI_ADDR_Type; |
mbed_official | 579:53297373a894 | 1221 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 1222 | |
mbed_official | 579:53297373a894 | 1223 | #define SERCOM_SPI_ADDR_OFFSET 0x24 /**< \brief (SERCOM_SPI_ADDR offset) SPI Address */ |
mbed_official | 579:53297373a894 | 1224 | #define SERCOM_SPI_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_ADDR reset_value) SPI Address */ |
mbed_official | 579:53297373a894 | 1225 | |
mbed_official | 579:53297373a894 | 1226 | #define SERCOM_SPI_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_SPI_ADDR) Address Value */ |
mbed_official | 579:53297373a894 | 1227 | #define SERCOM_SPI_ADDR_ADDR_Msk (0xFFul << SERCOM_SPI_ADDR_ADDR_Pos) |
mbed_official | 579:53297373a894 | 1228 | #define SERCOM_SPI_ADDR_ADDR(value) ((SERCOM_SPI_ADDR_ADDR_Msk & ((value) << SERCOM_SPI_ADDR_ADDR_Pos))) |
mbed_official | 579:53297373a894 | 1229 | #define SERCOM_SPI_ADDR_ADDRMASK_Pos 16 /**< \brief (SERCOM_SPI_ADDR) Address Mask */ |
mbed_official | 579:53297373a894 | 1230 | #define SERCOM_SPI_ADDR_ADDRMASK_Msk (0xFFul << SERCOM_SPI_ADDR_ADDRMASK_Pos) |
mbed_official | 579:53297373a894 | 1231 | #define SERCOM_SPI_ADDR_ADDRMASK(value) ((SERCOM_SPI_ADDR_ADDRMASK_Msk & ((value) << SERCOM_SPI_ADDR_ADDRMASK_Pos))) |
mbed_official | 579:53297373a894 | 1232 | #define SERCOM_SPI_ADDR_MASK 0x00FF00FFul /**< \brief (SERCOM_SPI_ADDR) MASK Register */ |
mbed_official | 579:53297373a894 | 1233 | |
mbed_official | 579:53297373a894 | 1234 | /* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CM I2CM Data -------- */ |
mbed_official | 579:53297373a894 | 1235 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 1236 | typedef union { |
mbed_official | 579:53297373a894 | 1237 | struct { |
mbed_official | 579:53297373a894 | 1238 | uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */ |
mbed_official | 579:53297373a894 | 1239 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 1240 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 1241 | } SERCOM_I2CM_DATA_Type; |
mbed_official | 579:53297373a894 | 1242 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 1243 | |
mbed_official | 579:53297373a894 | 1244 | #define SERCOM_I2CM_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CM_DATA offset) I2CM Data */ |
mbed_official | 579:53297373a894 | 1245 | #define SERCOM_I2CM_DATA_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_DATA reset_value) I2CM Data */ |
mbed_official | 579:53297373a894 | 1246 | |
mbed_official | 579:53297373a894 | 1247 | #define SERCOM_I2CM_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CM_DATA) Data Value */ |
mbed_official | 579:53297373a894 | 1248 | #define SERCOM_I2CM_DATA_DATA_Msk (0xFFul << SERCOM_I2CM_DATA_DATA_Pos) |
mbed_official | 579:53297373a894 | 1249 | #define SERCOM_I2CM_DATA_DATA(value) ((SERCOM_I2CM_DATA_DATA_Msk & ((value) << SERCOM_I2CM_DATA_DATA_Pos))) |
mbed_official | 579:53297373a894 | 1250 | #define SERCOM_I2CM_DATA_MASK 0xFFul /**< \brief (SERCOM_I2CM_DATA) MASK Register */ |
mbed_official | 579:53297373a894 | 1251 | |
mbed_official | 579:53297373a894 | 1252 | /* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CS I2CS Data -------- */ |
mbed_official | 579:53297373a894 | 1253 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 1254 | typedef union { |
mbed_official | 579:53297373a894 | 1255 | struct { |
mbed_official | 579:53297373a894 | 1256 | uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */ |
mbed_official | 579:53297373a894 | 1257 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 1258 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 1259 | } SERCOM_I2CS_DATA_Type; |
mbed_official | 579:53297373a894 | 1260 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 1261 | |
mbed_official | 579:53297373a894 | 1262 | #define SERCOM_I2CS_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CS_DATA offset) I2CS Data */ |
mbed_official | 579:53297373a894 | 1263 | #define SERCOM_I2CS_DATA_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_DATA reset_value) I2CS Data */ |
mbed_official | 579:53297373a894 | 1264 | |
mbed_official | 579:53297373a894 | 1265 | #define SERCOM_I2CS_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CS_DATA) Data Value */ |
mbed_official | 579:53297373a894 | 1266 | #define SERCOM_I2CS_DATA_DATA_Msk (0xFFul << SERCOM_I2CS_DATA_DATA_Pos) |
mbed_official | 579:53297373a894 | 1267 | #define SERCOM_I2CS_DATA_DATA(value) ((SERCOM_I2CS_DATA_DATA_Msk & ((value) << SERCOM_I2CS_DATA_DATA_Pos))) |
mbed_official | 579:53297373a894 | 1268 | #define SERCOM_I2CS_DATA_MASK 0xFFul /**< \brief (SERCOM_I2CS_DATA) MASK Register */ |
mbed_official | 579:53297373a894 | 1269 | |
mbed_official | 579:53297373a894 | 1270 | /* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x28) (R/W 32) SPI SPI Data -------- */ |
mbed_official | 579:53297373a894 | 1271 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 1272 | typedef union { |
mbed_official | 579:53297373a894 | 1273 | struct { |
mbed_official | 579:53297373a894 | 1274 | uint32_t DATA:9; /*!< bit: 0.. 8 Data Value */ |
mbed_official | 579:53297373a894 | 1275 | uint32_t :23; /*!< bit: 9..31 Reserved */ |
mbed_official | 579:53297373a894 | 1276 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 1277 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 1278 | } SERCOM_SPI_DATA_Type; |
mbed_official | 579:53297373a894 | 1279 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 1280 | |
mbed_official | 579:53297373a894 | 1281 | #define SERCOM_SPI_DATA_OFFSET 0x28 /**< \brief (SERCOM_SPI_DATA offset) SPI Data */ |
mbed_official | 579:53297373a894 | 1282 | #define SERCOM_SPI_DATA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_DATA reset_value) SPI Data */ |
mbed_official | 579:53297373a894 | 1283 | |
mbed_official | 579:53297373a894 | 1284 | #define SERCOM_SPI_DATA_DATA_Pos 0 /**< \brief (SERCOM_SPI_DATA) Data Value */ |
mbed_official | 579:53297373a894 | 1285 | #define SERCOM_SPI_DATA_DATA_Msk (0x1FFul << SERCOM_SPI_DATA_DATA_Pos) |
mbed_official | 579:53297373a894 | 1286 | #define SERCOM_SPI_DATA_DATA(value) ((SERCOM_SPI_DATA_DATA_Msk & ((value) << SERCOM_SPI_DATA_DATA_Pos))) |
mbed_official | 579:53297373a894 | 1287 | #define SERCOM_SPI_DATA_MASK 0x000001FFul /**< \brief (SERCOM_SPI_DATA) MASK Register */ |
mbed_official | 579:53297373a894 | 1288 | |
mbed_official | 579:53297373a894 | 1289 | /* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x28) (R/W 16) USART USART Data -------- */ |
mbed_official | 579:53297373a894 | 1290 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 1291 | typedef union { |
mbed_official | 579:53297373a894 | 1292 | struct { |
mbed_official | 579:53297373a894 | 1293 | uint16_t DATA:9; /*!< bit: 0.. 8 Data Value */ |
mbed_official | 579:53297373a894 | 1294 | uint16_t :7; /*!< bit: 9..15 Reserved */ |
mbed_official | 579:53297373a894 | 1295 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 1296 | uint16_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 1297 | } SERCOM_USART_DATA_Type; |
mbed_official | 579:53297373a894 | 1298 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 1299 | |
mbed_official | 579:53297373a894 | 1300 | #define SERCOM_USART_DATA_OFFSET 0x28 /**< \brief (SERCOM_USART_DATA offset) USART Data */ |
mbed_official | 579:53297373a894 | 1301 | #define SERCOM_USART_DATA_RESETVALUE 0x0000ul /**< \brief (SERCOM_USART_DATA reset_value) USART Data */ |
mbed_official | 579:53297373a894 | 1302 | |
mbed_official | 579:53297373a894 | 1303 | #define SERCOM_USART_DATA_DATA_Pos 0 /**< \brief (SERCOM_USART_DATA) Data Value */ |
mbed_official | 579:53297373a894 | 1304 | #define SERCOM_USART_DATA_DATA_Msk (0x1FFul << SERCOM_USART_DATA_DATA_Pos) |
mbed_official | 579:53297373a894 | 1305 | #define SERCOM_USART_DATA_DATA(value) ((SERCOM_USART_DATA_DATA_Msk & ((value) << SERCOM_USART_DATA_DATA_Pos))) |
mbed_official | 579:53297373a894 | 1306 | #define SERCOM_USART_DATA_MASK 0x01FFul /**< \brief (SERCOM_USART_DATA) MASK Register */ |
mbed_official | 579:53297373a894 | 1307 | |
mbed_official | 579:53297373a894 | 1308 | /* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) I2CM I2CM Debug Control -------- */ |
mbed_official | 579:53297373a894 | 1309 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 1310 | typedef union { |
mbed_official | 579:53297373a894 | 1311 | struct { |
mbed_official | 579:53297373a894 | 1312 | uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ |
mbed_official | 579:53297373a894 | 1313 | uint8_t :7; /*!< bit: 1.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 1314 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 1315 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 1316 | } SERCOM_I2CM_DBGCTRL_Type; |
mbed_official | 579:53297373a894 | 1317 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 1318 | |
mbed_official | 579:53297373a894 | 1319 | #define SERCOM_I2CM_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_I2CM_DBGCTRL offset) I2CM Debug Control */ |
mbed_official | 579:53297373a894 | 1320 | #define SERCOM_I2CM_DBGCTRL_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_DBGCTRL reset_value) I2CM Debug Control */ |
mbed_official | 579:53297373a894 | 1321 | |
mbed_official | 579:53297373a894 | 1322 | #define SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_I2CM_DBGCTRL) Debug Mode */ |
mbed_official | 579:53297373a894 | 1323 | #define SERCOM_I2CM_DBGCTRL_DBGSTOP (0x1ul << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos) |
mbed_official | 579:53297373a894 | 1324 | #define SERCOM_I2CM_DBGCTRL_MASK 0x01ul /**< \brief (SERCOM_I2CM_DBGCTRL) MASK Register */ |
mbed_official | 579:53297373a894 | 1325 | |
mbed_official | 579:53297373a894 | 1326 | /* -------- SERCOM_SPI_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) SPI SPI Debug Control -------- */ |
mbed_official | 579:53297373a894 | 1327 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 1328 | typedef union { |
mbed_official | 579:53297373a894 | 1329 | struct { |
mbed_official | 579:53297373a894 | 1330 | uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ |
mbed_official | 579:53297373a894 | 1331 | uint8_t :7; /*!< bit: 1.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 1332 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 1333 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 1334 | } SERCOM_SPI_DBGCTRL_Type; |
mbed_official | 579:53297373a894 | 1335 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 1336 | |
mbed_official | 579:53297373a894 | 1337 | #define SERCOM_SPI_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_SPI_DBGCTRL offset) SPI Debug Control */ |
mbed_official | 579:53297373a894 | 1338 | #define SERCOM_SPI_DBGCTRL_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_DBGCTRL reset_value) SPI Debug Control */ |
mbed_official | 579:53297373a894 | 1339 | |
mbed_official | 579:53297373a894 | 1340 | #define SERCOM_SPI_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_SPI_DBGCTRL) Debug Mode */ |
mbed_official | 579:53297373a894 | 1341 | #define SERCOM_SPI_DBGCTRL_DBGSTOP (0x1ul << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos) |
mbed_official | 579:53297373a894 | 1342 | #define SERCOM_SPI_DBGCTRL_MASK 0x01ul /**< \brief (SERCOM_SPI_DBGCTRL) MASK Register */ |
mbed_official | 579:53297373a894 | 1343 | |
mbed_official | 579:53297373a894 | 1344 | /* -------- SERCOM_USART_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) USART USART Debug Control -------- */ |
mbed_official | 579:53297373a894 | 1345 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 1346 | typedef union { |
mbed_official | 579:53297373a894 | 1347 | struct { |
mbed_official | 579:53297373a894 | 1348 | uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ |
mbed_official | 579:53297373a894 | 1349 | uint8_t :7; /*!< bit: 1.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 1350 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 1351 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 1352 | } SERCOM_USART_DBGCTRL_Type; |
mbed_official | 579:53297373a894 | 1353 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 1354 | |
mbed_official | 579:53297373a894 | 1355 | #define SERCOM_USART_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_USART_DBGCTRL offset) USART Debug Control */ |
mbed_official | 579:53297373a894 | 1356 | #define SERCOM_USART_DBGCTRL_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_DBGCTRL reset_value) USART Debug Control */ |
mbed_official | 579:53297373a894 | 1357 | |
mbed_official | 579:53297373a894 | 1358 | #define SERCOM_USART_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_USART_DBGCTRL) Debug Mode */ |
mbed_official | 579:53297373a894 | 1359 | #define SERCOM_USART_DBGCTRL_DBGSTOP (0x1ul << SERCOM_USART_DBGCTRL_DBGSTOP_Pos) |
mbed_official | 579:53297373a894 | 1360 | #define SERCOM_USART_DBGCTRL_MASK 0x01ul /**< \brief (SERCOM_USART_DBGCTRL) MASK Register */ |
mbed_official | 579:53297373a894 | 1361 | |
mbed_official | 579:53297373a894 | 1362 | /** \brief SERCOM_I2CM hardware registers */ |
mbed_official | 579:53297373a894 | 1363 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 1364 | typedef struct { /* I2C Master Mode */ |
mbed_official | 579:53297373a894 | 1365 | __IO SERCOM_I2CM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */ |
mbed_official | 579:53297373a894 | 1366 | __IO SERCOM_I2CM_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */ |
mbed_official | 579:53297373a894 | 1367 | RoReg8 Reserved1[0x4]; |
mbed_official | 579:53297373a894 | 1368 | __IO SERCOM_I2CM_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */ |
mbed_official | 579:53297373a894 | 1369 | RoReg8 Reserved2[0x4]; |
mbed_official | 579:53297373a894 | 1370 | __IO SERCOM_I2CM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CM Interrupt Enable Clear */ |
mbed_official | 579:53297373a894 | 1371 | RoReg8 Reserved3[0x1]; |
mbed_official | 579:53297373a894 | 1372 | __IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CM Interrupt Enable Set */ |
mbed_official | 579:53297373a894 | 1373 | RoReg8 Reserved4[0x1]; |
mbed_official | 579:53297373a894 | 1374 | __IO SERCOM_I2CM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CM Interrupt Flag Status and Clear */ |
mbed_official | 579:53297373a894 | 1375 | RoReg8 Reserved5[0x1]; |
mbed_official | 579:53297373a894 | 1376 | __IO SERCOM_I2CM_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CM Status */ |
mbed_official | 579:53297373a894 | 1377 | __I SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CM Syncbusy */ |
mbed_official | 579:53297373a894 | 1378 | RoReg8 Reserved6[0x4]; |
mbed_official | 579:53297373a894 | 1379 | __IO SERCOM_I2CM_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CM Address */ |
mbed_official | 579:53297373a894 | 1380 | __IO SERCOM_I2CM_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CM Data */ |
mbed_official | 579:53297373a894 | 1381 | RoReg8 Reserved7[0x7]; |
mbed_official | 579:53297373a894 | 1382 | __IO SERCOM_I2CM_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) I2CM Debug Control */ |
mbed_official | 579:53297373a894 | 1383 | } SercomI2cm; |
mbed_official | 579:53297373a894 | 1384 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 1385 | |
mbed_official | 579:53297373a894 | 1386 | /** \brief SERCOM_I2CS hardware registers */ |
mbed_official | 579:53297373a894 | 1387 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 1388 | typedef struct { /* I2C Slave Mode */ |
mbed_official | 579:53297373a894 | 1389 | __IO SERCOM_I2CS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */ |
mbed_official | 579:53297373a894 | 1390 | __IO SERCOM_I2CS_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */ |
mbed_official | 579:53297373a894 | 1391 | RoReg8 Reserved1[0xC]; |
mbed_official | 579:53297373a894 | 1392 | __IO SERCOM_I2CS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CS Interrupt Enable Clear */ |
mbed_official | 579:53297373a894 | 1393 | RoReg8 Reserved2[0x1]; |
mbed_official | 579:53297373a894 | 1394 | __IO SERCOM_I2CS_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CS Interrupt Enable Set */ |
mbed_official | 579:53297373a894 | 1395 | RoReg8 Reserved3[0x1]; |
mbed_official | 579:53297373a894 | 1396 | __IO SERCOM_I2CS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CS Interrupt Flag Status and Clear */ |
mbed_official | 579:53297373a894 | 1397 | RoReg8 Reserved4[0x1]; |
mbed_official | 579:53297373a894 | 1398 | __IO SERCOM_I2CS_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CS Status */ |
mbed_official | 579:53297373a894 | 1399 | __I SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CS Syncbusy */ |
mbed_official | 579:53297373a894 | 1400 | RoReg8 Reserved5[0x4]; |
mbed_official | 579:53297373a894 | 1401 | __IO SERCOM_I2CS_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CS Address */ |
mbed_official | 579:53297373a894 | 1402 | __IO SERCOM_I2CS_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CS Data */ |
mbed_official | 579:53297373a894 | 1403 | } SercomI2cs; |
mbed_official | 579:53297373a894 | 1404 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 1405 | |
mbed_official | 579:53297373a894 | 1406 | /** \brief SERCOM_SPI hardware registers */ |
mbed_official | 579:53297373a894 | 1407 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 1408 | typedef struct { /* SPI Mode */ |
mbed_official | 579:53297373a894 | 1409 | __IO SERCOM_SPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) SPI Control A */ |
mbed_official | 579:53297373a894 | 1410 | __IO SERCOM_SPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) SPI Control B */ |
mbed_official | 579:53297373a894 | 1411 | RoReg8 Reserved1[0x4]; |
mbed_official | 579:53297373a894 | 1412 | __IO SERCOM_SPI_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 8) SPI Baud Rate */ |
mbed_official | 579:53297373a894 | 1413 | RoReg8 Reserved2[0x7]; |
mbed_official | 579:53297373a894 | 1414 | __IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) SPI Interrupt Enable Clear */ |
mbed_official | 579:53297373a894 | 1415 | RoReg8 Reserved3[0x1]; |
mbed_official | 579:53297373a894 | 1416 | __IO SERCOM_SPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) SPI Interrupt Enable Set */ |
mbed_official | 579:53297373a894 | 1417 | RoReg8 Reserved4[0x1]; |
mbed_official | 579:53297373a894 | 1418 | __IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) SPI Interrupt Flag Status and Clear */ |
mbed_official | 579:53297373a894 | 1419 | RoReg8 Reserved5[0x1]; |
mbed_official | 579:53297373a894 | 1420 | __IO SERCOM_SPI_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) SPI Status */ |
mbed_official | 579:53297373a894 | 1421 | __I SERCOM_SPI_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) SPI Syncbusy */ |
mbed_official | 579:53297373a894 | 1422 | RoReg8 Reserved6[0x4]; |
mbed_official | 579:53297373a894 | 1423 | __IO SERCOM_SPI_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) SPI Address */ |
mbed_official | 579:53297373a894 | 1424 | __IO SERCOM_SPI_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) SPI Data */ |
mbed_official | 579:53297373a894 | 1425 | RoReg8 Reserved7[0x4]; |
mbed_official | 579:53297373a894 | 1426 | __IO SERCOM_SPI_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) SPI Debug Control */ |
mbed_official | 579:53297373a894 | 1427 | } SercomSpi; |
mbed_official | 579:53297373a894 | 1428 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 1429 | |
mbed_official | 579:53297373a894 | 1430 | /** \brief SERCOM_USART hardware registers */ |
mbed_official | 579:53297373a894 | 1431 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 1432 | typedef struct { /* USART Mode */ |
mbed_official | 579:53297373a894 | 1433 | __IO SERCOM_USART_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) USART Control A */ |
mbed_official | 579:53297373a894 | 1434 | __IO SERCOM_USART_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) USART Control B */ |
mbed_official | 579:53297373a894 | 1435 | RoReg8 Reserved1[0x4]; |
mbed_official | 579:53297373a894 | 1436 | __IO SERCOM_USART_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */ |
mbed_official | 579:53297373a894 | 1437 | __IO SERCOM_USART_RXPL_Type RXPL; /**< \brief Offset: 0x0E (R/W 8) USART Receive Pulse Length */ |
mbed_official | 579:53297373a894 | 1438 | RoReg8 Reserved2[0x5]; |
mbed_official | 579:53297373a894 | 1439 | __IO SERCOM_USART_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) USART Interrupt Enable Clear */ |
mbed_official | 579:53297373a894 | 1440 | RoReg8 Reserved3[0x1]; |
mbed_official | 579:53297373a894 | 1441 | __IO SERCOM_USART_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) USART Interrupt Enable Set */ |
mbed_official | 579:53297373a894 | 1442 | RoReg8 Reserved4[0x1]; |
mbed_official | 579:53297373a894 | 1443 | __IO SERCOM_USART_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) USART Interrupt Flag Status and Clear */ |
mbed_official | 579:53297373a894 | 1444 | RoReg8 Reserved5[0x1]; |
mbed_official | 579:53297373a894 | 1445 | __IO SERCOM_USART_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) USART Status */ |
mbed_official | 579:53297373a894 | 1446 | __I SERCOM_USART_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) USART Syncbusy */ |
mbed_official | 579:53297373a894 | 1447 | RoReg8 Reserved6[0x8]; |
mbed_official | 579:53297373a894 | 1448 | __IO SERCOM_USART_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 16) USART Data */ |
mbed_official | 579:53297373a894 | 1449 | RoReg8 Reserved7[0x6]; |
mbed_official | 579:53297373a894 | 1450 | __IO SERCOM_USART_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) USART Debug Control */ |
mbed_official | 579:53297373a894 | 1451 | } SercomUsart; |
mbed_official | 579:53297373a894 | 1452 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 1453 | |
mbed_official | 579:53297373a894 | 1454 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 1455 | typedef union { |
mbed_official | 579:53297373a894 | 1456 | SercomI2cm I2CM; /**< \brief Offset: 0x00 I2C Master Mode */ |
mbed_official | 579:53297373a894 | 1457 | SercomI2cs I2CS; /**< \brief Offset: 0x00 I2C Slave Mode */ |
mbed_official | 579:53297373a894 | 1458 | SercomSpi SPI; /**< \brief Offset: 0x00 SPI Mode */ |
mbed_official | 579:53297373a894 | 1459 | SercomUsart USART; /**< \brief Offset: 0x00 USART Mode */ |
mbed_official | 579:53297373a894 | 1460 | } Sercom; |
mbed_official | 579:53297373a894 | 1461 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 1462 | |
mbed_official | 579:53297373a894 | 1463 | /*@}*/ |
mbed_official | 579:53297373a894 | 1464 | |
mbed_official | 579:53297373a894 | 1465 | #endif /* _SAMD21_SERCOM_COMPONENT_ */ |