mbed library sources
Fork of mbed-src by
targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_pm.h@592:a274ee790e56, 2015-07-17 (annotated)
- Committer:
- mbed_official
- Date:
- Fri Jul 17 09:15:10 2015 +0100
- Revision:
- 592:a274ee790e56
- Parent:
- 579:53297373a894
Synchronized with git revision e7144f83a8d75df80c4877936b6ffe552b0be9e6
Full URL: https://github.com/mbedmicro/mbed/commit/e7144f83a8d75df80c4877936b6ffe552b0be9e6/
More API implementation for SAMR21
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 579:53297373a894 | 1 | #ifndef _SAMD21_PM_COMPONENT_ |
mbed_official | 579:53297373a894 | 2 | #define _SAMD21_PM_COMPONENT_ |
mbed_official | 579:53297373a894 | 3 | |
mbed_official | 579:53297373a894 | 4 | /* ========================================================================== */ |
mbed_official | 579:53297373a894 | 5 | /** SOFTWARE API DEFINITION FOR PM */ |
mbed_official | 579:53297373a894 | 6 | /* ========================================================================== */ |
mbed_official | 579:53297373a894 | 7 | /** \addtogroup SAMD21_PM Power Manager */ |
mbed_official | 579:53297373a894 | 8 | /*@{*/ |
mbed_official | 579:53297373a894 | 9 | |
mbed_official | 579:53297373a894 | 10 | #define PM_U2206 |
mbed_official | 579:53297373a894 | 11 | #define REV_PM 0x201 |
mbed_official | 579:53297373a894 | 12 | |
mbed_official | 579:53297373a894 | 13 | /* -------- PM_CTRL : (PM Offset: 0x00) (R/W 8) Control -------- */ |
mbed_official | 579:53297373a894 | 14 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 15 | typedef union { |
mbed_official | 579:53297373a894 | 16 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 17 | } PM_CTRL_Type; |
mbed_official | 579:53297373a894 | 18 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 19 | |
mbed_official | 579:53297373a894 | 20 | #define PM_CTRL_OFFSET 0x00 /**< \brief (PM_CTRL offset) Control */ |
mbed_official | 579:53297373a894 | 21 | #define PM_CTRL_RESETVALUE 0x00ul /**< \brief (PM_CTRL reset_value) Control */ |
mbed_official | 579:53297373a894 | 22 | |
mbed_official | 579:53297373a894 | 23 | #define PM_CTRL_MASK 0x00ul /**< \brief (PM_CTRL) MASK Register */ |
mbed_official | 579:53297373a894 | 24 | |
mbed_official | 579:53297373a894 | 25 | /* -------- PM_SLEEP : (PM Offset: 0x01) (R/W 8) Sleep Mode -------- */ |
mbed_official | 579:53297373a894 | 26 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 27 | typedef union { |
mbed_official | 579:53297373a894 | 28 | struct { |
mbed_official | 579:53297373a894 | 29 | uint8_t IDLE:2; /*!< bit: 0.. 1 Idle Mode Configuration */ |
mbed_official | 579:53297373a894 | 30 | uint8_t :6; /*!< bit: 2.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 31 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 32 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 33 | } PM_SLEEP_Type; |
mbed_official | 579:53297373a894 | 34 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 35 | |
mbed_official | 579:53297373a894 | 36 | #define PM_SLEEP_OFFSET 0x01 /**< \brief (PM_SLEEP offset) Sleep Mode */ |
mbed_official | 579:53297373a894 | 37 | #define PM_SLEEP_RESETVALUE 0x00ul /**< \brief (PM_SLEEP reset_value) Sleep Mode */ |
mbed_official | 579:53297373a894 | 38 | |
mbed_official | 579:53297373a894 | 39 | #define PM_SLEEP_IDLE_Pos 0 /**< \brief (PM_SLEEP) Idle Mode Configuration */ |
mbed_official | 579:53297373a894 | 40 | #define PM_SLEEP_IDLE_Msk (0x3ul << PM_SLEEP_IDLE_Pos) |
mbed_official | 579:53297373a894 | 41 | #define PM_SLEEP_IDLE(value) ((PM_SLEEP_IDLE_Msk & ((value) << PM_SLEEP_IDLE_Pos))) |
mbed_official | 579:53297373a894 | 42 | #define PM_SLEEP_IDLE_CPU_Val 0x0ul /**< \brief (PM_SLEEP) The CPU clock domain is stopped */ |
mbed_official | 579:53297373a894 | 43 | #define PM_SLEEP_IDLE_AHB_Val 0x1ul /**< \brief (PM_SLEEP) The CPU and AHB clock domains are stopped */ |
mbed_official | 579:53297373a894 | 44 | #define PM_SLEEP_IDLE_APB_Val 0x2ul /**< \brief (PM_SLEEP) The CPU, AHB and APB clock domains are stopped */ |
mbed_official | 579:53297373a894 | 45 | #define PM_SLEEP_IDLE_CPU (PM_SLEEP_IDLE_CPU_Val << PM_SLEEP_IDLE_Pos) |
mbed_official | 579:53297373a894 | 46 | #define PM_SLEEP_IDLE_AHB (PM_SLEEP_IDLE_AHB_Val << PM_SLEEP_IDLE_Pos) |
mbed_official | 579:53297373a894 | 47 | #define PM_SLEEP_IDLE_APB (PM_SLEEP_IDLE_APB_Val << PM_SLEEP_IDLE_Pos) |
mbed_official | 579:53297373a894 | 48 | #define PM_SLEEP_MASK 0x03ul /**< \brief (PM_SLEEP) MASK Register */ |
mbed_official | 579:53297373a894 | 49 | |
mbed_official | 579:53297373a894 | 50 | /* -------- PM_CPUSEL : (PM Offset: 0x08) (R/W 8) CPU Clock Select -------- */ |
mbed_official | 579:53297373a894 | 51 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 52 | typedef union { |
mbed_official | 579:53297373a894 | 53 | struct { |
mbed_official | 579:53297373a894 | 54 | uint8_t CPUDIV:3; /*!< bit: 0.. 2 CPU Prescaler Selection */ |
mbed_official | 579:53297373a894 | 55 | uint8_t :5; /*!< bit: 3.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 56 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 57 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 58 | } PM_CPUSEL_Type; |
mbed_official | 579:53297373a894 | 59 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 60 | |
mbed_official | 579:53297373a894 | 61 | #define PM_CPUSEL_OFFSET 0x08 /**< \brief (PM_CPUSEL offset) CPU Clock Select */ |
mbed_official | 579:53297373a894 | 62 | #define PM_CPUSEL_RESETVALUE 0x00ul /**< \brief (PM_CPUSEL reset_value) CPU Clock Select */ |
mbed_official | 579:53297373a894 | 63 | |
mbed_official | 579:53297373a894 | 64 | #define PM_CPUSEL_CPUDIV_Pos 0 /**< \brief (PM_CPUSEL) CPU Prescaler Selection */ |
mbed_official | 579:53297373a894 | 65 | #define PM_CPUSEL_CPUDIV_Msk (0x7ul << PM_CPUSEL_CPUDIV_Pos) |
mbed_official | 579:53297373a894 | 66 | #define PM_CPUSEL_CPUDIV(value) ((PM_CPUSEL_CPUDIV_Msk & ((value) << PM_CPUSEL_CPUDIV_Pos))) |
mbed_official | 579:53297373a894 | 67 | #define PM_CPUSEL_CPUDIV_DIV1_Val 0x0ul /**< \brief (PM_CPUSEL) Divide by 1 */ |
mbed_official | 579:53297373a894 | 68 | #define PM_CPUSEL_CPUDIV_DIV2_Val 0x1ul /**< \brief (PM_CPUSEL) Divide by 2 */ |
mbed_official | 579:53297373a894 | 69 | #define PM_CPUSEL_CPUDIV_DIV4_Val 0x2ul /**< \brief (PM_CPUSEL) Divide by 4 */ |
mbed_official | 579:53297373a894 | 70 | #define PM_CPUSEL_CPUDIV_DIV8_Val 0x3ul /**< \brief (PM_CPUSEL) Divide by 8 */ |
mbed_official | 579:53297373a894 | 71 | #define PM_CPUSEL_CPUDIV_DIV16_Val 0x4ul /**< \brief (PM_CPUSEL) Divide by 16 */ |
mbed_official | 579:53297373a894 | 72 | #define PM_CPUSEL_CPUDIV_DIV32_Val 0x5ul /**< \brief (PM_CPUSEL) Divide by 32 */ |
mbed_official | 579:53297373a894 | 73 | #define PM_CPUSEL_CPUDIV_DIV64_Val 0x6ul /**< \brief (PM_CPUSEL) Divide by 64 */ |
mbed_official | 579:53297373a894 | 74 | #define PM_CPUSEL_CPUDIV_DIV128_Val 0x7ul /**< \brief (PM_CPUSEL) Divide by 128 */ |
mbed_official | 579:53297373a894 | 75 | #define PM_CPUSEL_CPUDIV_DIV1 (PM_CPUSEL_CPUDIV_DIV1_Val << PM_CPUSEL_CPUDIV_Pos) |
mbed_official | 579:53297373a894 | 76 | #define PM_CPUSEL_CPUDIV_DIV2 (PM_CPUSEL_CPUDIV_DIV2_Val << PM_CPUSEL_CPUDIV_Pos) |
mbed_official | 579:53297373a894 | 77 | #define PM_CPUSEL_CPUDIV_DIV4 (PM_CPUSEL_CPUDIV_DIV4_Val << PM_CPUSEL_CPUDIV_Pos) |
mbed_official | 579:53297373a894 | 78 | #define PM_CPUSEL_CPUDIV_DIV8 (PM_CPUSEL_CPUDIV_DIV8_Val << PM_CPUSEL_CPUDIV_Pos) |
mbed_official | 579:53297373a894 | 79 | #define PM_CPUSEL_CPUDIV_DIV16 (PM_CPUSEL_CPUDIV_DIV16_Val << PM_CPUSEL_CPUDIV_Pos) |
mbed_official | 579:53297373a894 | 80 | #define PM_CPUSEL_CPUDIV_DIV32 (PM_CPUSEL_CPUDIV_DIV32_Val << PM_CPUSEL_CPUDIV_Pos) |
mbed_official | 579:53297373a894 | 81 | #define PM_CPUSEL_CPUDIV_DIV64 (PM_CPUSEL_CPUDIV_DIV64_Val << PM_CPUSEL_CPUDIV_Pos) |
mbed_official | 579:53297373a894 | 82 | #define PM_CPUSEL_CPUDIV_DIV128 (PM_CPUSEL_CPUDIV_DIV128_Val << PM_CPUSEL_CPUDIV_Pos) |
mbed_official | 579:53297373a894 | 83 | #define PM_CPUSEL_MASK 0x07ul /**< \brief (PM_CPUSEL) MASK Register */ |
mbed_official | 579:53297373a894 | 84 | |
mbed_official | 579:53297373a894 | 85 | /* -------- PM_APBASEL : (PM Offset: 0x09) (R/W 8) APBA Clock Select -------- */ |
mbed_official | 579:53297373a894 | 86 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 87 | typedef union { |
mbed_official | 579:53297373a894 | 88 | struct { |
mbed_official | 579:53297373a894 | 89 | uint8_t APBADIV:3; /*!< bit: 0.. 2 APBA Prescaler Selection */ |
mbed_official | 579:53297373a894 | 90 | uint8_t :5; /*!< bit: 3.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 91 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 92 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 93 | } PM_APBASEL_Type; |
mbed_official | 579:53297373a894 | 94 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 95 | |
mbed_official | 579:53297373a894 | 96 | #define PM_APBASEL_OFFSET 0x09 /**< \brief (PM_APBASEL offset) APBA Clock Select */ |
mbed_official | 579:53297373a894 | 97 | #define PM_APBASEL_RESETVALUE 0x00ul /**< \brief (PM_APBASEL reset_value) APBA Clock Select */ |
mbed_official | 579:53297373a894 | 98 | |
mbed_official | 579:53297373a894 | 99 | #define PM_APBASEL_APBADIV_Pos 0 /**< \brief (PM_APBASEL) APBA Prescaler Selection */ |
mbed_official | 579:53297373a894 | 100 | #define PM_APBASEL_APBADIV_Msk (0x7ul << PM_APBASEL_APBADIV_Pos) |
mbed_official | 579:53297373a894 | 101 | #define PM_APBASEL_APBADIV(value) ((PM_APBASEL_APBADIV_Msk & ((value) << PM_APBASEL_APBADIV_Pos))) |
mbed_official | 579:53297373a894 | 102 | #define PM_APBASEL_APBADIV_DIV1_Val 0x0ul /**< \brief (PM_APBASEL) Divide by 1 */ |
mbed_official | 579:53297373a894 | 103 | #define PM_APBASEL_APBADIV_DIV2_Val 0x1ul /**< \brief (PM_APBASEL) Divide by 2 */ |
mbed_official | 579:53297373a894 | 104 | #define PM_APBASEL_APBADIV_DIV4_Val 0x2ul /**< \brief (PM_APBASEL) Divide by 4 */ |
mbed_official | 579:53297373a894 | 105 | #define PM_APBASEL_APBADIV_DIV8_Val 0x3ul /**< \brief (PM_APBASEL) Divide by 8 */ |
mbed_official | 579:53297373a894 | 106 | #define PM_APBASEL_APBADIV_DIV16_Val 0x4ul /**< \brief (PM_APBASEL) Divide by 16 */ |
mbed_official | 579:53297373a894 | 107 | #define PM_APBASEL_APBADIV_DIV32_Val 0x5ul /**< \brief (PM_APBASEL) Divide by 32 */ |
mbed_official | 579:53297373a894 | 108 | #define PM_APBASEL_APBADIV_DIV64_Val 0x6ul /**< \brief (PM_APBASEL) Divide by 64 */ |
mbed_official | 579:53297373a894 | 109 | #define PM_APBASEL_APBADIV_DIV128_Val 0x7ul /**< \brief (PM_APBASEL) Divide by 128 */ |
mbed_official | 579:53297373a894 | 110 | #define PM_APBASEL_APBADIV_DIV1 (PM_APBASEL_APBADIV_DIV1_Val << PM_APBASEL_APBADIV_Pos) |
mbed_official | 579:53297373a894 | 111 | #define PM_APBASEL_APBADIV_DIV2 (PM_APBASEL_APBADIV_DIV2_Val << PM_APBASEL_APBADIV_Pos) |
mbed_official | 579:53297373a894 | 112 | #define PM_APBASEL_APBADIV_DIV4 (PM_APBASEL_APBADIV_DIV4_Val << PM_APBASEL_APBADIV_Pos) |
mbed_official | 579:53297373a894 | 113 | #define PM_APBASEL_APBADIV_DIV8 (PM_APBASEL_APBADIV_DIV8_Val << PM_APBASEL_APBADIV_Pos) |
mbed_official | 579:53297373a894 | 114 | #define PM_APBASEL_APBADIV_DIV16 (PM_APBASEL_APBADIV_DIV16_Val << PM_APBASEL_APBADIV_Pos) |
mbed_official | 579:53297373a894 | 115 | #define PM_APBASEL_APBADIV_DIV32 (PM_APBASEL_APBADIV_DIV32_Val << PM_APBASEL_APBADIV_Pos) |
mbed_official | 579:53297373a894 | 116 | #define PM_APBASEL_APBADIV_DIV64 (PM_APBASEL_APBADIV_DIV64_Val << PM_APBASEL_APBADIV_Pos) |
mbed_official | 579:53297373a894 | 117 | #define PM_APBASEL_APBADIV_DIV128 (PM_APBASEL_APBADIV_DIV128_Val << PM_APBASEL_APBADIV_Pos) |
mbed_official | 579:53297373a894 | 118 | #define PM_APBASEL_MASK 0x07ul /**< \brief (PM_APBASEL) MASK Register */ |
mbed_official | 579:53297373a894 | 119 | |
mbed_official | 579:53297373a894 | 120 | /* -------- PM_APBBSEL : (PM Offset: 0x0A) (R/W 8) APBB Clock Select -------- */ |
mbed_official | 579:53297373a894 | 121 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 122 | typedef union { |
mbed_official | 579:53297373a894 | 123 | struct { |
mbed_official | 579:53297373a894 | 124 | uint8_t APBBDIV:3; /*!< bit: 0.. 2 APBB Prescaler Selection */ |
mbed_official | 579:53297373a894 | 125 | uint8_t :5; /*!< bit: 3.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 126 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 127 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 128 | } PM_APBBSEL_Type; |
mbed_official | 579:53297373a894 | 129 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 130 | |
mbed_official | 579:53297373a894 | 131 | #define PM_APBBSEL_OFFSET 0x0A /**< \brief (PM_APBBSEL offset) APBB Clock Select */ |
mbed_official | 579:53297373a894 | 132 | #define PM_APBBSEL_RESETVALUE 0x00ul /**< \brief (PM_APBBSEL reset_value) APBB Clock Select */ |
mbed_official | 579:53297373a894 | 133 | |
mbed_official | 579:53297373a894 | 134 | #define PM_APBBSEL_APBBDIV_Pos 0 /**< \brief (PM_APBBSEL) APBB Prescaler Selection */ |
mbed_official | 579:53297373a894 | 135 | #define PM_APBBSEL_APBBDIV_Msk (0x7ul << PM_APBBSEL_APBBDIV_Pos) |
mbed_official | 579:53297373a894 | 136 | #define PM_APBBSEL_APBBDIV(value) ((PM_APBBSEL_APBBDIV_Msk & ((value) << PM_APBBSEL_APBBDIV_Pos))) |
mbed_official | 579:53297373a894 | 137 | #define PM_APBBSEL_APBBDIV_DIV1_Val 0x0ul /**< \brief (PM_APBBSEL) Divide by 1 */ |
mbed_official | 579:53297373a894 | 138 | #define PM_APBBSEL_APBBDIV_DIV2_Val 0x1ul /**< \brief (PM_APBBSEL) Divide by 2 */ |
mbed_official | 579:53297373a894 | 139 | #define PM_APBBSEL_APBBDIV_DIV4_Val 0x2ul /**< \brief (PM_APBBSEL) Divide by 4 */ |
mbed_official | 579:53297373a894 | 140 | #define PM_APBBSEL_APBBDIV_DIV8_Val 0x3ul /**< \brief (PM_APBBSEL) Divide by 8 */ |
mbed_official | 579:53297373a894 | 141 | #define PM_APBBSEL_APBBDIV_DIV16_Val 0x4ul /**< \brief (PM_APBBSEL) Divide by 16 */ |
mbed_official | 579:53297373a894 | 142 | #define PM_APBBSEL_APBBDIV_DIV32_Val 0x5ul /**< \brief (PM_APBBSEL) Divide by 32 */ |
mbed_official | 579:53297373a894 | 143 | #define PM_APBBSEL_APBBDIV_DIV64_Val 0x6ul /**< \brief (PM_APBBSEL) Divide by 64 */ |
mbed_official | 579:53297373a894 | 144 | #define PM_APBBSEL_APBBDIV_DIV128_Val 0x7ul /**< \brief (PM_APBBSEL) Divide by 128 */ |
mbed_official | 579:53297373a894 | 145 | #define PM_APBBSEL_APBBDIV_DIV1 (PM_APBBSEL_APBBDIV_DIV1_Val << PM_APBBSEL_APBBDIV_Pos) |
mbed_official | 579:53297373a894 | 146 | #define PM_APBBSEL_APBBDIV_DIV2 (PM_APBBSEL_APBBDIV_DIV2_Val << PM_APBBSEL_APBBDIV_Pos) |
mbed_official | 579:53297373a894 | 147 | #define PM_APBBSEL_APBBDIV_DIV4 (PM_APBBSEL_APBBDIV_DIV4_Val << PM_APBBSEL_APBBDIV_Pos) |
mbed_official | 579:53297373a894 | 148 | #define PM_APBBSEL_APBBDIV_DIV8 (PM_APBBSEL_APBBDIV_DIV8_Val << PM_APBBSEL_APBBDIV_Pos) |
mbed_official | 579:53297373a894 | 149 | #define PM_APBBSEL_APBBDIV_DIV16 (PM_APBBSEL_APBBDIV_DIV16_Val << PM_APBBSEL_APBBDIV_Pos) |
mbed_official | 579:53297373a894 | 150 | #define PM_APBBSEL_APBBDIV_DIV32 (PM_APBBSEL_APBBDIV_DIV32_Val << PM_APBBSEL_APBBDIV_Pos) |
mbed_official | 579:53297373a894 | 151 | #define PM_APBBSEL_APBBDIV_DIV64 (PM_APBBSEL_APBBDIV_DIV64_Val << PM_APBBSEL_APBBDIV_Pos) |
mbed_official | 579:53297373a894 | 152 | #define PM_APBBSEL_APBBDIV_DIV128 (PM_APBBSEL_APBBDIV_DIV128_Val << PM_APBBSEL_APBBDIV_Pos) |
mbed_official | 579:53297373a894 | 153 | #define PM_APBBSEL_MASK 0x07ul /**< \brief (PM_APBBSEL) MASK Register */ |
mbed_official | 579:53297373a894 | 154 | |
mbed_official | 579:53297373a894 | 155 | /* -------- PM_APBCSEL : (PM Offset: 0x0B) (R/W 8) APBC Clock Select -------- */ |
mbed_official | 579:53297373a894 | 156 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 157 | typedef union { |
mbed_official | 579:53297373a894 | 158 | struct { |
mbed_official | 579:53297373a894 | 159 | uint8_t APBCDIV:3; /*!< bit: 0.. 2 APBC Prescaler Selection */ |
mbed_official | 579:53297373a894 | 160 | uint8_t :5; /*!< bit: 3.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 161 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 162 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 163 | } PM_APBCSEL_Type; |
mbed_official | 579:53297373a894 | 164 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 165 | |
mbed_official | 579:53297373a894 | 166 | #define PM_APBCSEL_OFFSET 0x0B /**< \brief (PM_APBCSEL offset) APBC Clock Select */ |
mbed_official | 579:53297373a894 | 167 | #define PM_APBCSEL_RESETVALUE 0x00ul /**< \brief (PM_APBCSEL reset_value) APBC Clock Select */ |
mbed_official | 579:53297373a894 | 168 | |
mbed_official | 579:53297373a894 | 169 | #define PM_APBCSEL_APBCDIV_Pos 0 /**< \brief (PM_APBCSEL) APBC Prescaler Selection */ |
mbed_official | 579:53297373a894 | 170 | #define PM_APBCSEL_APBCDIV_Msk (0x7ul << PM_APBCSEL_APBCDIV_Pos) |
mbed_official | 579:53297373a894 | 171 | #define PM_APBCSEL_APBCDIV(value) ((PM_APBCSEL_APBCDIV_Msk & ((value) << PM_APBCSEL_APBCDIV_Pos))) |
mbed_official | 579:53297373a894 | 172 | #define PM_APBCSEL_APBCDIV_DIV1_Val 0x0ul /**< \brief (PM_APBCSEL) Divide by 1 */ |
mbed_official | 579:53297373a894 | 173 | #define PM_APBCSEL_APBCDIV_DIV2_Val 0x1ul /**< \brief (PM_APBCSEL) Divide by 2 */ |
mbed_official | 579:53297373a894 | 174 | #define PM_APBCSEL_APBCDIV_DIV4_Val 0x2ul /**< \brief (PM_APBCSEL) Divide by 4 */ |
mbed_official | 579:53297373a894 | 175 | #define PM_APBCSEL_APBCDIV_DIV8_Val 0x3ul /**< \brief (PM_APBCSEL) Divide by 8 */ |
mbed_official | 579:53297373a894 | 176 | #define PM_APBCSEL_APBCDIV_DIV16_Val 0x4ul /**< \brief (PM_APBCSEL) Divide by 16 */ |
mbed_official | 579:53297373a894 | 177 | #define PM_APBCSEL_APBCDIV_DIV32_Val 0x5ul /**< \brief (PM_APBCSEL) Divide by 32 */ |
mbed_official | 579:53297373a894 | 178 | #define PM_APBCSEL_APBCDIV_DIV64_Val 0x6ul /**< \brief (PM_APBCSEL) Divide by 64 */ |
mbed_official | 579:53297373a894 | 179 | #define PM_APBCSEL_APBCDIV_DIV128_Val 0x7ul /**< \brief (PM_APBCSEL) Divide by 128 */ |
mbed_official | 579:53297373a894 | 180 | #define PM_APBCSEL_APBCDIV_DIV1 (PM_APBCSEL_APBCDIV_DIV1_Val << PM_APBCSEL_APBCDIV_Pos) |
mbed_official | 579:53297373a894 | 181 | #define PM_APBCSEL_APBCDIV_DIV2 (PM_APBCSEL_APBCDIV_DIV2_Val << PM_APBCSEL_APBCDIV_Pos) |
mbed_official | 579:53297373a894 | 182 | #define PM_APBCSEL_APBCDIV_DIV4 (PM_APBCSEL_APBCDIV_DIV4_Val << PM_APBCSEL_APBCDIV_Pos) |
mbed_official | 579:53297373a894 | 183 | #define PM_APBCSEL_APBCDIV_DIV8 (PM_APBCSEL_APBCDIV_DIV8_Val << PM_APBCSEL_APBCDIV_Pos) |
mbed_official | 579:53297373a894 | 184 | #define PM_APBCSEL_APBCDIV_DIV16 (PM_APBCSEL_APBCDIV_DIV16_Val << PM_APBCSEL_APBCDIV_Pos) |
mbed_official | 579:53297373a894 | 185 | #define PM_APBCSEL_APBCDIV_DIV32 (PM_APBCSEL_APBCDIV_DIV32_Val << PM_APBCSEL_APBCDIV_Pos) |
mbed_official | 579:53297373a894 | 186 | #define PM_APBCSEL_APBCDIV_DIV64 (PM_APBCSEL_APBCDIV_DIV64_Val << PM_APBCSEL_APBCDIV_Pos) |
mbed_official | 579:53297373a894 | 187 | #define PM_APBCSEL_APBCDIV_DIV128 (PM_APBCSEL_APBCDIV_DIV128_Val << PM_APBCSEL_APBCDIV_Pos) |
mbed_official | 579:53297373a894 | 188 | #define PM_APBCSEL_MASK 0x07ul /**< \brief (PM_APBCSEL) MASK Register */ |
mbed_official | 579:53297373a894 | 189 | |
mbed_official | 579:53297373a894 | 190 | /* -------- PM_AHBMASK : (PM Offset: 0x14) (R/W 32) AHB Mask -------- */ |
mbed_official | 579:53297373a894 | 191 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 192 | typedef union { |
mbed_official | 579:53297373a894 | 193 | struct { |
mbed_official | 579:53297373a894 | 194 | uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */ |
mbed_official | 579:53297373a894 | 195 | uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */ |
mbed_official | 579:53297373a894 | 196 | uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */ |
mbed_official | 579:53297373a894 | 197 | uint32_t DSU_:1; /*!< bit: 3 DSU AHB Clock Mask */ |
mbed_official | 579:53297373a894 | 198 | uint32_t NVMCTRL_:1; /*!< bit: 4 NVMCTRL AHB Clock Mask */ |
mbed_official | 579:53297373a894 | 199 | uint32_t DMAC_:1; /*!< bit: 5 DMAC AHB Clock Mask */ |
mbed_official | 579:53297373a894 | 200 | uint32_t USB_:1; /*!< bit: 6 USB AHB Clock Mask */ |
mbed_official | 579:53297373a894 | 201 | uint32_t :25; /*!< bit: 7..31 Reserved */ |
mbed_official | 579:53297373a894 | 202 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 203 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 204 | } PM_AHBMASK_Type; |
mbed_official | 579:53297373a894 | 205 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 206 | |
mbed_official | 579:53297373a894 | 207 | #define PM_AHBMASK_OFFSET 0x14 /**< \brief (PM_AHBMASK offset) AHB Mask */ |
mbed_official | 579:53297373a894 | 208 | #define PM_AHBMASK_RESETVALUE 0x0000007Ful /**< \brief (PM_AHBMASK reset_value) AHB Mask */ |
mbed_official | 579:53297373a894 | 209 | |
mbed_official | 579:53297373a894 | 210 | #define PM_AHBMASK_HPB0_Pos 0 /**< \brief (PM_AHBMASK) HPB0 AHB Clock Mask */ |
mbed_official | 579:53297373a894 | 211 | #define PM_AHBMASK_HPB0 (0x1ul << PM_AHBMASK_HPB0_Pos) |
mbed_official | 579:53297373a894 | 212 | #define PM_AHBMASK_HPB1_Pos 1 /**< \brief (PM_AHBMASK) HPB1 AHB Clock Mask */ |
mbed_official | 579:53297373a894 | 213 | #define PM_AHBMASK_HPB1 (0x1ul << PM_AHBMASK_HPB1_Pos) |
mbed_official | 579:53297373a894 | 214 | #define PM_AHBMASK_HPB2_Pos 2 /**< \brief (PM_AHBMASK) HPB2 AHB Clock Mask */ |
mbed_official | 579:53297373a894 | 215 | #define PM_AHBMASK_HPB2 (0x1ul << PM_AHBMASK_HPB2_Pos) |
mbed_official | 579:53297373a894 | 216 | #define PM_AHBMASK_DSU_Pos 3 /**< \brief (PM_AHBMASK) DSU AHB Clock Mask */ |
mbed_official | 579:53297373a894 | 217 | #define PM_AHBMASK_DSU (0x1ul << PM_AHBMASK_DSU_Pos) |
mbed_official | 579:53297373a894 | 218 | #define PM_AHBMASK_NVMCTRL_Pos 4 /**< \brief (PM_AHBMASK) NVMCTRL AHB Clock Mask */ |
mbed_official | 579:53297373a894 | 219 | #define PM_AHBMASK_NVMCTRL (0x1ul << PM_AHBMASK_NVMCTRL_Pos) |
mbed_official | 579:53297373a894 | 220 | #define PM_AHBMASK_DMAC_Pos 5 /**< \brief (PM_AHBMASK) DMAC AHB Clock Mask */ |
mbed_official | 579:53297373a894 | 221 | #define PM_AHBMASK_DMAC (0x1ul << PM_AHBMASK_DMAC_Pos) |
mbed_official | 579:53297373a894 | 222 | #define PM_AHBMASK_USB_Pos 6 /**< \brief (PM_AHBMASK) USB AHB Clock Mask */ |
mbed_official | 579:53297373a894 | 223 | #define PM_AHBMASK_USB (0x1ul << PM_AHBMASK_USB_Pos) |
mbed_official | 579:53297373a894 | 224 | #define PM_AHBMASK_MASK 0x0000007Ful /**< \brief (PM_AHBMASK) MASK Register */ |
mbed_official | 579:53297373a894 | 225 | |
mbed_official | 579:53297373a894 | 226 | /* -------- PM_APBAMASK : (PM Offset: 0x18) (R/W 32) APBA Mask -------- */ |
mbed_official | 579:53297373a894 | 227 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 228 | typedef union { |
mbed_official | 579:53297373a894 | 229 | struct { |
mbed_official | 579:53297373a894 | 230 | uint32_t PAC0_:1; /*!< bit: 0 PAC0 APB Clock Enable */ |
mbed_official | 579:53297373a894 | 231 | uint32_t PM_:1; /*!< bit: 1 PM APB Clock Enable */ |
mbed_official | 579:53297373a894 | 232 | uint32_t SYSCTRL_:1; /*!< bit: 2 SYSCTRL APB Clock Enable */ |
mbed_official | 579:53297373a894 | 233 | uint32_t GCLK_:1; /*!< bit: 3 GCLK APB Clock Enable */ |
mbed_official | 579:53297373a894 | 234 | uint32_t WDT_:1; /*!< bit: 4 WDT APB Clock Enable */ |
mbed_official | 579:53297373a894 | 235 | uint32_t RTC_:1; /*!< bit: 5 RTC APB Clock Enable */ |
mbed_official | 579:53297373a894 | 236 | uint32_t EIC_:1; /*!< bit: 6 EIC APB Clock Enable */ |
mbed_official | 579:53297373a894 | 237 | uint32_t :25; /*!< bit: 7..31 Reserved */ |
mbed_official | 579:53297373a894 | 238 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 239 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 240 | } PM_APBAMASK_Type; |
mbed_official | 579:53297373a894 | 241 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 242 | |
mbed_official | 579:53297373a894 | 243 | #define PM_APBAMASK_OFFSET 0x18 /**< \brief (PM_APBAMASK offset) APBA Mask */ |
mbed_official | 579:53297373a894 | 244 | #define PM_APBAMASK_RESETVALUE 0x0000007Ful /**< \brief (PM_APBAMASK reset_value) APBA Mask */ |
mbed_official | 579:53297373a894 | 245 | |
mbed_official | 579:53297373a894 | 246 | #define PM_APBAMASK_PAC0_Pos 0 /**< \brief (PM_APBAMASK) PAC0 APB Clock Enable */ |
mbed_official | 579:53297373a894 | 247 | #define PM_APBAMASK_PAC0 (0x1ul << PM_APBAMASK_PAC0_Pos) |
mbed_official | 579:53297373a894 | 248 | #define PM_APBAMASK_PM_Pos 1 /**< \brief (PM_APBAMASK) PM APB Clock Enable */ |
mbed_official | 579:53297373a894 | 249 | #define PM_APBAMASK_PM (0x1ul << PM_APBAMASK_PM_Pos) |
mbed_official | 579:53297373a894 | 250 | #define PM_APBAMASK_SYSCTRL_Pos 2 /**< \brief (PM_APBAMASK) SYSCTRL APB Clock Enable */ |
mbed_official | 579:53297373a894 | 251 | #define PM_APBAMASK_SYSCTRL (0x1ul << PM_APBAMASK_SYSCTRL_Pos) |
mbed_official | 579:53297373a894 | 252 | #define PM_APBAMASK_GCLK_Pos 3 /**< \brief (PM_APBAMASK) GCLK APB Clock Enable */ |
mbed_official | 579:53297373a894 | 253 | #define PM_APBAMASK_GCLK (0x1ul << PM_APBAMASK_GCLK_Pos) |
mbed_official | 579:53297373a894 | 254 | #define PM_APBAMASK_WDT_Pos 4 /**< \brief (PM_APBAMASK) WDT APB Clock Enable */ |
mbed_official | 579:53297373a894 | 255 | #define PM_APBAMASK_WDT (0x1ul << PM_APBAMASK_WDT_Pos) |
mbed_official | 579:53297373a894 | 256 | #define PM_APBAMASK_RTC_Pos 5 /**< \brief (PM_APBAMASK) RTC APB Clock Enable */ |
mbed_official | 579:53297373a894 | 257 | #define PM_APBAMASK_RTC (0x1ul << PM_APBAMASK_RTC_Pos) |
mbed_official | 579:53297373a894 | 258 | #define PM_APBAMASK_EIC_Pos 6 /**< \brief (PM_APBAMASK) EIC APB Clock Enable */ |
mbed_official | 579:53297373a894 | 259 | #define PM_APBAMASK_EIC (0x1ul << PM_APBAMASK_EIC_Pos) |
mbed_official | 579:53297373a894 | 260 | #define PM_APBAMASK_MASK 0x0000007Ful /**< \brief (PM_APBAMASK) MASK Register */ |
mbed_official | 579:53297373a894 | 261 | |
mbed_official | 579:53297373a894 | 262 | /* -------- PM_APBBMASK : (PM Offset: 0x1C) (R/W 32) APBB Mask -------- */ |
mbed_official | 579:53297373a894 | 263 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 264 | typedef union { |
mbed_official | 579:53297373a894 | 265 | struct { |
mbed_official | 579:53297373a894 | 266 | uint32_t PAC1_:1; /*!< bit: 0 PAC1 APB Clock Enable */ |
mbed_official | 579:53297373a894 | 267 | uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */ |
mbed_official | 579:53297373a894 | 268 | uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */ |
mbed_official | 579:53297373a894 | 269 | uint32_t PORT_:1; /*!< bit: 3 PORT APB Clock Enable */ |
mbed_official | 579:53297373a894 | 270 | uint32_t DMAC_:1; /*!< bit: 4 DMAC APB Clock Enable */ |
mbed_official | 579:53297373a894 | 271 | uint32_t USB_:1; /*!< bit: 5 USB APB Clock Enable */ |
mbed_official | 579:53297373a894 | 272 | uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Clock Enable */ |
mbed_official | 579:53297373a894 | 273 | uint32_t :25; /*!< bit: 7..31 Reserved */ |
mbed_official | 579:53297373a894 | 274 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 275 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 276 | } PM_APBBMASK_Type; |
mbed_official | 579:53297373a894 | 277 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 278 | |
mbed_official | 579:53297373a894 | 279 | #define PM_APBBMASK_OFFSET 0x1C /**< \brief (PM_APBBMASK offset) APBB Mask */ |
mbed_official | 579:53297373a894 | 280 | #define PM_APBBMASK_RESETVALUE 0x0000007Ful /**< \brief (PM_APBBMASK reset_value) APBB Mask */ |
mbed_official | 579:53297373a894 | 281 | |
mbed_official | 579:53297373a894 | 282 | #define PM_APBBMASK_PAC1_Pos 0 /**< \brief (PM_APBBMASK) PAC1 APB Clock Enable */ |
mbed_official | 579:53297373a894 | 283 | #define PM_APBBMASK_PAC1 (0x1ul << PM_APBBMASK_PAC1_Pos) |
mbed_official | 579:53297373a894 | 284 | #define PM_APBBMASK_DSU_Pos 1 /**< \brief (PM_APBBMASK) DSU APB Clock Enable */ |
mbed_official | 579:53297373a894 | 285 | #define PM_APBBMASK_DSU (0x1ul << PM_APBBMASK_DSU_Pos) |
mbed_official | 579:53297373a894 | 286 | #define PM_APBBMASK_NVMCTRL_Pos 2 /**< \brief (PM_APBBMASK) NVMCTRL APB Clock Enable */ |
mbed_official | 579:53297373a894 | 287 | #define PM_APBBMASK_NVMCTRL (0x1ul << PM_APBBMASK_NVMCTRL_Pos) |
mbed_official | 579:53297373a894 | 288 | #define PM_APBBMASK_PORT_Pos 3 /**< \brief (PM_APBBMASK) PORT APB Clock Enable */ |
mbed_official | 579:53297373a894 | 289 | #define PM_APBBMASK_PORT (0x1ul << PM_APBBMASK_PORT_Pos) |
mbed_official | 579:53297373a894 | 290 | #define PM_APBBMASK_DMAC_Pos 4 /**< \brief (PM_APBBMASK) DMAC APB Clock Enable */ |
mbed_official | 579:53297373a894 | 291 | #define PM_APBBMASK_DMAC (0x1ul << PM_APBBMASK_DMAC_Pos) |
mbed_official | 579:53297373a894 | 292 | #define PM_APBBMASK_USB_Pos 5 /**< \brief (PM_APBBMASK) USB APB Clock Enable */ |
mbed_official | 579:53297373a894 | 293 | #define PM_APBBMASK_USB (0x1ul << PM_APBBMASK_USB_Pos) |
mbed_official | 579:53297373a894 | 294 | #define PM_APBBMASK_HMATRIX_Pos 6 /**< \brief (PM_APBBMASK) HMATRIX APB Clock Enable */ |
mbed_official | 579:53297373a894 | 295 | #define PM_APBBMASK_HMATRIX (0x1ul << PM_APBBMASK_HMATRIX_Pos) |
mbed_official | 579:53297373a894 | 296 | #define PM_APBBMASK_MASK 0x0000007Ful /**< \brief (PM_APBBMASK) MASK Register */ |
mbed_official | 579:53297373a894 | 297 | |
mbed_official | 579:53297373a894 | 298 | /* -------- PM_APBCMASK : (PM Offset: 0x20) (R/W 32) APBC Mask -------- */ |
mbed_official | 579:53297373a894 | 299 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 300 | typedef union { |
mbed_official | 579:53297373a894 | 301 | struct { |
mbed_official | 579:53297373a894 | 302 | uint32_t PAC2_:1; /*!< bit: 0 PAC2 APB Clock Enable */ |
mbed_official | 579:53297373a894 | 303 | uint32_t EVSYS_:1; /*!< bit: 1 EVSYS APB Clock Enable */ |
mbed_official | 579:53297373a894 | 304 | uint32_t SERCOM0_:1; /*!< bit: 2 SERCOM0 APB Clock Enable */ |
mbed_official | 579:53297373a894 | 305 | uint32_t SERCOM1_:1; /*!< bit: 3 SERCOM1 APB Clock Enable */ |
mbed_official | 579:53297373a894 | 306 | uint32_t SERCOM2_:1; /*!< bit: 4 SERCOM2 APB Clock Enable */ |
mbed_official | 579:53297373a894 | 307 | uint32_t SERCOM3_:1; /*!< bit: 5 SERCOM3 APB Clock Enable */ |
mbed_official | 579:53297373a894 | 308 | uint32_t SERCOM4_:1; /*!< bit: 6 SERCOM4 APB Clock Enable */ |
mbed_official | 579:53297373a894 | 309 | uint32_t SERCOM5_:1; /*!< bit: 7 SERCOM5 APB Clock Enable */ |
mbed_official | 579:53297373a894 | 310 | uint32_t TCC0_:1; /*!< bit: 8 TCC0 APB Clock Enable */ |
mbed_official | 579:53297373a894 | 311 | uint32_t TCC1_:1; /*!< bit: 9 TCC1 APB Clock Enable */ |
mbed_official | 579:53297373a894 | 312 | uint32_t TCC2_:1; /*!< bit: 10 TCC2 APB Clock Enable */ |
mbed_official | 579:53297373a894 | 313 | uint32_t TC3_:1; /*!< bit: 11 TC3 APB Clock Enable */ |
mbed_official | 579:53297373a894 | 314 | uint32_t TC4_:1; /*!< bit: 12 TC4 APB Clock Enable */ |
mbed_official | 579:53297373a894 | 315 | uint32_t TC5_:1; /*!< bit: 13 TC5 APB Clock Enable */ |
mbed_official | 579:53297373a894 | 316 | uint32_t TC6_:1; /*!< bit: 14 TC6 APB Clock Enable */ |
mbed_official | 579:53297373a894 | 317 | uint32_t TC7_:1; /*!< bit: 15 TC7 APB Clock Enable */ |
mbed_official | 579:53297373a894 | 318 | uint32_t ADC_:1; /*!< bit: 16 ADC APB Clock Enable */ |
mbed_official | 579:53297373a894 | 319 | uint32_t AC_:1; /*!< bit: 17 AC APB Clock Enable */ |
mbed_official | 579:53297373a894 | 320 | uint32_t DAC_:1; /*!< bit: 18 DAC APB Clock Enable */ |
mbed_official | 579:53297373a894 | 321 | uint32_t PTC_:1; /*!< bit: 19 PTC APB Clock Enable */ |
mbed_official | 579:53297373a894 | 322 | uint32_t I2S_:1; /*!< bit: 20 I2S APB Clock Enable */ |
mbed_official | 579:53297373a894 | 323 | uint32_t :11; /*!< bit: 21..31 Reserved */ |
mbed_official | 579:53297373a894 | 324 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 325 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 326 | } PM_APBCMASK_Type; |
mbed_official | 579:53297373a894 | 327 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 328 | |
mbed_official | 579:53297373a894 | 329 | #define PM_APBCMASK_OFFSET 0x20 /**< \brief (PM_APBCMASK offset) APBC Mask */ |
mbed_official | 579:53297373a894 | 330 | #define PM_APBCMASK_RESETVALUE 0x00010000ul /**< \brief (PM_APBCMASK reset_value) APBC Mask */ |
mbed_official | 579:53297373a894 | 331 | |
mbed_official | 579:53297373a894 | 332 | #define PM_APBCMASK_PAC2_Pos 0 /**< \brief (PM_APBCMASK) PAC2 APB Clock Enable */ |
mbed_official | 579:53297373a894 | 333 | #define PM_APBCMASK_PAC2 (0x1ul << PM_APBCMASK_PAC2_Pos) |
mbed_official | 579:53297373a894 | 334 | #define PM_APBCMASK_EVSYS_Pos 1 /**< \brief (PM_APBCMASK) EVSYS APB Clock Enable */ |
mbed_official | 579:53297373a894 | 335 | #define PM_APBCMASK_EVSYS (0x1ul << PM_APBCMASK_EVSYS_Pos) |
mbed_official | 579:53297373a894 | 336 | #define PM_APBCMASK_SERCOM0_Pos 2 /**< \brief (PM_APBCMASK) SERCOM0 APB Clock Enable */ |
mbed_official | 579:53297373a894 | 337 | #define PM_APBCMASK_SERCOM0 (0x1ul << PM_APBCMASK_SERCOM0_Pos) |
mbed_official | 579:53297373a894 | 338 | #define PM_APBCMASK_SERCOM1_Pos 3 /**< \brief (PM_APBCMASK) SERCOM1 APB Clock Enable */ |
mbed_official | 579:53297373a894 | 339 | #define PM_APBCMASK_SERCOM1 (0x1ul << PM_APBCMASK_SERCOM1_Pos) |
mbed_official | 579:53297373a894 | 340 | #define PM_APBCMASK_SERCOM2_Pos 4 /**< \brief (PM_APBCMASK) SERCOM2 APB Clock Enable */ |
mbed_official | 579:53297373a894 | 341 | #define PM_APBCMASK_SERCOM2 (0x1ul << PM_APBCMASK_SERCOM2_Pos) |
mbed_official | 579:53297373a894 | 342 | #define PM_APBCMASK_SERCOM3_Pos 5 /**< \brief (PM_APBCMASK) SERCOM3 APB Clock Enable */ |
mbed_official | 579:53297373a894 | 343 | #define PM_APBCMASK_SERCOM3 (0x1ul << PM_APBCMASK_SERCOM3_Pos) |
mbed_official | 579:53297373a894 | 344 | #define PM_APBCMASK_SERCOM4_Pos 6 /**< \brief (PM_APBCMASK) SERCOM4 APB Clock Enable */ |
mbed_official | 579:53297373a894 | 345 | #define PM_APBCMASK_SERCOM4 (0x1ul << PM_APBCMASK_SERCOM4_Pos) |
mbed_official | 579:53297373a894 | 346 | #define PM_APBCMASK_SERCOM5_Pos 7 /**< \brief (PM_APBCMASK) SERCOM5 APB Clock Enable */ |
mbed_official | 579:53297373a894 | 347 | #define PM_APBCMASK_SERCOM5 (0x1ul << PM_APBCMASK_SERCOM5_Pos) |
mbed_official | 579:53297373a894 | 348 | #define PM_APBCMASK_TCC0_Pos 8 /**< \brief (PM_APBCMASK) TCC0 APB Clock Enable */ |
mbed_official | 579:53297373a894 | 349 | #define PM_APBCMASK_TCC0 (0x1ul << PM_APBCMASK_TCC0_Pos) |
mbed_official | 579:53297373a894 | 350 | #define PM_APBCMASK_TCC1_Pos 9 /**< \brief (PM_APBCMASK) TCC1 APB Clock Enable */ |
mbed_official | 579:53297373a894 | 351 | #define PM_APBCMASK_TCC1 (0x1ul << PM_APBCMASK_TCC1_Pos) |
mbed_official | 579:53297373a894 | 352 | #define PM_APBCMASK_TCC2_Pos 10 /**< \brief (PM_APBCMASK) TCC2 APB Clock Enable */ |
mbed_official | 579:53297373a894 | 353 | #define PM_APBCMASK_TCC2 (0x1ul << PM_APBCMASK_TCC2_Pos) |
mbed_official | 579:53297373a894 | 354 | #define PM_APBCMASK_TC3_Pos 11 /**< \brief (PM_APBCMASK) TC3 APB Clock Enable */ |
mbed_official | 579:53297373a894 | 355 | #define PM_APBCMASK_TC3 (0x1ul << PM_APBCMASK_TC3_Pos) |
mbed_official | 579:53297373a894 | 356 | #define PM_APBCMASK_TC4_Pos 12 /**< \brief (PM_APBCMASK) TC4 APB Clock Enable */ |
mbed_official | 579:53297373a894 | 357 | #define PM_APBCMASK_TC4 (0x1ul << PM_APBCMASK_TC4_Pos) |
mbed_official | 579:53297373a894 | 358 | #define PM_APBCMASK_TC5_Pos 13 /**< \brief (PM_APBCMASK) TC5 APB Clock Enable */ |
mbed_official | 579:53297373a894 | 359 | #define PM_APBCMASK_TC5 (0x1ul << PM_APBCMASK_TC5_Pos) |
mbed_official | 579:53297373a894 | 360 | #define PM_APBCMASK_TC6_Pos 14 /**< \brief (PM_APBCMASK) TC6 APB Clock Enable */ |
mbed_official | 579:53297373a894 | 361 | #define PM_APBCMASK_TC6 (0x1ul << PM_APBCMASK_TC6_Pos) |
mbed_official | 579:53297373a894 | 362 | #define PM_APBCMASK_TC7_Pos 15 /**< \brief (PM_APBCMASK) TC7 APB Clock Enable */ |
mbed_official | 579:53297373a894 | 363 | #define PM_APBCMASK_TC7 (0x1ul << PM_APBCMASK_TC7_Pos) |
mbed_official | 579:53297373a894 | 364 | #define PM_APBCMASK_ADC_Pos 16 /**< \brief (PM_APBCMASK) ADC APB Clock Enable */ |
mbed_official | 579:53297373a894 | 365 | #define PM_APBCMASK_ADC (0x1ul << PM_APBCMASK_ADC_Pos) |
mbed_official | 579:53297373a894 | 366 | #define PM_APBCMASK_AC_Pos 17 /**< \brief (PM_APBCMASK) AC APB Clock Enable */ |
mbed_official | 579:53297373a894 | 367 | #define PM_APBCMASK_AC (0x1ul << PM_APBCMASK_AC_Pos) |
mbed_official | 579:53297373a894 | 368 | #define PM_APBCMASK_DAC_Pos 18 /**< \brief (PM_APBCMASK) DAC APB Clock Enable */ |
mbed_official | 579:53297373a894 | 369 | #define PM_APBCMASK_DAC (0x1ul << PM_APBCMASK_DAC_Pos) |
mbed_official | 579:53297373a894 | 370 | #define PM_APBCMASK_PTC_Pos 19 /**< \brief (PM_APBCMASK) PTC APB Clock Enable */ |
mbed_official | 579:53297373a894 | 371 | #define PM_APBCMASK_PTC (0x1ul << PM_APBCMASK_PTC_Pos) |
mbed_official | 579:53297373a894 | 372 | #define PM_APBCMASK_I2S_Pos 20 /**< \brief (PM_APBCMASK) I2S APB Clock Enable */ |
mbed_official | 579:53297373a894 | 373 | #define PM_APBCMASK_I2S (0x1ul << PM_APBCMASK_I2S_Pos) |
mbed_official | 579:53297373a894 | 374 | #define PM_APBCMASK_MASK 0x001FFFFFul /**< \brief (PM_APBCMASK) MASK Register */ |
mbed_official | 579:53297373a894 | 375 | |
mbed_official | 579:53297373a894 | 376 | /* -------- PM_INTENCLR : (PM Offset: 0x34) (R/W 8) Interrupt Enable Clear -------- */ |
mbed_official | 579:53297373a894 | 377 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 378 | typedef union { |
mbed_official | 579:53297373a894 | 379 | struct { |
mbed_official | 579:53297373a894 | 380 | uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */ |
mbed_official | 579:53297373a894 | 381 | uint8_t :7; /*!< bit: 1.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 382 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 383 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 384 | } PM_INTENCLR_Type; |
mbed_official | 579:53297373a894 | 385 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 386 | |
mbed_official | 579:53297373a894 | 387 | #define PM_INTENCLR_OFFSET 0x34 /**< \brief (PM_INTENCLR offset) Interrupt Enable Clear */ |
mbed_official | 579:53297373a894 | 388 | #define PM_INTENCLR_RESETVALUE 0x00ul /**< \brief (PM_INTENCLR reset_value) Interrupt Enable Clear */ |
mbed_official | 579:53297373a894 | 389 | |
mbed_official | 579:53297373a894 | 390 | #define PM_INTENCLR_CKRDY_Pos 0 /**< \brief (PM_INTENCLR) Clock Ready Interrupt Enable */ |
mbed_official | 579:53297373a894 | 391 | #define PM_INTENCLR_CKRDY (0x1ul << PM_INTENCLR_CKRDY_Pos) |
mbed_official | 579:53297373a894 | 392 | #define PM_INTENCLR_MASK 0x01ul /**< \brief (PM_INTENCLR) MASK Register */ |
mbed_official | 579:53297373a894 | 393 | |
mbed_official | 579:53297373a894 | 394 | /* -------- PM_INTENSET : (PM Offset: 0x35) (R/W 8) Interrupt Enable Set -------- */ |
mbed_official | 579:53297373a894 | 395 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 396 | typedef union { |
mbed_official | 579:53297373a894 | 397 | struct { |
mbed_official | 579:53297373a894 | 398 | uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */ |
mbed_official | 579:53297373a894 | 399 | uint8_t :7; /*!< bit: 1.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 400 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 401 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 402 | } PM_INTENSET_Type; |
mbed_official | 579:53297373a894 | 403 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 404 | |
mbed_official | 579:53297373a894 | 405 | #define PM_INTENSET_OFFSET 0x35 /**< \brief (PM_INTENSET offset) Interrupt Enable Set */ |
mbed_official | 579:53297373a894 | 406 | #define PM_INTENSET_RESETVALUE 0x00ul /**< \brief (PM_INTENSET reset_value) Interrupt Enable Set */ |
mbed_official | 579:53297373a894 | 407 | |
mbed_official | 579:53297373a894 | 408 | #define PM_INTENSET_CKRDY_Pos 0 /**< \brief (PM_INTENSET) Clock Ready Interrupt Enable */ |
mbed_official | 579:53297373a894 | 409 | #define PM_INTENSET_CKRDY (0x1ul << PM_INTENSET_CKRDY_Pos) |
mbed_official | 579:53297373a894 | 410 | #define PM_INTENSET_MASK 0x01ul /**< \brief (PM_INTENSET) MASK Register */ |
mbed_official | 579:53297373a894 | 411 | |
mbed_official | 579:53297373a894 | 412 | /* -------- PM_INTFLAG : (PM Offset: 0x36) (R/W 8) Interrupt Flag Status and Clear -------- */ |
mbed_official | 579:53297373a894 | 413 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 414 | typedef union { |
mbed_official | 579:53297373a894 | 415 | struct { |
mbed_official | 579:53297373a894 | 416 | uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */ |
mbed_official | 579:53297373a894 | 417 | uint8_t :7; /*!< bit: 1.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 418 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 419 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 420 | } PM_INTFLAG_Type; |
mbed_official | 579:53297373a894 | 421 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 422 | |
mbed_official | 579:53297373a894 | 423 | #define PM_INTFLAG_OFFSET 0x36 /**< \brief (PM_INTFLAG offset) Interrupt Flag Status and Clear */ |
mbed_official | 579:53297373a894 | 424 | #define PM_INTFLAG_RESETVALUE 0x00ul /**< \brief (PM_INTFLAG reset_value) Interrupt Flag Status and Clear */ |
mbed_official | 579:53297373a894 | 425 | |
mbed_official | 579:53297373a894 | 426 | #define PM_INTFLAG_CKRDY_Pos 0 /**< \brief (PM_INTFLAG) Clock Ready */ |
mbed_official | 579:53297373a894 | 427 | #define PM_INTFLAG_CKRDY (0x1ul << PM_INTFLAG_CKRDY_Pos) |
mbed_official | 579:53297373a894 | 428 | #define PM_INTFLAG_MASK 0x01ul /**< \brief (PM_INTFLAG) MASK Register */ |
mbed_official | 579:53297373a894 | 429 | |
mbed_official | 579:53297373a894 | 430 | /* -------- PM_RCAUSE : (PM Offset: 0x38) (R/ 8) Reset Cause -------- */ |
mbed_official | 579:53297373a894 | 431 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 432 | typedef union { |
mbed_official | 579:53297373a894 | 433 | struct { |
mbed_official | 579:53297373a894 | 434 | uint8_t POR:1; /*!< bit: 0 Power On Reset */ |
mbed_official | 579:53297373a894 | 435 | uint8_t BOD12:1; /*!< bit: 1 Brown Out 12 Detector Reset */ |
mbed_official | 579:53297373a894 | 436 | uint8_t BOD33:1; /*!< bit: 2 Brown Out 33 Detector Reset */ |
mbed_official | 579:53297373a894 | 437 | uint8_t :1; /*!< bit: 3 Reserved */ |
mbed_official | 579:53297373a894 | 438 | uint8_t EXT:1; /*!< bit: 4 External Reset */ |
mbed_official | 579:53297373a894 | 439 | uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */ |
mbed_official | 579:53297373a894 | 440 | uint8_t SYST:1; /*!< bit: 6 System Reset Request */ |
mbed_official | 579:53297373a894 | 441 | uint8_t :1; /*!< bit: 7 Reserved */ |
mbed_official | 579:53297373a894 | 442 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 443 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 444 | } PM_RCAUSE_Type; |
mbed_official | 579:53297373a894 | 445 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 446 | |
mbed_official | 579:53297373a894 | 447 | #define PM_RCAUSE_OFFSET 0x38 /**< \brief (PM_RCAUSE offset) Reset Cause */ |
mbed_official | 579:53297373a894 | 448 | #define PM_RCAUSE_RESETVALUE 0x01ul /**< \brief (PM_RCAUSE reset_value) Reset Cause */ |
mbed_official | 579:53297373a894 | 449 | |
mbed_official | 579:53297373a894 | 450 | #define PM_RCAUSE_POR_Pos 0 /**< \brief (PM_RCAUSE) Power On Reset */ |
mbed_official | 579:53297373a894 | 451 | #define PM_RCAUSE_POR (0x1ul << PM_RCAUSE_POR_Pos) |
mbed_official | 579:53297373a894 | 452 | #define PM_RCAUSE_BOD12_Pos 1 /**< \brief (PM_RCAUSE) Brown Out 12 Detector Reset */ |
mbed_official | 579:53297373a894 | 453 | #define PM_RCAUSE_BOD12 (0x1ul << PM_RCAUSE_BOD12_Pos) |
mbed_official | 579:53297373a894 | 454 | #define PM_RCAUSE_BOD33_Pos 2 /**< \brief (PM_RCAUSE) Brown Out 33 Detector Reset */ |
mbed_official | 579:53297373a894 | 455 | #define PM_RCAUSE_BOD33 (0x1ul << PM_RCAUSE_BOD33_Pos) |
mbed_official | 579:53297373a894 | 456 | #define PM_RCAUSE_EXT_Pos 4 /**< \brief (PM_RCAUSE) External Reset */ |
mbed_official | 579:53297373a894 | 457 | #define PM_RCAUSE_EXT (0x1ul << PM_RCAUSE_EXT_Pos) |
mbed_official | 579:53297373a894 | 458 | #define PM_RCAUSE_WDT_Pos 5 /**< \brief (PM_RCAUSE) Watchdog Reset */ |
mbed_official | 579:53297373a894 | 459 | #define PM_RCAUSE_WDT (0x1ul << PM_RCAUSE_WDT_Pos) |
mbed_official | 579:53297373a894 | 460 | #define PM_RCAUSE_SYST_Pos 6 /**< \brief (PM_RCAUSE) System Reset Request */ |
mbed_official | 579:53297373a894 | 461 | #define PM_RCAUSE_SYST (0x1ul << PM_RCAUSE_SYST_Pos) |
mbed_official | 579:53297373a894 | 462 | #define PM_RCAUSE_MASK 0x77ul /**< \brief (PM_RCAUSE) MASK Register */ |
mbed_official | 579:53297373a894 | 463 | |
mbed_official | 579:53297373a894 | 464 | /** \brief PM hardware registers */ |
mbed_official | 579:53297373a894 | 465 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 466 | typedef struct { |
mbed_official | 579:53297373a894 | 467 | __IO PM_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */ |
mbed_official | 579:53297373a894 | 468 | __IO PM_SLEEP_Type SLEEP; /**< \brief Offset: 0x01 (R/W 8) Sleep Mode */ |
mbed_official | 579:53297373a894 | 469 | RoReg8 Reserved1[0x6]; |
mbed_official | 579:53297373a894 | 470 | __IO PM_CPUSEL_Type CPUSEL; /**< \brief Offset: 0x08 (R/W 8) CPU Clock Select */ |
mbed_official | 579:53297373a894 | 471 | __IO PM_APBASEL_Type APBASEL; /**< \brief Offset: 0x09 (R/W 8) APBA Clock Select */ |
mbed_official | 579:53297373a894 | 472 | __IO PM_APBBSEL_Type APBBSEL; /**< \brief Offset: 0x0A (R/W 8) APBB Clock Select */ |
mbed_official | 579:53297373a894 | 473 | __IO PM_APBCSEL_Type APBCSEL; /**< \brief Offset: 0x0B (R/W 8) APBC Clock Select */ |
mbed_official | 579:53297373a894 | 474 | RoReg8 Reserved2[0x8]; |
mbed_official | 579:53297373a894 | 475 | __IO PM_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x14 (R/W 32) AHB Mask */ |
mbed_official | 579:53297373a894 | 476 | __IO PM_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x18 (R/W 32) APBA Mask */ |
mbed_official | 579:53297373a894 | 477 | __IO PM_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x1C (R/W 32) APBB Mask */ |
mbed_official | 579:53297373a894 | 478 | __IO PM_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x20 (R/W 32) APBC Mask */ |
mbed_official | 579:53297373a894 | 479 | RoReg8 Reserved3[0x10]; |
mbed_official | 579:53297373a894 | 480 | __IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x34 (R/W 8) Interrupt Enable Clear */ |
mbed_official | 579:53297373a894 | 481 | __IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x35 (R/W 8) Interrupt Enable Set */ |
mbed_official | 579:53297373a894 | 482 | __IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x36 (R/W 8) Interrupt Flag Status and Clear */ |
mbed_official | 579:53297373a894 | 483 | RoReg8 Reserved4[0x1]; |
mbed_official | 579:53297373a894 | 484 | __I PM_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x38 (R/ 8) Reset Cause */ |
mbed_official | 579:53297373a894 | 485 | } Pm; |
mbed_official | 579:53297373a894 | 486 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 487 | |
mbed_official | 579:53297373a894 | 488 | /*@}*/ |
mbed_official | 579:53297373a894 | 489 | |
mbed_official | 579:53297373a894 | 490 | #endif /* _SAMD21_PM_COMPONENT_ */ |