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targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_mtb.h@592:a274ee790e56, 2015-07-17 (annotated)

Committer:
mbed_official
Date:
Fri Jul 17 09:15:10 2015 +0100
Revision:
592:a274ee790e56
Parent:
579:53297373a894 
Synchronized with git revision e7144f83a8d75df80c4877936b6ffe552b0be9e6



Full URL: https://github.com/mbedmicro/mbed/commit/e7144f83a8d75df80c4877936b6ffe552b0be9e6/



More API implementation for SAMR21

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UserRevisionLine numberNew contents of line
mbed_official 579:53297373a894 1 #ifndef _SAMD21_MTB_COMPONENT_
mbed_official 579:53297373a894 2 #define _SAMD21_MTB_COMPONENT_
mbed_official 579:53297373a894 3
mbed_official 579:53297373a894 4 /* ========================================================================== */
mbed_official 579:53297373a894 5 /** SOFTWARE API DEFINITION FOR MTB */
mbed_official 579:53297373a894 6 /* ========================================================================== */
mbed_official 579:53297373a894 7 /** \addtogroup SAMD21_MTB Cortex-M0+ Micro-Trace Buffer */
mbed_official 579:53297373a894 8 /*@{*/
mbed_official 579:53297373a894 9
mbed_official 579:53297373a894 10 #define MTB_U2002
mbed_official 579:53297373a894 11 #define REV_MTB 0x100
mbed_official 579:53297373a894 12
mbed_official 579:53297373a894 13 /* -------- MTB_POSITION : (MTB Offset: 0x000) (R/W 32) MTB Position -------- */
mbed_official 579:53297373a894 14 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 15 typedef union {
mbed_official 579:53297373a894 16 struct {
mbed_official 579:53297373a894 17 uint32_t :2; /*!< bit: 0.. 1 Reserved */
mbed_official 579:53297373a894 18 uint32_t WRAP:1; /*!< bit: 2 Pointer Value Wraps */
mbed_official 579:53297373a894 19 uint32_t POINTER:29; /*!< bit: 3..31 Trace Packet Location Pointer */
mbed_official 579:53297373a894 20 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 21 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 22 } MTB_POSITION_Type;
mbed_official 579:53297373a894 23 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 24
mbed_official 579:53297373a894 25 #define MTB_POSITION_OFFSET 0x000 /**< \brief (MTB_POSITION offset) MTB Position */
mbed_official 579:53297373a894 26
mbed_official 579:53297373a894 27 #define MTB_POSITION_WRAP_Pos 2 /**< \brief (MTB_POSITION) Pointer Value Wraps */
mbed_official 579:53297373a894 28 #define MTB_POSITION_WRAP (0x1ul << MTB_POSITION_WRAP_Pos)
mbed_official 579:53297373a894 29 #define MTB_POSITION_POINTER_Pos 3 /**< \brief (MTB_POSITION) Trace Packet Location Pointer */
mbed_official 579:53297373a894 30 #define MTB_POSITION_POINTER_Msk (0x1FFFFFFFul << MTB_POSITION_POINTER_Pos)
mbed_official 579:53297373a894 31 #define MTB_POSITION_POINTER(value) ((MTB_POSITION_POINTER_Msk & ((value) << MTB_POSITION_POINTER_Pos)))
mbed_official 579:53297373a894 32 #define MTB_POSITION_MASK 0xFFFFFFFCul /**< \brief (MTB_POSITION) MASK Register */
mbed_official 579:53297373a894 33
mbed_official 579:53297373a894 34 /* -------- MTB_MASTER : (MTB Offset: 0x004) (R/W 32) MTB Master -------- */
mbed_official 579:53297373a894 35 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 36 typedef union {
mbed_official 579:53297373a894 37 struct {
mbed_official 579:53297373a894 38 uint32_t MASK:5; /*!< bit: 0.. 4 Maximum Value of the Trace Buffer in SRAM */
mbed_official 579:53297373a894 39 uint32_t TSTARTEN:1; /*!< bit: 5 Trace Start Input Enable */
mbed_official 579:53297373a894 40 uint32_t TSTOPEN:1; /*!< bit: 6 Trace Stop Input Enable */
mbed_official 579:53297373a894 41 uint32_t SFRWPRIV:1; /*!< bit: 7 Special Function Register Write Privilege */
mbed_official 579:53297373a894 42 uint32_t RAMPRIV:1; /*!< bit: 8 SRAM Privilege */
mbed_official 579:53297373a894 43 uint32_t HALTREQ:1; /*!< bit: 9 Halt Request */
mbed_official 579:53297373a894 44 uint32_t :21; /*!< bit: 10..30 Reserved */
mbed_official 579:53297373a894 45 uint32_t EN:1; /*!< bit: 31 Main Trace Enable */
mbed_official 579:53297373a894 46 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 47 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 48 } MTB_MASTER_Type;
mbed_official 579:53297373a894 49 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 50
mbed_official 579:53297373a894 51 #define MTB_MASTER_OFFSET 0x004 /**< \brief (MTB_MASTER offset) MTB Master */
mbed_official 579:53297373a894 52 #define MTB_MASTER_RESETVALUE 0x00000000ul /**< \brief (MTB_MASTER reset_value) MTB Master */
mbed_official 579:53297373a894 53
mbed_official 579:53297373a894 54 #define MTB_MASTER_MASK_Pos 0 /**< \brief (MTB_MASTER) Maximum Value of the Trace Buffer in SRAM */
mbed_official 579:53297373a894 55 #define MTB_MASTER_MASK_Msk (0x1Ful << MTB_MASTER_MASK_Pos)
mbed_official 579:53297373a894 56 #define MTB_MASTER_MASK(value) ((MTB_MASTER_MASK_Msk & ((value) << MTB_MASTER_MASK_Pos)))
mbed_official 579:53297373a894 57 #define MTB_MASTER_TSTARTEN_Pos 5 /**< \brief (MTB_MASTER) Trace Start Input Enable */
mbed_official 579:53297373a894 58 #define MTB_MASTER_TSTARTEN (0x1ul << MTB_MASTER_TSTARTEN_Pos)
mbed_official 579:53297373a894 59 #define MTB_MASTER_TSTOPEN_Pos 6 /**< \brief (MTB_MASTER) Trace Stop Input Enable */
mbed_official 579:53297373a894 60 #define MTB_MASTER_TSTOPEN (0x1ul << MTB_MASTER_TSTOPEN_Pos)
mbed_official 579:53297373a894 61 #define MTB_MASTER_SFRWPRIV_Pos 7 /**< \brief (MTB_MASTER) Special Function Register Write Privilege */
mbed_official 579:53297373a894 62 #define MTB_MASTER_SFRWPRIV (0x1ul << MTB_MASTER_SFRWPRIV_Pos)
mbed_official 579:53297373a894 63 #define MTB_MASTER_RAMPRIV_Pos 8 /**< \brief (MTB_MASTER) SRAM Privilege */
mbed_official 579:53297373a894 64 #define MTB_MASTER_RAMPRIV (0x1ul << MTB_MASTER_RAMPRIV_Pos)
mbed_official 579:53297373a894 65 #define MTB_MASTER_HALTREQ_Pos 9 /**< \brief (MTB_MASTER) Halt Request */
mbed_official 579:53297373a894 66 #define MTB_MASTER_HALTREQ (0x1ul << MTB_MASTER_HALTREQ_Pos)
mbed_official 579:53297373a894 67 #define MTB_MASTER_EN_Pos 31 /**< \brief (MTB_MASTER) Main Trace Enable */
mbed_official 579:53297373a894 68 #define MTB_MASTER_EN (0x1ul << MTB_MASTER_EN_Pos)
mbed_official 579:53297373a894 69 #define MTB_MASTER_MASK_ 0x800003FFul /**< \brief (MTB_MASTER) MASK Register */
mbed_official 579:53297373a894 70
mbed_official 579:53297373a894 71 /* -------- MTB_FLOW : (MTB Offset: 0x008) (R/W 32) MTB Flow -------- */
mbed_official 579:53297373a894 72 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 73 typedef union {
mbed_official 579:53297373a894 74 struct {
mbed_official 579:53297373a894 75 uint32_t AUTOSTOP:1; /*!< bit: 0 Auto Stop Tracing */
mbed_official 579:53297373a894 76 uint32_t AUTOHALT:1; /*!< bit: 1 Auto Halt Request */
mbed_official 579:53297373a894 77 uint32_t :1; /*!< bit: 2 Reserved */
mbed_official 579:53297373a894 78 uint32_t WATERMARK:29; /*!< bit: 3..31 Watermark value */
mbed_official 579:53297373a894 79 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 80 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 81 } MTB_FLOW_Type;
mbed_official 579:53297373a894 82 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 83
mbed_official 579:53297373a894 84 #define MTB_FLOW_OFFSET 0x008 /**< \brief (MTB_FLOW offset) MTB Flow */
mbed_official 579:53297373a894 85 #define MTB_FLOW_RESETVALUE 0x00000000ul /**< \brief (MTB_FLOW reset_value) MTB Flow */
mbed_official 579:53297373a894 86
mbed_official 579:53297373a894 87 #define MTB_FLOW_AUTOSTOP_Pos 0 /**< \brief (MTB_FLOW) Auto Stop Tracing */
mbed_official 579:53297373a894 88 #define MTB_FLOW_AUTOSTOP (0x1ul << MTB_FLOW_AUTOSTOP_Pos)
mbed_official 579:53297373a894 89 #define MTB_FLOW_AUTOHALT_Pos 1 /**< \brief (MTB_FLOW) Auto Halt Request */
mbed_official 579:53297373a894 90 #define MTB_FLOW_AUTOHALT (0x1ul << MTB_FLOW_AUTOHALT_Pos)
mbed_official 579:53297373a894 91 #define MTB_FLOW_WATERMARK_Pos 3 /**< \brief (MTB_FLOW) Watermark value */
mbed_official 579:53297373a894 92 #define MTB_FLOW_WATERMARK_Msk (0x1FFFFFFFul << MTB_FLOW_WATERMARK_Pos)
mbed_official 579:53297373a894 93 #define MTB_FLOW_WATERMARK(value) ((MTB_FLOW_WATERMARK_Msk & ((value) << MTB_FLOW_WATERMARK_Pos)))
mbed_official 579:53297373a894 94 #define MTB_FLOW_MASK 0xFFFFFFFBul /**< \brief (MTB_FLOW) MASK Register */
mbed_official 579:53297373a894 95
mbed_official 579:53297373a894 96 /* -------- MTB_BASE : (MTB Offset: 0x00C) (R/ 32) MTB Base -------- */
mbed_official 579:53297373a894 97 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 98 typedef union {
mbed_official 579:53297373a894 99 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 100 } MTB_BASE_Type;
mbed_official 579:53297373a894 101 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 102
mbed_official 579:53297373a894 103 #define MTB_BASE_OFFSET 0x00C /**< \brief (MTB_BASE offset) MTB Base */
mbed_official 579:53297373a894 104 #define MTB_BASE_MASK 0xFFFFFFFFul /**< \brief (MTB_BASE) MASK Register */
mbed_official 579:53297373a894 105
mbed_official 579:53297373a894 106 /* -------- MTB_ITCTRL : (MTB Offset: 0xF00) (R/W 32) MTB Integration Mode Control -------- */
mbed_official 579:53297373a894 107 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 108 typedef union {
mbed_official 579:53297373a894 109 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 110 } MTB_ITCTRL_Type;
mbed_official 579:53297373a894 111 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 112
mbed_official 579:53297373a894 113 #define MTB_ITCTRL_OFFSET 0xF00 /**< \brief (MTB_ITCTRL offset) MTB Integration Mode Control */
mbed_official 579:53297373a894 114 #define MTB_ITCTRL_MASK 0xFFFFFFFFul /**< \brief (MTB_ITCTRL) MASK Register */
mbed_official 579:53297373a894 115
mbed_official 579:53297373a894 116 /* -------- MTB_CLAIMSET : (MTB Offset: 0xFA0) (R/W 32) MTB Claim Set -------- */
mbed_official 579:53297373a894 117 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 118 typedef union {
mbed_official 579:53297373a894 119 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 120 } MTB_CLAIMSET_Type;
mbed_official 579:53297373a894 121 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 122
mbed_official 579:53297373a894 123 #define MTB_CLAIMSET_OFFSET 0xFA0 /**< \brief (MTB_CLAIMSET offset) MTB Claim Set */
mbed_official 579:53297373a894 124 #define MTB_CLAIMSET_MASK 0xFFFFFFFFul /**< \brief (MTB_CLAIMSET) MASK Register */
mbed_official 579:53297373a894 125
mbed_official 579:53297373a894 126 /* -------- MTB_CLAIMCLR : (MTB Offset: 0xFA4) (R/W 32) MTB Claim Clear -------- */
mbed_official 579:53297373a894 127 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 128 typedef union {
mbed_official 579:53297373a894 129 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 130 } MTB_CLAIMCLR_Type;
mbed_official 579:53297373a894 131 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 132
mbed_official 579:53297373a894 133 #define MTB_CLAIMCLR_OFFSET 0xFA4 /**< \brief (MTB_CLAIMCLR offset) MTB Claim Clear */
mbed_official 579:53297373a894 134 #define MTB_CLAIMCLR_MASK 0xFFFFFFFFul /**< \brief (MTB_CLAIMCLR) MASK Register */
mbed_official 579:53297373a894 135
mbed_official 579:53297373a894 136 /* -------- MTB_LOCKACCESS : (MTB Offset: 0xFB0) (R/W 32) MTB Lock Access -------- */
mbed_official 579:53297373a894 137 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 138 typedef union {
mbed_official 579:53297373a894 139 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 140 } MTB_LOCKACCESS_Type;
mbed_official 579:53297373a894 141 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 142
mbed_official 579:53297373a894 143 #define MTB_LOCKACCESS_OFFSET 0xFB0 /**< \brief (MTB_LOCKACCESS offset) MTB Lock Access */
mbed_official 579:53297373a894 144 #define MTB_LOCKACCESS_MASK 0xFFFFFFFFul /**< \brief (MTB_LOCKACCESS) MASK Register */
mbed_official 579:53297373a894 145
mbed_official 579:53297373a894 146 /* -------- MTB_LOCKSTATUS : (MTB Offset: 0xFB4) (R/ 32) MTB Lock Status -------- */
mbed_official 579:53297373a894 147 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 148 typedef union {
mbed_official 579:53297373a894 149 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 150 } MTB_LOCKSTATUS_Type;
mbed_official 579:53297373a894 151 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 152
mbed_official 579:53297373a894 153 #define MTB_LOCKSTATUS_OFFSET 0xFB4 /**< \brief (MTB_LOCKSTATUS offset) MTB Lock Status */
mbed_official 579:53297373a894 154 #define MTB_LOCKSTATUS_MASK 0xFFFFFFFFul /**< \brief (MTB_LOCKSTATUS) MASK Register */
mbed_official 579:53297373a894 155
mbed_official 579:53297373a894 156 /* -------- MTB_AUTHSTATUS : (MTB Offset: 0xFB8) (R/ 32) MTB Authentication Status -------- */
mbed_official 579:53297373a894 157 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 158 typedef union {
mbed_official 579:53297373a894 159 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 160 } MTB_AUTHSTATUS_Type;
mbed_official 579:53297373a894 161 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 162
mbed_official 579:53297373a894 163 #define MTB_AUTHSTATUS_OFFSET 0xFB8 /**< \brief (MTB_AUTHSTATUS offset) MTB Authentication Status */
mbed_official 579:53297373a894 164 #define MTB_AUTHSTATUS_MASK 0xFFFFFFFFul /**< \brief (MTB_AUTHSTATUS) MASK Register */
mbed_official 579:53297373a894 165
mbed_official 579:53297373a894 166 /* -------- MTB_DEVARCH : (MTB Offset: 0xFBC) (R/ 32) MTB Device Architecture -------- */
mbed_official 579:53297373a894 167 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 168 typedef union {
mbed_official 579:53297373a894 169 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 170 } MTB_DEVARCH_Type;
mbed_official 579:53297373a894 171 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 172
mbed_official 579:53297373a894 173 #define MTB_DEVARCH_OFFSET 0xFBC /**< \brief (MTB_DEVARCH offset) MTB Device Architecture */
mbed_official 579:53297373a894 174 #define MTB_DEVARCH_MASK 0xFFFFFFFFul /**< \brief (MTB_DEVARCH) MASK Register */
mbed_official 579:53297373a894 175
mbed_official 579:53297373a894 176 /* -------- MTB_DEVID : (MTB Offset: 0xFC8) (R/ 32) MTB Device Configuration -------- */
mbed_official 579:53297373a894 177 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 178 typedef union {
mbed_official 579:53297373a894 179 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 180 } MTB_DEVID_Type;
mbed_official 579:53297373a894 181 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 182
mbed_official 579:53297373a894 183 #define MTB_DEVID_OFFSET 0xFC8 /**< \brief (MTB_DEVID offset) MTB Device Configuration */
mbed_official 579:53297373a894 184 #define MTB_DEVID_MASK 0xFFFFFFFFul /**< \brief (MTB_DEVID) MASK Register */
mbed_official 579:53297373a894 185
mbed_official 579:53297373a894 186 /* -------- MTB_DEVTYPE : (MTB Offset: 0xFCC) (R/ 32) MTB Device Type -------- */
mbed_official 579:53297373a894 187 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 188 typedef union {
mbed_official 579:53297373a894 189 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 190 } MTB_DEVTYPE_Type;
mbed_official 579:53297373a894 191 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 192
mbed_official 579:53297373a894 193 #define MTB_DEVTYPE_OFFSET 0xFCC /**< \brief (MTB_DEVTYPE offset) MTB Device Type */
mbed_official 579:53297373a894 194 #define MTB_DEVTYPE_MASK 0xFFFFFFFFul /**< \brief (MTB_DEVTYPE) MASK Register */
mbed_official 579:53297373a894 195
mbed_official 579:53297373a894 196 /* -------- MTB_PID4 : (MTB Offset: 0xFD0) (R/ 32) CoreSight -------- */
mbed_official 579:53297373a894 197 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 198 typedef union {
mbed_official 579:53297373a894 199 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 200 } MTB_PID4_Type;
mbed_official 579:53297373a894 201 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 202
mbed_official 579:53297373a894 203 #define MTB_PID4_OFFSET 0xFD0 /**< \brief (MTB_PID4 offset) CoreSight */
mbed_official 579:53297373a894 204 #define MTB_PID4_MASK 0xFFFFFFFFul /**< \brief (MTB_PID4) MASK Register */
mbed_official 579:53297373a894 205
mbed_official 579:53297373a894 206 /* -------- MTB_PID5 : (MTB Offset: 0xFD4) (R/ 32) CoreSight -------- */
mbed_official 579:53297373a894 207 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 208 typedef union {
mbed_official 579:53297373a894 209 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 210 } MTB_PID5_Type;
mbed_official 579:53297373a894 211 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 212
mbed_official 579:53297373a894 213 #define MTB_PID5_OFFSET 0xFD4 /**< \brief (MTB_PID5 offset) CoreSight */
mbed_official 579:53297373a894 214 #define MTB_PID5_MASK 0xFFFFFFFFul /**< \brief (MTB_PID5) MASK Register */
mbed_official 579:53297373a894 215
mbed_official 579:53297373a894 216 /* -------- MTB_PID6 : (MTB Offset: 0xFD8) (R/ 32) CoreSight -------- */
mbed_official 579:53297373a894 217 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 218 typedef union {
mbed_official 579:53297373a894 219 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 220 } MTB_PID6_Type;
mbed_official 579:53297373a894 221 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 222
mbed_official 579:53297373a894 223 #define MTB_PID6_OFFSET 0xFD8 /**< \brief (MTB_PID6 offset) CoreSight */
mbed_official 579:53297373a894 224 #define MTB_PID6_MASK 0xFFFFFFFFul /**< \brief (MTB_PID6) MASK Register */
mbed_official 579:53297373a894 225
mbed_official 579:53297373a894 226 /* -------- MTB_PID7 : (MTB Offset: 0xFDC) (R/ 32) CoreSight -------- */
mbed_official 579:53297373a894 227 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 228 typedef union {
mbed_official 579:53297373a894 229 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 230 } MTB_PID7_Type;
mbed_official 579:53297373a894 231 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 232
mbed_official 579:53297373a894 233 #define MTB_PID7_OFFSET 0xFDC /**< \brief (MTB_PID7 offset) CoreSight */
mbed_official 579:53297373a894 234 #define MTB_PID7_MASK 0xFFFFFFFFul /**< \brief (MTB_PID7) MASK Register */
mbed_official 579:53297373a894 235
mbed_official 579:53297373a894 236 /* -------- MTB_PID0 : (MTB Offset: 0xFE0) (R/ 32) CoreSight -------- */
mbed_official 579:53297373a894 237 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 238 typedef union {
mbed_official 579:53297373a894 239 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 240 } MTB_PID0_Type;
mbed_official 579:53297373a894 241 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 242
mbed_official 579:53297373a894 243 #define MTB_PID0_OFFSET 0xFE0 /**< \brief (MTB_PID0 offset) CoreSight */
mbed_official 579:53297373a894 244 #define MTB_PID0_MASK 0xFFFFFFFFul /**< \brief (MTB_PID0) MASK Register */
mbed_official 579:53297373a894 245
mbed_official 579:53297373a894 246 /* -------- MTB_PID1 : (MTB Offset: 0xFE4) (R/ 32) CoreSight -------- */
mbed_official 579:53297373a894 247 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 248 typedef union {
mbed_official 579:53297373a894 249 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 250 } MTB_PID1_Type;
mbed_official 579:53297373a894 251 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 252
mbed_official 579:53297373a894 253 #define MTB_PID1_OFFSET 0xFE4 /**< \brief (MTB_PID1 offset) CoreSight */
mbed_official 579:53297373a894 254 #define MTB_PID1_MASK 0xFFFFFFFFul /**< \brief (MTB_PID1) MASK Register */
mbed_official 579:53297373a894 255
mbed_official 579:53297373a894 256 /* -------- MTB_PID2 : (MTB Offset: 0xFE8) (R/ 32) CoreSight -------- */
mbed_official 579:53297373a894 257 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 258 typedef union {
mbed_official 579:53297373a894 259 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 260 } MTB_PID2_Type;
mbed_official 579:53297373a894 261 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 262
mbed_official 579:53297373a894 263 #define MTB_PID2_OFFSET 0xFE8 /**< \brief (MTB_PID2 offset) CoreSight */
mbed_official 579:53297373a894 264 #define MTB_PID2_MASK 0xFFFFFFFFul /**< \brief (MTB_PID2) MASK Register */
mbed_official 579:53297373a894 265
mbed_official 579:53297373a894 266 /* -------- MTB_PID3 : (MTB Offset: 0xFEC) (R/ 32) CoreSight -------- */
mbed_official 579:53297373a894 267 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 268 typedef union {
mbed_official 579:53297373a894 269 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 270 } MTB_PID3_Type;
mbed_official 579:53297373a894 271 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 272
mbed_official 579:53297373a894 273 #define MTB_PID3_OFFSET 0xFEC /**< \brief (MTB_PID3 offset) CoreSight */
mbed_official 579:53297373a894 274 #define MTB_PID3_MASK 0xFFFFFFFFul /**< \brief (MTB_PID3) MASK Register */
mbed_official 579:53297373a894 275
mbed_official 579:53297373a894 276 /* -------- MTB_CID0 : (MTB Offset: 0xFF0) (R/ 32) CoreSight -------- */
mbed_official 579:53297373a894 277 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 278 typedef union {
mbed_official 579:53297373a894 279 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 280 } MTB_CID0_Type;
mbed_official 579:53297373a894 281 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 282
mbed_official 579:53297373a894 283 #define MTB_CID0_OFFSET 0xFF0 /**< \brief (MTB_CID0 offset) CoreSight */
mbed_official 579:53297373a894 284 #define MTB_CID0_MASK 0xFFFFFFFFul /**< \brief (MTB_CID0) MASK Register */
mbed_official 579:53297373a894 285
mbed_official 579:53297373a894 286 /* -------- MTB_CID1 : (MTB Offset: 0xFF4) (R/ 32) CoreSight -------- */
mbed_official 579:53297373a894 287 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 288 typedef union {
mbed_official 579:53297373a894 289 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 290 } MTB_CID1_Type;
mbed_official 579:53297373a894 291 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 292
mbed_official 579:53297373a894 293 #define MTB_CID1_OFFSET 0xFF4 /**< \brief (MTB_CID1 offset) CoreSight */
mbed_official 579:53297373a894 294 #define MTB_CID1_MASK 0xFFFFFFFFul /**< \brief (MTB_CID1) MASK Register */
mbed_official 579:53297373a894 295
mbed_official 579:53297373a894 296 /* -------- MTB_CID2 : (MTB Offset: 0xFF8) (R/ 32) CoreSight -------- */
mbed_official 579:53297373a894 297 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 298 typedef union {
mbed_official 579:53297373a894 299 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 300 } MTB_CID2_Type;
mbed_official 579:53297373a894 301 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 302
mbed_official 579:53297373a894 303 #define MTB_CID2_OFFSET 0xFF8 /**< \brief (MTB_CID2 offset) CoreSight */
mbed_official 579:53297373a894 304 #define MTB_CID2_MASK 0xFFFFFFFFul /**< \brief (MTB_CID2) MASK Register */
mbed_official 579:53297373a894 305
mbed_official 579:53297373a894 306 /* -------- MTB_CID3 : (MTB Offset: 0xFFC) (R/ 32) CoreSight -------- */
mbed_official 579:53297373a894 307 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 308 typedef union {
mbed_official 579:53297373a894 309 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 310 } MTB_CID3_Type;
mbed_official 579:53297373a894 311 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 312
mbed_official 579:53297373a894 313 #define MTB_CID3_OFFSET 0xFFC /**< \brief (MTB_CID3 offset) CoreSight */
mbed_official 579:53297373a894 314 #define MTB_CID3_MASK 0xFFFFFFFFul /**< \brief (MTB_CID3) MASK Register */
mbed_official 579:53297373a894 315
mbed_official 579:53297373a894 316 /** \brief MTB hardware registers */
mbed_official 579:53297373a894 317 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 318 typedef struct {
mbed_official 579:53297373a894 319 __IO MTB_POSITION_Type POSITION; /**< \brief Offset: 0x000 (R/W 32) MTB Position */
mbed_official 579:53297373a894 320 __IO MTB_MASTER_Type MASTER; /**< \brief Offset: 0x004 (R/W 32) MTB Master */
mbed_official 579:53297373a894 321 __IO MTB_FLOW_Type FLOW; /**< \brief Offset: 0x008 (R/W 32) MTB Flow */
mbed_official 579:53297373a894 322 __I MTB_BASE_Type BASE; /**< \brief Offset: 0x00C (R/ 32) MTB Base */
mbed_official 579:53297373a894 323 RoReg8 Reserved1[0xEF0];
mbed_official 579:53297373a894 324 __IO MTB_ITCTRL_Type ITCTRL; /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */
mbed_official 579:53297373a894 325 RoReg8 Reserved2[0x9C];
mbed_official 579:53297373a894 326 __IO MTB_CLAIMSET_Type CLAIMSET; /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */
mbed_official 579:53297373a894 327 __IO MTB_CLAIMCLR_Type CLAIMCLR; /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */
mbed_official 579:53297373a894 328 RoReg8 Reserved3[0x8];
mbed_official 579:53297373a894 329 __IO MTB_LOCKACCESS_Type LOCKACCESS; /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */
mbed_official 579:53297373a894 330 __I MTB_LOCKSTATUS_Type LOCKSTATUS; /**< \brief Offset: 0xFB4 (R/ 32) MTB Lock Status */
mbed_official 579:53297373a894 331 __I MTB_AUTHSTATUS_Type AUTHSTATUS; /**< \brief Offset: 0xFB8 (R/ 32) MTB Authentication Status */
mbed_official 579:53297373a894 332 __I MTB_DEVARCH_Type DEVARCH; /**< \brief Offset: 0xFBC (R/ 32) MTB Device Architecture */
mbed_official 579:53297373a894 333 RoReg8 Reserved4[0x8];
mbed_official 579:53297373a894 334 __I MTB_DEVID_Type DEVID; /**< \brief Offset: 0xFC8 (R/ 32) MTB Device Configuration */
mbed_official 579:53297373a894 335 __I MTB_DEVTYPE_Type DEVTYPE; /**< \brief Offset: 0xFCC (R/ 32) MTB Device Type */
mbed_official 579:53297373a894 336 __I MTB_PID4_Type PID4; /**< \brief Offset: 0xFD0 (R/ 32) CoreSight */
mbed_official 579:53297373a894 337 __I MTB_PID5_Type PID5; /**< \brief Offset: 0xFD4 (R/ 32) CoreSight */
mbed_official 579:53297373a894 338 __I MTB_PID6_Type PID6; /**< \brief Offset: 0xFD8 (R/ 32) CoreSight */
mbed_official 579:53297373a894 339 __I MTB_PID7_Type PID7; /**< \brief Offset: 0xFDC (R/ 32) CoreSight */
mbed_official 579:53297373a894 340 __I MTB_PID0_Type PID0; /**< \brief Offset: 0xFE0 (R/ 32) CoreSight */
mbed_official 579:53297373a894 341 __I MTB_PID1_Type PID1; /**< \brief Offset: 0xFE4 (R/ 32) CoreSight */
mbed_official 579:53297373a894 342 __I MTB_PID2_Type PID2; /**< \brief Offset: 0xFE8 (R/ 32) CoreSight */
mbed_official 579:53297373a894 343 __I MTB_PID3_Type PID3; /**< \brief Offset: 0xFEC (R/ 32) CoreSight */
mbed_official 579:53297373a894 344 __I MTB_CID0_Type CID0; /**< \brief Offset: 0xFF0 (R/ 32) CoreSight */
mbed_official 579:53297373a894 345 __I MTB_CID1_Type CID1; /**< \brief Offset: 0xFF4 (R/ 32) CoreSight */
mbed_official 579:53297373a894 346 __I MTB_CID2_Type CID2; /**< \brief Offset: 0xFF8 (R/ 32) CoreSight */
mbed_official 579:53297373a894 347 __I MTB_CID3_Type CID3; /**< \brief Offset: 0xFFC (R/ 32) CoreSight */
mbed_official 579:53297373a894 348 } Mtb;
mbed_official 579:53297373a894 349 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 350
mbed_official 579:53297373a894 351 /*@}*/
mbed_official 579:53297373a894 352
mbed_official 579:53297373a894 353 #endif /* _SAMD21_MTB_COMPONENT_ */