mbed library sources
Fork of mbed-src by
targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_i2s.h@592:a274ee790e56, 2015-07-17 (annotated)
- Committer:
- mbed_official
- Date:
- Fri Jul 17 09:15:10 2015 +0100
- Revision:
- 592:a274ee790e56
- Parent:
- 579:53297373a894
Synchronized with git revision e7144f83a8d75df80c4877936b6ffe552b0be9e6
Full URL: https://github.com/mbedmicro/mbed/commit/e7144f83a8d75df80c4877936b6ffe552b0be9e6/
More API implementation for SAMR21
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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mbed_official | 579:53297373a894 | 1 | #ifndef _SAMD21_I2S_COMPONENT_ |
mbed_official | 579:53297373a894 | 2 | #define _SAMD21_I2S_COMPONENT_ |
mbed_official | 579:53297373a894 | 3 | |
mbed_official | 579:53297373a894 | 4 | /* ========================================================================== */ |
mbed_official | 579:53297373a894 | 5 | /** SOFTWARE API DEFINITION FOR I2S */ |
mbed_official | 579:53297373a894 | 6 | /* ========================================================================== */ |
mbed_official | 579:53297373a894 | 7 | /** \addtogroup SAMD21_I2S Inter-IC Sound Interface */ |
mbed_official | 579:53297373a894 | 8 | /*@{*/ |
mbed_official | 579:53297373a894 | 9 | |
mbed_official | 579:53297373a894 | 10 | #define I2S_U2224 |
mbed_official | 579:53297373a894 | 11 | #define REV_I2S 0x102 |
mbed_official | 579:53297373a894 | 12 | |
mbed_official | 579:53297373a894 | 13 | /* -------- I2S_CTRLA : (I2S Offset: 0x00) (R/W 8) Control A -------- */ |
mbed_official | 579:53297373a894 | 14 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 15 | typedef union { |
mbed_official | 579:53297373a894 | 16 | struct { |
mbed_official | 579:53297373a894 | 17 | uint8_t SWRST:1; /*!< bit: 0 Software Reset */ |
mbed_official | 579:53297373a894 | 18 | uint8_t ENABLE:1; /*!< bit: 1 Enable */ |
mbed_official | 579:53297373a894 | 19 | uint8_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable */ |
mbed_official | 579:53297373a894 | 20 | uint8_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable */ |
mbed_official | 579:53297373a894 | 21 | uint8_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable */ |
mbed_official | 579:53297373a894 | 22 | uint8_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable */ |
mbed_official | 579:53297373a894 | 23 | uint8_t :2; /*!< bit: 6.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 24 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 25 | struct { |
mbed_official | 579:53297373a894 | 26 | uint8_t :2; /*!< bit: 0.. 1 Reserved */ |
mbed_official | 579:53297373a894 | 27 | uint8_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable */ |
mbed_official | 579:53297373a894 | 28 | uint8_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable */ |
mbed_official | 579:53297373a894 | 29 | uint8_t :2; /*!< bit: 6.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 30 | } vec; /*!< Structure used for vec access */ |
mbed_official | 579:53297373a894 | 31 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 32 | } I2S_CTRLA_Type; |
mbed_official | 579:53297373a894 | 33 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 34 | |
mbed_official | 579:53297373a894 | 35 | #define I2S_CTRLA_OFFSET 0x00 /**< \brief (I2S_CTRLA offset) Control A */ |
mbed_official | 579:53297373a894 | 36 | #define I2S_CTRLA_RESETVALUE 0x00ul /**< \brief (I2S_CTRLA reset_value) Control A */ |
mbed_official | 579:53297373a894 | 37 | |
mbed_official | 579:53297373a894 | 38 | #define I2S_CTRLA_SWRST_Pos 0 /**< \brief (I2S_CTRLA) Software Reset */ |
mbed_official | 579:53297373a894 | 39 | #define I2S_CTRLA_SWRST (0x1ul << I2S_CTRLA_SWRST_Pos) |
mbed_official | 579:53297373a894 | 40 | #define I2S_CTRLA_ENABLE_Pos 1 /**< \brief (I2S_CTRLA) Enable */ |
mbed_official | 579:53297373a894 | 41 | #define I2S_CTRLA_ENABLE (0x1ul << I2S_CTRLA_ENABLE_Pos) |
mbed_official | 579:53297373a894 | 42 | #define I2S_CTRLA_CKEN0_Pos 2 /**< \brief (I2S_CTRLA) Clock Unit 0 Enable */ |
mbed_official | 579:53297373a894 | 43 | #define I2S_CTRLA_CKEN0 (1 << I2S_CTRLA_CKEN0_Pos) |
mbed_official | 579:53297373a894 | 44 | #define I2S_CTRLA_CKEN1_Pos 3 /**< \brief (I2S_CTRLA) Clock Unit 1 Enable */ |
mbed_official | 579:53297373a894 | 45 | #define I2S_CTRLA_CKEN1 (1 << I2S_CTRLA_CKEN1_Pos) |
mbed_official | 579:53297373a894 | 46 | #define I2S_CTRLA_CKEN_Pos 2 /**< \brief (I2S_CTRLA) Clock Unit x Enable */ |
mbed_official | 579:53297373a894 | 47 | #define I2S_CTRLA_CKEN_Msk (0x3ul << I2S_CTRLA_CKEN_Pos) |
mbed_official | 579:53297373a894 | 48 | #define I2S_CTRLA_CKEN(value) ((I2S_CTRLA_CKEN_Msk & ((value) << I2S_CTRLA_CKEN_Pos))) |
mbed_official | 579:53297373a894 | 49 | #define I2S_CTRLA_SEREN0_Pos 4 /**< \brief (I2S_CTRLA) Serializer 0 Enable */ |
mbed_official | 579:53297373a894 | 50 | #define I2S_CTRLA_SEREN0 (1 << I2S_CTRLA_SEREN0_Pos) |
mbed_official | 579:53297373a894 | 51 | #define I2S_CTRLA_SEREN1_Pos 5 /**< \brief (I2S_CTRLA) Serializer 1 Enable */ |
mbed_official | 579:53297373a894 | 52 | #define I2S_CTRLA_SEREN1 (1 << I2S_CTRLA_SEREN1_Pos) |
mbed_official | 579:53297373a894 | 53 | #define I2S_CTRLA_SEREN_Pos 4 /**< \brief (I2S_CTRLA) Serializer x Enable */ |
mbed_official | 579:53297373a894 | 54 | #define I2S_CTRLA_SEREN_Msk (0x3ul << I2S_CTRLA_SEREN_Pos) |
mbed_official | 579:53297373a894 | 55 | #define I2S_CTRLA_SEREN(value) ((I2S_CTRLA_SEREN_Msk & ((value) << I2S_CTRLA_SEREN_Pos))) |
mbed_official | 579:53297373a894 | 56 | #define I2S_CTRLA_MASK 0x3Ful /**< \brief (I2S_CTRLA) MASK Register */ |
mbed_official | 579:53297373a894 | 57 | |
mbed_official | 579:53297373a894 | 58 | /* -------- I2S_CLKCTRL : (I2S Offset: 0x04) (R/W 32) Clock Unit n Control -------- */ |
mbed_official | 579:53297373a894 | 59 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 60 | typedef union { |
mbed_official | 579:53297373a894 | 61 | struct { |
mbed_official | 579:53297373a894 | 62 | uint32_t SLOTSIZE:2; /*!< bit: 0.. 1 Slot Size */ |
mbed_official | 579:53297373a894 | 63 | uint32_t NBSLOTS:3; /*!< bit: 2.. 4 Number of Slots in Frame */ |
mbed_official | 579:53297373a894 | 64 | uint32_t FSWIDTH:2; /*!< bit: 5.. 6 Frame Sync Width */ |
mbed_official | 579:53297373a894 | 65 | uint32_t BITDELAY:1; /*!< bit: 7 Data Delay from Frame Sync */ |
mbed_official | 579:53297373a894 | 66 | uint32_t FSSEL:1; /*!< bit: 8 Frame Sync Select */ |
mbed_official | 579:53297373a894 | 67 | uint32_t :2; /*!< bit: 9..10 Reserved */ |
mbed_official | 579:53297373a894 | 68 | uint32_t FSINV:1; /*!< bit: 11 Frame Sync Invert */ |
mbed_official | 579:53297373a894 | 69 | uint32_t SCKSEL:1; /*!< bit: 12 Serial Clock Select */ |
mbed_official | 579:53297373a894 | 70 | uint32_t :3; /*!< bit: 13..15 Reserved */ |
mbed_official | 579:53297373a894 | 71 | uint32_t MCKSEL:1; /*!< bit: 16 Master Clock Select */ |
mbed_official | 579:53297373a894 | 72 | uint32_t :1; /*!< bit: 17 Reserved */ |
mbed_official | 579:53297373a894 | 73 | uint32_t MCKEN:1; /*!< bit: 18 Master Clock Enable */ |
mbed_official | 579:53297373a894 | 74 | uint32_t MCKDIV:5; /*!< bit: 19..23 Master Clock Division Factor */ |
mbed_official | 579:53297373a894 | 75 | uint32_t MCKOUTDIV:5; /*!< bit: 24..28 Master Clock Output Division Factor */ |
mbed_official | 579:53297373a894 | 76 | uint32_t FSOUTINV:1; /*!< bit: 29 Frame Sync Output Invert */ |
mbed_official | 579:53297373a894 | 77 | uint32_t SCKOUTINV:1; /*!< bit: 30 Serial Clock Output Invert */ |
mbed_official | 579:53297373a894 | 78 | uint32_t MCKOUTINV:1; /*!< bit: 31 Master Clock Output Invert */ |
mbed_official | 579:53297373a894 | 79 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 80 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 81 | } I2S_CLKCTRL_Type; |
mbed_official | 579:53297373a894 | 82 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 83 | |
mbed_official | 579:53297373a894 | 84 | #define I2S_CLKCTRL_OFFSET 0x04 /**< \brief (I2S_CLKCTRL offset) Clock Unit n Control */ |
mbed_official | 579:53297373a894 | 85 | #define I2S_CLKCTRL_RESETVALUE 0x00000000ul /**< \brief (I2S_CLKCTRL reset_value) Clock Unit n Control */ |
mbed_official | 579:53297373a894 | 86 | |
mbed_official | 579:53297373a894 | 87 | #define I2S_CLKCTRL_SLOTSIZE_Pos 0 /**< \brief (I2S_CLKCTRL) Slot Size */ |
mbed_official | 579:53297373a894 | 88 | #define I2S_CLKCTRL_SLOTSIZE_Msk (0x3ul << I2S_CLKCTRL_SLOTSIZE_Pos) |
mbed_official | 579:53297373a894 | 89 | #define I2S_CLKCTRL_SLOTSIZE(value) ((I2S_CLKCTRL_SLOTSIZE_Msk & ((value) << I2S_CLKCTRL_SLOTSIZE_Pos))) |
mbed_official | 579:53297373a894 | 90 | #define I2S_CLKCTRL_SLOTSIZE_8_Val 0x0ul /**< \brief (I2S_CLKCTRL) 8-bit Slot for Clock Unit n */ |
mbed_official | 579:53297373a894 | 91 | #define I2S_CLKCTRL_SLOTSIZE_16_Val 0x1ul /**< \brief (I2S_CLKCTRL) 16-bit Slot for Clock Unit n */ |
mbed_official | 579:53297373a894 | 92 | #define I2S_CLKCTRL_SLOTSIZE_24_Val 0x2ul /**< \brief (I2S_CLKCTRL) 24-bit Slot for Clock Unit n */ |
mbed_official | 579:53297373a894 | 93 | #define I2S_CLKCTRL_SLOTSIZE_32_Val 0x3ul /**< \brief (I2S_CLKCTRL) 32-bit Slot for Clock Unit n */ |
mbed_official | 579:53297373a894 | 94 | #define I2S_CLKCTRL_SLOTSIZE_8 (I2S_CLKCTRL_SLOTSIZE_8_Val << I2S_CLKCTRL_SLOTSIZE_Pos) |
mbed_official | 579:53297373a894 | 95 | #define I2S_CLKCTRL_SLOTSIZE_16 (I2S_CLKCTRL_SLOTSIZE_16_Val << I2S_CLKCTRL_SLOTSIZE_Pos) |
mbed_official | 579:53297373a894 | 96 | #define I2S_CLKCTRL_SLOTSIZE_24 (I2S_CLKCTRL_SLOTSIZE_24_Val << I2S_CLKCTRL_SLOTSIZE_Pos) |
mbed_official | 579:53297373a894 | 97 | #define I2S_CLKCTRL_SLOTSIZE_32 (I2S_CLKCTRL_SLOTSIZE_32_Val << I2S_CLKCTRL_SLOTSIZE_Pos) |
mbed_official | 579:53297373a894 | 98 | #define I2S_CLKCTRL_NBSLOTS_Pos 2 /**< \brief (I2S_CLKCTRL) Number of Slots in Frame */ |
mbed_official | 579:53297373a894 | 99 | #define I2S_CLKCTRL_NBSLOTS_Msk (0x7ul << I2S_CLKCTRL_NBSLOTS_Pos) |
mbed_official | 579:53297373a894 | 100 | #define I2S_CLKCTRL_NBSLOTS(value) ((I2S_CLKCTRL_NBSLOTS_Msk & ((value) << I2S_CLKCTRL_NBSLOTS_Pos))) |
mbed_official | 579:53297373a894 | 101 | #define I2S_CLKCTRL_FSWIDTH_Pos 5 /**< \brief (I2S_CLKCTRL) Frame Sync Width */ |
mbed_official | 579:53297373a894 | 102 | #define I2S_CLKCTRL_FSWIDTH_Msk (0x3ul << I2S_CLKCTRL_FSWIDTH_Pos) |
mbed_official | 579:53297373a894 | 103 | #define I2S_CLKCTRL_FSWIDTH(value) ((I2S_CLKCTRL_FSWIDTH_Msk & ((value) << I2S_CLKCTRL_FSWIDTH_Pos))) |
mbed_official | 579:53297373a894 | 104 | #define I2S_CLKCTRL_FSWIDTH_SLOT_Val 0x0ul /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Slot wide (default for I2S protocol) */ |
mbed_official | 579:53297373a894 | 105 | #define I2S_CLKCTRL_FSWIDTH_HALF_Val 0x1ul /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is half a Frame wide */ |
mbed_official | 579:53297373a894 | 106 | #define I2S_CLKCTRL_FSWIDTH_BIT_Val 0x2ul /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Bit wide */ |
mbed_official | 579:53297373a894 | 107 | #define I2S_CLKCTRL_FSWIDTH_BURST_Val 0x3ul /**< \brief (I2S_CLKCTRL) Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested */ |
mbed_official | 579:53297373a894 | 108 | #define I2S_CLKCTRL_FSWIDTH_SLOT (I2S_CLKCTRL_FSWIDTH_SLOT_Val << I2S_CLKCTRL_FSWIDTH_Pos) |
mbed_official | 579:53297373a894 | 109 | #define I2S_CLKCTRL_FSWIDTH_HALF (I2S_CLKCTRL_FSWIDTH_HALF_Val << I2S_CLKCTRL_FSWIDTH_Pos) |
mbed_official | 579:53297373a894 | 110 | #define I2S_CLKCTRL_FSWIDTH_BIT (I2S_CLKCTRL_FSWIDTH_BIT_Val << I2S_CLKCTRL_FSWIDTH_Pos) |
mbed_official | 579:53297373a894 | 111 | #define I2S_CLKCTRL_FSWIDTH_BURST (I2S_CLKCTRL_FSWIDTH_BURST_Val << I2S_CLKCTRL_FSWIDTH_Pos) |
mbed_official | 579:53297373a894 | 112 | #define I2S_CLKCTRL_BITDELAY_Pos 7 /**< \brief (I2S_CLKCTRL) Data Delay from Frame Sync */ |
mbed_official | 579:53297373a894 | 113 | #define I2S_CLKCTRL_BITDELAY (0x1ul << I2S_CLKCTRL_BITDELAY_Pos) |
mbed_official | 579:53297373a894 | 114 | #define I2S_CLKCTRL_BITDELAY_LJ_Val 0x0ul /**< \brief (I2S_CLKCTRL) Left Justified (0 Bit Delay) */ |
mbed_official | 579:53297373a894 | 115 | #define I2S_CLKCTRL_BITDELAY_I2S_Val 0x1ul /**< \brief (I2S_CLKCTRL) I2S (1 Bit Delay) */ |
mbed_official | 579:53297373a894 | 116 | #define I2S_CLKCTRL_BITDELAY_LJ (I2S_CLKCTRL_BITDELAY_LJ_Val << I2S_CLKCTRL_BITDELAY_Pos) |
mbed_official | 579:53297373a894 | 117 | #define I2S_CLKCTRL_BITDELAY_I2S (I2S_CLKCTRL_BITDELAY_I2S_Val << I2S_CLKCTRL_BITDELAY_Pos) |
mbed_official | 579:53297373a894 | 118 | #define I2S_CLKCTRL_FSSEL_Pos 8 /**< \brief (I2S_CLKCTRL) Frame Sync Select */ |
mbed_official | 579:53297373a894 | 119 | #define I2S_CLKCTRL_FSSEL (0x1ul << I2S_CLKCTRL_FSSEL_Pos) |
mbed_official | 579:53297373a894 | 120 | #define I2S_CLKCTRL_FSSEL_SCKDIV_Val 0x0ul /**< \brief (I2S_CLKCTRL) Divided Serial Clock n is used as Frame Sync n source */ |
mbed_official | 579:53297373a894 | 121 | #define I2S_CLKCTRL_FSSEL_FSPIN_Val 0x1ul /**< \brief (I2S_CLKCTRL) FSn input pin is used as Frame Sync n source */ |
mbed_official | 579:53297373a894 | 122 | #define I2S_CLKCTRL_FSSEL_SCKDIV (I2S_CLKCTRL_FSSEL_SCKDIV_Val << I2S_CLKCTRL_FSSEL_Pos) |
mbed_official | 579:53297373a894 | 123 | #define I2S_CLKCTRL_FSSEL_FSPIN (I2S_CLKCTRL_FSSEL_FSPIN_Val << I2S_CLKCTRL_FSSEL_Pos) |
mbed_official | 579:53297373a894 | 124 | #define I2S_CLKCTRL_FSINV_Pos 11 /**< \brief (I2S_CLKCTRL) Frame Sync Invert */ |
mbed_official | 579:53297373a894 | 125 | #define I2S_CLKCTRL_FSINV (0x1ul << I2S_CLKCTRL_FSINV_Pos) |
mbed_official | 579:53297373a894 | 126 | #define I2S_CLKCTRL_SCKSEL_Pos 12 /**< \brief (I2S_CLKCTRL) Serial Clock Select */ |
mbed_official | 579:53297373a894 | 127 | #define I2S_CLKCTRL_SCKSEL (0x1ul << I2S_CLKCTRL_SCKSEL_Pos) |
mbed_official | 579:53297373a894 | 128 | #define I2S_CLKCTRL_SCKSEL_MCKDIV_Val 0x0ul /**< \brief (I2S_CLKCTRL) Divided Master Clock n is used as Serial Clock n source */ |
mbed_official | 579:53297373a894 | 129 | #define I2S_CLKCTRL_SCKSEL_SCKPIN_Val 0x1ul /**< \brief (I2S_CLKCTRL) SCKn input pin is used as Serial Clock n source */ |
mbed_official | 579:53297373a894 | 130 | #define I2S_CLKCTRL_SCKSEL_MCKDIV (I2S_CLKCTRL_SCKSEL_MCKDIV_Val << I2S_CLKCTRL_SCKSEL_Pos) |
mbed_official | 579:53297373a894 | 131 | #define I2S_CLKCTRL_SCKSEL_SCKPIN (I2S_CLKCTRL_SCKSEL_SCKPIN_Val << I2S_CLKCTRL_SCKSEL_Pos) |
mbed_official | 579:53297373a894 | 132 | #define I2S_CLKCTRL_MCKSEL_Pos 16 /**< \brief (I2S_CLKCTRL) Master Clock Select */ |
mbed_official | 579:53297373a894 | 133 | #define I2S_CLKCTRL_MCKSEL (0x1ul << I2S_CLKCTRL_MCKSEL_Pos) |
mbed_official | 579:53297373a894 | 134 | #define I2S_CLKCTRL_MCKSEL_GCLK_Val 0x0ul /**< \brief (I2S_CLKCTRL) GCLK_I2S_n is used as Master Clock n source */ |
mbed_official | 579:53297373a894 | 135 | #define I2S_CLKCTRL_MCKSEL_MCKPIN_Val 0x1ul /**< \brief (I2S_CLKCTRL) MCKn input pin is used as Master Clock n source */ |
mbed_official | 579:53297373a894 | 136 | #define I2S_CLKCTRL_MCKSEL_GCLK (I2S_CLKCTRL_MCKSEL_GCLK_Val << I2S_CLKCTRL_MCKSEL_Pos) |
mbed_official | 579:53297373a894 | 137 | #define I2S_CLKCTRL_MCKSEL_MCKPIN (I2S_CLKCTRL_MCKSEL_MCKPIN_Val << I2S_CLKCTRL_MCKSEL_Pos) |
mbed_official | 579:53297373a894 | 138 | #define I2S_CLKCTRL_MCKEN_Pos 18 /**< \brief (I2S_CLKCTRL) Master Clock Enable */ |
mbed_official | 579:53297373a894 | 139 | #define I2S_CLKCTRL_MCKEN (0x1ul << I2S_CLKCTRL_MCKEN_Pos) |
mbed_official | 579:53297373a894 | 140 | #define I2S_CLKCTRL_MCKDIV_Pos 19 /**< \brief (I2S_CLKCTRL) Master Clock Division Factor */ |
mbed_official | 579:53297373a894 | 141 | #define I2S_CLKCTRL_MCKDIV_Msk (0x1Ful << I2S_CLKCTRL_MCKDIV_Pos) |
mbed_official | 579:53297373a894 | 142 | #define I2S_CLKCTRL_MCKDIV(value) ((I2S_CLKCTRL_MCKDIV_Msk & ((value) << I2S_CLKCTRL_MCKDIV_Pos))) |
mbed_official | 579:53297373a894 | 143 | #define I2S_CLKCTRL_MCKOUTDIV_Pos 24 /**< \brief (I2S_CLKCTRL) Master Clock Output Division Factor */ |
mbed_official | 579:53297373a894 | 144 | #define I2S_CLKCTRL_MCKOUTDIV_Msk (0x1Ful << I2S_CLKCTRL_MCKOUTDIV_Pos) |
mbed_official | 579:53297373a894 | 145 | #define I2S_CLKCTRL_MCKOUTDIV(value) ((I2S_CLKCTRL_MCKOUTDIV_Msk & ((value) << I2S_CLKCTRL_MCKOUTDIV_Pos))) |
mbed_official | 579:53297373a894 | 146 | #define I2S_CLKCTRL_FSOUTINV_Pos 29 /**< \brief (I2S_CLKCTRL) Frame Sync Output Invert */ |
mbed_official | 579:53297373a894 | 147 | #define I2S_CLKCTRL_FSOUTINV (0x1ul << I2S_CLKCTRL_FSOUTINV_Pos) |
mbed_official | 579:53297373a894 | 148 | #define I2S_CLKCTRL_SCKOUTINV_Pos 30 /**< \brief (I2S_CLKCTRL) Serial Clock Output Invert */ |
mbed_official | 579:53297373a894 | 149 | #define I2S_CLKCTRL_SCKOUTINV (0x1ul << I2S_CLKCTRL_SCKOUTINV_Pos) |
mbed_official | 579:53297373a894 | 150 | #define I2S_CLKCTRL_MCKOUTINV_Pos 31 /**< \brief (I2S_CLKCTRL) Master Clock Output Invert */ |
mbed_official | 579:53297373a894 | 151 | #define I2S_CLKCTRL_MCKOUTINV (0x1ul << I2S_CLKCTRL_MCKOUTINV_Pos) |
mbed_official | 579:53297373a894 | 152 | #define I2S_CLKCTRL_MASK 0xFFFD19FFul /**< \brief (I2S_CLKCTRL) MASK Register */ |
mbed_official | 579:53297373a894 | 153 | |
mbed_official | 579:53297373a894 | 154 | /* -------- I2S_INTENCLR : (I2S Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */ |
mbed_official | 579:53297373a894 | 155 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 156 | typedef union { |
mbed_official | 579:53297373a894 | 157 | struct { |
mbed_official | 579:53297373a894 | 158 | uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 159 | uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 160 | uint16_t :2; /*!< bit: 2.. 3 Reserved */ |
mbed_official | 579:53297373a894 | 161 | uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 162 | uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 163 | uint16_t :2; /*!< bit: 6.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 164 | uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 165 | uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 166 | uint16_t :2; /*!< bit: 10..11 Reserved */ |
mbed_official | 579:53297373a894 | 167 | uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 168 | uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 169 | uint16_t :2; /*!< bit: 14..15 Reserved */ |
mbed_official | 579:53297373a894 | 170 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 171 | struct { |
mbed_official | 579:53297373a894 | 172 | uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */ |
mbed_official | 579:53297373a894 | 173 | uint16_t :2; /*!< bit: 2.. 3 Reserved */ |
mbed_official | 579:53297373a894 | 174 | uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */ |
mbed_official | 579:53297373a894 | 175 | uint16_t :2; /*!< bit: 6.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 176 | uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */ |
mbed_official | 579:53297373a894 | 177 | uint16_t :2; /*!< bit: 10..11 Reserved */ |
mbed_official | 579:53297373a894 | 178 | uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */ |
mbed_official | 579:53297373a894 | 179 | uint16_t :2; /*!< bit: 14..15 Reserved */ |
mbed_official | 579:53297373a894 | 180 | } vec; /*!< Structure used for vec access */ |
mbed_official | 579:53297373a894 | 181 | uint16_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 182 | } I2S_INTENCLR_Type; |
mbed_official | 579:53297373a894 | 183 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 184 | |
mbed_official | 579:53297373a894 | 185 | #define I2S_INTENCLR_OFFSET 0x0C /**< \brief (I2S_INTENCLR offset) Interrupt Enable Clear */ |
mbed_official | 579:53297373a894 | 186 | #define I2S_INTENCLR_RESETVALUE 0x0000ul /**< \brief (I2S_INTENCLR reset_value) Interrupt Enable Clear */ |
mbed_official | 579:53297373a894 | 187 | |
mbed_official | 579:53297373a894 | 188 | #define I2S_INTENCLR_RXRDY0_Pos 0 /**< \brief (I2S_INTENCLR) Receive Ready 0 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 189 | #define I2S_INTENCLR_RXRDY0 (1 << I2S_INTENCLR_RXRDY0_Pos) |
mbed_official | 579:53297373a894 | 190 | #define I2S_INTENCLR_RXRDY1_Pos 1 /**< \brief (I2S_INTENCLR) Receive Ready 1 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 191 | #define I2S_INTENCLR_RXRDY1 (1 << I2S_INTENCLR_RXRDY1_Pos) |
mbed_official | 579:53297373a894 | 192 | #define I2S_INTENCLR_RXRDY_Pos 0 /**< \brief (I2S_INTENCLR) Receive Ready x Interrupt Enable */ |
mbed_official | 579:53297373a894 | 193 | #define I2S_INTENCLR_RXRDY_Msk (0x3ul << I2S_INTENCLR_RXRDY_Pos) |
mbed_official | 579:53297373a894 | 194 | #define I2S_INTENCLR_RXRDY(value) ((I2S_INTENCLR_RXRDY_Msk & ((value) << I2S_INTENCLR_RXRDY_Pos))) |
mbed_official | 579:53297373a894 | 195 | #define I2S_INTENCLR_RXOR0_Pos 4 /**< \brief (I2S_INTENCLR) Receive Overrun 0 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 196 | #define I2S_INTENCLR_RXOR0 (1 << I2S_INTENCLR_RXOR0_Pos) |
mbed_official | 579:53297373a894 | 197 | #define I2S_INTENCLR_RXOR1_Pos 5 /**< \brief (I2S_INTENCLR) Receive Overrun 1 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 198 | #define I2S_INTENCLR_RXOR1 (1 << I2S_INTENCLR_RXOR1_Pos) |
mbed_official | 579:53297373a894 | 199 | #define I2S_INTENCLR_RXOR_Pos 4 /**< \brief (I2S_INTENCLR) Receive Overrun x Interrupt Enable */ |
mbed_official | 579:53297373a894 | 200 | #define I2S_INTENCLR_RXOR_Msk (0x3ul << I2S_INTENCLR_RXOR_Pos) |
mbed_official | 579:53297373a894 | 201 | #define I2S_INTENCLR_RXOR(value) ((I2S_INTENCLR_RXOR_Msk & ((value) << I2S_INTENCLR_RXOR_Pos))) |
mbed_official | 579:53297373a894 | 202 | #define I2S_INTENCLR_TXRDY0_Pos 8 /**< \brief (I2S_INTENCLR) Transmit Ready 0 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 203 | #define I2S_INTENCLR_TXRDY0 (1 << I2S_INTENCLR_TXRDY0_Pos) |
mbed_official | 579:53297373a894 | 204 | #define I2S_INTENCLR_TXRDY1_Pos 9 /**< \brief (I2S_INTENCLR) Transmit Ready 1 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 205 | #define I2S_INTENCLR_TXRDY1 (1 << I2S_INTENCLR_TXRDY1_Pos) |
mbed_official | 579:53297373a894 | 206 | #define I2S_INTENCLR_TXRDY_Pos 8 /**< \brief (I2S_INTENCLR) Transmit Ready x Interrupt Enable */ |
mbed_official | 579:53297373a894 | 207 | #define I2S_INTENCLR_TXRDY_Msk (0x3ul << I2S_INTENCLR_TXRDY_Pos) |
mbed_official | 579:53297373a894 | 208 | #define I2S_INTENCLR_TXRDY(value) ((I2S_INTENCLR_TXRDY_Msk & ((value) << I2S_INTENCLR_TXRDY_Pos))) |
mbed_official | 579:53297373a894 | 209 | #define I2S_INTENCLR_TXUR0_Pos 12 /**< \brief (I2S_INTENCLR) Transmit Underrun 0 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 210 | #define I2S_INTENCLR_TXUR0 (1 << I2S_INTENCLR_TXUR0_Pos) |
mbed_official | 579:53297373a894 | 211 | #define I2S_INTENCLR_TXUR1_Pos 13 /**< \brief (I2S_INTENCLR) Transmit Underrun 1 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 212 | #define I2S_INTENCLR_TXUR1 (1 << I2S_INTENCLR_TXUR1_Pos) |
mbed_official | 579:53297373a894 | 213 | #define I2S_INTENCLR_TXUR_Pos 12 /**< \brief (I2S_INTENCLR) Transmit Underrun x Interrupt Enable */ |
mbed_official | 579:53297373a894 | 214 | #define I2S_INTENCLR_TXUR_Msk (0x3ul << I2S_INTENCLR_TXUR_Pos) |
mbed_official | 579:53297373a894 | 215 | #define I2S_INTENCLR_TXUR(value) ((I2S_INTENCLR_TXUR_Msk & ((value) << I2S_INTENCLR_TXUR_Pos))) |
mbed_official | 579:53297373a894 | 216 | #define I2S_INTENCLR_MASK 0x3333ul /**< \brief (I2S_INTENCLR) MASK Register */ |
mbed_official | 579:53297373a894 | 217 | |
mbed_official | 579:53297373a894 | 218 | /* -------- I2S_INTENSET : (I2S Offset: 0x10) (R/W 16) Interrupt Enable Set -------- */ |
mbed_official | 579:53297373a894 | 219 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 220 | typedef union { |
mbed_official | 579:53297373a894 | 221 | struct { |
mbed_official | 579:53297373a894 | 222 | uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 223 | uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 224 | uint16_t :2; /*!< bit: 2.. 3 Reserved */ |
mbed_official | 579:53297373a894 | 225 | uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 226 | uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 227 | uint16_t :2; /*!< bit: 6.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 228 | uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 229 | uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 230 | uint16_t :2; /*!< bit: 10..11 Reserved */ |
mbed_official | 579:53297373a894 | 231 | uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 232 | uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 233 | uint16_t :2; /*!< bit: 14..15 Reserved */ |
mbed_official | 579:53297373a894 | 234 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 235 | struct { |
mbed_official | 579:53297373a894 | 236 | uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */ |
mbed_official | 579:53297373a894 | 237 | uint16_t :2; /*!< bit: 2.. 3 Reserved */ |
mbed_official | 579:53297373a894 | 238 | uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */ |
mbed_official | 579:53297373a894 | 239 | uint16_t :2; /*!< bit: 6.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 240 | uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */ |
mbed_official | 579:53297373a894 | 241 | uint16_t :2; /*!< bit: 10..11 Reserved */ |
mbed_official | 579:53297373a894 | 242 | uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */ |
mbed_official | 579:53297373a894 | 243 | uint16_t :2; /*!< bit: 14..15 Reserved */ |
mbed_official | 579:53297373a894 | 244 | } vec; /*!< Structure used for vec access */ |
mbed_official | 579:53297373a894 | 245 | uint16_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 246 | } I2S_INTENSET_Type; |
mbed_official | 579:53297373a894 | 247 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 248 | |
mbed_official | 579:53297373a894 | 249 | #define I2S_INTENSET_OFFSET 0x10 /**< \brief (I2S_INTENSET offset) Interrupt Enable Set */ |
mbed_official | 579:53297373a894 | 250 | #define I2S_INTENSET_RESETVALUE 0x0000ul /**< \brief (I2S_INTENSET reset_value) Interrupt Enable Set */ |
mbed_official | 579:53297373a894 | 251 | |
mbed_official | 579:53297373a894 | 252 | #define I2S_INTENSET_RXRDY0_Pos 0 /**< \brief (I2S_INTENSET) Receive Ready 0 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 253 | #define I2S_INTENSET_RXRDY0 (1 << I2S_INTENSET_RXRDY0_Pos) |
mbed_official | 579:53297373a894 | 254 | #define I2S_INTENSET_RXRDY1_Pos 1 /**< \brief (I2S_INTENSET) Receive Ready 1 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 255 | #define I2S_INTENSET_RXRDY1 (1 << I2S_INTENSET_RXRDY1_Pos) |
mbed_official | 579:53297373a894 | 256 | #define I2S_INTENSET_RXRDY_Pos 0 /**< \brief (I2S_INTENSET) Receive Ready x Interrupt Enable */ |
mbed_official | 579:53297373a894 | 257 | #define I2S_INTENSET_RXRDY_Msk (0x3ul << I2S_INTENSET_RXRDY_Pos) |
mbed_official | 579:53297373a894 | 258 | #define I2S_INTENSET_RXRDY(value) ((I2S_INTENSET_RXRDY_Msk & ((value) << I2S_INTENSET_RXRDY_Pos))) |
mbed_official | 579:53297373a894 | 259 | #define I2S_INTENSET_RXOR0_Pos 4 /**< \brief (I2S_INTENSET) Receive Overrun 0 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 260 | #define I2S_INTENSET_RXOR0 (1 << I2S_INTENSET_RXOR0_Pos) |
mbed_official | 579:53297373a894 | 261 | #define I2S_INTENSET_RXOR1_Pos 5 /**< \brief (I2S_INTENSET) Receive Overrun 1 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 262 | #define I2S_INTENSET_RXOR1 (1 << I2S_INTENSET_RXOR1_Pos) |
mbed_official | 579:53297373a894 | 263 | #define I2S_INTENSET_RXOR_Pos 4 /**< \brief (I2S_INTENSET) Receive Overrun x Interrupt Enable */ |
mbed_official | 579:53297373a894 | 264 | #define I2S_INTENSET_RXOR_Msk (0x3ul << I2S_INTENSET_RXOR_Pos) |
mbed_official | 579:53297373a894 | 265 | #define I2S_INTENSET_RXOR(value) ((I2S_INTENSET_RXOR_Msk & ((value) << I2S_INTENSET_RXOR_Pos))) |
mbed_official | 579:53297373a894 | 266 | #define I2S_INTENSET_TXRDY0_Pos 8 /**< \brief (I2S_INTENSET) Transmit Ready 0 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 267 | #define I2S_INTENSET_TXRDY0 (1 << I2S_INTENSET_TXRDY0_Pos) |
mbed_official | 579:53297373a894 | 268 | #define I2S_INTENSET_TXRDY1_Pos 9 /**< \brief (I2S_INTENSET) Transmit Ready 1 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 269 | #define I2S_INTENSET_TXRDY1 (1 << I2S_INTENSET_TXRDY1_Pos) |
mbed_official | 579:53297373a894 | 270 | #define I2S_INTENSET_TXRDY_Pos 8 /**< \brief (I2S_INTENSET) Transmit Ready x Interrupt Enable */ |
mbed_official | 579:53297373a894 | 271 | #define I2S_INTENSET_TXRDY_Msk (0x3ul << I2S_INTENSET_TXRDY_Pos) |
mbed_official | 579:53297373a894 | 272 | #define I2S_INTENSET_TXRDY(value) ((I2S_INTENSET_TXRDY_Msk & ((value) << I2S_INTENSET_TXRDY_Pos))) |
mbed_official | 579:53297373a894 | 273 | #define I2S_INTENSET_TXUR0_Pos 12 /**< \brief (I2S_INTENSET) Transmit Underrun 0 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 274 | #define I2S_INTENSET_TXUR0 (1 << I2S_INTENSET_TXUR0_Pos) |
mbed_official | 579:53297373a894 | 275 | #define I2S_INTENSET_TXUR1_Pos 13 /**< \brief (I2S_INTENSET) Transmit Underrun 1 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 276 | #define I2S_INTENSET_TXUR1 (1 << I2S_INTENSET_TXUR1_Pos) |
mbed_official | 579:53297373a894 | 277 | #define I2S_INTENSET_TXUR_Pos 12 /**< \brief (I2S_INTENSET) Transmit Underrun x Interrupt Enable */ |
mbed_official | 579:53297373a894 | 278 | #define I2S_INTENSET_TXUR_Msk (0x3ul << I2S_INTENSET_TXUR_Pos) |
mbed_official | 579:53297373a894 | 279 | #define I2S_INTENSET_TXUR(value) ((I2S_INTENSET_TXUR_Msk & ((value) << I2S_INTENSET_TXUR_Pos))) |
mbed_official | 579:53297373a894 | 280 | #define I2S_INTENSET_MASK 0x3333ul /**< \brief (I2S_INTENSET) MASK Register */ |
mbed_official | 579:53297373a894 | 281 | |
mbed_official | 579:53297373a894 | 282 | /* -------- I2S_INTFLAG : (I2S Offset: 0x14) (R/W 16) Interrupt Flag Status and Clear -------- */ |
mbed_official | 579:53297373a894 | 283 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 284 | typedef union { |
mbed_official | 579:53297373a894 | 285 | struct { |
mbed_official | 579:53297373a894 | 286 | uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 */ |
mbed_official | 579:53297373a894 | 287 | uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 */ |
mbed_official | 579:53297373a894 | 288 | uint16_t :2; /*!< bit: 2.. 3 Reserved */ |
mbed_official | 579:53297373a894 | 289 | uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 */ |
mbed_official | 579:53297373a894 | 290 | uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 */ |
mbed_official | 579:53297373a894 | 291 | uint16_t :2; /*!< bit: 6.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 292 | uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 */ |
mbed_official | 579:53297373a894 | 293 | uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 */ |
mbed_official | 579:53297373a894 | 294 | uint16_t :2; /*!< bit: 10..11 Reserved */ |
mbed_official | 579:53297373a894 | 295 | uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 */ |
mbed_official | 579:53297373a894 | 296 | uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 */ |
mbed_official | 579:53297373a894 | 297 | uint16_t :2; /*!< bit: 14..15 Reserved */ |
mbed_official | 579:53297373a894 | 298 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 299 | struct { |
mbed_official | 579:53297373a894 | 300 | uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x */ |
mbed_official | 579:53297373a894 | 301 | uint16_t :2; /*!< bit: 2.. 3 Reserved */ |
mbed_official | 579:53297373a894 | 302 | uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x */ |
mbed_official | 579:53297373a894 | 303 | uint16_t :2; /*!< bit: 6.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 304 | uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x */ |
mbed_official | 579:53297373a894 | 305 | uint16_t :2; /*!< bit: 10..11 Reserved */ |
mbed_official | 579:53297373a894 | 306 | uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x */ |
mbed_official | 579:53297373a894 | 307 | uint16_t :2; /*!< bit: 14..15 Reserved */ |
mbed_official | 579:53297373a894 | 308 | } vec; /*!< Structure used for vec access */ |
mbed_official | 579:53297373a894 | 309 | uint16_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 310 | } I2S_INTFLAG_Type; |
mbed_official | 579:53297373a894 | 311 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 312 | |
mbed_official | 579:53297373a894 | 313 | #define I2S_INTFLAG_OFFSET 0x14 /**< \brief (I2S_INTFLAG offset) Interrupt Flag Status and Clear */ |
mbed_official | 579:53297373a894 | 314 | #define I2S_INTFLAG_RESETVALUE 0x0000ul /**< \brief (I2S_INTFLAG reset_value) Interrupt Flag Status and Clear */ |
mbed_official | 579:53297373a894 | 315 | |
mbed_official | 579:53297373a894 | 316 | #define I2S_INTFLAG_RXRDY0_Pos 0 /**< \brief (I2S_INTFLAG) Receive Ready 0 */ |
mbed_official | 579:53297373a894 | 317 | #define I2S_INTFLAG_RXRDY0 (1 << I2S_INTFLAG_RXRDY0_Pos) |
mbed_official | 579:53297373a894 | 318 | #define I2S_INTFLAG_RXRDY1_Pos 1 /**< \brief (I2S_INTFLAG) Receive Ready 1 */ |
mbed_official | 579:53297373a894 | 319 | #define I2S_INTFLAG_RXRDY1 (1 << I2S_INTFLAG_RXRDY1_Pos) |
mbed_official | 579:53297373a894 | 320 | #define I2S_INTFLAG_RXRDY_Pos 0 /**< \brief (I2S_INTFLAG) Receive Ready x */ |
mbed_official | 579:53297373a894 | 321 | #define I2S_INTFLAG_RXRDY_Msk (0x3ul << I2S_INTFLAG_RXRDY_Pos) |
mbed_official | 579:53297373a894 | 322 | #define I2S_INTFLAG_RXRDY(value) ((I2S_INTFLAG_RXRDY_Msk & ((value) << I2S_INTFLAG_RXRDY_Pos))) |
mbed_official | 579:53297373a894 | 323 | #define I2S_INTFLAG_RXOR0_Pos 4 /**< \brief (I2S_INTFLAG) Receive Overrun 0 */ |
mbed_official | 579:53297373a894 | 324 | #define I2S_INTFLAG_RXOR0 (1 << I2S_INTFLAG_RXOR0_Pos) |
mbed_official | 579:53297373a894 | 325 | #define I2S_INTFLAG_RXOR1_Pos 5 /**< \brief (I2S_INTFLAG) Receive Overrun 1 */ |
mbed_official | 579:53297373a894 | 326 | #define I2S_INTFLAG_RXOR1 (1 << I2S_INTFLAG_RXOR1_Pos) |
mbed_official | 579:53297373a894 | 327 | #define I2S_INTFLAG_RXOR_Pos 4 /**< \brief (I2S_INTFLAG) Receive Overrun x */ |
mbed_official | 579:53297373a894 | 328 | #define I2S_INTFLAG_RXOR_Msk (0x3ul << I2S_INTFLAG_RXOR_Pos) |
mbed_official | 579:53297373a894 | 329 | #define I2S_INTFLAG_RXOR(value) ((I2S_INTFLAG_RXOR_Msk & ((value) << I2S_INTFLAG_RXOR_Pos))) |
mbed_official | 579:53297373a894 | 330 | #define I2S_INTFLAG_TXRDY0_Pos 8 /**< \brief (I2S_INTFLAG) Transmit Ready 0 */ |
mbed_official | 579:53297373a894 | 331 | #define I2S_INTFLAG_TXRDY0 (1 << I2S_INTFLAG_TXRDY0_Pos) |
mbed_official | 579:53297373a894 | 332 | #define I2S_INTFLAG_TXRDY1_Pos 9 /**< \brief (I2S_INTFLAG) Transmit Ready 1 */ |
mbed_official | 579:53297373a894 | 333 | #define I2S_INTFLAG_TXRDY1 (1 << I2S_INTFLAG_TXRDY1_Pos) |
mbed_official | 579:53297373a894 | 334 | #define I2S_INTFLAG_TXRDY_Pos 8 /**< \brief (I2S_INTFLAG) Transmit Ready x */ |
mbed_official | 579:53297373a894 | 335 | #define I2S_INTFLAG_TXRDY_Msk (0x3ul << I2S_INTFLAG_TXRDY_Pos) |
mbed_official | 579:53297373a894 | 336 | #define I2S_INTFLAG_TXRDY(value) ((I2S_INTFLAG_TXRDY_Msk & ((value) << I2S_INTFLAG_TXRDY_Pos))) |
mbed_official | 579:53297373a894 | 337 | #define I2S_INTFLAG_TXUR0_Pos 12 /**< \brief (I2S_INTFLAG) Transmit Underrun 0 */ |
mbed_official | 579:53297373a894 | 338 | #define I2S_INTFLAG_TXUR0 (1 << I2S_INTFLAG_TXUR0_Pos) |
mbed_official | 579:53297373a894 | 339 | #define I2S_INTFLAG_TXUR1_Pos 13 /**< \brief (I2S_INTFLAG) Transmit Underrun 1 */ |
mbed_official | 579:53297373a894 | 340 | #define I2S_INTFLAG_TXUR1 (1 << I2S_INTFLAG_TXUR1_Pos) |
mbed_official | 579:53297373a894 | 341 | #define I2S_INTFLAG_TXUR_Pos 12 /**< \brief (I2S_INTFLAG) Transmit Underrun x */ |
mbed_official | 579:53297373a894 | 342 | #define I2S_INTFLAG_TXUR_Msk (0x3ul << I2S_INTFLAG_TXUR_Pos) |
mbed_official | 579:53297373a894 | 343 | #define I2S_INTFLAG_TXUR(value) ((I2S_INTFLAG_TXUR_Msk & ((value) << I2S_INTFLAG_TXUR_Pos))) |
mbed_official | 579:53297373a894 | 344 | #define I2S_INTFLAG_MASK 0x3333ul /**< \brief (I2S_INTFLAG) MASK Register */ |
mbed_official | 579:53297373a894 | 345 | |
mbed_official | 579:53297373a894 | 346 | /* -------- I2S_SYNCBUSY : (I2S Offset: 0x18) (R/ 16) Synchronization Status -------- */ |
mbed_official | 579:53297373a894 | 347 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 348 | typedef union { |
mbed_official | 579:53297373a894 | 349 | struct { |
mbed_official | 579:53297373a894 | 350 | uint16_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Status */ |
mbed_official | 579:53297373a894 | 351 | uint16_t ENABLE:1; /*!< bit: 1 Enable Synchronization Status */ |
mbed_official | 579:53297373a894 | 352 | uint16_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable Synchronization Status */ |
mbed_official | 579:53297373a894 | 353 | uint16_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable Synchronization Status */ |
mbed_official | 579:53297373a894 | 354 | uint16_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable Synchronization Status */ |
mbed_official | 579:53297373a894 | 355 | uint16_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable Synchronization Status */ |
mbed_official | 579:53297373a894 | 356 | uint16_t :2; /*!< bit: 6.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 357 | uint16_t DATA0:1; /*!< bit: 8 Data 0 Synchronization Status */ |
mbed_official | 579:53297373a894 | 358 | uint16_t DATA1:1; /*!< bit: 9 Data 1 Synchronization Status */ |
mbed_official | 579:53297373a894 | 359 | uint16_t :6; /*!< bit: 10..15 Reserved */ |
mbed_official | 579:53297373a894 | 360 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 361 | struct { |
mbed_official | 579:53297373a894 | 362 | uint16_t :2; /*!< bit: 0.. 1 Reserved */ |
mbed_official | 579:53297373a894 | 363 | uint16_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable Synchronization Status */ |
mbed_official | 579:53297373a894 | 364 | uint16_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable Synchronization Status */ |
mbed_official | 579:53297373a894 | 365 | uint16_t :2; /*!< bit: 6.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 366 | uint16_t DATA:2; /*!< bit: 8.. 9 Data x Synchronization Status */ |
mbed_official | 579:53297373a894 | 367 | uint16_t :6; /*!< bit: 10..15 Reserved */ |
mbed_official | 579:53297373a894 | 368 | } vec; /*!< Structure used for vec access */ |
mbed_official | 579:53297373a894 | 369 | uint16_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 370 | } I2S_SYNCBUSY_Type; |
mbed_official | 579:53297373a894 | 371 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 372 | |
mbed_official | 579:53297373a894 | 373 | #define I2S_SYNCBUSY_OFFSET 0x18 /**< \brief (I2S_SYNCBUSY offset) Synchronization Status */ |
mbed_official | 579:53297373a894 | 374 | #define I2S_SYNCBUSY_RESETVALUE 0x0000ul /**< \brief (I2S_SYNCBUSY reset_value) Synchronization Status */ |
mbed_official | 579:53297373a894 | 375 | |
mbed_official | 579:53297373a894 | 376 | #define I2S_SYNCBUSY_SWRST_Pos 0 /**< \brief (I2S_SYNCBUSY) Software Reset Synchronization Status */ |
mbed_official | 579:53297373a894 | 377 | #define I2S_SYNCBUSY_SWRST (0x1ul << I2S_SYNCBUSY_SWRST_Pos) |
mbed_official | 579:53297373a894 | 378 | #define I2S_SYNCBUSY_ENABLE_Pos 1 /**< \brief (I2S_SYNCBUSY) Enable Synchronization Status */ |
mbed_official | 579:53297373a894 | 379 | #define I2S_SYNCBUSY_ENABLE (0x1ul << I2S_SYNCBUSY_ENABLE_Pos) |
mbed_official | 579:53297373a894 | 380 | #define I2S_SYNCBUSY_CKEN0_Pos 2 /**< \brief (I2S_SYNCBUSY) Clock Unit 0 Enable Synchronization Status */ |
mbed_official | 579:53297373a894 | 381 | #define I2S_SYNCBUSY_CKEN0 (1 << I2S_SYNCBUSY_CKEN0_Pos) |
mbed_official | 579:53297373a894 | 382 | #define I2S_SYNCBUSY_CKEN1_Pos 3 /**< \brief (I2S_SYNCBUSY) Clock Unit 1 Enable Synchronization Status */ |
mbed_official | 579:53297373a894 | 383 | #define I2S_SYNCBUSY_CKEN1 (1 << I2S_SYNCBUSY_CKEN1_Pos) |
mbed_official | 579:53297373a894 | 384 | #define I2S_SYNCBUSY_CKEN_Pos 2 /**< \brief (I2S_SYNCBUSY) Clock Unit x Enable Synchronization Status */ |
mbed_official | 579:53297373a894 | 385 | #define I2S_SYNCBUSY_CKEN_Msk (0x3ul << I2S_SYNCBUSY_CKEN_Pos) |
mbed_official | 579:53297373a894 | 386 | #define I2S_SYNCBUSY_CKEN(value) ((I2S_SYNCBUSY_CKEN_Msk & ((value) << I2S_SYNCBUSY_CKEN_Pos))) |
mbed_official | 579:53297373a894 | 387 | #define I2S_SYNCBUSY_SEREN0_Pos 4 /**< \brief (I2S_SYNCBUSY) Serializer 0 Enable Synchronization Status */ |
mbed_official | 579:53297373a894 | 388 | #define I2S_SYNCBUSY_SEREN0 (1 << I2S_SYNCBUSY_SEREN0_Pos) |
mbed_official | 579:53297373a894 | 389 | #define I2S_SYNCBUSY_SEREN1_Pos 5 /**< \brief (I2S_SYNCBUSY) Serializer 1 Enable Synchronization Status */ |
mbed_official | 579:53297373a894 | 390 | #define I2S_SYNCBUSY_SEREN1 (1 << I2S_SYNCBUSY_SEREN1_Pos) |
mbed_official | 579:53297373a894 | 391 | #define I2S_SYNCBUSY_SEREN_Pos 4 /**< \brief (I2S_SYNCBUSY) Serializer x Enable Synchronization Status */ |
mbed_official | 579:53297373a894 | 392 | #define I2S_SYNCBUSY_SEREN_Msk (0x3ul << I2S_SYNCBUSY_SEREN_Pos) |
mbed_official | 579:53297373a894 | 393 | #define I2S_SYNCBUSY_SEREN(value) ((I2S_SYNCBUSY_SEREN_Msk & ((value) << I2S_SYNCBUSY_SEREN_Pos))) |
mbed_official | 579:53297373a894 | 394 | #define I2S_SYNCBUSY_DATA0_Pos 8 /**< \brief (I2S_SYNCBUSY) Data 0 Synchronization Status */ |
mbed_official | 579:53297373a894 | 395 | #define I2S_SYNCBUSY_DATA0 (1 << I2S_SYNCBUSY_DATA0_Pos) |
mbed_official | 579:53297373a894 | 396 | #define I2S_SYNCBUSY_DATA1_Pos 9 /**< \brief (I2S_SYNCBUSY) Data 1 Synchronization Status */ |
mbed_official | 579:53297373a894 | 397 | #define I2S_SYNCBUSY_DATA1 (1 << I2S_SYNCBUSY_DATA1_Pos) |
mbed_official | 579:53297373a894 | 398 | #define I2S_SYNCBUSY_DATA_Pos 8 /**< \brief (I2S_SYNCBUSY) Data x Synchronization Status */ |
mbed_official | 579:53297373a894 | 399 | #define I2S_SYNCBUSY_DATA_Msk (0x3ul << I2S_SYNCBUSY_DATA_Pos) |
mbed_official | 579:53297373a894 | 400 | #define I2S_SYNCBUSY_DATA(value) ((I2S_SYNCBUSY_DATA_Msk & ((value) << I2S_SYNCBUSY_DATA_Pos))) |
mbed_official | 579:53297373a894 | 401 | #define I2S_SYNCBUSY_MASK 0x033Ful /**< \brief (I2S_SYNCBUSY) MASK Register */ |
mbed_official | 579:53297373a894 | 402 | |
mbed_official | 579:53297373a894 | 403 | /* -------- I2S_SERCTRL : (I2S Offset: 0x20) (R/W 32) Serializer n Control -------- */ |
mbed_official | 579:53297373a894 | 404 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 405 | typedef union { |
mbed_official | 579:53297373a894 | 406 | struct { |
mbed_official | 579:53297373a894 | 407 | uint32_t SERMODE:2; /*!< bit: 0.. 1 Serializer Mode */ |
mbed_official | 579:53297373a894 | 408 | uint32_t TXDEFAULT:2; /*!< bit: 2.. 3 Line Default Line when Slot Disabled */ |
mbed_official | 579:53297373a894 | 409 | uint32_t TXSAME:1; /*!< bit: 4 Transmit Data when Underrun */ |
mbed_official | 579:53297373a894 | 410 | uint32_t CLKSEL:1; /*!< bit: 5 Clock Unit Selection */ |
mbed_official | 579:53297373a894 | 411 | uint32_t :1; /*!< bit: 6 Reserved */ |
mbed_official | 579:53297373a894 | 412 | uint32_t SLOTADJ:1; /*!< bit: 7 Data Slot Formatting Adjust */ |
mbed_official | 579:53297373a894 | 413 | uint32_t DATASIZE:3; /*!< bit: 8..10 Data Word Size */ |
mbed_official | 579:53297373a894 | 414 | uint32_t :1; /*!< bit: 11 Reserved */ |
mbed_official | 579:53297373a894 | 415 | uint32_t WORDADJ:1; /*!< bit: 12 Data Word Formatting Adjust */ |
mbed_official | 579:53297373a894 | 416 | uint32_t EXTEND:2; /*!< bit: 13..14 Data Formatting Bit Extension */ |
mbed_official | 579:53297373a894 | 417 | uint32_t BITREV:1; /*!< bit: 15 Data Formatting Bit Reverse */ |
mbed_official | 579:53297373a894 | 418 | uint32_t SLOTDIS0:1; /*!< bit: 16 Slot 0 Disabled for this Serializer */ |
mbed_official | 579:53297373a894 | 419 | uint32_t SLOTDIS1:1; /*!< bit: 17 Slot 1 Disabled for this Serializer */ |
mbed_official | 579:53297373a894 | 420 | uint32_t SLOTDIS2:1; /*!< bit: 18 Slot 2 Disabled for this Serializer */ |
mbed_official | 579:53297373a894 | 421 | uint32_t SLOTDIS3:1; /*!< bit: 19 Slot 3 Disabled for this Serializer */ |
mbed_official | 579:53297373a894 | 422 | uint32_t SLOTDIS4:1; /*!< bit: 20 Slot 4 Disabled for this Serializer */ |
mbed_official | 579:53297373a894 | 423 | uint32_t SLOTDIS5:1; /*!< bit: 21 Slot 5 Disabled for this Serializer */ |
mbed_official | 579:53297373a894 | 424 | uint32_t SLOTDIS6:1; /*!< bit: 22 Slot 6 Disabled for this Serializer */ |
mbed_official | 579:53297373a894 | 425 | uint32_t SLOTDIS7:1; /*!< bit: 23 Slot 7 Disabled for this Serializer */ |
mbed_official | 579:53297373a894 | 426 | uint32_t MONO:1; /*!< bit: 24 Mono Mode */ |
mbed_official | 579:53297373a894 | 427 | uint32_t DMA:1; /*!< bit: 25 Single or Multiple DMA Channels */ |
mbed_official | 579:53297373a894 | 428 | uint32_t RXLOOP:1; /*!< bit: 26 Loop-back Test Mode */ |
mbed_official | 579:53297373a894 | 429 | uint32_t :5; /*!< bit: 27..31 Reserved */ |
mbed_official | 579:53297373a894 | 430 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 431 | struct { |
mbed_official | 579:53297373a894 | 432 | uint32_t :16; /*!< bit: 0..15 Reserved */ |
mbed_official | 579:53297373a894 | 433 | uint32_t SLOTDIS:8; /*!< bit: 16..23 Slot x Disabled for this Serializer */ |
mbed_official | 579:53297373a894 | 434 | uint32_t :8; /*!< bit: 24..31 Reserved */ |
mbed_official | 579:53297373a894 | 435 | } vec; /*!< Structure used for vec access */ |
mbed_official | 579:53297373a894 | 436 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 437 | } I2S_SERCTRL_Type; |
mbed_official | 579:53297373a894 | 438 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 439 | |
mbed_official | 579:53297373a894 | 440 | #define I2S_SERCTRL_OFFSET 0x20 /**< \brief (I2S_SERCTRL offset) Serializer n Control */ |
mbed_official | 579:53297373a894 | 441 | #define I2S_SERCTRL_RESETVALUE 0x00000000ul /**< \brief (I2S_SERCTRL reset_value) Serializer n Control */ |
mbed_official | 579:53297373a894 | 442 | |
mbed_official | 579:53297373a894 | 443 | #define I2S_SERCTRL_SERMODE_Pos 0 /**< \brief (I2S_SERCTRL) Serializer Mode */ |
mbed_official | 579:53297373a894 | 444 | #define I2S_SERCTRL_SERMODE_Msk (0x3ul << I2S_SERCTRL_SERMODE_Pos) |
mbed_official | 579:53297373a894 | 445 | #define I2S_SERCTRL_SERMODE(value) ((I2S_SERCTRL_SERMODE_Msk & ((value) << I2S_SERCTRL_SERMODE_Pos))) |
mbed_official | 579:53297373a894 | 446 | #define I2S_SERCTRL_SERMODE_RX_Val 0x0ul /**< \brief (I2S_SERCTRL) Receive */ |
mbed_official | 579:53297373a894 | 447 | #define I2S_SERCTRL_SERMODE_TX_Val 0x1ul /**< \brief (I2S_SERCTRL) Transmit */ |
mbed_official | 579:53297373a894 | 448 | #define I2S_SERCTRL_SERMODE_PDM2_Val 0x2ul /**< \brief (I2S_SERCTRL) Receive one PDM data on each serial clock edge */ |
mbed_official | 579:53297373a894 | 449 | #define I2S_SERCTRL_SERMODE_RX (I2S_SERCTRL_SERMODE_RX_Val << I2S_SERCTRL_SERMODE_Pos) |
mbed_official | 579:53297373a894 | 450 | #define I2S_SERCTRL_SERMODE_TX (I2S_SERCTRL_SERMODE_TX_Val << I2S_SERCTRL_SERMODE_Pos) |
mbed_official | 579:53297373a894 | 451 | #define I2S_SERCTRL_SERMODE_PDM2 (I2S_SERCTRL_SERMODE_PDM2_Val << I2S_SERCTRL_SERMODE_Pos) |
mbed_official | 579:53297373a894 | 452 | #define I2S_SERCTRL_TXDEFAULT_Pos 2 /**< \brief (I2S_SERCTRL) Line Default Line when Slot Disabled */ |
mbed_official | 579:53297373a894 | 453 | #define I2S_SERCTRL_TXDEFAULT_Msk (0x3ul << I2S_SERCTRL_TXDEFAULT_Pos) |
mbed_official | 579:53297373a894 | 454 | #define I2S_SERCTRL_TXDEFAULT(value) ((I2S_SERCTRL_TXDEFAULT_Msk & ((value) << I2S_SERCTRL_TXDEFAULT_Pos))) |
mbed_official | 579:53297373a894 | 455 | #define I2S_SERCTRL_TXDEFAULT_ZERO_Val 0x0ul /**< \brief (I2S_SERCTRL) Output Default Value is 0 */ |
mbed_official | 579:53297373a894 | 456 | #define I2S_SERCTRL_TXDEFAULT_ONE_Val 0x1ul /**< \brief (I2S_SERCTRL) Output Default Value is 1 */ |
mbed_official | 579:53297373a894 | 457 | #define I2S_SERCTRL_TXDEFAULT_HIZ_Val 0x3ul /**< \brief (I2S_SERCTRL) Output Default Value is high impedance */ |
mbed_official | 579:53297373a894 | 458 | #define I2S_SERCTRL_TXDEFAULT_ZERO (I2S_SERCTRL_TXDEFAULT_ZERO_Val << I2S_SERCTRL_TXDEFAULT_Pos) |
mbed_official | 579:53297373a894 | 459 | #define I2S_SERCTRL_TXDEFAULT_ONE (I2S_SERCTRL_TXDEFAULT_ONE_Val << I2S_SERCTRL_TXDEFAULT_Pos) |
mbed_official | 579:53297373a894 | 460 | #define I2S_SERCTRL_TXDEFAULT_HIZ (I2S_SERCTRL_TXDEFAULT_HIZ_Val << I2S_SERCTRL_TXDEFAULT_Pos) |
mbed_official | 579:53297373a894 | 461 | #define I2S_SERCTRL_TXSAME_Pos 4 /**< \brief (I2S_SERCTRL) Transmit Data when Underrun */ |
mbed_official | 579:53297373a894 | 462 | #define I2S_SERCTRL_TXSAME (0x1ul << I2S_SERCTRL_TXSAME_Pos) |
mbed_official | 579:53297373a894 | 463 | #define I2S_SERCTRL_TXSAME_ZERO_Val 0x0ul /**< \brief (I2S_SERCTRL) Zero data transmitted in case of underrun */ |
mbed_official | 579:53297373a894 | 464 | #define I2S_SERCTRL_TXSAME_SAME_Val 0x1ul /**< \brief (I2S_SERCTRL) Last data transmitted in case of underrun */ |
mbed_official | 579:53297373a894 | 465 | #define I2S_SERCTRL_TXSAME_ZERO (I2S_SERCTRL_TXSAME_ZERO_Val << I2S_SERCTRL_TXSAME_Pos) |
mbed_official | 579:53297373a894 | 466 | #define I2S_SERCTRL_TXSAME_SAME (I2S_SERCTRL_TXSAME_SAME_Val << I2S_SERCTRL_TXSAME_Pos) |
mbed_official | 579:53297373a894 | 467 | #define I2S_SERCTRL_CLKSEL_Pos 5 /**< \brief (I2S_SERCTRL) Clock Unit Selection */ |
mbed_official | 579:53297373a894 | 468 | #define I2S_SERCTRL_CLKSEL (0x1ul << I2S_SERCTRL_CLKSEL_Pos) |
mbed_official | 579:53297373a894 | 469 | #define I2S_SERCTRL_CLKSEL_CLK0_Val 0x0ul /**< \brief (I2S_SERCTRL) Use Clock Unit 0 */ |
mbed_official | 579:53297373a894 | 470 | #define I2S_SERCTRL_CLKSEL_CLK1_Val 0x1ul /**< \brief (I2S_SERCTRL) Use Clock Unit 1 */ |
mbed_official | 579:53297373a894 | 471 | #define I2S_SERCTRL_CLKSEL_CLK0 (I2S_SERCTRL_CLKSEL_CLK0_Val << I2S_SERCTRL_CLKSEL_Pos) |
mbed_official | 579:53297373a894 | 472 | #define I2S_SERCTRL_CLKSEL_CLK1 (I2S_SERCTRL_CLKSEL_CLK1_Val << I2S_SERCTRL_CLKSEL_Pos) |
mbed_official | 579:53297373a894 | 473 | #define I2S_SERCTRL_SLOTADJ_Pos 7 /**< \brief (I2S_SERCTRL) Data Slot Formatting Adjust */ |
mbed_official | 579:53297373a894 | 474 | #define I2S_SERCTRL_SLOTADJ (0x1ul << I2S_SERCTRL_SLOTADJ_Pos) |
mbed_official | 579:53297373a894 | 475 | #define I2S_SERCTRL_SLOTADJ_RIGHT_Val 0x0ul /**< \brief (I2S_SERCTRL) Data is right adjusted in slot */ |
mbed_official | 579:53297373a894 | 476 | #define I2S_SERCTRL_SLOTADJ_LEFT_Val 0x1ul /**< \brief (I2S_SERCTRL) Data is left adjusted in slot */ |
mbed_official | 579:53297373a894 | 477 | #define I2S_SERCTRL_SLOTADJ_RIGHT (I2S_SERCTRL_SLOTADJ_RIGHT_Val << I2S_SERCTRL_SLOTADJ_Pos) |
mbed_official | 579:53297373a894 | 478 | #define I2S_SERCTRL_SLOTADJ_LEFT (I2S_SERCTRL_SLOTADJ_LEFT_Val << I2S_SERCTRL_SLOTADJ_Pos) |
mbed_official | 579:53297373a894 | 479 | #define I2S_SERCTRL_DATASIZE_Pos 8 /**< \brief (I2S_SERCTRL) Data Word Size */ |
mbed_official | 579:53297373a894 | 480 | #define I2S_SERCTRL_DATASIZE_Msk (0x7ul << I2S_SERCTRL_DATASIZE_Pos) |
mbed_official | 579:53297373a894 | 481 | #define I2S_SERCTRL_DATASIZE(value) ((I2S_SERCTRL_DATASIZE_Msk & ((value) << I2S_SERCTRL_DATASIZE_Pos))) |
mbed_official | 579:53297373a894 | 482 | #define I2S_SERCTRL_DATASIZE_32_Val 0x0ul /**< \brief (I2S_SERCTRL) 32 bits */ |
mbed_official | 579:53297373a894 | 483 | #define I2S_SERCTRL_DATASIZE_24_Val 0x1ul /**< \brief (I2S_SERCTRL) 24 bits */ |
mbed_official | 579:53297373a894 | 484 | #define I2S_SERCTRL_DATASIZE_20_Val 0x2ul /**< \brief (I2S_SERCTRL) 20 bits */ |
mbed_official | 579:53297373a894 | 485 | #define I2S_SERCTRL_DATASIZE_18_Val 0x3ul /**< \brief (I2S_SERCTRL) 18 bits */ |
mbed_official | 579:53297373a894 | 486 | #define I2S_SERCTRL_DATASIZE_16_Val 0x4ul /**< \brief (I2S_SERCTRL) 16 bits */ |
mbed_official | 579:53297373a894 | 487 | #define I2S_SERCTRL_DATASIZE_16C_Val 0x5ul /**< \brief (I2S_SERCTRL) 16 bits compact stereo */ |
mbed_official | 579:53297373a894 | 488 | #define I2S_SERCTRL_DATASIZE_8_Val 0x6ul /**< \brief (I2S_SERCTRL) 8 bits */ |
mbed_official | 579:53297373a894 | 489 | #define I2S_SERCTRL_DATASIZE_8C_Val 0x7ul /**< \brief (I2S_SERCTRL) 8 bits compact stereo */ |
mbed_official | 579:53297373a894 | 490 | #define I2S_SERCTRL_DATASIZE_32 (I2S_SERCTRL_DATASIZE_32_Val << I2S_SERCTRL_DATASIZE_Pos) |
mbed_official | 579:53297373a894 | 491 | #define I2S_SERCTRL_DATASIZE_24 (I2S_SERCTRL_DATASIZE_24_Val << I2S_SERCTRL_DATASIZE_Pos) |
mbed_official | 579:53297373a894 | 492 | #define I2S_SERCTRL_DATASIZE_20 (I2S_SERCTRL_DATASIZE_20_Val << I2S_SERCTRL_DATASIZE_Pos) |
mbed_official | 579:53297373a894 | 493 | #define I2S_SERCTRL_DATASIZE_18 (I2S_SERCTRL_DATASIZE_18_Val << I2S_SERCTRL_DATASIZE_Pos) |
mbed_official | 579:53297373a894 | 494 | #define I2S_SERCTRL_DATASIZE_16 (I2S_SERCTRL_DATASIZE_16_Val << I2S_SERCTRL_DATASIZE_Pos) |
mbed_official | 579:53297373a894 | 495 | #define I2S_SERCTRL_DATASIZE_16C (I2S_SERCTRL_DATASIZE_16C_Val << I2S_SERCTRL_DATASIZE_Pos) |
mbed_official | 579:53297373a894 | 496 | #define I2S_SERCTRL_DATASIZE_8 (I2S_SERCTRL_DATASIZE_8_Val << I2S_SERCTRL_DATASIZE_Pos) |
mbed_official | 579:53297373a894 | 497 | #define I2S_SERCTRL_DATASIZE_8C (I2S_SERCTRL_DATASIZE_8C_Val << I2S_SERCTRL_DATASIZE_Pos) |
mbed_official | 579:53297373a894 | 498 | #define I2S_SERCTRL_WORDADJ_Pos 12 /**< \brief (I2S_SERCTRL) Data Word Formatting Adjust */ |
mbed_official | 579:53297373a894 | 499 | #define I2S_SERCTRL_WORDADJ (0x1ul << I2S_SERCTRL_WORDADJ_Pos) |
mbed_official | 579:53297373a894 | 500 | #define I2S_SERCTRL_WORDADJ_RIGHT_Val 0x0ul /**< \brief (I2S_SERCTRL) Data is right adjusted in word */ |
mbed_official | 579:53297373a894 | 501 | #define I2S_SERCTRL_WORDADJ_LEFT_Val 0x1ul /**< \brief (I2S_SERCTRL) Data is left adjusted in word */ |
mbed_official | 579:53297373a894 | 502 | #define I2S_SERCTRL_WORDADJ_RIGHT (I2S_SERCTRL_WORDADJ_RIGHT_Val << I2S_SERCTRL_WORDADJ_Pos) |
mbed_official | 579:53297373a894 | 503 | #define I2S_SERCTRL_WORDADJ_LEFT (I2S_SERCTRL_WORDADJ_LEFT_Val << I2S_SERCTRL_WORDADJ_Pos) |
mbed_official | 579:53297373a894 | 504 | #define I2S_SERCTRL_EXTEND_Pos 13 /**< \brief (I2S_SERCTRL) Data Formatting Bit Extension */ |
mbed_official | 579:53297373a894 | 505 | #define I2S_SERCTRL_EXTEND_Msk (0x3ul << I2S_SERCTRL_EXTEND_Pos) |
mbed_official | 579:53297373a894 | 506 | #define I2S_SERCTRL_EXTEND(value) ((I2S_SERCTRL_EXTEND_Msk & ((value) << I2S_SERCTRL_EXTEND_Pos))) |
mbed_official | 579:53297373a894 | 507 | #define I2S_SERCTRL_EXTEND_ZERO_Val 0x0ul /**< \brief (I2S_SERCTRL) Extend with zeroes */ |
mbed_official | 579:53297373a894 | 508 | #define I2S_SERCTRL_EXTEND_ONE_Val 0x1ul /**< \brief (I2S_SERCTRL) Extend with ones */ |
mbed_official | 579:53297373a894 | 509 | #define I2S_SERCTRL_EXTEND_MSBIT_Val 0x2ul /**< \brief (I2S_SERCTRL) Extend with Most Significant Bit */ |
mbed_official | 579:53297373a894 | 510 | #define I2S_SERCTRL_EXTEND_LSBIT_Val 0x3ul /**< \brief (I2S_SERCTRL) Extend with Least Significant Bit */ |
mbed_official | 579:53297373a894 | 511 | #define I2S_SERCTRL_EXTEND_ZERO (I2S_SERCTRL_EXTEND_ZERO_Val << I2S_SERCTRL_EXTEND_Pos) |
mbed_official | 579:53297373a894 | 512 | #define I2S_SERCTRL_EXTEND_ONE (I2S_SERCTRL_EXTEND_ONE_Val << I2S_SERCTRL_EXTEND_Pos) |
mbed_official | 579:53297373a894 | 513 | #define I2S_SERCTRL_EXTEND_MSBIT (I2S_SERCTRL_EXTEND_MSBIT_Val << I2S_SERCTRL_EXTEND_Pos) |
mbed_official | 579:53297373a894 | 514 | #define I2S_SERCTRL_EXTEND_LSBIT (I2S_SERCTRL_EXTEND_LSBIT_Val << I2S_SERCTRL_EXTEND_Pos) |
mbed_official | 579:53297373a894 | 515 | #define I2S_SERCTRL_BITREV_Pos 15 /**< \brief (I2S_SERCTRL) Data Formatting Bit Reverse */ |
mbed_official | 579:53297373a894 | 516 | #define I2S_SERCTRL_BITREV (0x1ul << I2S_SERCTRL_BITREV_Pos) |
mbed_official | 579:53297373a894 | 517 | #define I2S_SERCTRL_BITREV_MSBIT_Val 0x0ul /**< \brief (I2S_SERCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) */ |
mbed_official | 579:53297373a894 | 518 | #define I2S_SERCTRL_BITREV_LSBIT_Val 0x1ul /**< \brief (I2S_SERCTRL) Transfer Data Least Significant Bit (LSB) first */ |
mbed_official | 579:53297373a894 | 519 | #define I2S_SERCTRL_BITREV_MSBIT (I2S_SERCTRL_BITREV_MSBIT_Val << I2S_SERCTRL_BITREV_Pos) |
mbed_official | 579:53297373a894 | 520 | #define I2S_SERCTRL_BITREV_LSBIT (I2S_SERCTRL_BITREV_LSBIT_Val << I2S_SERCTRL_BITREV_Pos) |
mbed_official | 579:53297373a894 | 521 | #define I2S_SERCTRL_SLOTDIS0_Pos 16 /**< \brief (I2S_SERCTRL) Slot 0 Disabled for this Serializer */ |
mbed_official | 579:53297373a894 | 522 | #define I2S_SERCTRL_SLOTDIS0 (1 << I2S_SERCTRL_SLOTDIS0_Pos) |
mbed_official | 579:53297373a894 | 523 | #define I2S_SERCTRL_SLOTDIS1_Pos 17 /**< \brief (I2S_SERCTRL) Slot 1 Disabled for this Serializer */ |
mbed_official | 579:53297373a894 | 524 | #define I2S_SERCTRL_SLOTDIS1 (1 << I2S_SERCTRL_SLOTDIS1_Pos) |
mbed_official | 579:53297373a894 | 525 | #define I2S_SERCTRL_SLOTDIS2_Pos 18 /**< \brief (I2S_SERCTRL) Slot 2 Disabled for this Serializer */ |
mbed_official | 579:53297373a894 | 526 | #define I2S_SERCTRL_SLOTDIS2 (1 << I2S_SERCTRL_SLOTDIS2_Pos) |
mbed_official | 579:53297373a894 | 527 | #define I2S_SERCTRL_SLOTDIS3_Pos 19 /**< \brief (I2S_SERCTRL) Slot 3 Disabled for this Serializer */ |
mbed_official | 579:53297373a894 | 528 | #define I2S_SERCTRL_SLOTDIS3 (1 << I2S_SERCTRL_SLOTDIS3_Pos) |
mbed_official | 579:53297373a894 | 529 | #define I2S_SERCTRL_SLOTDIS4_Pos 20 /**< \brief (I2S_SERCTRL) Slot 4 Disabled for this Serializer */ |
mbed_official | 579:53297373a894 | 530 | #define I2S_SERCTRL_SLOTDIS4 (1 << I2S_SERCTRL_SLOTDIS4_Pos) |
mbed_official | 579:53297373a894 | 531 | #define I2S_SERCTRL_SLOTDIS5_Pos 21 /**< \brief (I2S_SERCTRL) Slot 5 Disabled for this Serializer */ |
mbed_official | 579:53297373a894 | 532 | #define I2S_SERCTRL_SLOTDIS5 (1 << I2S_SERCTRL_SLOTDIS5_Pos) |
mbed_official | 579:53297373a894 | 533 | #define I2S_SERCTRL_SLOTDIS6_Pos 22 /**< \brief (I2S_SERCTRL) Slot 6 Disabled for this Serializer */ |
mbed_official | 579:53297373a894 | 534 | #define I2S_SERCTRL_SLOTDIS6 (1 << I2S_SERCTRL_SLOTDIS6_Pos) |
mbed_official | 579:53297373a894 | 535 | #define I2S_SERCTRL_SLOTDIS7_Pos 23 /**< \brief (I2S_SERCTRL) Slot 7 Disabled for this Serializer */ |
mbed_official | 579:53297373a894 | 536 | #define I2S_SERCTRL_SLOTDIS7 (1 << I2S_SERCTRL_SLOTDIS7_Pos) |
mbed_official | 579:53297373a894 | 537 | #define I2S_SERCTRL_SLOTDIS_Pos 16 /**< \brief (I2S_SERCTRL) Slot x Disabled for this Serializer */ |
mbed_official | 579:53297373a894 | 538 | #define I2S_SERCTRL_SLOTDIS_Msk (0xFFul << I2S_SERCTRL_SLOTDIS_Pos) |
mbed_official | 579:53297373a894 | 539 | #define I2S_SERCTRL_SLOTDIS(value) ((I2S_SERCTRL_SLOTDIS_Msk & ((value) << I2S_SERCTRL_SLOTDIS_Pos))) |
mbed_official | 579:53297373a894 | 540 | #define I2S_SERCTRL_MONO_Pos 24 /**< \brief (I2S_SERCTRL) Mono Mode */ |
mbed_official | 579:53297373a894 | 541 | #define I2S_SERCTRL_MONO (0x1ul << I2S_SERCTRL_MONO_Pos) |
mbed_official | 579:53297373a894 | 542 | #define I2S_SERCTRL_MONO_STEREO_Val 0x0ul /**< \brief (I2S_SERCTRL) Normal mode */ |
mbed_official | 579:53297373a894 | 543 | #define I2S_SERCTRL_MONO_MONO_Val 0x1ul /**< \brief (I2S_SERCTRL) Left channel data is duplicated to right channel */ |
mbed_official | 579:53297373a894 | 544 | #define I2S_SERCTRL_MONO_STEREO (I2S_SERCTRL_MONO_STEREO_Val << I2S_SERCTRL_MONO_Pos) |
mbed_official | 579:53297373a894 | 545 | #define I2S_SERCTRL_MONO_MONO (I2S_SERCTRL_MONO_MONO_Val << I2S_SERCTRL_MONO_Pos) |
mbed_official | 579:53297373a894 | 546 | #define I2S_SERCTRL_DMA_Pos 25 /**< \brief (I2S_SERCTRL) Single or Multiple DMA Channels */ |
mbed_official | 579:53297373a894 | 547 | #define I2S_SERCTRL_DMA (0x1ul << I2S_SERCTRL_DMA_Pos) |
mbed_official | 579:53297373a894 | 548 | #define I2S_SERCTRL_DMA_SINGLE_Val 0x0ul /**< \brief (I2S_SERCTRL) Single DMA channel */ |
mbed_official | 579:53297373a894 | 549 | #define I2S_SERCTRL_DMA_MULTIPLE_Val 0x1ul /**< \brief (I2S_SERCTRL) One DMA channel per data channel */ |
mbed_official | 579:53297373a894 | 550 | #define I2S_SERCTRL_DMA_SINGLE (I2S_SERCTRL_DMA_SINGLE_Val << I2S_SERCTRL_DMA_Pos) |
mbed_official | 579:53297373a894 | 551 | #define I2S_SERCTRL_DMA_MULTIPLE (I2S_SERCTRL_DMA_MULTIPLE_Val << I2S_SERCTRL_DMA_Pos) |
mbed_official | 579:53297373a894 | 552 | #define I2S_SERCTRL_RXLOOP_Pos 26 /**< \brief (I2S_SERCTRL) Loop-back Test Mode */ |
mbed_official | 579:53297373a894 | 553 | #define I2S_SERCTRL_RXLOOP (0x1ul << I2S_SERCTRL_RXLOOP_Pos) |
mbed_official | 579:53297373a894 | 554 | #define I2S_SERCTRL_MASK 0x07FFF7BFul /**< \brief (I2S_SERCTRL) MASK Register */ |
mbed_official | 579:53297373a894 | 555 | |
mbed_official | 579:53297373a894 | 556 | /* -------- I2S_DATA : (I2S Offset: 0x30) (R/W 32) Data n -------- */ |
mbed_official | 579:53297373a894 | 557 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 558 | typedef union { |
mbed_official | 579:53297373a894 | 559 | struct { |
mbed_official | 579:53297373a894 | 560 | uint32_t DATA:32; /*!< bit: 0..31 Sample Data */ |
mbed_official | 579:53297373a894 | 561 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 562 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 563 | } I2S_DATA_Type; |
mbed_official | 579:53297373a894 | 564 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 565 | |
mbed_official | 579:53297373a894 | 566 | #define I2S_DATA_OFFSET 0x30 /**< \brief (I2S_DATA offset) Data n */ |
mbed_official | 579:53297373a894 | 567 | #define I2S_DATA_RESETVALUE 0x00000000ul /**< \brief (I2S_DATA reset_value) Data n */ |
mbed_official | 579:53297373a894 | 568 | |
mbed_official | 579:53297373a894 | 569 | #define I2S_DATA_DATA_Pos 0 /**< \brief (I2S_DATA) Sample Data */ |
mbed_official | 579:53297373a894 | 570 | #define I2S_DATA_DATA_Msk (0xFFFFFFFFul << I2S_DATA_DATA_Pos) |
mbed_official | 579:53297373a894 | 571 | #define I2S_DATA_DATA(value) ((I2S_DATA_DATA_Msk & ((value) << I2S_DATA_DATA_Pos))) |
mbed_official | 579:53297373a894 | 572 | #define I2S_DATA_MASK 0xFFFFFFFFul /**< \brief (I2S_DATA) MASK Register */ |
mbed_official | 579:53297373a894 | 573 | |
mbed_official | 579:53297373a894 | 574 | /** \brief I2S hardware registers */ |
mbed_official | 579:53297373a894 | 575 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 576 | typedef struct { |
mbed_official | 579:53297373a894 | 577 | __IO I2S_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ |
mbed_official | 579:53297373a894 | 578 | RoReg8 Reserved1[0x3]; |
mbed_official | 579:53297373a894 | 579 | __IO I2S_CLKCTRL_Type CLKCTRL[2]; /**< \brief Offset: 0x04 (R/W 32) Clock Unit n Control */ |
mbed_official | 579:53297373a894 | 580 | __IO I2S_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */ |
mbed_official | 579:53297373a894 | 581 | RoReg8 Reserved2[0x2]; |
mbed_official | 579:53297373a894 | 582 | __IO I2S_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 16) Interrupt Enable Set */ |
mbed_official | 579:53297373a894 | 583 | RoReg8 Reserved3[0x2]; |
mbed_official | 579:53297373a894 | 584 | __IO I2S_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 16) Interrupt Flag Status and Clear */ |
mbed_official | 579:53297373a894 | 585 | RoReg8 Reserved4[0x2]; |
mbed_official | 579:53297373a894 | 586 | __I I2S_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x18 (R/ 16) Synchronization Status */ |
mbed_official | 579:53297373a894 | 587 | RoReg8 Reserved5[0x6]; |
mbed_official | 579:53297373a894 | 588 | __IO I2S_SERCTRL_Type SERCTRL[2]; /**< \brief Offset: 0x20 (R/W 32) Serializer n Control */ |
mbed_official | 579:53297373a894 | 589 | RoReg8 Reserved6[0x8]; |
mbed_official | 579:53297373a894 | 590 | __IO I2S_DATA_Type DATA[2]; /**< \brief Offset: 0x30 (R/W 32) Data n */ |
mbed_official | 579:53297373a894 | 591 | } I2s; |
mbed_official | 579:53297373a894 | 592 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 593 | |
mbed_official | 579:53297373a894 | 594 | /*@}*/ |
mbed_official | 579:53297373a894 | 595 | |
mbed_official | 579:53297373a894 | 596 | #endif /* _SAMD21_I2S_COMPONENT_ */ |