mbed library sources
Fork of mbed-src by
targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_evsys.h@592:a274ee790e56, 2015-07-17 (annotated)
- Committer:
- mbed_official
- Date:
- Fri Jul 17 09:15:10 2015 +0100
- Revision:
- 592:a274ee790e56
- Parent:
- 579:53297373a894
Synchronized with git revision e7144f83a8d75df80c4877936b6ffe552b0be9e6
Full URL: https://github.com/mbedmicro/mbed/commit/e7144f83a8d75df80c4877936b6ffe552b0be9e6/
More API implementation for SAMR21
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 579:53297373a894 | 1 | #ifndef _SAMD21_EVSYS_COMPONENT_ |
mbed_official | 579:53297373a894 | 2 | #define _SAMD21_EVSYS_COMPONENT_ |
mbed_official | 579:53297373a894 | 3 | |
mbed_official | 579:53297373a894 | 4 | /* ========================================================================== */ |
mbed_official | 579:53297373a894 | 5 | /** SOFTWARE API DEFINITION FOR EVSYS */ |
mbed_official | 579:53297373a894 | 6 | /* ========================================================================== */ |
mbed_official | 579:53297373a894 | 7 | /** \addtogroup SAMD21_EVSYS Event System Interface */ |
mbed_official | 579:53297373a894 | 8 | /*@{*/ |
mbed_official | 579:53297373a894 | 9 | |
mbed_official | 579:53297373a894 | 10 | #define EVSYS_U2208 |
mbed_official | 579:53297373a894 | 11 | #define REV_EVSYS 0x101 |
mbed_official | 579:53297373a894 | 12 | |
mbed_official | 579:53297373a894 | 13 | /* -------- EVSYS_CTRL : (EVSYS Offset: 0x00) ( /W 8) Control -------- */ |
mbed_official | 579:53297373a894 | 14 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 15 | typedef union { |
mbed_official | 579:53297373a894 | 16 | struct { |
mbed_official | 579:53297373a894 | 17 | uint8_t SWRST:1; /*!< bit: 0 Software Reset */ |
mbed_official | 579:53297373a894 | 18 | uint8_t :3; /*!< bit: 1.. 3 Reserved */ |
mbed_official | 579:53297373a894 | 19 | uint8_t GCLKREQ:1; /*!< bit: 4 Generic Clock Requests */ |
mbed_official | 579:53297373a894 | 20 | uint8_t :3; /*!< bit: 5.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 21 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 22 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 23 | } EVSYS_CTRL_Type; |
mbed_official | 579:53297373a894 | 24 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 25 | |
mbed_official | 579:53297373a894 | 26 | #define EVSYS_CTRL_OFFSET 0x00 /**< \brief (EVSYS_CTRL offset) Control */ |
mbed_official | 579:53297373a894 | 27 | #define EVSYS_CTRL_RESETVALUE 0x00ul /**< \brief (EVSYS_CTRL reset_value) Control */ |
mbed_official | 579:53297373a894 | 28 | |
mbed_official | 579:53297373a894 | 29 | #define EVSYS_CTRL_SWRST_Pos 0 /**< \brief (EVSYS_CTRL) Software Reset */ |
mbed_official | 579:53297373a894 | 30 | #define EVSYS_CTRL_SWRST (0x1ul << EVSYS_CTRL_SWRST_Pos) |
mbed_official | 579:53297373a894 | 31 | #define EVSYS_CTRL_GCLKREQ_Pos 4 /**< \brief (EVSYS_CTRL) Generic Clock Requests */ |
mbed_official | 579:53297373a894 | 32 | #define EVSYS_CTRL_GCLKREQ (0x1ul << EVSYS_CTRL_GCLKREQ_Pos) |
mbed_official | 579:53297373a894 | 33 | #define EVSYS_CTRL_MASK 0x11ul /**< \brief (EVSYS_CTRL) MASK Register */ |
mbed_official | 579:53297373a894 | 34 | |
mbed_official | 579:53297373a894 | 35 | /* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x04) (R/W 32) Channel -------- */ |
mbed_official | 579:53297373a894 | 36 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 37 | typedef union { |
mbed_official | 579:53297373a894 | 38 | struct { |
mbed_official | 579:53297373a894 | 39 | uint32_t CHANNEL:4; /*!< bit: 0.. 3 Channel Selection */ |
mbed_official | 579:53297373a894 | 40 | uint32_t :4; /*!< bit: 4.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 41 | uint32_t SWEVT:1; /*!< bit: 8 Software Event */ |
mbed_official | 579:53297373a894 | 42 | uint32_t :7; /*!< bit: 9..15 Reserved */ |
mbed_official | 579:53297373a894 | 43 | uint32_t EVGEN:7; /*!< bit: 16..22 Event Generator Selection */ |
mbed_official | 579:53297373a894 | 44 | uint32_t :1; /*!< bit: 23 Reserved */ |
mbed_official | 579:53297373a894 | 45 | uint32_t PATH:2; /*!< bit: 24..25 Path Selection */ |
mbed_official | 579:53297373a894 | 46 | uint32_t EDGSEL:2; /*!< bit: 26..27 Edge Detection Selection */ |
mbed_official | 579:53297373a894 | 47 | uint32_t :4; /*!< bit: 28..31 Reserved */ |
mbed_official | 579:53297373a894 | 48 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 49 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 50 | } EVSYS_CHANNEL_Type; |
mbed_official | 579:53297373a894 | 51 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 52 | |
mbed_official | 579:53297373a894 | 53 | #define EVSYS_CHANNEL_OFFSET 0x04 /**< \brief (EVSYS_CHANNEL offset) Channel */ |
mbed_official | 579:53297373a894 | 54 | #define EVSYS_CHANNEL_RESETVALUE 0x00000000ul /**< \brief (EVSYS_CHANNEL reset_value) Channel */ |
mbed_official | 579:53297373a894 | 55 | |
mbed_official | 579:53297373a894 | 56 | #define EVSYS_CHANNEL_CHANNEL_Pos 0 /**< \brief (EVSYS_CHANNEL) Channel Selection */ |
mbed_official | 579:53297373a894 | 57 | #define EVSYS_CHANNEL_CHANNEL_Msk (0xFul << EVSYS_CHANNEL_CHANNEL_Pos) |
mbed_official | 579:53297373a894 | 58 | #define EVSYS_CHANNEL_CHANNEL(value) ((EVSYS_CHANNEL_CHANNEL_Msk & ((value) << EVSYS_CHANNEL_CHANNEL_Pos))) |
mbed_official | 579:53297373a894 | 59 | #define EVSYS_CHANNEL_SWEVT_Pos 8 /**< \brief (EVSYS_CHANNEL) Software Event */ |
mbed_official | 579:53297373a894 | 60 | #define EVSYS_CHANNEL_SWEVT (0x1ul << EVSYS_CHANNEL_SWEVT_Pos) |
mbed_official | 579:53297373a894 | 61 | #define EVSYS_CHANNEL_EVGEN_Pos 16 /**< \brief (EVSYS_CHANNEL) Event Generator Selection */ |
mbed_official | 579:53297373a894 | 62 | #define EVSYS_CHANNEL_EVGEN_Msk (0x7Ful << EVSYS_CHANNEL_EVGEN_Pos) |
mbed_official | 579:53297373a894 | 63 | #define EVSYS_CHANNEL_EVGEN(value) ((EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos))) |
mbed_official | 579:53297373a894 | 64 | #define EVSYS_CHANNEL_PATH_Pos 24 /**< \brief (EVSYS_CHANNEL) Path Selection */ |
mbed_official | 579:53297373a894 | 65 | #define EVSYS_CHANNEL_PATH_Msk (0x3ul << EVSYS_CHANNEL_PATH_Pos) |
mbed_official | 579:53297373a894 | 66 | #define EVSYS_CHANNEL_PATH(value) ((EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos))) |
mbed_official | 579:53297373a894 | 67 | #define EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val 0x0ul /**< \brief (EVSYS_CHANNEL) Synchronous path */ |
mbed_official | 579:53297373a894 | 68 | #define EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val 0x1ul /**< \brief (EVSYS_CHANNEL) Resynchronized path */ |
mbed_official | 579:53297373a894 | 69 | #define EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val 0x2ul /**< \brief (EVSYS_CHANNEL) Asynchronous path */ |
mbed_official | 579:53297373a894 | 70 | #define EVSYS_CHANNEL_PATH_SYNCHRONOUS (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos) |
mbed_official | 579:53297373a894 | 71 | #define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos) |
mbed_official | 579:53297373a894 | 72 | #define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos) |
mbed_official | 579:53297373a894 | 73 | #define EVSYS_CHANNEL_EDGSEL_Pos 26 /**< \brief (EVSYS_CHANNEL) Edge Detection Selection */ |
mbed_official | 579:53297373a894 | 74 | #define EVSYS_CHANNEL_EDGSEL_Msk (0x3ul << EVSYS_CHANNEL_EDGSEL_Pos) |
mbed_official | 579:53297373a894 | 75 | #define EVSYS_CHANNEL_EDGSEL(value) ((EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos))) |
mbed_official | 579:53297373a894 | 76 | #define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val 0x0ul /**< \brief (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */ |
mbed_official | 579:53297373a894 | 77 | #define EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val 0x1ul /**< \brief (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */ |
mbed_official | 579:53297373a894 | 78 | #define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val 0x2ul /**< \brief (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */ |
mbed_official | 579:53297373a894 | 79 | #define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val 0x3ul /**< \brief (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path */ |
mbed_official | 579:53297373a894 | 80 | #define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos) |
mbed_official | 579:53297373a894 | 81 | #define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos) |
mbed_official | 579:53297373a894 | 82 | #define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos) |
mbed_official | 579:53297373a894 | 83 | #define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos) |
mbed_official | 579:53297373a894 | 84 | #define EVSYS_CHANNEL_MASK 0x0F7F010Ful /**< \brief (EVSYS_CHANNEL) MASK Register */ |
mbed_official | 579:53297373a894 | 85 | |
mbed_official | 579:53297373a894 | 86 | /* -------- EVSYS_USER : (EVSYS Offset: 0x08) (R/W 16) User Multiplexer -------- */ |
mbed_official | 579:53297373a894 | 87 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 88 | typedef union { |
mbed_official | 579:53297373a894 | 89 | struct { |
mbed_official | 579:53297373a894 | 90 | uint16_t USER:5; /*!< bit: 0.. 4 User Multiplexer Selection */ |
mbed_official | 579:53297373a894 | 91 | uint16_t :3; /*!< bit: 5.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 92 | uint16_t CHANNEL:5; /*!< bit: 8..12 Channel Event Selection */ |
mbed_official | 579:53297373a894 | 93 | uint16_t :3; /*!< bit: 13..15 Reserved */ |
mbed_official | 579:53297373a894 | 94 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 95 | uint16_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 96 | } EVSYS_USER_Type; |
mbed_official | 579:53297373a894 | 97 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 98 | |
mbed_official | 579:53297373a894 | 99 | #define EVSYS_USER_OFFSET 0x08 /**< \brief (EVSYS_USER offset) User Multiplexer */ |
mbed_official | 579:53297373a894 | 100 | #define EVSYS_USER_RESETVALUE 0x0000ul /**< \brief (EVSYS_USER reset_value) User Multiplexer */ |
mbed_official | 579:53297373a894 | 101 | |
mbed_official | 579:53297373a894 | 102 | #define EVSYS_USER_USER_Pos 0 /**< \brief (EVSYS_USER) User Multiplexer Selection */ |
mbed_official | 579:53297373a894 | 103 | #define EVSYS_USER_USER_Msk (0x1Ful << EVSYS_USER_USER_Pos) |
mbed_official | 579:53297373a894 | 104 | #define EVSYS_USER_USER(value) ((EVSYS_USER_USER_Msk & ((value) << EVSYS_USER_USER_Pos))) |
mbed_official | 579:53297373a894 | 105 | #define EVSYS_USER_CHANNEL_Pos 8 /**< \brief (EVSYS_USER) Channel Event Selection */ |
mbed_official | 579:53297373a894 | 106 | #define EVSYS_USER_CHANNEL_Msk (0x1Ful << EVSYS_USER_CHANNEL_Pos) |
mbed_official | 579:53297373a894 | 107 | #define EVSYS_USER_CHANNEL(value) ((EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos))) |
mbed_official | 579:53297373a894 | 108 | #define EVSYS_USER_CHANNEL_0_Val 0x0ul /**< \brief (EVSYS_USER) No Channel Output Selected */ |
mbed_official | 579:53297373a894 | 109 | #define EVSYS_USER_CHANNEL_0 (EVSYS_USER_CHANNEL_0_Val << EVSYS_USER_CHANNEL_Pos) |
mbed_official | 579:53297373a894 | 110 | #define EVSYS_USER_MASK 0x1F1Ful /**< \brief (EVSYS_USER) MASK Register */ |
mbed_official | 579:53297373a894 | 111 | |
mbed_official | 579:53297373a894 | 112 | /* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/ 32) Channel Status -------- */ |
mbed_official | 579:53297373a894 | 113 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 114 | typedef union { |
mbed_official | 579:53297373a894 | 115 | struct { |
mbed_official | 579:53297373a894 | 116 | uint32_t USRRDY0:1; /*!< bit: 0 Channel 0 User Ready */ |
mbed_official | 579:53297373a894 | 117 | uint32_t USRRDY1:1; /*!< bit: 1 Channel 1 User Ready */ |
mbed_official | 579:53297373a894 | 118 | uint32_t USRRDY2:1; /*!< bit: 2 Channel 2 User Ready */ |
mbed_official | 579:53297373a894 | 119 | uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */ |
mbed_official | 579:53297373a894 | 120 | uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */ |
mbed_official | 579:53297373a894 | 121 | uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */ |
mbed_official | 579:53297373a894 | 122 | uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */ |
mbed_official | 579:53297373a894 | 123 | uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */ |
mbed_official | 579:53297373a894 | 124 | uint32_t CHBUSY0:1; /*!< bit: 8 Channel 0 Busy */ |
mbed_official | 579:53297373a894 | 125 | uint32_t CHBUSY1:1; /*!< bit: 9 Channel 1 Busy */ |
mbed_official | 579:53297373a894 | 126 | uint32_t CHBUSY2:1; /*!< bit: 10 Channel 2 Busy */ |
mbed_official | 579:53297373a894 | 127 | uint32_t CHBUSY3:1; /*!< bit: 11 Channel 3 Busy */ |
mbed_official | 579:53297373a894 | 128 | uint32_t CHBUSY4:1; /*!< bit: 12 Channel 4 Busy */ |
mbed_official | 579:53297373a894 | 129 | uint32_t CHBUSY5:1; /*!< bit: 13 Channel 5 Busy */ |
mbed_official | 579:53297373a894 | 130 | uint32_t CHBUSY6:1; /*!< bit: 14 Channel 6 Busy */ |
mbed_official | 579:53297373a894 | 131 | uint32_t CHBUSY7:1; /*!< bit: 15 Channel 7 Busy */ |
mbed_official | 579:53297373a894 | 132 | uint32_t USRRDY8:1; /*!< bit: 16 Channel 8 User Ready */ |
mbed_official | 579:53297373a894 | 133 | uint32_t USRRDY9:1; /*!< bit: 17 Channel 9 User Ready */ |
mbed_official | 579:53297373a894 | 134 | uint32_t USRRDY10:1; /*!< bit: 18 Channel 10 User Ready */ |
mbed_official | 579:53297373a894 | 135 | uint32_t USRRDY11:1; /*!< bit: 19 Channel 11 User Ready */ |
mbed_official | 579:53297373a894 | 136 | uint32_t :4; /*!< bit: 20..23 Reserved */ |
mbed_official | 579:53297373a894 | 137 | uint32_t CHBUSY8:1; /*!< bit: 24 Channel 8 Busy */ |
mbed_official | 579:53297373a894 | 138 | uint32_t CHBUSY9:1; /*!< bit: 25 Channel 9 Busy */ |
mbed_official | 579:53297373a894 | 139 | uint32_t CHBUSY10:1; /*!< bit: 26 Channel 10 Busy */ |
mbed_official | 579:53297373a894 | 140 | uint32_t CHBUSY11:1; /*!< bit: 27 Channel 11 Busy */ |
mbed_official | 579:53297373a894 | 141 | uint32_t :4; /*!< bit: 28..31 Reserved */ |
mbed_official | 579:53297373a894 | 142 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 143 | struct { |
mbed_official | 579:53297373a894 | 144 | uint32_t USRRDY:8; /*!< bit: 0.. 7 Channel x User Ready */ |
mbed_official | 579:53297373a894 | 145 | uint32_t CHBUSY:8; /*!< bit: 8..15 Channel x Busy */ |
mbed_official | 579:53297373a894 | 146 | uint32_t USRRDYp8:4; /*!< bit: 16..19 Channel x+8 User Ready */ |
mbed_official | 579:53297373a894 | 147 | uint32_t :4; /*!< bit: 20..23 Reserved */ |
mbed_official | 579:53297373a894 | 148 | uint32_t CHBUSYp8:4; /*!< bit: 24..27 Channel x+8 Busy */ |
mbed_official | 579:53297373a894 | 149 | uint32_t :4; /*!< bit: 28..31 Reserved */ |
mbed_official | 579:53297373a894 | 150 | } vec; /*!< Structure used for vec access */ |
mbed_official | 579:53297373a894 | 151 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 152 | } EVSYS_CHSTATUS_Type; |
mbed_official | 579:53297373a894 | 153 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 154 | |
mbed_official | 579:53297373a894 | 155 | #define EVSYS_CHSTATUS_OFFSET 0x0C /**< \brief (EVSYS_CHSTATUS offset) Channel Status */ |
mbed_official | 579:53297373a894 | 156 | #define EVSYS_CHSTATUS_RESETVALUE 0x000F00FFul /**< \brief (EVSYS_CHSTATUS reset_value) Channel Status */ |
mbed_official | 579:53297373a894 | 157 | |
mbed_official | 579:53297373a894 | 158 | #define EVSYS_CHSTATUS_USRRDY0_Pos 0 /**< \brief (EVSYS_CHSTATUS) Channel 0 User Ready */ |
mbed_official | 579:53297373a894 | 159 | #define EVSYS_CHSTATUS_USRRDY0 (1 << EVSYS_CHSTATUS_USRRDY0_Pos) |
mbed_official | 579:53297373a894 | 160 | #define EVSYS_CHSTATUS_USRRDY1_Pos 1 /**< \brief (EVSYS_CHSTATUS) Channel 1 User Ready */ |
mbed_official | 579:53297373a894 | 161 | #define EVSYS_CHSTATUS_USRRDY1 (1 << EVSYS_CHSTATUS_USRRDY1_Pos) |
mbed_official | 579:53297373a894 | 162 | #define EVSYS_CHSTATUS_USRRDY2_Pos 2 /**< \brief (EVSYS_CHSTATUS) Channel 2 User Ready */ |
mbed_official | 579:53297373a894 | 163 | #define EVSYS_CHSTATUS_USRRDY2 (1 << EVSYS_CHSTATUS_USRRDY2_Pos) |
mbed_official | 579:53297373a894 | 164 | #define EVSYS_CHSTATUS_USRRDY3_Pos 3 /**< \brief (EVSYS_CHSTATUS) Channel 3 User Ready */ |
mbed_official | 579:53297373a894 | 165 | #define EVSYS_CHSTATUS_USRRDY3 (1 << EVSYS_CHSTATUS_USRRDY3_Pos) |
mbed_official | 579:53297373a894 | 166 | #define EVSYS_CHSTATUS_USRRDY4_Pos 4 /**< \brief (EVSYS_CHSTATUS) Channel 4 User Ready */ |
mbed_official | 579:53297373a894 | 167 | #define EVSYS_CHSTATUS_USRRDY4 (1 << EVSYS_CHSTATUS_USRRDY4_Pos) |
mbed_official | 579:53297373a894 | 168 | #define EVSYS_CHSTATUS_USRRDY5_Pos 5 /**< \brief (EVSYS_CHSTATUS) Channel 5 User Ready */ |
mbed_official | 579:53297373a894 | 169 | #define EVSYS_CHSTATUS_USRRDY5 (1 << EVSYS_CHSTATUS_USRRDY5_Pos) |
mbed_official | 579:53297373a894 | 170 | #define EVSYS_CHSTATUS_USRRDY6_Pos 6 /**< \brief (EVSYS_CHSTATUS) Channel 6 User Ready */ |
mbed_official | 579:53297373a894 | 171 | #define EVSYS_CHSTATUS_USRRDY6 (1 << EVSYS_CHSTATUS_USRRDY6_Pos) |
mbed_official | 579:53297373a894 | 172 | #define EVSYS_CHSTATUS_USRRDY7_Pos 7 /**< \brief (EVSYS_CHSTATUS) Channel 7 User Ready */ |
mbed_official | 579:53297373a894 | 173 | #define EVSYS_CHSTATUS_USRRDY7 (1 << EVSYS_CHSTATUS_USRRDY7_Pos) |
mbed_official | 579:53297373a894 | 174 | #define EVSYS_CHSTATUS_USRRDY_Pos 0 /**< \brief (EVSYS_CHSTATUS) Channel x User Ready */ |
mbed_official | 579:53297373a894 | 175 | #define EVSYS_CHSTATUS_USRRDY_Msk (0xFFul << EVSYS_CHSTATUS_USRRDY_Pos) |
mbed_official | 579:53297373a894 | 176 | #define EVSYS_CHSTATUS_USRRDY(value) ((EVSYS_CHSTATUS_USRRDY_Msk & ((value) << EVSYS_CHSTATUS_USRRDY_Pos))) |
mbed_official | 579:53297373a894 | 177 | #define EVSYS_CHSTATUS_CHBUSY0_Pos 8 /**< \brief (EVSYS_CHSTATUS) Channel 0 Busy */ |
mbed_official | 579:53297373a894 | 178 | #define EVSYS_CHSTATUS_CHBUSY0 (1 << EVSYS_CHSTATUS_CHBUSY0_Pos) |
mbed_official | 579:53297373a894 | 179 | #define EVSYS_CHSTATUS_CHBUSY1_Pos 9 /**< \brief (EVSYS_CHSTATUS) Channel 1 Busy */ |
mbed_official | 579:53297373a894 | 180 | #define EVSYS_CHSTATUS_CHBUSY1 (1 << EVSYS_CHSTATUS_CHBUSY1_Pos) |
mbed_official | 579:53297373a894 | 181 | #define EVSYS_CHSTATUS_CHBUSY2_Pos 10 /**< \brief (EVSYS_CHSTATUS) Channel 2 Busy */ |
mbed_official | 579:53297373a894 | 182 | #define EVSYS_CHSTATUS_CHBUSY2 (1 << EVSYS_CHSTATUS_CHBUSY2_Pos) |
mbed_official | 579:53297373a894 | 183 | #define EVSYS_CHSTATUS_CHBUSY3_Pos 11 /**< \brief (EVSYS_CHSTATUS) Channel 3 Busy */ |
mbed_official | 579:53297373a894 | 184 | #define EVSYS_CHSTATUS_CHBUSY3 (1 << EVSYS_CHSTATUS_CHBUSY3_Pos) |
mbed_official | 579:53297373a894 | 185 | #define EVSYS_CHSTATUS_CHBUSY4_Pos 12 /**< \brief (EVSYS_CHSTATUS) Channel 4 Busy */ |
mbed_official | 579:53297373a894 | 186 | #define EVSYS_CHSTATUS_CHBUSY4 (1 << EVSYS_CHSTATUS_CHBUSY4_Pos) |
mbed_official | 579:53297373a894 | 187 | #define EVSYS_CHSTATUS_CHBUSY5_Pos 13 /**< \brief (EVSYS_CHSTATUS) Channel 5 Busy */ |
mbed_official | 579:53297373a894 | 188 | #define EVSYS_CHSTATUS_CHBUSY5 (1 << EVSYS_CHSTATUS_CHBUSY5_Pos) |
mbed_official | 579:53297373a894 | 189 | #define EVSYS_CHSTATUS_CHBUSY6_Pos 14 /**< \brief (EVSYS_CHSTATUS) Channel 6 Busy */ |
mbed_official | 579:53297373a894 | 190 | #define EVSYS_CHSTATUS_CHBUSY6 (1 << EVSYS_CHSTATUS_CHBUSY6_Pos) |
mbed_official | 579:53297373a894 | 191 | #define EVSYS_CHSTATUS_CHBUSY7_Pos 15 /**< \brief (EVSYS_CHSTATUS) Channel 7 Busy */ |
mbed_official | 579:53297373a894 | 192 | #define EVSYS_CHSTATUS_CHBUSY7 (1 << EVSYS_CHSTATUS_CHBUSY7_Pos) |
mbed_official | 579:53297373a894 | 193 | #define EVSYS_CHSTATUS_CHBUSY_Pos 8 /**< \brief (EVSYS_CHSTATUS) Channel x Busy */ |
mbed_official | 579:53297373a894 | 194 | #define EVSYS_CHSTATUS_CHBUSY_Msk (0xFFul << EVSYS_CHSTATUS_CHBUSY_Pos) |
mbed_official | 579:53297373a894 | 195 | #define EVSYS_CHSTATUS_CHBUSY(value) ((EVSYS_CHSTATUS_CHBUSY_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY_Pos))) |
mbed_official | 579:53297373a894 | 196 | #define EVSYS_CHSTATUS_USRRDY8_Pos 16 /**< \brief (EVSYS_CHSTATUS) Channel 8 User Ready */ |
mbed_official | 579:53297373a894 | 197 | #define EVSYS_CHSTATUS_USRRDY8 (1 << EVSYS_CHSTATUS_USRRDY8_Pos) |
mbed_official | 579:53297373a894 | 198 | #define EVSYS_CHSTATUS_USRRDY9_Pos 17 /**< \brief (EVSYS_CHSTATUS) Channel 9 User Ready */ |
mbed_official | 579:53297373a894 | 199 | #define EVSYS_CHSTATUS_USRRDY9 (1 << EVSYS_CHSTATUS_USRRDY9_Pos) |
mbed_official | 579:53297373a894 | 200 | #define EVSYS_CHSTATUS_USRRDY10_Pos 18 /**< \brief (EVSYS_CHSTATUS) Channel 10 User Ready */ |
mbed_official | 579:53297373a894 | 201 | #define EVSYS_CHSTATUS_USRRDY10 (1 << EVSYS_CHSTATUS_USRRDY10_Pos) |
mbed_official | 579:53297373a894 | 202 | #define EVSYS_CHSTATUS_USRRDY11_Pos 19 /**< \brief (EVSYS_CHSTATUS) Channel 11 User Ready */ |
mbed_official | 579:53297373a894 | 203 | #define EVSYS_CHSTATUS_USRRDY11 (1 << EVSYS_CHSTATUS_USRRDY11_Pos) |
mbed_official | 579:53297373a894 | 204 | #define EVSYS_CHSTATUS_USRRDYp8_Pos 16 /**< \brief (EVSYS_CHSTATUS) Channel x+8 User Ready */ |
mbed_official | 579:53297373a894 | 205 | #define EVSYS_CHSTATUS_USRRDYp8_Msk (0xFul << EVSYS_CHSTATUS_USRRDYp8_Pos) |
mbed_official | 579:53297373a894 | 206 | #define EVSYS_CHSTATUS_USRRDYp8(value) ((EVSYS_CHSTATUS_USRRDYp8_Msk & ((value) << EVSYS_CHSTATUS_USRRDYp8_Pos))) |
mbed_official | 579:53297373a894 | 207 | #define EVSYS_CHSTATUS_CHBUSY8_Pos 24 /**< \brief (EVSYS_CHSTATUS) Channel 8 Busy */ |
mbed_official | 579:53297373a894 | 208 | #define EVSYS_CHSTATUS_CHBUSY8 (1 << EVSYS_CHSTATUS_CHBUSY8_Pos) |
mbed_official | 579:53297373a894 | 209 | #define EVSYS_CHSTATUS_CHBUSY9_Pos 25 /**< \brief (EVSYS_CHSTATUS) Channel 9 Busy */ |
mbed_official | 579:53297373a894 | 210 | #define EVSYS_CHSTATUS_CHBUSY9 (1 << EVSYS_CHSTATUS_CHBUSY9_Pos) |
mbed_official | 579:53297373a894 | 211 | #define EVSYS_CHSTATUS_CHBUSY10_Pos 26 /**< \brief (EVSYS_CHSTATUS) Channel 10 Busy */ |
mbed_official | 579:53297373a894 | 212 | #define EVSYS_CHSTATUS_CHBUSY10 (1 << EVSYS_CHSTATUS_CHBUSY10_Pos) |
mbed_official | 579:53297373a894 | 213 | #define EVSYS_CHSTATUS_CHBUSY11_Pos 27 /**< \brief (EVSYS_CHSTATUS) Channel 11 Busy */ |
mbed_official | 579:53297373a894 | 214 | #define EVSYS_CHSTATUS_CHBUSY11 (1 << EVSYS_CHSTATUS_CHBUSY11_Pos) |
mbed_official | 579:53297373a894 | 215 | #define EVSYS_CHSTATUS_CHBUSYp8_Pos 24 /**< \brief (EVSYS_CHSTATUS) Channel x+8 Busy */ |
mbed_official | 579:53297373a894 | 216 | #define EVSYS_CHSTATUS_CHBUSYp8_Msk (0xFul << EVSYS_CHSTATUS_CHBUSYp8_Pos) |
mbed_official | 579:53297373a894 | 217 | #define EVSYS_CHSTATUS_CHBUSYp8(value) ((EVSYS_CHSTATUS_CHBUSYp8_Msk & ((value) << EVSYS_CHSTATUS_CHBUSYp8_Pos))) |
mbed_official | 579:53297373a894 | 218 | #define EVSYS_CHSTATUS_MASK 0x0F0FFFFFul /**< \brief (EVSYS_CHSTATUS) MASK Register */ |
mbed_official | 579:53297373a894 | 219 | |
mbed_official | 579:53297373a894 | 220 | /* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */ |
mbed_official | 579:53297373a894 | 221 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 222 | typedef union { |
mbed_official | 579:53297373a894 | 223 | struct { |
mbed_official | 579:53297373a894 | 224 | uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 225 | uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 226 | uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 227 | uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 228 | uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 229 | uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 230 | uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 231 | uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 232 | uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 233 | uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 234 | uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 235 | uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 236 | uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 237 | uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 238 | uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 239 | uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 240 | uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 241 | uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 242 | uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 243 | uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 244 | uint32_t :4; /*!< bit: 20..23 Reserved */ |
mbed_official | 579:53297373a894 | 245 | uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 246 | uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 247 | uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 248 | uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 249 | uint32_t :4; /*!< bit: 28..31 Reserved */ |
mbed_official | 579:53297373a894 | 250 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 251 | struct { |
mbed_official | 579:53297373a894 | 252 | uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 253 | uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 254 | uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 255 | uint32_t :4; /*!< bit: 20..23 Reserved */ |
mbed_official | 579:53297373a894 | 256 | uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 257 | uint32_t :4; /*!< bit: 28..31 Reserved */ |
mbed_official | 579:53297373a894 | 258 | } vec; /*!< Structure used for vec access */ |
mbed_official | 579:53297373a894 | 259 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 260 | } EVSYS_INTENCLR_Type; |
mbed_official | 579:53297373a894 | 261 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 262 | |
mbed_official | 579:53297373a894 | 263 | #define EVSYS_INTENCLR_OFFSET 0x10 /**< \brief (EVSYS_INTENCLR offset) Interrupt Enable Clear */ |
mbed_official | 579:53297373a894 | 264 | #define EVSYS_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (EVSYS_INTENCLR reset_value) Interrupt Enable Clear */ |
mbed_official | 579:53297373a894 | 265 | |
mbed_official | 579:53297373a894 | 266 | #define EVSYS_INTENCLR_OVR0_Pos 0 /**< \brief (EVSYS_INTENCLR) Channel 0 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 267 | #define EVSYS_INTENCLR_OVR0 (1 << EVSYS_INTENCLR_OVR0_Pos) |
mbed_official | 579:53297373a894 | 268 | #define EVSYS_INTENCLR_OVR1_Pos 1 /**< \brief (EVSYS_INTENCLR) Channel 1 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 269 | #define EVSYS_INTENCLR_OVR1 (1 << EVSYS_INTENCLR_OVR1_Pos) |
mbed_official | 579:53297373a894 | 270 | #define EVSYS_INTENCLR_OVR2_Pos 2 /**< \brief (EVSYS_INTENCLR) Channel 2 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 271 | #define EVSYS_INTENCLR_OVR2 (1 << EVSYS_INTENCLR_OVR2_Pos) |
mbed_official | 579:53297373a894 | 272 | #define EVSYS_INTENCLR_OVR3_Pos 3 /**< \brief (EVSYS_INTENCLR) Channel 3 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 273 | #define EVSYS_INTENCLR_OVR3 (1 << EVSYS_INTENCLR_OVR3_Pos) |
mbed_official | 579:53297373a894 | 274 | #define EVSYS_INTENCLR_OVR4_Pos 4 /**< \brief (EVSYS_INTENCLR) Channel 4 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 275 | #define EVSYS_INTENCLR_OVR4 (1 << EVSYS_INTENCLR_OVR4_Pos) |
mbed_official | 579:53297373a894 | 276 | #define EVSYS_INTENCLR_OVR5_Pos 5 /**< \brief (EVSYS_INTENCLR) Channel 5 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 277 | #define EVSYS_INTENCLR_OVR5 (1 << EVSYS_INTENCLR_OVR5_Pos) |
mbed_official | 579:53297373a894 | 278 | #define EVSYS_INTENCLR_OVR6_Pos 6 /**< \brief (EVSYS_INTENCLR) Channel 6 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 279 | #define EVSYS_INTENCLR_OVR6 (1 << EVSYS_INTENCLR_OVR6_Pos) |
mbed_official | 579:53297373a894 | 280 | #define EVSYS_INTENCLR_OVR7_Pos 7 /**< \brief (EVSYS_INTENCLR) Channel 7 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 281 | #define EVSYS_INTENCLR_OVR7 (1 << EVSYS_INTENCLR_OVR7_Pos) |
mbed_official | 579:53297373a894 | 282 | #define EVSYS_INTENCLR_OVR_Pos 0 /**< \brief (EVSYS_INTENCLR) Channel x Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 283 | #define EVSYS_INTENCLR_OVR_Msk (0xFFul << EVSYS_INTENCLR_OVR_Pos) |
mbed_official | 579:53297373a894 | 284 | #define EVSYS_INTENCLR_OVR(value) ((EVSYS_INTENCLR_OVR_Msk & ((value) << EVSYS_INTENCLR_OVR_Pos))) |
mbed_official | 579:53297373a894 | 285 | #define EVSYS_INTENCLR_EVD0_Pos 8 /**< \brief (EVSYS_INTENCLR) Channel 0 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 286 | #define EVSYS_INTENCLR_EVD0 (1 << EVSYS_INTENCLR_EVD0_Pos) |
mbed_official | 579:53297373a894 | 287 | #define EVSYS_INTENCLR_EVD1_Pos 9 /**< \brief (EVSYS_INTENCLR) Channel 1 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 288 | #define EVSYS_INTENCLR_EVD1 (1 << EVSYS_INTENCLR_EVD1_Pos) |
mbed_official | 579:53297373a894 | 289 | #define EVSYS_INTENCLR_EVD2_Pos 10 /**< \brief (EVSYS_INTENCLR) Channel 2 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 290 | #define EVSYS_INTENCLR_EVD2 (1 << EVSYS_INTENCLR_EVD2_Pos) |
mbed_official | 579:53297373a894 | 291 | #define EVSYS_INTENCLR_EVD3_Pos 11 /**< \brief (EVSYS_INTENCLR) Channel 3 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 292 | #define EVSYS_INTENCLR_EVD3 (1 << EVSYS_INTENCLR_EVD3_Pos) |
mbed_official | 579:53297373a894 | 293 | #define EVSYS_INTENCLR_EVD4_Pos 12 /**< \brief (EVSYS_INTENCLR) Channel 4 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 294 | #define EVSYS_INTENCLR_EVD4 (1 << EVSYS_INTENCLR_EVD4_Pos) |
mbed_official | 579:53297373a894 | 295 | #define EVSYS_INTENCLR_EVD5_Pos 13 /**< \brief (EVSYS_INTENCLR) Channel 5 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 296 | #define EVSYS_INTENCLR_EVD5 (1 << EVSYS_INTENCLR_EVD5_Pos) |
mbed_official | 579:53297373a894 | 297 | #define EVSYS_INTENCLR_EVD6_Pos 14 /**< \brief (EVSYS_INTENCLR) Channel 6 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 298 | #define EVSYS_INTENCLR_EVD6 (1 << EVSYS_INTENCLR_EVD6_Pos) |
mbed_official | 579:53297373a894 | 299 | #define EVSYS_INTENCLR_EVD7_Pos 15 /**< \brief (EVSYS_INTENCLR) Channel 7 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 300 | #define EVSYS_INTENCLR_EVD7 (1 << EVSYS_INTENCLR_EVD7_Pos) |
mbed_official | 579:53297373a894 | 301 | #define EVSYS_INTENCLR_EVD_Pos 8 /**< \brief (EVSYS_INTENCLR) Channel x Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 302 | #define EVSYS_INTENCLR_EVD_Msk (0xFFul << EVSYS_INTENCLR_EVD_Pos) |
mbed_official | 579:53297373a894 | 303 | #define EVSYS_INTENCLR_EVD(value) ((EVSYS_INTENCLR_EVD_Msk & ((value) << EVSYS_INTENCLR_EVD_Pos))) |
mbed_official | 579:53297373a894 | 304 | #define EVSYS_INTENCLR_OVR8_Pos 16 /**< \brief (EVSYS_INTENCLR) Channel 8 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 305 | #define EVSYS_INTENCLR_OVR8 (1 << EVSYS_INTENCLR_OVR8_Pos) |
mbed_official | 579:53297373a894 | 306 | #define EVSYS_INTENCLR_OVR9_Pos 17 /**< \brief (EVSYS_INTENCLR) Channel 9 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 307 | #define EVSYS_INTENCLR_OVR9 (1 << EVSYS_INTENCLR_OVR9_Pos) |
mbed_official | 579:53297373a894 | 308 | #define EVSYS_INTENCLR_OVR10_Pos 18 /**< \brief (EVSYS_INTENCLR) Channel 10 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 309 | #define EVSYS_INTENCLR_OVR10 (1 << EVSYS_INTENCLR_OVR10_Pos) |
mbed_official | 579:53297373a894 | 310 | #define EVSYS_INTENCLR_OVR11_Pos 19 /**< \brief (EVSYS_INTENCLR) Channel 11 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 311 | #define EVSYS_INTENCLR_OVR11 (1 << EVSYS_INTENCLR_OVR11_Pos) |
mbed_official | 579:53297373a894 | 312 | #define EVSYS_INTENCLR_OVRp8_Pos 16 /**< \brief (EVSYS_INTENCLR) Channel x+8 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 313 | #define EVSYS_INTENCLR_OVRp8_Msk (0xFul << EVSYS_INTENCLR_OVRp8_Pos) |
mbed_official | 579:53297373a894 | 314 | #define EVSYS_INTENCLR_OVRp8(value) ((EVSYS_INTENCLR_OVRp8_Msk & ((value) << EVSYS_INTENCLR_OVRp8_Pos))) |
mbed_official | 579:53297373a894 | 315 | #define EVSYS_INTENCLR_EVD8_Pos 24 /**< \brief (EVSYS_INTENCLR) Channel 8 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 316 | #define EVSYS_INTENCLR_EVD8 (1 << EVSYS_INTENCLR_EVD8_Pos) |
mbed_official | 579:53297373a894 | 317 | #define EVSYS_INTENCLR_EVD9_Pos 25 /**< \brief (EVSYS_INTENCLR) Channel 9 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 318 | #define EVSYS_INTENCLR_EVD9 (1 << EVSYS_INTENCLR_EVD9_Pos) |
mbed_official | 579:53297373a894 | 319 | #define EVSYS_INTENCLR_EVD10_Pos 26 /**< \brief (EVSYS_INTENCLR) Channel 10 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 320 | #define EVSYS_INTENCLR_EVD10 (1 << EVSYS_INTENCLR_EVD10_Pos) |
mbed_official | 579:53297373a894 | 321 | #define EVSYS_INTENCLR_EVD11_Pos 27 /**< \brief (EVSYS_INTENCLR) Channel 11 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 322 | #define EVSYS_INTENCLR_EVD11 (1 << EVSYS_INTENCLR_EVD11_Pos) |
mbed_official | 579:53297373a894 | 323 | #define EVSYS_INTENCLR_EVDp8_Pos 24 /**< \brief (EVSYS_INTENCLR) Channel x+8 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 324 | #define EVSYS_INTENCLR_EVDp8_Msk (0xFul << EVSYS_INTENCLR_EVDp8_Pos) |
mbed_official | 579:53297373a894 | 325 | #define EVSYS_INTENCLR_EVDp8(value) ((EVSYS_INTENCLR_EVDp8_Msk & ((value) << EVSYS_INTENCLR_EVDp8_Pos))) |
mbed_official | 579:53297373a894 | 326 | #define EVSYS_INTENCLR_MASK 0x0F0FFFFFul /**< \brief (EVSYS_INTENCLR) MASK Register */ |
mbed_official | 579:53297373a894 | 327 | |
mbed_official | 579:53297373a894 | 328 | /* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */ |
mbed_official | 579:53297373a894 | 329 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 330 | typedef union { |
mbed_official | 579:53297373a894 | 331 | struct { |
mbed_official | 579:53297373a894 | 332 | uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 333 | uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 334 | uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 335 | uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 336 | uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 337 | uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 338 | uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 339 | uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 340 | uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 341 | uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 342 | uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 343 | uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 344 | uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 345 | uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 346 | uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 347 | uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 348 | uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 349 | uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 350 | uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 351 | uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 352 | uint32_t :4; /*!< bit: 20..23 Reserved */ |
mbed_official | 579:53297373a894 | 353 | uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 354 | uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 355 | uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 356 | uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 357 | uint32_t :4; /*!< bit: 28..31 Reserved */ |
mbed_official | 579:53297373a894 | 358 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 359 | struct { |
mbed_official | 579:53297373a894 | 360 | uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 361 | uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 362 | uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 363 | uint32_t :4; /*!< bit: 20..23 Reserved */ |
mbed_official | 579:53297373a894 | 364 | uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 365 | uint32_t :4; /*!< bit: 28..31 Reserved */ |
mbed_official | 579:53297373a894 | 366 | } vec; /*!< Structure used for vec access */ |
mbed_official | 579:53297373a894 | 367 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 368 | } EVSYS_INTENSET_Type; |
mbed_official | 579:53297373a894 | 369 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 370 | |
mbed_official | 579:53297373a894 | 371 | #define EVSYS_INTENSET_OFFSET 0x14 /**< \brief (EVSYS_INTENSET offset) Interrupt Enable Set */ |
mbed_official | 579:53297373a894 | 372 | #define EVSYS_INTENSET_RESETVALUE 0x00000000ul /**< \brief (EVSYS_INTENSET reset_value) Interrupt Enable Set */ |
mbed_official | 579:53297373a894 | 373 | |
mbed_official | 579:53297373a894 | 374 | #define EVSYS_INTENSET_OVR0_Pos 0 /**< \brief (EVSYS_INTENSET) Channel 0 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 375 | #define EVSYS_INTENSET_OVR0 (1 << EVSYS_INTENSET_OVR0_Pos) |
mbed_official | 579:53297373a894 | 376 | #define EVSYS_INTENSET_OVR1_Pos 1 /**< \brief (EVSYS_INTENSET) Channel 1 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 377 | #define EVSYS_INTENSET_OVR1 (1 << EVSYS_INTENSET_OVR1_Pos) |
mbed_official | 579:53297373a894 | 378 | #define EVSYS_INTENSET_OVR2_Pos 2 /**< \brief (EVSYS_INTENSET) Channel 2 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 379 | #define EVSYS_INTENSET_OVR2 (1 << EVSYS_INTENSET_OVR2_Pos) |
mbed_official | 579:53297373a894 | 380 | #define EVSYS_INTENSET_OVR3_Pos 3 /**< \brief (EVSYS_INTENSET) Channel 3 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 381 | #define EVSYS_INTENSET_OVR3 (1 << EVSYS_INTENSET_OVR3_Pos) |
mbed_official | 579:53297373a894 | 382 | #define EVSYS_INTENSET_OVR4_Pos 4 /**< \brief (EVSYS_INTENSET) Channel 4 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 383 | #define EVSYS_INTENSET_OVR4 (1 << EVSYS_INTENSET_OVR4_Pos) |
mbed_official | 579:53297373a894 | 384 | #define EVSYS_INTENSET_OVR5_Pos 5 /**< \brief (EVSYS_INTENSET) Channel 5 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 385 | #define EVSYS_INTENSET_OVR5 (1 << EVSYS_INTENSET_OVR5_Pos) |
mbed_official | 579:53297373a894 | 386 | #define EVSYS_INTENSET_OVR6_Pos 6 /**< \brief (EVSYS_INTENSET) Channel 6 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 387 | #define EVSYS_INTENSET_OVR6 (1 << EVSYS_INTENSET_OVR6_Pos) |
mbed_official | 579:53297373a894 | 388 | #define EVSYS_INTENSET_OVR7_Pos 7 /**< \brief (EVSYS_INTENSET) Channel 7 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 389 | #define EVSYS_INTENSET_OVR7 (1 << EVSYS_INTENSET_OVR7_Pos) |
mbed_official | 579:53297373a894 | 390 | #define EVSYS_INTENSET_OVR_Pos 0 /**< \brief (EVSYS_INTENSET) Channel x Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 391 | #define EVSYS_INTENSET_OVR_Msk (0xFFul << EVSYS_INTENSET_OVR_Pos) |
mbed_official | 579:53297373a894 | 392 | #define EVSYS_INTENSET_OVR(value) ((EVSYS_INTENSET_OVR_Msk & ((value) << EVSYS_INTENSET_OVR_Pos))) |
mbed_official | 579:53297373a894 | 393 | #define EVSYS_INTENSET_EVD0_Pos 8 /**< \brief (EVSYS_INTENSET) Channel 0 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 394 | #define EVSYS_INTENSET_EVD0 (1 << EVSYS_INTENSET_EVD0_Pos) |
mbed_official | 579:53297373a894 | 395 | #define EVSYS_INTENSET_EVD1_Pos 9 /**< \brief (EVSYS_INTENSET) Channel 1 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 396 | #define EVSYS_INTENSET_EVD1 (1 << EVSYS_INTENSET_EVD1_Pos) |
mbed_official | 579:53297373a894 | 397 | #define EVSYS_INTENSET_EVD2_Pos 10 /**< \brief (EVSYS_INTENSET) Channel 2 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 398 | #define EVSYS_INTENSET_EVD2 (1 << EVSYS_INTENSET_EVD2_Pos) |
mbed_official | 579:53297373a894 | 399 | #define EVSYS_INTENSET_EVD3_Pos 11 /**< \brief (EVSYS_INTENSET) Channel 3 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 400 | #define EVSYS_INTENSET_EVD3 (1 << EVSYS_INTENSET_EVD3_Pos) |
mbed_official | 579:53297373a894 | 401 | #define EVSYS_INTENSET_EVD4_Pos 12 /**< \brief (EVSYS_INTENSET) Channel 4 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 402 | #define EVSYS_INTENSET_EVD4 (1 << EVSYS_INTENSET_EVD4_Pos) |
mbed_official | 579:53297373a894 | 403 | #define EVSYS_INTENSET_EVD5_Pos 13 /**< \brief (EVSYS_INTENSET) Channel 5 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 404 | #define EVSYS_INTENSET_EVD5 (1 << EVSYS_INTENSET_EVD5_Pos) |
mbed_official | 579:53297373a894 | 405 | #define EVSYS_INTENSET_EVD6_Pos 14 /**< \brief (EVSYS_INTENSET) Channel 6 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 406 | #define EVSYS_INTENSET_EVD6 (1 << EVSYS_INTENSET_EVD6_Pos) |
mbed_official | 579:53297373a894 | 407 | #define EVSYS_INTENSET_EVD7_Pos 15 /**< \brief (EVSYS_INTENSET) Channel 7 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 408 | #define EVSYS_INTENSET_EVD7 (1 << EVSYS_INTENSET_EVD7_Pos) |
mbed_official | 579:53297373a894 | 409 | #define EVSYS_INTENSET_EVD_Pos 8 /**< \brief (EVSYS_INTENSET) Channel x Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 410 | #define EVSYS_INTENSET_EVD_Msk (0xFFul << EVSYS_INTENSET_EVD_Pos) |
mbed_official | 579:53297373a894 | 411 | #define EVSYS_INTENSET_EVD(value) ((EVSYS_INTENSET_EVD_Msk & ((value) << EVSYS_INTENSET_EVD_Pos))) |
mbed_official | 579:53297373a894 | 412 | #define EVSYS_INTENSET_OVR8_Pos 16 /**< \brief (EVSYS_INTENSET) Channel 8 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 413 | #define EVSYS_INTENSET_OVR8 (1 << EVSYS_INTENSET_OVR8_Pos) |
mbed_official | 579:53297373a894 | 414 | #define EVSYS_INTENSET_OVR9_Pos 17 /**< \brief (EVSYS_INTENSET) Channel 9 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 415 | #define EVSYS_INTENSET_OVR9 (1 << EVSYS_INTENSET_OVR9_Pos) |
mbed_official | 579:53297373a894 | 416 | #define EVSYS_INTENSET_OVR10_Pos 18 /**< \brief (EVSYS_INTENSET) Channel 10 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 417 | #define EVSYS_INTENSET_OVR10 (1 << EVSYS_INTENSET_OVR10_Pos) |
mbed_official | 579:53297373a894 | 418 | #define EVSYS_INTENSET_OVR11_Pos 19 /**< \brief (EVSYS_INTENSET) Channel 11 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 419 | #define EVSYS_INTENSET_OVR11 (1 << EVSYS_INTENSET_OVR11_Pos) |
mbed_official | 579:53297373a894 | 420 | #define EVSYS_INTENSET_OVRp8_Pos 16 /**< \brief (EVSYS_INTENSET) Channel x+8 Overrun Interrupt Enable */ |
mbed_official | 579:53297373a894 | 421 | #define EVSYS_INTENSET_OVRp8_Msk (0xFul << EVSYS_INTENSET_OVRp8_Pos) |
mbed_official | 579:53297373a894 | 422 | #define EVSYS_INTENSET_OVRp8(value) ((EVSYS_INTENSET_OVRp8_Msk & ((value) << EVSYS_INTENSET_OVRp8_Pos))) |
mbed_official | 579:53297373a894 | 423 | #define EVSYS_INTENSET_EVD8_Pos 24 /**< \brief (EVSYS_INTENSET) Channel 8 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 424 | #define EVSYS_INTENSET_EVD8 (1 << EVSYS_INTENSET_EVD8_Pos) |
mbed_official | 579:53297373a894 | 425 | #define EVSYS_INTENSET_EVD9_Pos 25 /**< \brief (EVSYS_INTENSET) Channel 9 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 426 | #define EVSYS_INTENSET_EVD9 (1 << EVSYS_INTENSET_EVD9_Pos) |
mbed_official | 579:53297373a894 | 427 | #define EVSYS_INTENSET_EVD10_Pos 26 /**< \brief (EVSYS_INTENSET) Channel 10 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 428 | #define EVSYS_INTENSET_EVD10 (1 << EVSYS_INTENSET_EVD10_Pos) |
mbed_official | 579:53297373a894 | 429 | #define EVSYS_INTENSET_EVD11_Pos 27 /**< \brief (EVSYS_INTENSET) Channel 11 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 430 | #define EVSYS_INTENSET_EVD11 (1 << EVSYS_INTENSET_EVD11_Pos) |
mbed_official | 579:53297373a894 | 431 | #define EVSYS_INTENSET_EVDp8_Pos 24 /**< \brief (EVSYS_INTENSET) Channel x+8 Event Detection Interrupt Enable */ |
mbed_official | 579:53297373a894 | 432 | #define EVSYS_INTENSET_EVDp8_Msk (0xFul << EVSYS_INTENSET_EVDp8_Pos) |
mbed_official | 579:53297373a894 | 433 | #define EVSYS_INTENSET_EVDp8(value) ((EVSYS_INTENSET_EVDp8_Msk & ((value) << EVSYS_INTENSET_EVDp8_Pos))) |
mbed_official | 579:53297373a894 | 434 | #define EVSYS_INTENSET_MASK 0x0F0FFFFFul /**< \brief (EVSYS_INTENSET) MASK Register */ |
mbed_official | 579:53297373a894 | 435 | |
mbed_official | 579:53297373a894 | 436 | /* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */ |
mbed_official | 579:53297373a894 | 437 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 438 | typedef union { |
mbed_official | 579:53297373a894 | 439 | struct { |
mbed_official | 579:53297373a894 | 440 | uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */ |
mbed_official | 579:53297373a894 | 441 | uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */ |
mbed_official | 579:53297373a894 | 442 | uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */ |
mbed_official | 579:53297373a894 | 443 | uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */ |
mbed_official | 579:53297373a894 | 444 | uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */ |
mbed_official | 579:53297373a894 | 445 | uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */ |
mbed_official | 579:53297373a894 | 446 | uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */ |
mbed_official | 579:53297373a894 | 447 | uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */ |
mbed_official | 579:53297373a894 | 448 | uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection */ |
mbed_official | 579:53297373a894 | 449 | uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection */ |
mbed_official | 579:53297373a894 | 450 | uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection */ |
mbed_official | 579:53297373a894 | 451 | uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection */ |
mbed_official | 579:53297373a894 | 452 | uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection */ |
mbed_official | 579:53297373a894 | 453 | uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection */ |
mbed_official | 579:53297373a894 | 454 | uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection */ |
mbed_official | 579:53297373a894 | 455 | uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection */ |
mbed_official | 579:53297373a894 | 456 | uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun */ |
mbed_official | 579:53297373a894 | 457 | uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun */ |
mbed_official | 579:53297373a894 | 458 | uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun */ |
mbed_official | 579:53297373a894 | 459 | uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun */ |
mbed_official | 579:53297373a894 | 460 | uint32_t :4; /*!< bit: 20..23 Reserved */ |
mbed_official | 579:53297373a894 | 461 | uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */ |
mbed_official | 579:53297373a894 | 462 | uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */ |
mbed_official | 579:53297373a894 | 463 | uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */ |
mbed_official | 579:53297373a894 | 464 | uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */ |
mbed_official | 579:53297373a894 | 465 | uint32_t :4; /*!< bit: 28..31 Reserved */ |
mbed_official | 579:53297373a894 | 466 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 467 | struct { |
mbed_official | 579:53297373a894 | 468 | uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun */ |
mbed_official | 579:53297373a894 | 469 | uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection */ |
mbed_official | 579:53297373a894 | 470 | uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun */ |
mbed_official | 579:53297373a894 | 471 | uint32_t :4; /*!< bit: 20..23 Reserved */ |
mbed_official | 579:53297373a894 | 472 | uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection */ |
mbed_official | 579:53297373a894 | 473 | uint32_t :4; /*!< bit: 28..31 Reserved */ |
mbed_official | 579:53297373a894 | 474 | } vec; /*!< Structure used for vec access */ |
mbed_official | 579:53297373a894 | 475 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 476 | } EVSYS_INTFLAG_Type; |
mbed_official | 579:53297373a894 | 477 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 478 | |
mbed_official | 579:53297373a894 | 479 | #define EVSYS_INTFLAG_OFFSET 0x18 /**< \brief (EVSYS_INTFLAG offset) Interrupt Flag Status and Clear */ |
mbed_official | 579:53297373a894 | 480 | #define EVSYS_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (EVSYS_INTFLAG reset_value) Interrupt Flag Status and Clear */ |
mbed_official | 579:53297373a894 | 481 | |
mbed_official | 579:53297373a894 | 482 | #define EVSYS_INTFLAG_OVR0_Pos 0 /**< \brief (EVSYS_INTFLAG) Channel 0 Overrun */ |
mbed_official | 579:53297373a894 | 483 | #define EVSYS_INTFLAG_OVR0 (1 << EVSYS_INTFLAG_OVR0_Pos) |
mbed_official | 579:53297373a894 | 484 | #define EVSYS_INTFLAG_OVR1_Pos 1 /**< \brief (EVSYS_INTFLAG) Channel 1 Overrun */ |
mbed_official | 579:53297373a894 | 485 | #define EVSYS_INTFLAG_OVR1 (1 << EVSYS_INTFLAG_OVR1_Pos) |
mbed_official | 579:53297373a894 | 486 | #define EVSYS_INTFLAG_OVR2_Pos 2 /**< \brief (EVSYS_INTFLAG) Channel 2 Overrun */ |
mbed_official | 579:53297373a894 | 487 | #define EVSYS_INTFLAG_OVR2 (1 << EVSYS_INTFLAG_OVR2_Pos) |
mbed_official | 579:53297373a894 | 488 | #define EVSYS_INTFLAG_OVR3_Pos 3 /**< \brief (EVSYS_INTFLAG) Channel 3 Overrun */ |
mbed_official | 579:53297373a894 | 489 | #define EVSYS_INTFLAG_OVR3 (1 << EVSYS_INTFLAG_OVR3_Pos) |
mbed_official | 579:53297373a894 | 490 | #define EVSYS_INTFLAG_OVR4_Pos 4 /**< \brief (EVSYS_INTFLAG) Channel 4 Overrun */ |
mbed_official | 579:53297373a894 | 491 | #define EVSYS_INTFLAG_OVR4 (1 << EVSYS_INTFLAG_OVR4_Pos) |
mbed_official | 579:53297373a894 | 492 | #define EVSYS_INTFLAG_OVR5_Pos 5 /**< \brief (EVSYS_INTFLAG) Channel 5 Overrun */ |
mbed_official | 579:53297373a894 | 493 | #define EVSYS_INTFLAG_OVR5 (1 << EVSYS_INTFLAG_OVR5_Pos) |
mbed_official | 579:53297373a894 | 494 | #define EVSYS_INTFLAG_OVR6_Pos 6 /**< \brief (EVSYS_INTFLAG) Channel 6 Overrun */ |
mbed_official | 579:53297373a894 | 495 | #define EVSYS_INTFLAG_OVR6 (1 << EVSYS_INTFLAG_OVR6_Pos) |
mbed_official | 579:53297373a894 | 496 | #define EVSYS_INTFLAG_OVR7_Pos 7 /**< \brief (EVSYS_INTFLAG) Channel 7 Overrun */ |
mbed_official | 579:53297373a894 | 497 | #define EVSYS_INTFLAG_OVR7 (1 << EVSYS_INTFLAG_OVR7_Pos) |
mbed_official | 579:53297373a894 | 498 | #define EVSYS_INTFLAG_OVR_Pos 0 /**< \brief (EVSYS_INTFLAG) Channel x Overrun */ |
mbed_official | 579:53297373a894 | 499 | #define EVSYS_INTFLAG_OVR_Msk (0xFFul << EVSYS_INTFLAG_OVR_Pos) |
mbed_official | 579:53297373a894 | 500 | #define EVSYS_INTFLAG_OVR(value) ((EVSYS_INTFLAG_OVR_Msk & ((value) << EVSYS_INTFLAG_OVR_Pos))) |
mbed_official | 579:53297373a894 | 501 | #define EVSYS_INTFLAG_EVD0_Pos 8 /**< \brief (EVSYS_INTFLAG) Channel 0 Event Detection */ |
mbed_official | 579:53297373a894 | 502 | #define EVSYS_INTFLAG_EVD0 (1 << EVSYS_INTFLAG_EVD0_Pos) |
mbed_official | 579:53297373a894 | 503 | #define EVSYS_INTFLAG_EVD1_Pos 9 /**< \brief (EVSYS_INTFLAG) Channel 1 Event Detection */ |
mbed_official | 579:53297373a894 | 504 | #define EVSYS_INTFLAG_EVD1 (1 << EVSYS_INTFLAG_EVD1_Pos) |
mbed_official | 579:53297373a894 | 505 | #define EVSYS_INTFLAG_EVD2_Pos 10 /**< \brief (EVSYS_INTFLAG) Channel 2 Event Detection */ |
mbed_official | 579:53297373a894 | 506 | #define EVSYS_INTFLAG_EVD2 (1 << EVSYS_INTFLAG_EVD2_Pos) |
mbed_official | 579:53297373a894 | 507 | #define EVSYS_INTFLAG_EVD3_Pos 11 /**< \brief (EVSYS_INTFLAG) Channel 3 Event Detection */ |
mbed_official | 579:53297373a894 | 508 | #define EVSYS_INTFLAG_EVD3 (1 << EVSYS_INTFLAG_EVD3_Pos) |
mbed_official | 579:53297373a894 | 509 | #define EVSYS_INTFLAG_EVD4_Pos 12 /**< \brief (EVSYS_INTFLAG) Channel 4 Event Detection */ |
mbed_official | 579:53297373a894 | 510 | #define EVSYS_INTFLAG_EVD4 (1 << EVSYS_INTFLAG_EVD4_Pos) |
mbed_official | 579:53297373a894 | 511 | #define EVSYS_INTFLAG_EVD5_Pos 13 /**< \brief (EVSYS_INTFLAG) Channel 5 Event Detection */ |
mbed_official | 579:53297373a894 | 512 | #define EVSYS_INTFLAG_EVD5 (1 << EVSYS_INTFLAG_EVD5_Pos) |
mbed_official | 579:53297373a894 | 513 | #define EVSYS_INTFLAG_EVD6_Pos 14 /**< \brief (EVSYS_INTFLAG) Channel 6 Event Detection */ |
mbed_official | 579:53297373a894 | 514 | #define EVSYS_INTFLAG_EVD6 (1 << EVSYS_INTFLAG_EVD6_Pos) |
mbed_official | 579:53297373a894 | 515 | #define EVSYS_INTFLAG_EVD7_Pos 15 /**< \brief (EVSYS_INTFLAG) Channel 7 Event Detection */ |
mbed_official | 579:53297373a894 | 516 | #define EVSYS_INTFLAG_EVD7 (1 << EVSYS_INTFLAG_EVD7_Pos) |
mbed_official | 579:53297373a894 | 517 | #define EVSYS_INTFLAG_EVD_Pos 8 /**< \brief (EVSYS_INTFLAG) Channel x Event Detection */ |
mbed_official | 579:53297373a894 | 518 | #define EVSYS_INTFLAG_EVD_Msk (0xFFul << EVSYS_INTFLAG_EVD_Pos) |
mbed_official | 579:53297373a894 | 519 | #define EVSYS_INTFLAG_EVD(value) ((EVSYS_INTFLAG_EVD_Msk & ((value) << EVSYS_INTFLAG_EVD_Pos))) |
mbed_official | 579:53297373a894 | 520 | #define EVSYS_INTFLAG_OVR8_Pos 16 /**< \brief (EVSYS_INTFLAG) Channel 8 Overrun */ |
mbed_official | 579:53297373a894 | 521 | #define EVSYS_INTFLAG_OVR8 (1 << EVSYS_INTFLAG_OVR8_Pos) |
mbed_official | 579:53297373a894 | 522 | #define EVSYS_INTFLAG_OVR9_Pos 17 /**< \brief (EVSYS_INTFLAG) Channel 9 Overrun */ |
mbed_official | 579:53297373a894 | 523 | #define EVSYS_INTFLAG_OVR9 (1 << EVSYS_INTFLAG_OVR9_Pos) |
mbed_official | 579:53297373a894 | 524 | #define EVSYS_INTFLAG_OVR10_Pos 18 /**< \brief (EVSYS_INTFLAG) Channel 10 Overrun */ |
mbed_official | 579:53297373a894 | 525 | #define EVSYS_INTFLAG_OVR10 (1 << EVSYS_INTFLAG_OVR10_Pos) |
mbed_official | 579:53297373a894 | 526 | #define EVSYS_INTFLAG_OVR11_Pos 19 /**< \brief (EVSYS_INTFLAG) Channel 11 Overrun */ |
mbed_official | 579:53297373a894 | 527 | #define EVSYS_INTFLAG_OVR11 (1 << EVSYS_INTFLAG_OVR11_Pos) |
mbed_official | 579:53297373a894 | 528 | #define EVSYS_INTFLAG_OVRp8_Pos 16 /**< \brief (EVSYS_INTFLAG) Channel x+8 Overrun */ |
mbed_official | 579:53297373a894 | 529 | #define EVSYS_INTFLAG_OVRp8_Msk (0xFul << EVSYS_INTFLAG_OVRp8_Pos) |
mbed_official | 579:53297373a894 | 530 | #define EVSYS_INTFLAG_OVRp8(value) ((EVSYS_INTFLAG_OVRp8_Msk & ((value) << EVSYS_INTFLAG_OVRp8_Pos))) |
mbed_official | 579:53297373a894 | 531 | #define EVSYS_INTFLAG_EVD8_Pos 24 /**< \brief (EVSYS_INTFLAG) Channel 8 Event Detection */ |
mbed_official | 579:53297373a894 | 532 | #define EVSYS_INTFLAG_EVD8 (1 << EVSYS_INTFLAG_EVD8_Pos) |
mbed_official | 579:53297373a894 | 533 | #define EVSYS_INTFLAG_EVD9_Pos 25 /**< \brief (EVSYS_INTFLAG) Channel 9 Event Detection */ |
mbed_official | 579:53297373a894 | 534 | #define EVSYS_INTFLAG_EVD9 (1 << EVSYS_INTFLAG_EVD9_Pos) |
mbed_official | 579:53297373a894 | 535 | #define EVSYS_INTFLAG_EVD10_Pos 26 /**< \brief (EVSYS_INTFLAG) Channel 10 Event Detection */ |
mbed_official | 579:53297373a894 | 536 | #define EVSYS_INTFLAG_EVD10 (1 << EVSYS_INTFLAG_EVD10_Pos) |
mbed_official | 579:53297373a894 | 537 | #define EVSYS_INTFLAG_EVD11_Pos 27 /**< \brief (EVSYS_INTFLAG) Channel 11 Event Detection */ |
mbed_official | 579:53297373a894 | 538 | #define EVSYS_INTFLAG_EVD11 (1 << EVSYS_INTFLAG_EVD11_Pos) |
mbed_official | 579:53297373a894 | 539 | #define EVSYS_INTFLAG_EVDp8_Pos 24 /**< \brief (EVSYS_INTFLAG) Channel x+8 Event Detection */ |
mbed_official | 579:53297373a894 | 540 | #define EVSYS_INTFLAG_EVDp8_Msk (0xFul << EVSYS_INTFLAG_EVDp8_Pos) |
mbed_official | 579:53297373a894 | 541 | #define EVSYS_INTFLAG_EVDp8(value) ((EVSYS_INTFLAG_EVDp8_Msk & ((value) << EVSYS_INTFLAG_EVDp8_Pos))) |
mbed_official | 579:53297373a894 | 542 | #define EVSYS_INTFLAG_MASK 0x0F0FFFFFul /**< \brief (EVSYS_INTFLAG) MASK Register */ |
mbed_official | 579:53297373a894 | 543 | |
mbed_official | 579:53297373a894 | 544 | /** \brief EVSYS hardware registers */ |
mbed_official | 579:53297373a894 | 545 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 546 | typedef struct { |
mbed_official | 579:53297373a894 | 547 | __O EVSYS_CTRL_Type CTRL; /**< \brief Offset: 0x00 ( /W 8) Control */ |
mbed_official | 579:53297373a894 | 548 | RoReg8 Reserved1[0x3]; |
mbed_official | 579:53297373a894 | 549 | __IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x04 (R/W 32) Channel */ |
mbed_official | 579:53297373a894 | 550 | __IO EVSYS_USER_Type USER; /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */ |
mbed_official | 579:53297373a894 | 551 | RoReg8 Reserved2[0x2]; |
mbed_official | 579:53297373a894 | 552 | __I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0C (R/ 32) Channel Status */ |
mbed_official | 579:53297373a894 | 553 | __IO EVSYS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */ |
mbed_official | 579:53297373a894 | 554 | __IO EVSYS_INTENSET_Type INTENSET; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */ |
mbed_official | 579:53297373a894 | 555 | __IO EVSYS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */ |
mbed_official | 579:53297373a894 | 556 | } Evsys; |
mbed_official | 579:53297373a894 | 557 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 558 | |
mbed_official | 579:53297373a894 | 559 | /*@}*/ |
mbed_official | 579:53297373a894 | 560 | |
mbed_official | 579:53297373a894 | 561 | #endif /* _SAMD21_EVSYS_COMPONENT_ */ |