mbed library sources
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targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim.h@600:7d17ca308cd1, 2015-07-31 (annotated)
- Committer:
- mbed_official
- Date:
- Fri Jul 31 14:15:09 2015 +0100
- Revision:
- 600:7d17ca308cd1
- Parent:
- 573:ad23fe03a082
- Child:
- 610:813dcc80987e
Synchronized with git revision e4cd8bbd3e05b68e5a7f466c74035a85743d45e0
Full URL: https://github.com/mbedmicro/mbed/commit/e4cd8bbd3e05b68e5a7f466c74035a85743d45e0/
Enable LPC8xx usart when configuring it
Who changed what in which revision?
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mbed_official | 573:ad23fe03a082 | 1 | /** |
mbed_official | 573:ad23fe03a082 | 2 | ****************************************************************************** |
mbed_official | 573:ad23fe03a082 | 3 | * @file stm32f7xx_hal_tim.h |
mbed_official | 573:ad23fe03a082 | 4 | * @author MCD Application Team |
mbed_official | 573:ad23fe03a082 | 5 | * @version V1.0.0 |
mbed_official | 573:ad23fe03a082 | 6 | * @date 12-May-2015 |
mbed_official | 573:ad23fe03a082 | 7 | * @brief Header file of TIM HAL module. |
mbed_official | 573:ad23fe03a082 | 8 | ****************************************************************************** |
mbed_official | 573:ad23fe03a082 | 9 | * @attention |
mbed_official | 573:ad23fe03a082 | 10 | * |
mbed_official | 573:ad23fe03a082 | 11 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
mbed_official | 573:ad23fe03a082 | 12 | * |
mbed_official | 573:ad23fe03a082 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
mbed_official | 573:ad23fe03a082 | 14 | * are permitted provided that the following conditions are met: |
mbed_official | 573:ad23fe03a082 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
mbed_official | 573:ad23fe03a082 | 16 | * this list of conditions and the following disclaimer. |
mbed_official | 573:ad23fe03a082 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
mbed_official | 573:ad23fe03a082 | 18 | * this list of conditions and the following disclaimer in the documentation |
mbed_official | 573:ad23fe03a082 | 19 | * and/or other materials provided with the distribution. |
mbed_official | 573:ad23fe03a082 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
mbed_official | 573:ad23fe03a082 | 21 | * may be used to endorse or promote products derived from this software |
mbed_official | 573:ad23fe03a082 | 22 | * without specific prior written permission. |
mbed_official | 573:ad23fe03a082 | 23 | * |
mbed_official | 573:ad23fe03a082 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
mbed_official | 573:ad23fe03a082 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
mbed_official | 573:ad23fe03a082 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
mbed_official | 573:ad23fe03a082 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
mbed_official | 573:ad23fe03a082 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
mbed_official | 573:ad23fe03a082 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
mbed_official | 573:ad23fe03a082 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
mbed_official | 573:ad23fe03a082 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
mbed_official | 573:ad23fe03a082 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
mbed_official | 573:ad23fe03a082 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 573:ad23fe03a082 | 34 | * |
mbed_official | 573:ad23fe03a082 | 35 | ****************************************************************************** |
mbed_official | 573:ad23fe03a082 | 36 | */ |
mbed_official | 573:ad23fe03a082 | 37 | |
mbed_official | 573:ad23fe03a082 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 39 | #ifndef __STM32F7xx_HAL_TIM_H |
mbed_official | 573:ad23fe03a082 | 40 | #define __STM32F7xx_HAL_TIM_H |
mbed_official | 573:ad23fe03a082 | 41 | |
mbed_official | 573:ad23fe03a082 | 42 | #ifdef __cplusplus |
mbed_official | 573:ad23fe03a082 | 43 | extern "C" { |
mbed_official | 573:ad23fe03a082 | 44 | #endif |
mbed_official | 573:ad23fe03a082 | 45 | |
mbed_official | 573:ad23fe03a082 | 46 | /* Includes ------------------------------------------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 47 | #include "stm32f7xx_hal_def.h" |
mbed_official | 573:ad23fe03a082 | 48 | |
mbed_official | 573:ad23fe03a082 | 49 | /** @addtogroup STM32F7xx_HAL_Driver |
mbed_official | 573:ad23fe03a082 | 50 | * @{ |
mbed_official | 573:ad23fe03a082 | 51 | */ |
mbed_official | 573:ad23fe03a082 | 52 | |
mbed_official | 573:ad23fe03a082 | 53 | /** @addtogroup TIM |
mbed_official | 573:ad23fe03a082 | 54 | * @{ |
mbed_official | 573:ad23fe03a082 | 55 | */ |
mbed_official | 573:ad23fe03a082 | 56 | |
mbed_official | 573:ad23fe03a082 | 57 | /* Exported types ------------------------------------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 58 | /** @defgroup TIM_Exported_Types TIM Exported Types |
mbed_official | 573:ad23fe03a082 | 59 | * @{ |
mbed_official | 573:ad23fe03a082 | 60 | */ |
mbed_official | 573:ad23fe03a082 | 61 | |
mbed_official | 573:ad23fe03a082 | 62 | /** |
mbed_official | 573:ad23fe03a082 | 63 | * @brief TIM Time base Configuration Structure definition |
mbed_official | 573:ad23fe03a082 | 64 | */ |
mbed_official | 573:ad23fe03a082 | 65 | typedef struct |
mbed_official | 573:ad23fe03a082 | 66 | { |
mbed_official | 573:ad23fe03a082 | 67 | uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. |
mbed_official | 573:ad23fe03a082 | 68 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
mbed_official | 573:ad23fe03a082 | 69 | |
mbed_official | 573:ad23fe03a082 | 70 | uint32_t CounterMode; /*!< Specifies the counter mode. |
mbed_official | 573:ad23fe03a082 | 71 | This parameter can be a value of @ref TIM_Counter_Mode */ |
mbed_official | 573:ad23fe03a082 | 72 | |
mbed_official | 573:ad23fe03a082 | 73 | uint32_t Period; /*!< Specifies the period value to be loaded into the active |
mbed_official | 573:ad23fe03a082 | 74 | Auto-Reload Register at the next update event. |
mbed_official | 573:ad23fe03a082 | 75 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ |
mbed_official | 573:ad23fe03a082 | 76 | |
mbed_official | 573:ad23fe03a082 | 77 | uint32_t ClockDivision; /*!< Specifies the clock division. |
mbed_official | 573:ad23fe03a082 | 78 | This parameter can be a value of @ref TIM_ClockDivision */ |
mbed_official | 573:ad23fe03a082 | 79 | |
mbed_official | 573:ad23fe03a082 | 80 | uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter |
mbed_official | 573:ad23fe03a082 | 81 | reaches zero, an update event is generated and counting restarts |
mbed_official | 573:ad23fe03a082 | 82 | from the RCR value (N). |
mbed_official | 573:ad23fe03a082 | 83 | This means in PWM mode that (N+1) corresponds to: |
mbed_official | 573:ad23fe03a082 | 84 | - the number of PWM periods in edge-aligned mode |
mbed_official | 573:ad23fe03a082 | 85 | - the number of half PWM period in center-aligned mode |
mbed_official | 573:ad23fe03a082 | 86 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. |
mbed_official | 573:ad23fe03a082 | 87 | @note This parameter is valid only for TIM1 and TIM8. */ |
mbed_official | 573:ad23fe03a082 | 88 | } TIM_Base_InitTypeDef; |
mbed_official | 573:ad23fe03a082 | 89 | |
mbed_official | 573:ad23fe03a082 | 90 | /** |
mbed_official | 573:ad23fe03a082 | 91 | * @brief TIM Output Compare Configuration Structure definition |
mbed_official | 573:ad23fe03a082 | 92 | */ |
mbed_official | 573:ad23fe03a082 | 93 | |
mbed_official | 573:ad23fe03a082 | 94 | typedef struct |
mbed_official | 573:ad23fe03a082 | 95 | { |
mbed_official | 573:ad23fe03a082 | 96 | uint32_t OCMode; /*!< Specifies the TIM mode. |
mbed_official | 573:ad23fe03a082 | 97 | This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */ |
mbed_official | 573:ad23fe03a082 | 98 | |
mbed_official | 573:ad23fe03a082 | 99 | uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. |
mbed_official | 573:ad23fe03a082 | 100 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
mbed_official | 573:ad23fe03a082 | 101 | |
mbed_official | 573:ad23fe03a082 | 102 | uint32_t OCPolarity; /*!< Specifies the output polarity. |
mbed_official | 573:ad23fe03a082 | 103 | This parameter can be a value of @ref TIM_Output_Compare_Polarity */ |
mbed_official | 573:ad23fe03a082 | 104 | |
mbed_official | 573:ad23fe03a082 | 105 | uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. |
mbed_official | 573:ad23fe03a082 | 106 | This parameter can be a value of @ref TIM_Output_Compare_N_Polarity |
mbed_official | 573:ad23fe03a082 | 107 | @note This parameter is valid only for TIM1 and TIM8. */ |
mbed_official | 573:ad23fe03a082 | 108 | |
mbed_official | 573:ad23fe03a082 | 109 | uint32_t OCFastMode; /*!< Specifies the Fast mode state. |
mbed_official | 573:ad23fe03a082 | 110 | This parameter can be a value of @ref TIM_Output_Fast_State |
mbed_official | 573:ad23fe03a082 | 111 | @note This parameter is valid only in PWM1 and PWM2 mode. */ |
mbed_official | 573:ad23fe03a082 | 112 | |
mbed_official | 573:ad23fe03a082 | 113 | |
mbed_official | 573:ad23fe03a082 | 114 | uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
mbed_official | 573:ad23fe03a082 | 115 | This parameter can be a value of @ref TIM_Output_Compare_Idle_State |
mbed_official | 573:ad23fe03a082 | 116 | @note This parameter is valid only for TIM1 and TIM8. */ |
mbed_official | 573:ad23fe03a082 | 117 | |
mbed_official | 573:ad23fe03a082 | 118 | uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
mbed_official | 573:ad23fe03a082 | 119 | This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State |
mbed_official | 573:ad23fe03a082 | 120 | @note This parameter is valid only for TIM1 and TIM8. */ |
mbed_official | 573:ad23fe03a082 | 121 | } TIM_OC_InitTypeDef; |
mbed_official | 573:ad23fe03a082 | 122 | |
mbed_official | 573:ad23fe03a082 | 123 | /** |
mbed_official | 573:ad23fe03a082 | 124 | * @brief TIM One Pulse Mode Configuration Structure definition |
mbed_official | 573:ad23fe03a082 | 125 | */ |
mbed_official | 573:ad23fe03a082 | 126 | typedef struct |
mbed_official | 573:ad23fe03a082 | 127 | { |
mbed_official | 573:ad23fe03a082 | 128 | uint32_t OCMode; /*!< Specifies the TIM mode. |
mbed_official | 573:ad23fe03a082 | 129 | This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */ |
mbed_official | 573:ad23fe03a082 | 130 | |
mbed_official | 573:ad23fe03a082 | 131 | uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. |
mbed_official | 573:ad23fe03a082 | 132 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
mbed_official | 573:ad23fe03a082 | 133 | |
mbed_official | 573:ad23fe03a082 | 134 | uint32_t OCPolarity; /*!< Specifies the output polarity. |
mbed_official | 573:ad23fe03a082 | 135 | This parameter can be a value of @ref TIM_Output_Compare_Polarity */ |
mbed_official | 573:ad23fe03a082 | 136 | |
mbed_official | 573:ad23fe03a082 | 137 | uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. |
mbed_official | 573:ad23fe03a082 | 138 | This parameter can be a value of @ref TIM_Output_Compare_N_Polarity |
mbed_official | 573:ad23fe03a082 | 139 | @note This parameter is valid only for TIM1 and TIM8. */ |
mbed_official | 573:ad23fe03a082 | 140 | |
mbed_official | 573:ad23fe03a082 | 141 | uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
mbed_official | 573:ad23fe03a082 | 142 | This parameter can be a value of @ref TIM_Output_Compare_Idle_State |
mbed_official | 573:ad23fe03a082 | 143 | @note This parameter is valid only for TIM1 and TIM8. */ |
mbed_official | 573:ad23fe03a082 | 144 | |
mbed_official | 573:ad23fe03a082 | 145 | uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
mbed_official | 573:ad23fe03a082 | 146 | This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State |
mbed_official | 573:ad23fe03a082 | 147 | @note This parameter is valid only for TIM1 and TIM8. */ |
mbed_official | 573:ad23fe03a082 | 148 | |
mbed_official | 573:ad23fe03a082 | 149 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. |
mbed_official | 573:ad23fe03a082 | 150 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
mbed_official | 573:ad23fe03a082 | 151 | |
mbed_official | 573:ad23fe03a082 | 152 | uint32_t ICSelection; /*!< Specifies the input. |
mbed_official | 573:ad23fe03a082 | 153 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
mbed_official | 573:ad23fe03a082 | 154 | |
mbed_official | 573:ad23fe03a082 | 155 | uint32_t ICFilter; /*!< Specifies the input capture filter. |
mbed_official | 573:ad23fe03a082 | 156 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
mbed_official | 573:ad23fe03a082 | 157 | } TIM_OnePulse_InitTypeDef; |
mbed_official | 573:ad23fe03a082 | 158 | |
mbed_official | 573:ad23fe03a082 | 159 | |
mbed_official | 573:ad23fe03a082 | 160 | /** |
mbed_official | 573:ad23fe03a082 | 161 | * @brief TIM Input Capture Configuration Structure definition |
mbed_official | 573:ad23fe03a082 | 162 | */ |
mbed_official | 573:ad23fe03a082 | 163 | |
mbed_official | 573:ad23fe03a082 | 164 | typedef struct |
mbed_official | 573:ad23fe03a082 | 165 | { |
mbed_official | 573:ad23fe03a082 | 166 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. |
mbed_official | 573:ad23fe03a082 | 167 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
mbed_official | 573:ad23fe03a082 | 168 | |
mbed_official | 573:ad23fe03a082 | 169 | uint32_t ICSelection; /*!< Specifies the input. |
mbed_official | 573:ad23fe03a082 | 170 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
mbed_official | 573:ad23fe03a082 | 171 | |
mbed_official | 573:ad23fe03a082 | 172 | uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. |
mbed_official | 573:ad23fe03a082 | 173 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
mbed_official | 573:ad23fe03a082 | 174 | |
mbed_official | 573:ad23fe03a082 | 175 | uint32_t ICFilter; /*!< Specifies the input capture filter. |
mbed_official | 573:ad23fe03a082 | 176 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
mbed_official | 573:ad23fe03a082 | 177 | } TIM_IC_InitTypeDef; |
mbed_official | 573:ad23fe03a082 | 178 | |
mbed_official | 573:ad23fe03a082 | 179 | /** |
mbed_official | 573:ad23fe03a082 | 180 | * @brief TIM Encoder Configuration Structure definition |
mbed_official | 573:ad23fe03a082 | 181 | */ |
mbed_official | 573:ad23fe03a082 | 182 | |
mbed_official | 573:ad23fe03a082 | 183 | typedef struct |
mbed_official | 573:ad23fe03a082 | 184 | { |
mbed_official | 573:ad23fe03a082 | 185 | uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. |
mbed_official | 573:ad23fe03a082 | 186 | This parameter can be a value of @ref TIM_Encoder_Mode */ |
mbed_official | 573:ad23fe03a082 | 187 | |
mbed_official | 573:ad23fe03a082 | 188 | uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. |
mbed_official | 573:ad23fe03a082 | 189 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
mbed_official | 573:ad23fe03a082 | 190 | |
mbed_official | 573:ad23fe03a082 | 191 | uint32_t IC1Selection; /*!< Specifies the input. |
mbed_official | 573:ad23fe03a082 | 192 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
mbed_official | 573:ad23fe03a082 | 193 | |
mbed_official | 573:ad23fe03a082 | 194 | uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. |
mbed_official | 573:ad23fe03a082 | 195 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
mbed_official | 573:ad23fe03a082 | 196 | |
mbed_official | 573:ad23fe03a082 | 197 | uint32_t IC1Filter; /*!< Specifies the input capture filter. |
mbed_official | 573:ad23fe03a082 | 198 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
mbed_official | 573:ad23fe03a082 | 199 | |
mbed_official | 573:ad23fe03a082 | 200 | uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. |
mbed_official | 573:ad23fe03a082 | 201 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
mbed_official | 573:ad23fe03a082 | 202 | |
mbed_official | 573:ad23fe03a082 | 203 | uint32_t IC2Selection; /*!< Specifies the input. |
mbed_official | 573:ad23fe03a082 | 204 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
mbed_official | 573:ad23fe03a082 | 205 | |
mbed_official | 573:ad23fe03a082 | 206 | uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. |
mbed_official | 573:ad23fe03a082 | 207 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
mbed_official | 573:ad23fe03a082 | 208 | |
mbed_official | 573:ad23fe03a082 | 209 | uint32_t IC2Filter; /*!< Specifies the input capture filter. |
mbed_official | 573:ad23fe03a082 | 210 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
mbed_official | 573:ad23fe03a082 | 211 | } TIM_Encoder_InitTypeDef; |
mbed_official | 573:ad23fe03a082 | 212 | |
mbed_official | 573:ad23fe03a082 | 213 | /** |
mbed_official | 573:ad23fe03a082 | 214 | * @brief Clock Configuration Handle Structure definition |
mbed_official | 573:ad23fe03a082 | 215 | */ |
mbed_official | 573:ad23fe03a082 | 216 | typedef struct |
mbed_official | 573:ad23fe03a082 | 217 | { |
mbed_official | 573:ad23fe03a082 | 218 | uint32_t ClockSource; /*!< TIM clock sources. |
mbed_official | 573:ad23fe03a082 | 219 | This parameter can be a value of @ref TIM_Clock_Source */ |
mbed_official | 573:ad23fe03a082 | 220 | uint32_t ClockPolarity; /*!< TIM clock polarity. |
mbed_official | 573:ad23fe03a082 | 221 | This parameter can be a value of @ref TIM_Clock_Polarity */ |
mbed_official | 573:ad23fe03a082 | 222 | uint32_t ClockPrescaler; /*!< TIM clock prescaler. |
mbed_official | 573:ad23fe03a082 | 223 | This parameter can be a value of @ref TIM_Clock_Prescaler */ |
mbed_official | 573:ad23fe03a082 | 224 | uint32_t ClockFilter; /*!< TIM clock filter. |
mbed_official | 573:ad23fe03a082 | 225 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
mbed_official | 573:ad23fe03a082 | 226 | }TIM_ClockConfigTypeDef; |
mbed_official | 573:ad23fe03a082 | 227 | |
mbed_official | 573:ad23fe03a082 | 228 | /** |
mbed_official | 573:ad23fe03a082 | 229 | * @brief Clear Input Configuration Handle Structure definition |
mbed_official | 573:ad23fe03a082 | 230 | */ |
mbed_official | 573:ad23fe03a082 | 231 | typedef struct |
mbed_official | 573:ad23fe03a082 | 232 | { |
mbed_official | 573:ad23fe03a082 | 233 | uint32_t ClearInputState; /*!< TIM clear Input state. |
mbed_official | 573:ad23fe03a082 | 234 | This parameter can be ENABLE or DISABLE */ |
mbed_official | 573:ad23fe03a082 | 235 | uint32_t ClearInputSource; /*!< TIM clear Input sources. |
mbed_official | 573:ad23fe03a082 | 236 | This parameter can be a value of @ref TIMEx_ClearInput_Source */ |
mbed_official | 573:ad23fe03a082 | 237 | uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity. |
mbed_official | 573:ad23fe03a082 | 238 | This parameter can be a value of @ref TIM_ClearInput_Polarity */ |
mbed_official | 573:ad23fe03a082 | 239 | uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler. |
mbed_official | 573:ad23fe03a082 | 240 | This parameter can be a value of @ref TIM_ClearInput_Prescaler */ |
mbed_official | 573:ad23fe03a082 | 241 | uint32_t ClearInputFilter; /*!< TIM Clear Input filter. |
mbed_official | 573:ad23fe03a082 | 242 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
mbed_official | 573:ad23fe03a082 | 243 | }TIM_ClearInputConfigTypeDef; |
mbed_official | 573:ad23fe03a082 | 244 | |
mbed_official | 573:ad23fe03a082 | 245 | /** |
mbed_official | 573:ad23fe03a082 | 246 | * @brief TIM Slave configuration Structure definition |
mbed_official | 573:ad23fe03a082 | 247 | */ |
mbed_official | 573:ad23fe03a082 | 248 | typedef struct { |
mbed_official | 573:ad23fe03a082 | 249 | uint32_t SlaveMode; /*!< Slave mode selection |
mbed_official | 573:ad23fe03a082 | 250 | This parameter can be a value of @ref TIMEx_Slave_Mode */ |
mbed_official | 573:ad23fe03a082 | 251 | uint32_t InputTrigger; /*!< Input Trigger source |
mbed_official | 573:ad23fe03a082 | 252 | This parameter can be a value of @ref TIM_Trigger_Selection */ |
mbed_official | 573:ad23fe03a082 | 253 | uint32_t TriggerPolarity; /*!< Input Trigger polarity |
mbed_official | 573:ad23fe03a082 | 254 | This parameter can be a value of @ref TIM_Trigger_Polarity */ |
mbed_official | 573:ad23fe03a082 | 255 | uint32_t TriggerPrescaler; /*!< Input trigger prescaler |
mbed_official | 573:ad23fe03a082 | 256 | This parameter can be a value of @ref TIM_Trigger_Prescaler */ |
mbed_official | 573:ad23fe03a082 | 257 | uint32_t TriggerFilter; /*!< Input trigger filter |
mbed_official | 573:ad23fe03a082 | 258 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
mbed_official | 573:ad23fe03a082 | 259 | |
mbed_official | 573:ad23fe03a082 | 260 | }TIM_SlaveConfigTypeDef; |
mbed_official | 573:ad23fe03a082 | 261 | |
mbed_official | 573:ad23fe03a082 | 262 | /** |
mbed_official | 573:ad23fe03a082 | 263 | * @brief HAL State structures definition |
mbed_official | 573:ad23fe03a082 | 264 | */ |
mbed_official | 573:ad23fe03a082 | 265 | typedef enum |
mbed_official | 573:ad23fe03a082 | 266 | { |
mbed_official | 573:ad23fe03a082 | 267 | HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */ |
mbed_official | 573:ad23fe03a082 | 268 | HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ |
mbed_official | 573:ad23fe03a082 | 269 | HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ |
mbed_official | 573:ad23fe03a082 | 270 | HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */ |
mbed_official | 573:ad23fe03a082 | 271 | HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */ |
mbed_official | 573:ad23fe03a082 | 272 | }HAL_TIM_StateTypeDef; |
mbed_official | 573:ad23fe03a082 | 273 | |
mbed_official | 573:ad23fe03a082 | 274 | /** |
mbed_official | 573:ad23fe03a082 | 275 | * @brief HAL Active channel structures definition |
mbed_official | 573:ad23fe03a082 | 276 | */ |
mbed_official | 573:ad23fe03a082 | 277 | typedef enum |
mbed_official | 573:ad23fe03a082 | 278 | { |
mbed_official | 573:ad23fe03a082 | 279 | HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */ |
mbed_official | 573:ad23fe03a082 | 280 | HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */ |
mbed_official | 573:ad23fe03a082 | 281 | HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */ |
mbed_official | 573:ad23fe03a082 | 282 | HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */ |
mbed_official | 573:ad23fe03a082 | 283 | HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */ |
mbed_official | 573:ad23fe03a082 | 284 | }HAL_TIM_ActiveChannel; |
mbed_official | 573:ad23fe03a082 | 285 | |
mbed_official | 573:ad23fe03a082 | 286 | /** |
mbed_official | 573:ad23fe03a082 | 287 | * @brief TIM Time Base Handle Structure definition |
mbed_official | 573:ad23fe03a082 | 288 | */ |
mbed_official | 573:ad23fe03a082 | 289 | typedef struct |
mbed_official | 573:ad23fe03a082 | 290 | { |
mbed_official | 573:ad23fe03a082 | 291 | TIM_TypeDef *Instance; /*!< Register base address */ |
mbed_official | 573:ad23fe03a082 | 292 | TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ |
mbed_official | 573:ad23fe03a082 | 293 | HAL_TIM_ActiveChannel Channel; /*!< Active channel */ |
mbed_official | 573:ad23fe03a082 | 294 | DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array |
mbed_official | 573:ad23fe03a082 | 295 | This array is accessed by a @ref DMA_Handle_index */ |
mbed_official | 573:ad23fe03a082 | 296 | HAL_LockTypeDef Lock; /*!< Locking object */ |
mbed_official | 573:ad23fe03a082 | 297 | __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ |
mbed_official | 573:ad23fe03a082 | 298 | }TIM_HandleTypeDef; |
mbed_official | 573:ad23fe03a082 | 299 | /** |
mbed_official | 573:ad23fe03a082 | 300 | * @} |
mbed_official | 573:ad23fe03a082 | 301 | */ |
mbed_official | 573:ad23fe03a082 | 302 | |
mbed_official | 573:ad23fe03a082 | 303 | /* Exported constants --------------------------------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 304 | /** @defgroup TIM_Exported_Constants TIM Exported Constants |
mbed_official | 573:ad23fe03a082 | 305 | * @{ |
mbed_official | 573:ad23fe03a082 | 306 | */ |
mbed_official | 573:ad23fe03a082 | 307 | |
mbed_official | 573:ad23fe03a082 | 308 | /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity |
mbed_official | 573:ad23fe03a082 | 309 | * @{ |
mbed_official | 573:ad23fe03a082 | 310 | */ |
mbed_official | 573:ad23fe03a082 | 311 | #define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */ |
mbed_official | 573:ad23fe03a082 | 312 | #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */ |
mbed_official | 573:ad23fe03a082 | 313 | #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ |
mbed_official | 573:ad23fe03a082 | 314 | /** |
mbed_official | 573:ad23fe03a082 | 315 | * @} |
mbed_official | 573:ad23fe03a082 | 316 | */ |
mbed_official | 573:ad23fe03a082 | 317 | |
mbed_official | 573:ad23fe03a082 | 318 | /** @defgroup TIM_ETR_Polarity TIM ETR Polarity |
mbed_official | 573:ad23fe03a082 | 319 | * @{ |
mbed_official | 573:ad23fe03a082 | 320 | */ |
mbed_official | 573:ad23fe03a082 | 321 | #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ |
mbed_official | 573:ad23fe03a082 | 322 | #define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */ |
mbed_official | 573:ad23fe03a082 | 323 | /** |
mbed_official | 573:ad23fe03a082 | 324 | * @} |
mbed_official | 573:ad23fe03a082 | 325 | */ |
mbed_official | 573:ad23fe03a082 | 326 | |
mbed_official | 573:ad23fe03a082 | 327 | /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler |
mbed_official | 573:ad23fe03a082 | 328 | * @{ |
mbed_official | 573:ad23fe03a082 | 329 | */ |
mbed_official | 573:ad23fe03a082 | 330 | #define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */ |
mbed_official | 573:ad23fe03a082 | 331 | #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */ |
mbed_official | 573:ad23fe03a082 | 332 | #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */ |
mbed_official | 573:ad23fe03a082 | 333 | #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */ |
mbed_official | 573:ad23fe03a082 | 334 | /** |
mbed_official | 573:ad23fe03a082 | 335 | * @} |
mbed_official | 573:ad23fe03a082 | 336 | */ |
mbed_official | 573:ad23fe03a082 | 337 | |
mbed_official | 573:ad23fe03a082 | 338 | /** @defgroup TIM_Counter_Mode TIM Counter Mode |
mbed_official | 573:ad23fe03a082 | 339 | * @{ |
mbed_official | 573:ad23fe03a082 | 340 | */ |
mbed_official | 573:ad23fe03a082 | 341 | #define TIM_COUNTERMODE_UP ((uint32_t)0x0000) |
mbed_official | 573:ad23fe03a082 | 342 | #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR |
mbed_official | 573:ad23fe03a082 | 343 | #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 |
mbed_official | 573:ad23fe03a082 | 344 | #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 |
mbed_official | 573:ad23fe03a082 | 345 | #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS |
mbed_official | 573:ad23fe03a082 | 346 | /** |
mbed_official | 573:ad23fe03a082 | 347 | * @} |
mbed_official | 573:ad23fe03a082 | 348 | */ |
mbed_official | 573:ad23fe03a082 | 349 | |
mbed_official | 573:ad23fe03a082 | 350 | /** @defgroup TIM_ClockDivision TIM Clock Division |
mbed_official | 573:ad23fe03a082 | 351 | * @{ |
mbed_official | 573:ad23fe03a082 | 352 | */ |
mbed_official | 573:ad23fe03a082 | 353 | #define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000) |
mbed_official | 573:ad23fe03a082 | 354 | #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) |
mbed_official | 573:ad23fe03a082 | 355 | #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) |
mbed_official | 573:ad23fe03a082 | 356 | /** |
mbed_official | 573:ad23fe03a082 | 357 | * @} |
mbed_official | 573:ad23fe03a082 | 358 | */ |
mbed_official | 573:ad23fe03a082 | 359 | |
mbed_official | 573:ad23fe03a082 | 360 | /** @defgroup TIM_Output_Compare_State TIM Output Compare State |
mbed_official | 573:ad23fe03a082 | 361 | * @{ |
mbed_official | 573:ad23fe03a082 | 362 | */ |
mbed_official | 573:ad23fe03a082 | 363 | #define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000) |
mbed_official | 573:ad23fe03a082 | 364 | #define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E) |
mbed_official | 573:ad23fe03a082 | 365 | |
mbed_official | 573:ad23fe03a082 | 366 | /** |
mbed_official | 573:ad23fe03a082 | 367 | * @} |
mbed_official | 573:ad23fe03a082 | 368 | */ |
mbed_official | 573:ad23fe03a082 | 369 | |
mbed_official | 573:ad23fe03a082 | 370 | /** @defgroup TIM_Output_Fast_State TIM Output Fast State |
mbed_official | 573:ad23fe03a082 | 371 | * @{ |
mbed_official | 573:ad23fe03a082 | 372 | */ |
mbed_official | 573:ad23fe03a082 | 373 | #define TIM_OCFAST_DISABLE ((uint32_t)0x0000) |
mbed_official | 573:ad23fe03a082 | 374 | #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) |
mbed_official | 573:ad23fe03a082 | 375 | /** |
mbed_official | 573:ad23fe03a082 | 376 | * @} |
mbed_official | 573:ad23fe03a082 | 377 | */ |
mbed_official | 573:ad23fe03a082 | 378 | |
mbed_official | 573:ad23fe03a082 | 379 | /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State |
mbed_official | 573:ad23fe03a082 | 380 | * @{ |
mbed_official | 573:ad23fe03a082 | 381 | */ |
mbed_official | 573:ad23fe03a082 | 382 | #define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000) |
mbed_official | 573:ad23fe03a082 | 383 | #define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE) |
mbed_official | 573:ad23fe03a082 | 384 | /** |
mbed_official | 573:ad23fe03a082 | 385 | * @} |
mbed_official | 573:ad23fe03a082 | 386 | */ |
mbed_official | 573:ad23fe03a082 | 387 | |
mbed_official | 573:ad23fe03a082 | 388 | /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity |
mbed_official | 573:ad23fe03a082 | 389 | * @{ |
mbed_official | 573:ad23fe03a082 | 390 | */ |
mbed_official | 573:ad23fe03a082 | 391 | #define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000) |
mbed_official | 573:ad23fe03a082 | 392 | #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P) |
mbed_official | 573:ad23fe03a082 | 393 | /** |
mbed_official | 573:ad23fe03a082 | 394 | * @} |
mbed_official | 573:ad23fe03a082 | 395 | */ |
mbed_official | 573:ad23fe03a082 | 396 | |
mbed_official | 573:ad23fe03a082 | 397 | /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity |
mbed_official | 573:ad23fe03a082 | 398 | * @{ |
mbed_official | 573:ad23fe03a082 | 399 | */ |
mbed_official | 573:ad23fe03a082 | 400 | #define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000) |
mbed_official | 573:ad23fe03a082 | 401 | #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP) |
mbed_official | 573:ad23fe03a082 | 402 | /** |
mbed_official | 573:ad23fe03a082 | 403 | * @} |
mbed_official | 573:ad23fe03a082 | 404 | */ |
mbed_official | 573:ad23fe03a082 | 405 | |
mbed_official | 573:ad23fe03a082 | 406 | /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State |
mbed_official | 573:ad23fe03a082 | 407 | * @{ |
mbed_official | 573:ad23fe03a082 | 408 | */ |
mbed_official | 573:ad23fe03a082 | 409 | #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1) |
mbed_official | 573:ad23fe03a082 | 410 | #define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000) |
mbed_official | 573:ad23fe03a082 | 411 | /** |
mbed_official | 573:ad23fe03a082 | 412 | * @} |
mbed_official | 573:ad23fe03a082 | 413 | */ |
mbed_official | 573:ad23fe03a082 | 414 | |
mbed_official | 573:ad23fe03a082 | 415 | /** @defgroup TIM_Output_Compare_N_Idle_State TIM Output Compare N Idle State |
mbed_official | 573:ad23fe03a082 | 416 | * @{ |
mbed_official | 573:ad23fe03a082 | 417 | */ |
mbed_official | 573:ad23fe03a082 | 418 | #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N) |
mbed_official | 573:ad23fe03a082 | 419 | #define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000) |
mbed_official | 573:ad23fe03a082 | 420 | /** |
mbed_official | 573:ad23fe03a082 | 421 | * @} |
mbed_official | 573:ad23fe03a082 | 422 | */ |
mbed_official | 573:ad23fe03a082 | 423 | |
mbed_official | 573:ad23fe03a082 | 424 | /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity |
mbed_official | 573:ad23fe03a082 | 425 | * @{ |
mbed_official | 573:ad23fe03a082 | 426 | */ |
mbed_official | 573:ad23fe03a082 | 427 | #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING |
mbed_official | 573:ad23fe03a082 | 428 | #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING |
mbed_official | 573:ad23fe03a082 | 429 | #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE |
mbed_official | 573:ad23fe03a082 | 430 | /** |
mbed_official | 573:ad23fe03a082 | 431 | * @} |
mbed_official | 573:ad23fe03a082 | 432 | */ |
mbed_official | 573:ad23fe03a082 | 433 | |
mbed_official | 573:ad23fe03a082 | 434 | /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection |
mbed_official | 573:ad23fe03a082 | 435 | * @{ |
mbed_official | 573:ad23fe03a082 | 436 | */ |
mbed_official | 573:ad23fe03a082 | 437 | #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be |
mbed_official | 573:ad23fe03a082 | 438 | connected to IC1, IC2, IC3 or IC4, respectively */ |
mbed_official | 573:ad23fe03a082 | 439 | #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be |
mbed_official | 573:ad23fe03a082 | 440 | connected to IC2, IC1, IC4 or IC3, respectively */ |
mbed_official | 573:ad23fe03a082 | 441 | #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ |
mbed_official | 573:ad23fe03a082 | 442 | |
mbed_official | 573:ad23fe03a082 | 443 | /** |
mbed_official | 573:ad23fe03a082 | 444 | * @} |
mbed_official | 573:ad23fe03a082 | 445 | */ |
mbed_official | 573:ad23fe03a082 | 446 | |
mbed_official | 573:ad23fe03a082 | 447 | /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler |
mbed_official | 573:ad23fe03a082 | 448 | * @{ |
mbed_official | 573:ad23fe03a082 | 449 | */ |
mbed_official | 573:ad23fe03a082 | 450 | #define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */ |
mbed_official | 573:ad23fe03a082 | 451 | #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */ |
mbed_official | 573:ad23fe03a082 | 452 | #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */ |
mbed_official | 573:ad23fe03a082 | 453 | #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */ |
mbed_official | 573:ad23fe03a082 | 454 | /** |
mbed_official | 573:ad23fe03a082 | 455 | * @} |
mbed_official | 573:ad23fe03a082 | 456 | */ |
mbed_official | 573:ad23fe03a082 | 457 | |
mbed_official | 573:ad23fe03a082 | 458 | /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode |
mbed_official | 573:ad23fe03a082 | 459 | * @{ |
mbed_official | 573:ad23fe03a082 | 460 | */ |
mbed_official | 573:ad23fe03a082 | 461 | #define TIM_OPMODE_SINGLE (TIM_CR1_OPM) |
mbed_official | 573:ad23fe03a082 | 462 | #define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000) |
mbed_official | 573:ad23fe03a082 | 463 | /** |
mbed_official | 573:ad23fe03a082 | 464 | * @} |
mbed_official | 573:ad23fe03a082 | 465 | */ |
mbed_official | 573:ad23fe03a082 | 466 | |
mbed_official | 573:ad23fe03a082 | 467 | /** @defgroup TIM_Encoder_Mode TIM Encoder Mode |
mbed_official | 573:ad23fe03a082 | 468 | * @{ |
mbed_official | 573:ad23fe03a082 | 469 | */ |
mbed_official | 573:ad23fe03a082 | 470 | #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0) |
mbed_official | 573:ad23fe03a082 | 471 | #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1) |
mbed_official | 573:ad23fe03a082 | 472 | #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) |
mbed_official | 573:ad23fe03a082 | 473 | |
mbed_official | 573:ad23fe03a082 | 474 | /** |
mbed_official | 573:ad23fe03a082 | 475 | * @} |
mbed_official | 573:ad23fe03a082 | 476 | */ |
mbed_official | 573:ad23fe03a082 | 477 | |
mbed_official | 573:ad23fe03a082 | 478 | /** @defgroup TIM_Interrupt_definition TIM Interrupt definition |
mbed_official | 573:ad23fe03a082 | 479 | * @{ |
mbed_official | 573:ad23fe03a082 | 480 | */ |
mbed_official | 573:ad23fe03a082 | 481 | #define TIM_IT_UPDATE (TIM_DIER_UIE) |
mbed_official | 573:ad23fe03a082 | 482 | #define TIM_IT_CC1 (TIM_DIER_CC1IE) |
mbed_official | 573:ad23fe03a082 | 483 | #define TIM_IT_CC2 (TIM_DIER_CC2IE) |
mbed_official | 573:ad23fe03a082 | 484 | #define TIM_IT_CC3 (TIM_DIER_CC3IE) |
mbed_official | 573:ad23fe03a082 | 485 | #define TIM_IT_CC4 (TIM_DIER_CC4IE) |
mbed_official | 573:ad23fe03a082 | 486 | #define TIM_IT_COM (TIM_DIER_COMIE) |
mbed_official | 573:ad23fe03a082 | 487 | #define TIM_IT_TRIGGER (TIM_DIER_TIE) |
mbed_official | 573:ad23fe03a082 | 488 | #define TIM_IT_BREAK (TIM_DIER_BIE) |
mbed_official | 573:ad23fe03a082 | 489 | /** |
mbed_official | 573:ad23fe03a082 | 490 | * @} |
mbed_official | 573:ad23fe03a082 | 491 | */ |
mbed_official | 573:ad23fe03a082 | 492 | |
mbed_official | 573:ad23fe03a082 | 493 | /** @defgroup TIM_Commutation_Source TIM Commutation Source |
mbed_official | 573:ad23fe03a082 | 494 | * @{ |
mbed_official | 573:ad23fe03a082 | 495 | */ |
mbed_official | 573:ad23fe03a082 | 496 | #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS) |
mbed_official | 573:ad23fe03a082 | 497 | #define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000) |
mbed_official | 573:ad23fe03a082 | 498 | /** |
mbed_official | 573:ad23fe03a082 | 499 | * @} |
mbed_official | 573:ad23fe03a082 | 500 | */ |
mbed_official | 573:ad23fe03a082 | 501 | |
mbed_official | 573:ad23fe03a082 | 502 | /** @defgroup TIM_DMA_sources TIM DMA sources |
mbed_official | 573:ad23fe03a082 | 503 | * @{ |
mbed_official | 573:ad23fe03a082 | 504 | */ |
mbed_official | 573:ad23fe03a082 | 505 | #define TIM_DMA_UPDATE (TIM_DIER_UDE) |
mbed_official | 573:ad23fe03a082 | 506 | #define TIM_DMA_CC1 (TIM_DIER_CC1DE) |
mbed_official | 573:ad23fe03a082 | 507 | #define TIM_DMA_CC2 (TIM_DIER_CC2DE) |
mbed_official | 573:ad23fe03a082 | 508 | #define TIM_DMA_CC3 (TIM_DIER_CC3DE) |
mbed_official | 573:ad23fe03a082 | 509 | #define TIM_DMA_CC4 (TIM_DIER_CC4DE) |
mbed_official | 573:ad23fe03a082 | 510 | #define TIM_DMA_COM (TIM_DIER_COMDE) |
mbed_official | 573:ad23fe03a082 | 511 | #define TIM_DMA_TRIGGER (TIM_DIER_TDE) |
mbed_official | 573:ad23fe03a082 | 512 | /** |
mbed_official | 573:ad23fe03a082 | 513 | * @} |
mbed_official | 573:ad23fe03a082 | 514 | */ |
mbed_official | 573:ad23fe03a082 | 515 | |
mbed_official | 573:ad23fe03a082 | 516 | /** @defgroup TIM_Event_Source TIM Event Source |
mbed_official | 573:ad23fe03a082 | 517 | * @{ |
mbed_official | 573:ad23fe03a082 | 518 | */ |
mbed_official | 573:ad23fe03a082 | 519 | #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG |
mbed_official | 573:ad23fe03a082 | 520 | #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G |
mbed_official | 573:ad23fe03a082 | 521 | #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G |
mbed_official | 573:ad23fe03a082 | 522 | #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G |
mbed_official | 573:ad23fe03a082 | 523 | #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G |
mbed_official | 573:ad23fe03a082 | 524 | #define TIM_EVENTSOURCE_COM TIM_EGR_COMG |
mbed_official | 573:ad23fe03a082 | 525 | #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG |
mbed_official | 573:ad23fe03a082 | 526 | #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG |
mbed_official | 573:ad23fe03a082 | 527 | #define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G |
mbed_official | 573:ad23fe03a082 | 528 | /** |
mbed_official | 573:ad23fe03a082 | 529 | * @} |
mbed_official | 573:ad23fe03a082 | 530 | */ |
mbed_official | 573:ad23fe03a082 | 531 | |
mbed_official | 573:ad23fe03a082 | 532 | /** @defgroup TIM_Flag_definition TIM Flag definition |
mbed_official | 573:ad23fe03a082 | 533 | * @{ |
mbed_official | 573:ad23fe03a082 | 534 | */ |
mbed_official | 573:ad23fe03a082 | 535 | #define TIM_FLAG_UPDATE (TIM_SR_UIF) |
mbed_official | 573:ad23fe03a082 | 536 | #define TIM_FLAG_CC1 (TIM_SR_CC1IF) |
mbed_official | 573:ad23fe03a082 | 537 | #define TIM_FLAG_CC2 (TIM_SR_CC2IF) |
mbed_official | 573:ad23fe03a082 | 538 | #define TIM_FLAG_CC3 (TIM_SR_CC3IF) |
mbed_official | 573:ad23fe03a082 | 539 | #define TIM_FLAG_CC4 (TIM_SR_CC4IF) |
mbed_official | 573:ad23fe03a082 | 540 | #define TIM_FLAG_COM (TIM_SR_COMIF) |
mbed_official | 573:ad23fe03a082 | 541 | #define TIM_FLAG_TRIGGER (TIM_SR_TIF) |
mbed_official | 573:ad23fe03a082 | 542 | #define TIM_FLAG_BREAK (TIM_SR_BIF) |
mbed_official | 573:ad23fe03a082 | 543 | #define TIM_FLAG_BREAK2 (TIM_SR_B2IF) |
mbed_official | 573:ad23fe03a082 | 544 | #define TIM_FLAG_CC1OF (TIM_SR_CC1OF) |
mbed_official | 573:ad23fe03a082 | 545 | #define TIM_FLAG_CC2OF (TIM_SR_CC2OF) |
mbed_official | 573:ad23fe03a082 | 546 | #define TIM_FLAG_CC3OF (TIM_SR_CC3OF) |
mbed_official | 573:ad23fe03a082 | 547 | #define TIM_FLAG_CC4OF (TIM_SR_CC4OF) |
mbed_official | 573:ad23fe03a082 | 548 | /** |
mbed_official | 573:ad23fe03a082 | 549 | * @} |
mbed_official | 573:ad23fe03a082 | 550 | */ |
mbed_official | 573:ad23fe03a082 | 551 | |
mbed_official | 573:ad23fe03a082 | 552 | /** @defgroup TIM_Clock_Source TIM Clock Source |
mbed_official | 573:ad23fe03a082 | 553 | * @{ |
mbed_official | 573:ad23fe03a082 | 554 | */ |
mbed_official | 573:ad23fe03a082 | 555 | #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) |
mbed_official | 573:ad23fe03a082 | 556 | #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) |
mbed_official | 573:ad23fe03a082 | 557 | #define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000) |
mbed_official | 573:ad23fe03a082 | 558 | #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) |
mbed_official | 573:ad23fe03a082 | 559 | #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) |
mbed_official | 573:ad23fe03a082 | 560 | #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) |
mbed_official | 573:ad23fe03a082 | 561 | #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2) |
mbed_official | 573:ad23fe03a082 | 562 | #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) |
mbed_official | 573:ad23fe03a082 | 563 | #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) |
mbed_official | 573:ad23fe03a082 | 564 | #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS) |
mbed_official | 573:ad23fe03a082 | 565 | /** |
mbed_official | 573:ad23fe03a082 | 566 | * @} |
mbed_official | 573:ad23fe03a082 | 567 | */ |
mbed_official | 573:ad23fe03a082 | 568 | |
mbed_official | 573:ad23fe03a082 | 569 | /** @defgroup TIM_Clock_Polarity TIM Clock Polarity |
mbed_official | 573:ad23fe03a082 | 570 | * @{ |
mbed_official | 573:ad23fe03a082 | 571 | */ |
mbed_official | 573:ad23fe03a082 | 572 | #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ |
mbed_official | 573:ad23fe03a082 | 573 | #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ |
mbed_official | 573:ad23fe03a082 | 574 | #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ |
mbed_official | 573:ad23fe03a082 | 575 | #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ |
mbed_official | 573:ad23fe03a082 | 576 | #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ |
mbed_official | 573:ad23fe03a082 | 577 | /** |
mbed_official | 573:ad23fe03a082 | 578 | * @} |
mbed_official | 573:ad23fe03a082 | 579 | */ |
mbed_official | 573:ad23fe03a082 | 580 | |
mbed_official | 573:ad23fe03a082 | 581 | /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler |
mbed_official | 573:ad23fe03a082 | 582 | * @{ |
mbed_official | 573:ad23fe03a082 | 583 | */ |
mbed_official | 573:ad23fe03a082 | 584 | #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
mbed_official | 573:ad23fe03a082 | 585 | #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ |
mbed_official | 573:ad23fe03a082 | 586 | #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ |
mbed_official | 573:ad23fe03a082 | 587 | #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ |
mbed_official | 573:ad23fe03a082 | 588 | /** |
mbed_official | 573:ad23fe03a082 | 589 | * @} |
mbed_official | 573:ad23fe03a082 | 590 | */ |
mbed_official | 573:ad23fe03a082 | 591 | |
mbed_official | 573:ad23fe03a082 | 592 | /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity |
mbed_official | 573:ad23fe03a082 | 593 | * @{ |
mbed_official | 573:ad23fe03a082 | 594 | */ |
mbed_official | 573:ad23fe03a082 | 595 | #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ |
mbed_official | 573:ad23fe03a082 | 596 | #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ |
mbed_official | 573:ad23fe03a082 | 597 | /** |
mbed_official | 573:ad23fe03a082 | 598 | * @} |
mbed_official | 573:ad23fe03a082 | 599 | */ |
mbed_official | 573:ad23fe03a082 | 600 | |
mbed_official | 573:ad23fe03a082 | 601 | /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler |
mbed_official | 573:ad23fe03a082 | 602 | * @{ |
mbed_official | 573:ad23fe03a082 | 603 | */ |
mbed_official | 573:ad23fe03a082 | 604 | #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
mbed_official | 573:ad23fe03a082 | 605 | #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ |
mbed_official | 573:ad23fe03a082 | 606 | #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ |
mbed_official | 573:ad23fe03a082 | 607 | #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ |
mbed_official | 573:ad23fe03a082 | 608 | /** |
mbed_official | 573:ad23fe03a082 | 609 | * @} |
mbed_official | 573:ad23fe03a082 | 610 | */ |
mbed_official | 573:ad23fe03a082 | 611 | |
mbed_official | 573:ad23fe03a082 | 612 | /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state |
mbed_official | 573:ad23fe03a082 | 613 | * @{ |
mbed_official | 573:ad23fe03a082 | 614 | */ |
mbed_official | 573:ad23fe03a082 | 615 | #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR) |
mbed_official | 573:ad23fe03a082 | 616 | #define TIM_OSSR_DISABLE ((uint32_t)0x0000) |
mbed_official | 573:ad23fe03a082 | 617 | /** |
mbed_official | 573:ad23fe03a082 | 618 | * @} |
mbed_official | 573:ad23fe03a082 | 619 | */ |
mbed_official | 573:ad23fe03a082 | 620 | |
mbed_official | 573:ad23fe03a082 | 621 | /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state |
mbed_official | 573:ad23fe03a082 | 622 | * @{ |
mbed_official | 573:ad23fe03a082 | 623 | */ |
mbed_official | 573:ad23fe03a082 | 624 | #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI) |
mbed_official | 573:ad23fe03a082 | 625 | #define TIM_OSSI_DISABLE ((uint32_t)0x0000) |
mbed_official | 573:ad23fe03a082 | 626 | /** |
mbed_official | 573:ad23fe03a082 | 627 | * @} |
mbed_official | 573:ad23fe03a082 | 628 | */ |
mbed_official | 573:ad23fe03a082 | 629 | |
mbed_official | 573:ad23fe03a082 | 630 | /** @defgroup TIM_Lock_level TIM Lock level |
mbed_official | 573:ad23fe03a082 | 631 | * @{ |
mbed_official | 573:ad23fe03a082 | 632 | */ |
mbed_official | 573:ad23fe03a082 | 633 | #define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000) |
mbed_official | 573:ad23fe03a082 | 634 | #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0) |
mbed_official | 573:ad23fe03a082 | 635 | #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1) |
mbed_official | 573:ad23fe03a082 | 636 | #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK) |
mbed_official | 573:ad23fe03a082 | 637 | /** |
mbed_official | 573:ad23fe03a082 | 638 | * @} |
mbed_official | 573:ad23fe03a082 | 639 | */ |
mbed_official | 573:ad23fe03a082 | 640 | /** @defgroup TIM_Break_Input_enable_disable TIM Break Input State |
mbed_official | 573:ad23fe03a082 | 641 | * @{ |
mbed_official | 573:ad23fe03a082 | 642 | */ |
mbed_official | 573:ad23fe03a082 | 643 | #define TIM_BREAK_ENABLE (TIM_BDTR_BKE) |
mbed_official | 573:ad23fe03a082 | 644 | #define TIM_BREAK_DISABLE ((uint32_t)0x0000) |
mbed_official | 573:ad23fe03a082 | 645 | /** |
mbed_official | 573:ad23fe03a082 | 646 | * @} |
mbed_official | 573:ad23fe03a082 | 647 | */ |
mbed_official | 573:ad23fe03a082 | 648 | |
mbed_official | 573:ad23fe03a082 | 649 | /** @defgroup TIM_Break_Polarity TIM Break Polarity |
mbed_official | 573:ad23fe03a082 | 650 | * @{ |
mbed_official | 573:ad23fe03a082 | 651 | */ |
mbed_official | 573:ad23fe03a082 | 652 | #define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000) |
mbed_official | 573:ad23fe03a082 | 653 | #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP) |
mbed_official | 573:ad23fe03a082 | 654 | /** |
mbed_official | 573:ad23fe03a082 | 655 | * @} |
mbed_official | 573:ad23fe03a082 | 656 | */ |
mbed_official | 573:ad23fe03a082 | 657 | |
mbed_official | 573:ad23fe03a082 | 658 | /** @defgroup TIM_AOE_Bit_Set_Reset TIM AOE Bit State |
mbed_official | 573:ad23fe03a082 | 659 | * @{ |
mbed_official | 573:ad23fe03a082 | 660 | */ |
mbed_official | 573:ad23fe03a082 | 661 | #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE) |
mbed_official | 573:ad23fe03a082 | 662 | #define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000) |
mbed_official | 573:ad23fe03a082 | 663 | /** |
mbed_official | 573:ad23fe03a082 | 664 | * @} |
mbed_official | 573:ad23fe03a082 | 665 | */ |
mbed_official | 573:ad23fe03a082 | 666 | |
mbed_official | 573:ad23fe03a082 | 667 | /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection |
mbed_official | 573:ad23fe03a082 | 668 | * @{ |
mbed_official | 573:ad23fe03a082 | 669 | */ |
mbed_official | 573:ad23fe03a082 | 670 | #define TIM_TRGO_RESET ((uint32_t)0x0000) |
mbed_official | 573:ad23fe03a082 | 671 | #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) |
mbed_official | 573:ad23fe03a082 | 672 | #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) |
mbed_official | 573:ad23fe03a082 | 673 | #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) |
mbed_official | 573:ad23fe03a082 | 674 | #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) |
mbed_official | 573:ad23fe03a082 | 675 | #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) |
mbed_official | 573:ad23fe03a082 | 676 | #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) |
mbed_official | 573:ad23fe03a082 | 677 | #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) |
mbed_official | 573:ad23fe03a082 | 678 | /** |
mbed_official | 573:ad23fe03a082 | 679 | * @} |
mbed_official | 573:ad23fe03a082 | 680 | */ |
mbed_official | 573:ad23fe03a082 | 681 | |
mbed_official | 573:ad23fe03a082 | 682 | /** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode |
mbed_official | 573:ad23fe03a082 | 683 | * @{ |
mbed_official | 573:ad23fe03a082 | 684 | */ |
mbed_official | 573:ad23fe03a082 | 685 | #define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080) |
mbed_official | 573:ad23fe03a082 | 686 | #define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000) |
mbed_official | 573:ad23fe03a082 | 687 | /** |
mbed_official | 573:ad23fe03a082 | 688 | * @} |
mbed_official | 573:ad23fe03a082 | 689 | */ |
mbed_official | 573:ad23fe03a082 | 690 | |
mbed_official | 573:ad23fe03a082 | 691 | /** @defgroup TIM_Trigger_Selection TIM Trigger Selection |
mbed_official | 573:ad23fe03a082 | 692 | * @{ |
mbed_official | 573:ad23fe03a082 | 693 | */ |
mbed_official | 573:ad23fe03a082 | 694 | #define TIM_TS_ITR0 ((uint32_t)0x0000) |
mbed_official | 573:ad23fe03a082 | 695 | #define TIM_TS_ITR1 ((uint32_t)0x0010) |
mbed_official | 573:ad23fe03a082 | 696 | #define TIM_TS_ITR2 ((uint32_t)0x0020) |
mbed_official | 573:ad23fe03a082 | 697 | #define TIM_TS_ITR3 ((uint32_t)0x0030) |
mbed_official | 573:ad23fe03a082 | 698 | #define TIM_TS_TI1F_ED ((uint32_t)0x0040) |
mbed_official | 573:ad23fe03a082 | 699 | #define TIM_TS_TI1FP1 ((uint32_t)0x0050) |
mbed_official | 573:ad23fe03a082 | 700 | #define TIM_TS_TI2FP2 ((uint32_t)0x0060) |
mbed_official | 573:ad23fe03a082 | 701 | #define TIM_TS_ETRF ((uint32_t)0x0070) |
mbed_official | 573:ad23fe03a082 | 702 | #define TIM_TS_NONE ((uint32_t)0xFFFF) |
mbed_official | 573:ad23fe03a082 | 703 | /** |
mbed_official | 573:ad23fe03a082 | 704 | * @} |
mbed_official | 573:ad23fe03a082 | 705 | */ |
mbed_official | 573:ad23fe03a082 | 706 | |
mbed_official | 573:ad23fe03a082 | 707 | /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity |
mbed_official | 573:ad23fe03a082 | 708 | * @{ |
mbed_official | 573:ad23fe03a082 | 709 | */ |
mbed_official | 573:ad23fe03a082 | 710 | #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ |
mbed_official | 573:ad23fe03a082 | 711 | #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ |
mbed_official | 573:ad23fe03a082 | 712 | #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
mbed_official | 573:ad23fe03a082 | 713 | #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
mbed_official | 573:ad23fe03a082 | 714 | #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
mbed_official | 573:ad23fe03a082 | 715 | /** |
mbed_official | 573:ad23fe03a082 | 716 | * @} |
mbed_official | 573:ad23fe03a082 | 717 | */ |
mbed_official | 573:ad23fe03a082 | 718 | |
mbed_official | 573:ad23fe03a082 | 719 | /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler |
mbed_official | 573:ad23fe03a082 | 720 | * @{ |
mbed_official | 573:ad23fe03a082 | 721 | */ |
mbed_official | 573:ad23fe03a082 | 722 | #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
mbed_official | 573:ad23fe03a082 | 723 | #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ |
mbed_official | 573:ad23fe03a082 | 724 | #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ |
mbed_official | 573:ad23fe03a082 | 725 | #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ |
mbed_official | 573:ad23fe03a082 | 726 | /** |
mbed_official | 573:ad23fe03a082 | 727 | * @} |
mbed_official | 573:ad23fe03a082 | 728 | */ |
mbed_official | 573:ad23fe03a082 | 729 | |
mbed_official | 573:ad23fe03a082 | 730 | |
mbed_official | 573:ad23fe03a082 | 731 | /** @defgroup TIM_TI1_Selection TIM TI1 Selection |
mbed_official | 573:ad23fe03a082 | 732 | * @{ |
mbed_official | 573:ad23fe03a082 | 733 | */ |
mbed_official | 573:ad23fe03a082 | 734 | #define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000) |
mbed_official | 573:ad23fe03a082 | 735 | #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S) |
mbed_official | 573:ad23fe03a082 | 736 | /** |
mbed_official | 573:ad23fe03a082 | 737 | * @} |
mbed_official | 573:ad23fe03a082 | 738 | */ |
mbed_official | 573:ad23fe03a082 | 739 | |
mbed_official | 573:ad23fe03a082 | 740 | /** @defgroup TIM_DMA_Base_address TIM DMA Base address |
mbed_official | 573:ad23fe03a082 | 741 | * @{ |
mbed_official | 573:ad23fe03a082 | 742 | */ |
mbed_official | 573:ad23fe03a082 | 743 | #define TIM_DMABASE_CR1 (0x00000000) |
mbed_official | 573:ad23fe03a082 | 744 | #define TIM_DMABASE_CR2 (0x00000001) |
mbed_official | 573:ad23fe03a082 | 745 | #define TIM_DMABASE_SMCR (0x00000002) |
mbed_official | 573:ad23fe03a082 | 746 | #define TIM_DMABASE_DIER (0x00000003) |
mbed_official | 573:ad23fe03a082 | 747 | #define TIM_DMABASE_SR (0x00000004) |
mbed_official | 573:ad23fe03a082 | 748 | #define TIM_DMABASE_EGR (0x00000005) |
mbed_official | 573:ad23fe03a082 | 749 | #define TIM_DMABASE_CCMR1 (0x00000006) |
mbed_official | 573:ad23fe03a082 | 750 | #define TIM_DMABASE_CCMR2 (0x00000007) |
mbed_official | 573:ad23fe03a082 | 751 | #define TIM_DMABASE_CCER (0x00000008) |
mbed_official | 573:ad23fe03a082 | 752 | #define TIM_DMABASE_CNT (0x00000009) |
mbed_official | 573:ad23fe03a082 | 753 | #define TIM_DMABASE_PSC (0x0000000A) |
mbed_official | 573:ad23fe03a082 | 754 | #define TIM_DMABASE_ARR (0x0000000B) |
mbed_official | 573:ad23fe03a082 | 755 | #define TIM_DMABASE_RCR (0x0000000C) |
mbed_official | 573:ad23fe03a082 | 756 | #define TIM_DMABASE_CCR1 (0x0000000D) |
mbed_official | 573:ad23fe03a082 | 757 | #define TIM_DMABASE_CCR2 (0x0000000E) |
mbed_official | 573:ad23fe03a082 | 758 | #define TIM_DMABASE_CCR3 (0x0000000F) |
mbed_official | 573:ad23fe03a082 | 759 | #define TIM_DMABASE_CCR4 (0x00000010) |
mbed_official | 573:ad23fe03a082 | 760 | #define TIM_DMABASE_BDTR (0x00000011) |
mbed_official | 573:ad23fe03a082 | 761 | #define TIM_DMABASE_DCR (0x00000012) |
mbed_official | 573:ad23fe03a082 | 762 | #define TIM_DMABASE_OR (0x00000013) |
mbed_official | 573:ad23fe03a082 | 763 | /** |
mbed_official | 573:ad23fe03a082 | 764 | * @} |
mbed_official | 573:ad23fe03a082 | 765 | */ |
mbed_official | 573:ad23fe03a082 | 766 | |
mbed_official | 573:ad23fe03a082 | 767 | /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length |
mbed_official | 573:ad23fe03a082 | 768 | * @{ |
mbed_official | 573:ad23fe03a082 | 769 | */ |
mbed_official | 573:ad23fe03a082 | 770 | #define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000) |
mbed_official | 573:ad23fe03a082 | 771 | #define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100) |
mbed_official | 573:ad23fe03a082 | 772 | #define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200) |
mbed_official | 573:ad23fe03a082 | 773 | #define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300) |
mbed_official | 573:ad23fe03a082 | 774 | #define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400) |
mbed_official | 573:ad23fe03a082 | 775 | #define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500) |
mbed_official | 573:ad23fe03a082 | 776 | #define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600) |
mbed_official | 573:ad23fe03a082 | 777 | #define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700) |
mbed_official | 573:ad23fe03a082 | 778 | #define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800) |
mbed_official | 573:ad23fe03a082 | 779 | #define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900) |
mbed_official | 573:ad23fe03a082 | 780 | #define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00) |
mbed_official | 573:ad23fe03a082 | 781 | #define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00) |
mbed_official | 573:ad23fe03a082 | 782 | #define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00) |
mbed_official | 573:ad23fe03a082 | 783 | #define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00) |
mbed_official | 573:ad23fe03a082 | 784 | #define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00) |
mbed_official | 573:ad23fe03a082 | 785 | #define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00) |
mbed_official | 573:ad23fe03a082 | 786 | #define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000) |
mbed_official | 573:ad23fe03a082 | 787 | #define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100) |
mbed_official | 573:ad23fe03a082 | 788 | /** |
mbed_official | 573:ad23fe03a082 | 789 | * @} |
mbed_official | 573:ad23fe03a082 | 790 | */ |
mbed_official | 573:ad23fe03a082 | 791 | |
mbed_official | 573:ad23fe03a082 | 792 | /** @defgroup DMA_Handle_index DMA Handle index |
mbed_official | 573:ad23fe03a082 | 793 | * @{ |
mbed_official | 573:ad23fe03a082 | 794 | */ |
mbed_official | 573:ad23fe03a082 | 795 | #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */ |
mbed_official | 573:ad23fe03a082 | 796 | #define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ |
mbed_official | 573:ad23fe03a082 | 797 | #define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ |
mbed_official | 573:ad23fe03a082 | 798 | #define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ |
mbed_official | 573:ad23fe03a082 | 799 | #define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ |
mbed_official | 573:ad23fe03a082 | 800 | #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /*!< Index of the DMA handle used for Commutation DMA requests */ |
mbed_official | 573:ad23fe03a082 | 801 | #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */ |
mbed_official | 573:ad23fe03a082 | 802 | /** |
mbed_official | 573:ad23fe03a082 | 803 | * @} |
mbed_official | 573:ad23fe03a082 | 804 | */ |
mbed_official | 573:ad23fe03a082 | 805 | |
mbed_official | 573:ad23fe03a082 | 806 | /** @defgroup Channel_CC_State Channel CC State |
mbed_official | 573:ad23fe03a082 | 807 | * @{ |
mbed_official | 573:ad23fe03a082 | 808 | */ |
mbed_official | 573:ad23fe03a082 | 809 | #define TIM_CCx_ENABLE ((uint32_t)0x0001) |
mbed_official | 573:ad23fe03a082 | 810 | #define TIM_CCx_DISABLE ((uint32_t)0x0000) |
mbed_official | 573:ad23fe03a082 | 811 | #define TIM_CCxN_ENABLE ((uint32_t)0x0004) |
mbed_official | 573:ad23fe03a082 | 812 | #define TIM_CCxN_DISABLE ((uint32_t)0x0000) |
mbed_official | 573:ad23fe03a082 | 813 | /** |
mbed_official | 573:ad23fe03a082 | 814 | * @} |
mbed_official | 573:ad23fe03a082 | 815 | */ |
mbed_official | 573:ad23fe03a082 | 816 | |
mbed_official | 573:ad23fe03a082 | 817 | /** |
mbed_official | 573:ad23fe03a082 | 818 | * @} |
mbed_official | 573:ad23fe03a082 | 819 | */ |
mbed_official | 573:ad23fe03a082 | 820 | |
mbed_official | 573:ad23fe03a082 | 821 | /* Exported macro ------------------------------------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 822 | /** @defgroup TIM_Exported_Macros TIM Exported Macros |
mbed_official | 573:ad23fe03a082 | 823 | * @{ |
mbed_official | 573:ad23fe03a082 | 824 | */ |
mbed_official | 573:ad23fe03a082 | 825 | /** @brief Reset TIM handle state |
mbed_official | 573:ad23fe03a082 | 826 | * @param __HANDLE__: TIM handle |
mbed_official | 573:ad23fe03a082 | 827 | * @retval None |
mbed_official | 573:ad23fe03a082 | 828 | */ |
mbed_official | 573:ad23fe03a082 | 829 | #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) |
mbed_official | 573:ad23fe03a082 | 830 | |
mbed_official | 573:ad23fe03a082 | 831 | /** |
mbed_official | 573:ad23fe03a082 | 832 | * @brief Enable the TIM peripheral. |
mbed_official | 573:ad23fe03a082 | 833 | * @param __HANDLE__: TIM handle |
mbed_official | 573:ad23fe03a082 | 834 | * @retval None |
mbed_official | 573:ad23fe03a082 | 835 | */ |
mbed_official | 573:ad23fe03a082 | 836 | #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) |
mbed_official | 573:ad23fe03a082 | 837 | |
mbed_official | 573:ad23fe03a082 | 838 | /** |
mbed_official | 573:ad23fe03a082 | 839 | * @brief Enable the TIM update source request. |
mbed_official | 573:ad23fe03a082 | 840 | * @param __HANDLE__: TIM handle |
mbed_official | 573:ad23fe03a082 | 841 | * @retval None |
mbed_official | 573:ad23fe03a082 | 842 | */ |
mbed_official | 573:ad23fe03a082 | 843 | #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_URS)) |
mbed_official | 573:ad23fe03a082 | 844 | |
mbed_official | 573:ad23fe03a082 | 845 | /** |
mbed_official | 573:ad23fe03a082 | 846 | * @brief Enable the TIM main Output. |
mbed_official | 573:ad23fe03a082 | 847 | * @param __HANDLE__: TIM handle |
mbed_official | 573:ad23fe03a082 | 848 | * @retval None |
mbed_official | 573:ad23fe03a082 | 849 | */ |
mbed_official | 573:ad23fe03a082 | 850 | #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) |
mbed_official | 573:ad23fe03a082 | 851 | |
mbed_official | 573:ad23fe03a082 | 852 | |
mbed_official | 573:ad23fe03a082 | 853 | /* The counter of a timer instance is disabled only if all the CCx and CCxN |
mbed_official | 573:ad23fe03a082 | 854 | channels have been disabled */ |
mbed_official | 573:ad23fe03a082 | 855 | #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) |
mbed_official | 573:ad23fe03a082 | 856 | #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) |
mbed_official | 573:ad23fe03a082 | 857 | |
mbed_official | 573:ad23fe03a082 | 858 | /** |
mbed_official | 573:ad23fe03a082 | 859 | * @brief Disable the TIM peripheral. |
mbed_official | 573:ad23fe03a082 | 860 | * @param __HANDLE__: TIM handle |
mbed_official | 573:ad23fe03a082 | 861 | * @retval None |
mbed_official | 573:ad23fe03a082 | 862 | */ |
mbed_official | 573:ad23fe03a082 | 863 | #define __HAL_TIM_DISABLE(__HANDLE__) \ |
mbed_official | 573:ad23fe03a082 | 864 | do { \ |
mbed_official | 573:ad23fe03a082 | 865 | if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \ |
mbed_official | 573:ad23fe03a082 | 866 | { \ |
mbed_official | 573:ad23fe03a082 | 867 | if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \ |
mbed_official | 573:ad23fe03a082 | 868 | { \ |
mbed_official | 573:ad23fe03a082 | 869 | (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ |
mbed_official | 573:ad23fe03a082 | 870 | } \ |
mbed_official | 573:ad23fe03a082 | 871 | } \ |
mbed_official | 573:ad23fe03a082 | 872 | } while(0) |
mbed_official | 573:ad23fe03a082 | 873 | |
mbed_official | 573:ad23fe03a082 | 874 | /** |
mbed_official | 573:ad23fe03a082 | 875 | * @brief Disable the TIM update source request. |
mbed_official | 573:ad23fe03a082 | 876 | * @param __HANDLE__: TIM handle |
mbed_official | 573:ad23fe03a082 | 877 | * @retval None |
mbed_official | 573:ad23fe03a082 | 878 | */ |
mbed_official | 573:ad23fe03a082 | 879 | #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS)) |
mbed_official | 573:ad23fe03a082 | 880 | |
mbed_official | 573:ad23fe03a082 | 881 | |
mbed_official | 573:ad23fe03a082 | 882 | /* The Main Output of a timer instance is disabled only if all the CCx and CCxN |
mbed_official | 573:ad23fe03a082 | 883 | channels have been disabled */ |
mbed_official | 573:ad23fe03a082 | 884 | /** |
mbed_official | 573:ad23fe03a082 | 885 | * @brief Disable the TIM main Output. |
mbed_official | 573:ad23fe03a082 | 886 | * @param __HANDLE__: TIM handle |
mbed_official | 573:ad23fe03a082 | 887 | * @retval None |
mbed_official | 573:ad23fe03a082 | 888 | */ |
mbed_official | 573:ad23fe03a082 | 889 | #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ |
mbed_official | 573:ad23fe03a082 | 890 | do { \ |
mbed_official | 573:ad23fe03a082 | 891 | if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \ |
mbed_official | 573:ad23fe03a082 | 892 | { \ |
mbed_official | 573:ad23fe03a082 | 893 | if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \ |
mbed_official | 573:ad23fe03a082 | 894 | { \ |
mbed_official | 573:ad23fe03a082 | 895 | (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ |
mbed_official | 573:ad23fe03a082 | 896 | } \ |
mbed_official | 573:ad23fe03a082 | 897 | } \ |
mbed_official | 573:ad23fe03a082 | 898 | } while(0) |
mbed_official | 573:ad23fe03a082 | 899 | |
mbed_official | 573:ad23fe03a082 | 900 | #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) |
mbed_official | 573:ad23fe03a082 | 901 | #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) |
mbed_official | 573:ad23fe03a082 | 902 | #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) |
mbed_official | 573:ad23fe03a082 | 903 | #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) |
mbed_official | 573:ad23fe03a082 | 904 | #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) |
mbed_official | 573:ad23fe03a082 | 905 | #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) |
mbed_official | 573:ad23fe03a082 | 906 | |
mbed_official | 573:ad23fe03a082 | 907 | #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
mbed_official | 573:ad23fe03a082 | 908 | #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) |
mbed_official | 573:ad23fe03a082 | 909 | |
mbed_official | 573:ad23fe03a082 | 910 | #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) |
mbed_official | 573:ad23fe03a082 | 911 | #define __HAL_TIM_SET_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) |
mbed_official | 573:ad23fe03a082 | 912 | |
mbed_official | 573:ad23fe03a082 | 913 | #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ |
mbed_official | 573:ad23fe03a082 | 914 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ |
mbed_official | 573:ad23fe03a082 | 915 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\ |
mbed_official | 573:ad23fe03a082 | 916 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ |
mbed_official | 573:ad23fe03a082 | 917 | ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8))) |
mbed_official | 573:ad23fe03a082 | 918 | |
mbed_official | 573:ad23fe03a082 | 919 | #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ |
mbed_official | 573:ad23fe03a082 | 920 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\ |
mbed_official | 573:ad23fe03a082 | 921 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\ |
mbed_official | 573:ad23fe03a082 | 922 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\ |
mbed_official | 573:ad23fe03a082 | 923 | ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC)) |
mbed_official | 573:ad23fe03a082 | 924 | |
mbed_official | 573:ad23fe03a082 | 925 | #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ |
mbed_official | 573:ad23fe03a082 | 926 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ |
mbed_official | 573:ad23fe03a082 | 927 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\ |
mbed_official | 573:ad23fe03a082 | 928 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\ |
mbed_official | 573:ad23fe03a082 | 929 | ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P))) |
mbed_official | 573:ad23fe03a082 | 930 | |
mbed_official | 573:ad23fe03a082 | 931 | #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ |
mbed_official | 573:ad23fe03a082 | 932 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ |
mbed_official | 573:ad23fe03a082 | 933 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ |
mbed_official | 573:ad23fe03a082 | 934 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ |
mbed_official | 573:ad23fe03a082 | 935 | ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P)) |
mbed_official | 573:ad23fe03a082 | 936 | |
mbed_official | 573:ad23fe03a082 | 937 | /** |
mbed_official | 573:ad23fe03a082 | 938 | * @brief Sets the TIM Counter Register value on runtime. |
mbed_official | 573:ad23fe03a082 | 939 | * @param __HANDLE__: TIM handle. |
mbed_official | 573:ad23fe03a082 | 940 | * @param __COUNTER__: specifies the Counter register new value. |
mbed_official | 573:ad23fe03a082 | 941 | * @retval None |
mbed_official | 573:ad23fe03a082 | 942 | */ |
mbed_official | 573:ad23fe03a082 | 943 | #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) |
mbed_official | 573:ad23fe03a082 | 944 | |
mbed_official | 573:ad23fe03a082 | 945 | /** |
mbed_official | 573:ad23fe03a082 | 946 | * @brief Gets the TIM Counter Register value on runtime. |
mbed_official | 573:ad23fe03a082 | 947 | * @param __HANDLE__: TIM handle. |
mbed_official | 573:ad23fe03a082 | 948 | * @retval None |
mbed_official | 573:ad23fe03a082 | 949 | */ |
mbed_official | 573:ad23fe03a082 | 950 | #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) |
mbed_official | 573:ad23fe03a082 | 951 | |
mbed_official | 573:ad23fe03a082 | 952 | /** |
mbed_official | 573:ad23fe03a082 | 953 | * @brief Sets the TIM Autoreload Register value on runtime without calling |
mbed_official | 573:ad23fe03a082 | 954 | * another time any Init function. |
mbed_official | 573:ad23fe03a082 | 955 | * @param __HANDLE__: TIM handle. |
mbed_official | 573:ad23fe03a082 | 956 | * @param __AUTORELOAD__: specifies the Counter register new value. |
mbed_official | 573:ad23fe03a082 | 957 | * @retval None |
mbed_official | 573:ad23fe03a082 | 958 | */ |
mbed_official | 573:ad23fe03a082 | 959 | #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ |
mbed_official | 573:ad23fe03a082 | 960 | do{ \ |
mbed_official | 573:ad23fe03a082 | 961 | (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ |
mbed_official | 573:ad23fe03a082 | 962 | (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ |
mbed_official | 573:ad23fe03a082 | 963 | } while(0) |
mbed_official | 573:ad23fe03a082 | 964 | /** |
mbed_official | 573:ad23fe03a082 | 965 | * @brief Gets the TIM Autoreload Register value on runtime |
mbed_official | 573:ad23fe03a082 | 966 | * @param __HANDLE__: TIM handle. |
mbed_official | 573:ad23fe03a082 | 967 | * @retval None |
mbed_official | 573:ad23fe03a082 | 968 | */ |
mbed_official | 573:ad23fe03a082 | 969 | #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) |
mbed_official | 573:ad23fe03a082 | 970 | |
mbed_official | 573:ad23fe03a082 | 971 | /** |
mbed_official | 573:ad23fe03a082 | 972 | * @brief Sets the TIM Clock Division value on runtime without calling |
mbed_official | 573:ad23fe03a082 | 973 | * another time any Init function. |
mbed_official | 573:ad23fe03a082 | 974 | * @param __HANDLE__: TIM handle. |
mbed_official | 573:ad23fe03a082 | 975 | * @param __CKD__: specifies the clock division value. |
mbed_official | 573:ad23fe03a082 | 976 | * This parameter can be one of the following value: |
mbed_official | 573:ad23fe03a082 | 977 | * @arg TIM_CLOCKDIVISION_DIV1 |
mbed_official | 573:ad23fe03a082 | 978 | * @arg TIM_CLOCKDIVISION_DIV2 |
mbed_official | 573:ad23fe03a082 | 979 | * @arg TIM_CLOCKDIVISION_DIV4 |
mbed_official | 573:ad23fe03a082 | 980 | * @retval None |
mbed_official | 573:ad23fe03a082 | 981 | */ |
mbed_official | 573:ad23fe03a082 | 982 | #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ |
mbed_official | 573:ad23fe03a082 | 983 | do{ \ |
mbed_official | 573:ad23fe03a082 | 984 | (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \ |
mbed_official | 573:ad23fe03a082 | 985 | (__HANDLE__)->Instance->CR1 |= (__CKD__); \ |
mbed_official | 573:ad23fe03a082 | 986 | (__HANDLE__)->Init.ClockDivision = (__CKD__); \ |
mbed_official | 573:ad23fe03a082 | 987 | } while(0) |
mbed_official | 573:ad23fe03a082 | 988 | /** |
mbed_official | 573:ad23fe03a082 | 989 | * @brief Gets the TIM Clock Division value on runtime |
mbed_official | 573:ad23fe03a082 | 990 | * @param __HANDLE__: TIM handle. |
mbed_official | 573:ad23fe03a082 | 991 | * @retval None |
mbed_official | 573:ad23fe03a082 | 992 | */ |
mbed_official | 573:ad23fe03a082 | 993 | #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) |
mbed_official | 573:ad23fe03a082 | 994 | |
mbed_official | 573:ad23fe03a082 | 995 | /** |
mbed_official | 573:ad23fe03a082 | 996 | * @brief Sets the TIM Input Capture prescaler on runtime without calling |
mbed_official | 573:ad23fe03a082 | 997 | * another time HAL_TIM_IC_ConfigChannel() function. |
mbed_official | 573:ad23fe03a082 | 998 | * @param __HANDLE__: TIM handle. |
mbed_official | 573:ad23fe03a082 | 999 | * @param __CHANNEL__ : TIM Channels to be configured. |
mbed_official | 573:ad23fe03a082 | 1000 | * This parameter can be one of the following values: |
mbed_official | 573:ad23fe03a082 | 1001 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
mbed_official | 573:ad23fe03a082 | 1002 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
mbed_official | 573:ad23fe03a082 | 1003 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
mbed_official | 573:ad23fe03a082 | 1004 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
mbed_official | 573:ad23fe03a082 | 1005 | * @param __ICPSC__: specifies the Input Capture4 prescaler new value. |
mbed_official | 573:ad23fe03a082 | 1006 | * This parameter can be one of the following values: |
mbed_official | 573:ad23fe03a082 | 1007 | * @arg TIM_ICPSC_DIV1: no prescaler |
mbed_official | 573:ad23fe03a082 | 1008 | * @arg TIM_ICPSC_DIV2: capture is done once every 2 events |
mbed_official | 573:ad23fe03a082 | 1009 | * @arg TIM_ICPSC_DIV4: capture is done once every 4 events |
mbed_official | 573:ad23fe03a082 | 1010 | * @arg TIM_ICPSC_DIV8: capture is done once every 8 events |
mbed_official | 573:ad23fe03a082 | 1011 | * @retval None |
mbed_official | 573:ad23fe03a082 | 1012 | */ |
mbed_official | 573:ad23fe03a082 | 1013 | #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ |
mbed_official | 573:ad23fe03a082 | 1014 | do{ \ |
mbed_official | 573:ad23fe03a082 | 1015 | TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ |
mbed_official | 573:ad23fe03a082 | 1016 | TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ |
mbed_official | 573:ad23fe03a082 | 1017 | } while(0) |
mbed_official | 573:ad23fe03a082 | 1018 | |
mbed_official | 573:ad23fe03a082 | 1019 | /** |
mbed_official | 573:ad23fe03a082 | 1020 | * @brief Gets the TIM Input Capture prescaler on runtime |
mbed_official | 573:ad23fe03a082 | 1021 | * @param __HANDLE__: TIM handle. |
mbed_official | 573:ad23fe03a082 | 1022 | * @param __CHANNEL__ : TIM Channels to be configured. |
mbed_official | 573:ad23fe03a082 | 1023 | * This parameter can be one of the following values: |
mbed_official | 573:ad23fe03a082 | 1024 | * @arg TIM_CHANNEL_1: get input capture 1 prescaler value |
mbed_official | 573:ad23fe03a082 | 1025 | * @arg TIM_CHANNEL_2: get input capture 2 prescaler value |
mbed_official | 573:ad23fe03a082 | 1026 | * @arg TIM_CHANNEL_3: get input capture 3 prescaler value |
mbed_official | 573:ad23fe03a082 | 1027 | * @arg TIM_CHANNEL_4: get input capture 4 prescaler value |
mbed_official | 573:ad23fe03a082 | 1028 | * @retval None |
mbed_official | 573:ad23fe03a082 | 1029 | */ |
mbed_official | 573:ad23fe03a082 | 1030 | #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ |
mbed_official | 573:ad23fe03a082 | 1031 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ |
mbed_official | 573:ad23fe03a082 | 1032 | ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\ |
mbed_official | 573:ad23fe03a082 | 1033 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ |
mbed_official | 573:ad23fe03a082 | 1034 | (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8) |
mbed_official | 573:ad23fe03a082 | 1035 | |
mbed_official | 573:ad23fe03a082 | 1036 | /** |
mbed_official | 573:ad23fe03a082 | 1037 | * @brief Sets the TIM Capture x input polarity on runtime. |
mbed_official | 573:ad23fe03a082 | 1038 | * @param __HANDLE__: TIM handle. |
mbed_official | 573:ad23fe03a082 | 1039 | * @param __CHANNEL__: TIM Channels to be configured. |
mbed_official | 573:ad23fe03a082 | 1040 | * This parameter can be one of the following values: |
mbed_official | 573:ad23fe03a082 | 1041 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
mbed_official | 573:ad23fe03a082 | 1042 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
mbed_official | 573:ad23fe03a082 | 1043 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
mbed_official | 573:ad23fe03a082 | 1044 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
mbed_official | 573:ad23fe03a082 | 1045 | * @param __POLARITY__: Polarity for TIx source |
mbed_official | 573:ad23fe03a082 | 1046 | * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge |
mbed_official | 573:ad23fe03a082 | 1047 | * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge |
mbed_official | 573:ad23fe03a082 | 1048 | * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge |
mbed_official | 573:ad23fe03a082 | 1049 | * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4. |
mbed_official | 573:ad23fe03a082 | 1050 | * @retval None |
mbed_official | 573:ad23fe03a082 | 1051 | */ |
mbed_official | 573:ad23fe03a082 | 1052 | #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ |
mbed_official | 573:ad23fe03a082 | 1053 | do{ \ |
mbed_official | 573:ad23fe03a082 | 1054 | TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ |
mbed_official | 573:ad23fe03a082 | 1055 | TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ |
mbed_official | 573:ad23fe03a082 | 1056 | }while(0) |
mbed_official | 573:ad23fe03a082 | 1057 | |
mbed_official | 573:ad23fe03a082 | 1058 | /** |
mbed_official | 573:ad23fe03a082 | 1059 | * @} |
mbed_official | 573:ad23fe03a082 | 1060 | */ |
mbed_official | 573:ad23fe03a082 | 1061 | |
mbed_official | 573:ad23fe03a082 | 1062 | /* Include TIM HAL Extension module */ |
mbed_official | 573:ad23fe03a082 | 1063 | #include "stm32f7xx_hal_tim_ex.h" |
mbed_official | 573:ad23fe03a082 | 1064 | |
mbed_official | 573:ad23fe03a082 | 1065 | /* Exported functions --------------------------------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 1066 | /** @addtogroup TIM_Exported_Functions |
mbed_official | 573:ad23fe03a082 | 1067 | * @{ |
mbed_official | 573:ad23fe03a082 | 1068 | */ |
mbed_official | 573:ad23fe03a082 | 1069 | |
mbed_official | 573:ad23fe03a082 | 1070 | /** @addtogroup TIM_Exported_Functions_Group1 |
mbed_official | 573:ad23fe03a082 | 1071 | * @{ |
mbed_official | 573:ad23fe03a082 | 1072 | */ |
mbed_official | 573:ad23fe03a082 | 1073 | |
mbed_official | 573:ad23fe03a082 | 1074 | /* Time Base functions ********************************************************/ |
mbed_official | 573:ad23fe03a082 | 1075 | HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1076 | HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1077 | void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1078 | void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1079 | /* Blocking mode: Polling */ |
mbed_official | 573:ad23fe03a082 | 1080 | HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1081 | HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1082 | /* Non-Blocking mode: Interrupt */ |
mbed_official | 573:ad23fe03a082 | 1083 | HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1084 | HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1085 | /* Non-Blocking mode: DMA */ |
mbed_official | 573:ad23fe03a082 | 1086 | HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); |
mbed_official | 573:ad23fe03a082 | 1087 | HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1088 | /** |
mbed_official | 573:ad23fe03a082 | 1089 | * @} |
mbed_official | 573:ad23fe03a082 | 1090 | */ |
mbed_official | 573:ad23fe03a082 | 1091 | |
mbed_official | 573:ad23fe03a082 | 1092 | /** @addtogroup TIM_Exported_Functions_Group2 |
mbed_official | 573:ad23fe03a082 | 1093 | * @{ |
mbed_official | 573:ad23fe03a082 | 1094 | */ |
mbed_official | 573:ad23fe03a082 | 1095 | /* Timer Output Compare functions **********************************************/ |
mbed_official | 573:ad23fe03a082 | 1096 | HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1097 | HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1098 | void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1099 | void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1100 | /* Blocking mode: Polling */ |
mbed_official | 573:ad23fe03a082 | 1101 | HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 573:ad23fe03a082 | 1102 | HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 573:ad23fe03a082 | 1103 | /* Non-Blocking mode: Interrupt */ |
mbed_official | 573:ad23fe03a082 | 1104 | HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 573:ad23fe03a082 | 1105 | HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 573:ad23fe03a082 | 1106 | /* Non-Blocking mode: DMA */ |
mbed_official | 573:ad23fe03a082 | 1107 | HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
mbed_official | 573:ad23fe03a082 | 1108 | HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 573:ad23fe03a082 | 1109 | |
mbed_official | 573:ad23fe03a082 | 1110 | /** |
mbed_official | 573:ad23fe03a082 | 1111 | * @} |
mbed_official | 573:ad23fe03a082 | 1112 | */ |
mbed_official | 573:ad23fe03a082 | 1113 | |
mbed_official | 573:ad23fe03a082 | 1114 | /** @addtogroup TIM_Exported_Functions_Group3 |
mbed_official | 573:ad23fe03a082 | 1115 | * @{ |
mbed_official | 573:ad23fe03a082 | 1116 | */ |
mbed_official | 573:ad23fe03a082 | 1117 | /* Timer PWM functions *********************************************************/ |
mbed_official | 573:ad23fe03a082 | 1118 | HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1119 | HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1120 | void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1121 | void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1122 | /* Blocking mode: Polling */ |
mbed_official | 573:ad23fe03a082 | 1123 | HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 573:ad23fe03a082 | 1124 | HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 573:ad23fe03a082 | 1125 | /* Non-Blocking mode: Interrupt */ |
mbed_official | 573:ad23fe03a082 | 1126 | HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 573:ad23fe03a082 | 1127 | HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 573:ad23fe03a082 | 1128 | /* Non-Blocking mode: DMA */ |
mbed_official | 573:ad23fe03a082 | 1129 | HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
mbed_official | 573:ad23fe03a082 | 1130 | HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 573:ad23fe03a082 | 1131 | |
mbed_official | 573:ad23fe03a082 | 1132 | /** |
mbed_official | 573:ad23fe03a082 | 1133 | * @} |
mbed_official | 573:ad23fe03a082 | 1134 | */ |
mbed_official | 573:ad23fe03a082 | 1135 | |
mbed_official | 573:ad23fe03a082 | 1136 | /** @addtogroup TIM_Exported_Functions_Group4 |
mbed_official | 573:ad23fe03a082 | 1137 | * @{ |
mbed_official | 573:ad23fe03a082 | 1138 | */ |
mbed_official | 573:ad23fe03a082 | 1139 | /* Timer Input Capture functions ***********************************************/ |
mbed_official | 573:ad23fe03a082 | 1140 | HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1141 | HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1142 | void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1143 | void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1144 | /* Blocking mode: Polling */ |
mbed_official | 573:ad23fe03a082 | 1145 | HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 573:ad23fe03a082 | 1146 | HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 573:ad23fe03a082 | 1147 | /* Non-Blocking mode: Interrupt */ |
mbed_official | 573:ad23fe03a082 | 1148 | HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 573:ad23fe03a082 | 1149 | HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 573:ad23fe03a082 | 1150 | /* Non-Blocking mode: DMA */ |
mbed_official | 573:ad23fe03a082 | 1151 | HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
mbed_official | 573:ad23fe03a082 | 1152 | HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 573:ad23fe03a082 | 1153 | |
mbed_official | 573:ad23fe03a082 | 1154 | /** |
mbed_official | 573:ad23fe03a082 | 1155 | * @} |
mbed_official | 573:ad23fe03a082 | 1156 | */ |
mbed_official | 573:ad23fe03a082 | 1157 | |
mbed_official | 573:ad23fe03a082 | 1158 | /** @addtogroup TIM_Exported_Functions_Group5 |
mbed_official | 573:ad23fe03a082 | 1159 | * @{ |
mbed_official | 573:ad23fe03a082 | 1160 | */ |
mbed_official | 573:ad23fe03a082 | 1161 | /* Timer One Pulse functions ***************************************************/ |
mbed_official | 573:ad23fe03a082 | 1162 | HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); |
mbed_official | 573:ad23fe03a082 | 1163 | HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1164 | void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1165 | void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1166 | /* Blocking mode: Polling */ |
mbed_official | 573:ad23fe03a082 | 1167 | HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
mbed_official | 573:ad23fe03a082 | 1168 | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
mbed_official | 573:ad23fe03a082 | 1169 | |
mbed_official | 573:ad23fe03a082 | 1170 | /* Non-Blocking mode: Interrupt */ |
mbed_official | 573:ad23fe03a082 | 1171 | HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
mbed_official | 573:ad23fe03a082 | 1172 | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
mbed_official | 573:ad23fe03a082 | 1173 | |
mbed_official | 573:ad23fe03a082 | 1174 | /** |
mbed_official | 573:ad23fe03a082 | 1175 | * @} |
mbed_official | 573:ad23fe03a082 | 1176 | */ |
mbed_official | 573:ad23fe03a082 | 1177 | |
mbed_official | 573:ad23fe03a082 | 1178 | /** @addtogroup TIM_Exported_Functions_Group6 |
mbed_official | 573:ad23fe03a082 | 1179 | * @{ |
mbed_official | 573:ad23fe03a082 | 1180 | */ |
mbed_official | 573:ad23fe03a082 | 1181 | /* Timer Encoder functions *****************************************************/ |
mbed_official | 573:ad23fe03a082 | 1182 | HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig); |
mbed_official | 573:ad23fe03a082 | 1183 | HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1184 | void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1185 | void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1186 | /* Blocking mode: Polling */ |
mbed_official | 573:ad23fe03a082 | 1187 | HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 573:ad23fe03a082 | 1188 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 573:ad23fe03a082 | 1189 | /* Non-Blocking mode: Interrupt */ |
mbed_official | 573:ad23fe03a082 | 1190 | HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 573:ad23fe03a082 | 1191 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 573:ad23fe03a082 | 1192 | /* Non-Blocking mode: DMA */ |
mbed_official | 573:ad23fe03a082 | 1193 | HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); |
mbed_official | 573:ad23fe03a082 | 1194 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 573:ad23fe03a082 | 1195 | |
mbed_official | 573:ad23fe03a082 | 1196 | /** |
mbed_official | 573:ad23fe03a082 | 1197 | * @} |
mbed_official | 573:ad23fe03a082 | 1198 | */ |
mbed_official | 573:ad23fe03a082 | 1199 | |
mbed_official | 573:ad23fe03a082 | 1200 | /** @addtogroup TIM_Exported_Functions_Group7 |
mbed_official | 573:ad23fe03a082 | 1201 | * @{ |
mbed_official | 573:ad23fe03a082 | 1202 | */ |
mbed_official | 573:ad23fe03a082 | 1203 | /* Interrupt Handler functions **********************************************/ |
mbed_official | 573:ad23fe03a082 | 1204 | void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1205 | |
mbed_official | 573:ad23fe03a082 | 1206 | /** |
mbed_official | 573:ad23fe03a082 | 1207 | * @} |
mbed_official | 573:ad23fe03a082 | 1208 | */ |
mbed_official | 573:ad23fe03a082 | 1209 | |
mbed_official | 573:ad23fe03a082 | 1210 | /** @addtogroup TIM_Exported_Functions_Group8 |
mbed_official | 573:ad23fe03a082 | 1211 | * @{ |
mbed_official | 573:ad23fe03a082 | 1212 | */ |
mbed_official | 573:ad23fe03a082 | 1213 | /* Control functions *********************************************************/ |
mbed_official | 573:ad23fe03a082 | 1214 | HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); |
mbed_official | 573:ad23fe03a082 | 1215 | HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); |
mbed_official | 573:ad23fe03a082 | 1216 | HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel); |
mbed_official | 573:ad23fe03a082 | 1217 | HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel); |
mbed_official | 573:ad23fe03a082 | 1218 | HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel); |
mbed_official | 573:ad23fe03a082 | 1219 | HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig); |
mbed_official | 573:ad23fe03a082 | 1220 | HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); |
mbed_official | 573:ad23fe03a082 | 1221 | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); |
mbed_official | 573:ad23fe03a082 | 1222 | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); |
mbed_official | 573:ad23fe03a082 | 1223 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ |
mbed_official | 573:ad23fe03a082 | 1224 | uint32_t *BurstBuffer, uint32_t BurstLength); |
mbed_official | 573:ad23fe03a082 | 1225 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); |
mbed_official | 573:ad23fe03a082 | 1226 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ |
mbed_official | 573:ad23fe03a082 | 1227 | uint32_t *BurstBuffer, uint32_t BurstLength); |
mbed_official | 573:ad23fe03a082 | 1228 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); |
mbed_official | 573:ad23fe03a082 | 1229 | HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); |
mbed_official | 573:ad23fe03a082 | 1230 | uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 573:ad23fe03a082 | 1231 | |
mbed_official | 573:ad23fe03a082 | 1232 | /** |
mbed_official | 573:ad23fe03a082 | 1233 | * @} |
mbed_official | 573:ad23fe03a082 | 1234 | */ |
mbed_official | 573:ad23fe03a082 | 1235 | |
mbed_official | 573:ad23fe03a082 | 1236 | /** @addtogroup TIM_Exported_Functions_Group9 |
mbed_official | 573:ad23fe03a082 | 1237 | * @{ |
mbed_official | 573:ad23fe03a082 | 1238 | */ |
mbed_official | 573:ad23fe03a082 | 1239 | /* Callback in non blocking modes (Interrupt and DMA) *************************/ |
mbed_official | 573:ad23fe03a082 | 1240 | void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1241 | void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1242 | void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1243 | void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1244 | void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1245 | void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1246 | |
mbed_official | 573:ad23fe03a082 | 1247 | /** |
mbed_official | 573:ad23fe03a082 | 1248 | * @} |
mbed_official | 573:ad23fe03a082 | 1249 | */ |
mbed_official | 573:ad23fe03a082 | 1250 | |
mbed_official | 573:ad23fe03a082 | 1251 | /** @addtogroup TIM_Exported_Functions_Group10 |
mbed_official | 573:ad23fe03a082 | 1252 | * @{ |
mbed_official | 573:ad23fe03a082 | 1253 | */ |
mbed_official | 573:ad23fe03a082 | 1254 | /* Peripheral State functions **************************************************/ |
mbed_official | 573:ad23fe03a082 | 1255 | HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1256 | HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1257 | HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1258 | HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1259 | HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1260 | HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); |
mbed_official | 573:ad23fe03a082 | 1261 | |
mbed_official | 573:ad23fe03a082 | 1262 | /** |
mbed_official | 573:ad23fe03a082 | 1263 | * @} |
mbed_official | 573:ad23fe03a082 | 1264 | */ |
mbed_official | 573:ad23fe03a082 | 1265 | |
mbed_official | 573:ad23fe03a082 | 1266 | /** |
mbed_official | 573:ad23fe03a082 | 1267 | * @} |
mbed_official | 573:ad23fe03a082 | 1268 | */ |
mbed_official | 573:ad23fe03a082 | 1269 | |
mbed_official | 573:ad23fe03a082 | 1270 | /* Private macros ------------------------------------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 1271 | /** @defgroup TIM_Private_Macros TIM Private Macros |
mbed_official | 573:ad23fe03a082 | 1272 | * @{ |
mbed_official | 573:ad23fe03a082 | 1273 | */ |
mbed_official | 573:ad23fe03a082 | 1274 | |
mbed_official | 573:ad23fe03a082 | 1275 | /** @defgroup TIM_IS_TIM_Definitions TIM Private macros to check input parameters |
mbed_official | 573:ad23fe03a082 | 1276 | * @{ |
mbed_official | 573:ad23fe03a082 | 1277 | */ |
mbed_official | 573:ad23fe03a082 | 1278 | #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ |
mbed_official | 573:ad23fe03a082 | 1279 | ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ |
mbed_official | 573:ad23fe03a082 | 1280 | ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ |
mbed_official | 573:ad23fe03a082 | 1281 | ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ |
mbed_official | 573:ad23fe03a082 | 1282 | ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) |
mbed_official | 573:ad23fe03a082 | 1283 | |
mbed_official | 573:ad23fe03a082 | 1284 | #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ |
mbed_official | 573:ad23fe03a082 | 1285 | ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ |
mbed_official | 573:ad23fe03a082 | 1286 | ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) |
mbed_official | 573:ad23fe03a082 | 1287 | |
mbed_official | 573:ad23fe03a082 | 1288 | #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ |
mbed_official | 573:ad23fe03a082 | 1289 | ((__STATE__) == TIM_OCFAST_ENABLE)) |
mbed_official | 573:ad23fe03a082 | 1290 | |
mbed_official | 573:ad23fe03a082 | 1291 | #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \ |
mbed_official | 573:ad23fe03a082 | 1292 | ((STATE) == TIM_OUTPUTSTATE_ENABLE)) |
mbed_official | 573:ad23fe03a082 | 1293 | |
mbed_official | 573:ad23fe03a082 | 1294 | #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \ |
mbed_official | 573:ad23fe03a082 | 1295 | ((STATE) == TIM_OUTPUTNSTATE_ENABLE)) |
mbed_official | 573:ad23fe03a082 | 1296 | |
mbed_official | 573:ad23fe03a082 | 1297 | #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ |
mbed_official | 573:ad23fe03a082 | 1298 | ((__POLARITY__) == TIM_OCPOLARITY_LOW)) |
mbed_official | 573:ad23fe03a082 | 1299 | |
mbed_official | 573:ad23fe03a082 | 1300 | #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ |
mbed_official | 573:ad23fe03a082 | 1301 | ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) |
mbed_official | 573:ad23fe03a082 | 1302 | |
mbed_official | 573:ad23fe03a082 | 1303 | #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ |
mbed_official | 573:ad23fe03a082 | 1304 | ((__STATE__) == TIM_OCIDLESTATE_RESET)) |
mbed_official | 573:ad23fe03a082 | 1305 | |
mbed_official | 573:ad23fe03a082 | 1306 | #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ |
mbed_official | 573:ad23fe03a082 | 1307 | ((__STATE__) == TIM_OCNIDLESTATE_RESET)) |
mbed_official | 573:ad23fe03a082 | 1308 | |
mbed_official | 573:ad23fe03a082 | 1309 | #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ |
mbed_official | 573:ad23fe03a082 | 1310 | ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ |
mbed_official | 573:ad23fe03a082 | 1311 | ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) |
mbed_official | 573:ad23fe03a082 | 1312 | |
mbed_official | 573:ad23fe03a082 | 1313 | #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ |
mbed_official | 573:ad23fe03a082 | 1314 | ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ |
mbed_official | 573:ad23fe03a082 | 1315 | ((__SELECTION__) == TIM_ICSELECTION_TRC)) |
mbed_official | 573:ad23fe03a082 | 1316 | |
mbed_official | 573:ad23fe03a082 | 1317 | #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ |
mbed_official | 573:ad23fe03a082 | 1318 | ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ |
mbed_official | 573:ad23fe03a082 | 1319 | ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ |
mbed_official | 573:ad23fe03a082 | 1320 | ((__PRESCALER__) == TIM_ICPSC_DIV8)) |
mbed_official | 573:ad23fe03a082 | 1321 | |
mbed_official | 573:ad23fe03a082 | 1322 | #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ |
mbed_official | 573:ad23fe03a082 | 1323 | ((__MODE__) == TIM_OPMODE_REPETITIVE)) |
mbed_official | 573:ad23fe03a082 | 1324 | |
mbed_official | 573:ad23fe03a082 | 1325 | #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ |
mbed_official | 573:ad23fe03a082 | 1326 | ((__MODE__) == TIM_ENCODERMODE_TI2) || \ |
mbed_official | 573:ad23fe03a082 | 1327 | ((__MODE__) == TIM_ENCODERMODE_TI12)) |
mbed_official | 573:ad23fe03a082 | 1328 | |
mbed_official | 573:ad23fe03a082 | 1329 | #define IS_TIM_IT(__IT__) ((((__IT__) & 0xFFFFFF00) == 0x00000000) && ((__IT__) != 0x00000000)) |
mbed_official | 573:ad23fe03a082 | 1330 | |
mbed_official | 573:ad23fe03a082 | 1331 | |
mbed_official | 573:ad23fe03a082 | 1332 | #define IS_TIM_GET_IT(__IT__) (((__IT__) == TIM_IT_UPDATE) || \ |
mbed_official | 573:ad23fe03a082 | 1333 | ((__IT__) == TIM_IT_CC1) || \ |
mbed_official | 573:ad23fe03a082 | 1334 | ((__IT__) == TIM_IT_CC2) || \ |
mbed_official | 573:ad23fe03a082 | 1335 | ((__IT__) == TIM_IT_CC3) || \ |
mbed_official | 573:ad23fe03a082 | 1336 | ((__IT__) == TIM_IT_CC4) || \ |
mbed_official | 573:ad23fe03a082 | 1337 | ((__IT__) == TIM_IT_COM) || \ |
mbed_official | 573:ad23fe03a082 | 1338 | ((__IT__) == TIM_IT_TRIGGER) || \ |
mbed_official | 573:ad23fe03a082 | 1339 | ((__IT__) == TIM_IT_BREAK)) |
mbed_official | 573:ad23fe03a082 | 1340 | |
mbed_official | 573:ad23fe03a082 | 1341 | #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FF) == 0x00000000) && ((__SOURCE__) != 0x00000000)) |
mbed_official | 573:ad23fe03a082 | 1342 | |
mbed_official | 573:ad23fe03a082 | 1343 | #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00) == 0x00000000) && ((__SOURCE__) != 0x00000000)) |
mbed_official | 573:ad23fe03a082 | 1344 | |
mbed_official | 573:ad23fe03a082 | 1345 | #define IS_TIM_FLAG(__FLAG__) (((__FLAG__) == TIM_FLAG_UPDATE) || \ |
mbed_official | 573:ad23fe03a082 | 1346 | ((__FLAG__) == TIM_FLAG_CC1) || \ |
mbed_official | 573:ad23fe03a082 | 1347 | ((__FLAG__) == TIM_FLAG_CC2) || \ |
mbed_official | 573:ad23fe03a082 | 1348 | ((__FLAG__) == TIM_FLAG_CC3) || \ |
mbed_official | 573:ad23fe03a082 | 1349 | ((__FLAG__) == TIM_FLAG_CC4) || \ |
mbed_official | 573:ad23fe03a082 | 1350 | ((__FLAG__) == TIM_FLAG_COM) || \ |
mbed_official | 573:ad23fe03a082 | 1351 | ((__FLAG__) == TIM_FLAG_TRIGGER) || \ |
mbed_official | 573:ad23fe03a082 | 1352 | ((__FLAG__) == TIM_FLAG_BREAK) || \ |
mbed_official | 573:ad23fe03a082 | 1353 | ((__FLAG__) == TIM_FLAG_BREAK2) || \ |
mbed_official | 573:ad23fe03a082 | 1354 | ((__FLAG__) == TIM_FLAG_CC1OF) || \ |
mbed_official | 573:ad23fe03a082 | 1355 | ((__FLAG__) == TIM_FLAG_CC2OF) || \ |
mbed_official | 573:ad23fe03a082 | 1356 | ((__FLAG__) == TIM_FLAG_CC3OF) || \ |
mbed_official | 573:ad23fe03a082 | 1357 | ((__FLAG__) == TIM_FLAG_CC4OF)) |
mbed_official | 573:ad23fe03a082 | 1358 | |
mbed_official | 573:ad23fe03a082 | 1359 | #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ |
mbed_official | 573:ad23fe03a082 | 1360 | ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ |
mbed_official | 573:ad23fe03a082 | 1361 | ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ |
mbed_official | 573:ad23fe03a082 | 1362 | ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ |
mbed_official | 573:ad23fe03a082 | 1363 | ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ |
mbed_official | 573:ad23fe03a082 | 1364 | ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ |
mbed_official | 573:ad23fe03a082 | 1365 | ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ |
mbed_official | 573:ad23fe03a082 | 1366 | ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ |
mbed_official | 573:ad23fe03a082 | 1367 | ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ |
mbed_official | 573:ad23fe03a082 | 1368 | ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) |
mbed_official | 573:ad23fe03a082 | 1369 | |
mbed_official | 573:ad23fe03a082 | 1370 | #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ |
mbed_official | 573:ad23fe03a082 | 1371 | ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ |
mbed_official | 573:ad23fe03a082 | 1372 | ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ |
mbed_official | 573:ad23fe03a082 | 1373 | ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ |
mbed_official | 573:ad23fe03a082 | 1374 | ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) |
mbed_official | 573:ad23fe03a082 | 1375 | |
mbed_official | 573:ad23fe03a082 | 1376 | #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ |
mbed_official | 573:ad23fe03a082 | 1377 | ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ |
mbed_official | 573:ad23fe03a082 | 1378 | ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ |
mbed_official | 573:ad23fe03a082 | 1379 | ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) |
mbed_official | 573:ad23fe03a082 | 1380 | |
mbed_official | 573:ad23fe03a082 | 1381 | #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF) |
mbed_official | 573:ad23fe03a082 | 1382 | |
mbed_official | 573:ad23fe03a082 | 1383 | #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ |
mbed_official | 573:ad23fe03a082 | 1384 | ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) |
mbed_official | 573:ad23fe03a082 | 1385 | |
mbed_official | 573:ad23fe03a082 | 1386 | #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ |
mbed_official | 573:ad23fe03a082 | 1387 | ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ |
mbed_official | 573:ad23fe03a082 | 1388 | ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ |
mbed_official | 573:ad23fe03a082 | 1389 | ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) |
mbed_official | 573:ad23fe03a082 | 1390 | |
mbed_official | 573:ad23fe03a082 | 1391 | #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF) |
mbed_official | 573:ad23fe03a082 | 1392 | |
mbed_official | 573:ad23fe03a082 | 1393 | #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ |
mbed_official | 573:ad23fe03a082 | 1394 | ((__STATE__) == TIM_OSSR_DISABLE)) |
mbed_official | 573:ad23fe03a082 | 1395 | |
mbed_official | 573:ad23fe03a082 | 1396 | #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ |
mbed_official | 573:ad23fe03a082 | 1397 | ((__STATE__) == TIM_OSSI_DISABLE)) |
mbed_official | 573:ad23fe03a082 | 1398 | |
mbed_official | 573:ad23fe03a082 | 1399 | #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ |
mbed_official | 573:ad23fe03a082 | 1400 | ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ |
mbed_official | 573:ad23fe03a082 | 1401 | ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ |
mbed_official | 573:ad23fe03a082 | 1402 | ((__LEVEL__) == TIM_LOCKLEVEL_3)) |
mbed_official | 573:ad23fe03a082 | 1403 | |
mbed_official | 573:ad23fe03a082 | 1404 | #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ |
mbed_official | 573:ad23fe03a082 | 1405 | ((__STATE__) == TIM_BREAK_DISABLE)) |
mbed_official | 573:ad23fe03a082 | 1406 | |
mbed_official | 573:ad23fe03a082 | 1407 | #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ |
mbed_official | 573:ad23fe03a082 | 1408 | ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) |
mbed_official | 573:ad23fe03a082 | 1409 | |
mbed_official | 573:ad23fe03a082 | 1410 | #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ |
mbed_official | 573:ad23fe03a082 | 1411 | ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) |
mbed_official | 573:ad23fe03a082 | 1412 | |
mbed_official | 573:ad23fe03a082 | 1413 | #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ |
mbed_official | 573:ad23fe03a082 | 1414 | ((__SOURCE__) == TIM_TRGO_ENABLE) || \ |
mbed_official | 573:ad23fe03a082 | 1415 | ((__SOURCE__) == TIM_TRGO_UPDATE) || \ |
mbed_official | 573:ad23fe03a082 | 1416 | ((__SOURCE__) == TIM_TRGO_OC1) || \ |
mbed_official | 573:ad23fe03a082 | 1417 | ((__SOURCE__) == TIM_TRGO_OC1REF) || \ |
mbed_official | 573:ad23fe03a082 | 1418 | ((__SOURCE__) == TIM_TRGO_OC2REF) || \ |
mbed_official | 573:ad23fe03a082 | 1419 | ((__SOURCE__) == TIM_TRGO_OC3REF) || \ |
mbed_official | 573:ad23fe03a082 | 1420 | ((__SOURCE__) == TIM_TRGO_OC4REF)) |
mbed_official | 573:ad23fe03a082 | 1421 | |
mbed_official | 573:ad23fe03a082 | 1422 | #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ |
mbed_official | 573:ad23fe03a082 | 1423 | ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) |
mbed_official | 573:ad23fe03a082 | 1424 | |
mbed_official | 573:ad23fe03a082 | 1425 | #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ |
mbed_official | 573:ad23fe03a082 | 1426 | ((__SELECTION__) == TIM_TS_ITR1) || \ |
mbed_official | 573:ad23fe03a082 | 1427 | ((__SELECTION__) == TIM_TS_ITR2) || \ |
mbed_official | 573:ad23fe03a082 | 1428 | ((__SELECTION__) == TIM_TS_ITR3) || \ |
mbed_official | 573:ad23fe03a082 | 1429 | ((__SELECTION__) == TIM_TS_TI1F_ED) || \ |
mbed_official | 573:ad23fe03a082 | 1430 | ((__SELECTION__) == TIM_TS_TI1FP1) || \ |
mbed_official | 573:ad23fe03a082 | 1431 | ((__SELECTION__) == TIM_TS_TI2FP2) || \ |
mbed_official | 573:ad23fe03a082 | 1432 | ((__SELECTION__) == TIM_TS_ETRF)) |
mbed_official | 573:ad23fe03a082 | 1433 | |
mbed_official | 573:ad23fe03a082 | 1434 | #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ |
mbed_official | 573:ad23fe03a082 | 1435 | ((SELECTION) == TIM_TS_ITR1) || \ |
mbed_official | 573:ad23fe03a082 | 1436 | ((SELECTION) == TIM_TS_ITR2) || \ |
mbed_official | 573:ad23fe03a082 | 1437 | ((SELECTION) == TIM_TS_ITR3)) |
mbed_official | 573:ad23fe03a082 | 1438 | |
mbed_official | 573:ad23fe03a082 | 1439 | #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ |
mbed_official | 573:ad23fe03a082 | 1440 | ((__SELECTION__) == TIM_TS_ITR1) || \ |
mbed_official | 573:ad23fe03a082 | 1441 | ((__SELECTION__) == TIM_TS_ITR2) || \ |
mbed_official | 573:ad23fe03a082 | 1442 | ((__SELECTION__) == TIM_TS_ITR3) || \ |
mbed_official | 573:ad23fe03a082 | 1443 | ((__SELECTION__) == TIM_TS_NONE)) |
mbed_official | 573:ad23fe03a082 | 1444 | |
mbed_official | 573:ad23fe03a082 | 1445 | #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ |
mbed_official | 573:ad23fe03a082 | 1446 | ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ |
mbed_official | 573:ad23fe03a082 | 1447 | ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ |
mbed_official | 573:ad23fe03a082 | 1448 | ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ |
mbed_official | 573:ad23fe03a082 | 1449 | ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) |
mbed_official | 573:ad23fe03a082 | 1450 | |
mbed_official | 573:ad23fe03a082 | 1451 | #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ |
mbed_official | 573:ad23fe03a082 | 1452 | ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ |
mbed_official | 573:ad23fe03a082 | 1453 | ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ |
mbed_official | 573:ad23fe03a082 | 1454 | ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) |
mbed_official | 573:ad23fe03a082 | 1455 | |
mbed_official | 573:ad23fe03a082 | 1456 | #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF) |
mbed_official | 573:ad23fe03a082 | 1457 | |
mbed_official | 573:ad23fe03a082 | 1458 | #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ |
mbed_official | 573:ad23fe03a082 | 1459 | ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) |
mbed_official | 573:ad23fe03a082 | 1460 | |
mbed_official | 573:ad23fe03a082 | 1461 | #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ |
mbed_official | 573:ad23fe03a082 | 1462 | ((__BASE__) == TIM_DMABASE_CR2) || \ |
mbed_official | 573:ad23fe03a082 | 1463 | ((__BASE__) == TIM_DMABASE_SMCR) || \ |
mbed_official | 573:ad23fe03a082 | 1464 | ((__BASE__) == TIM_DMABASE_DIER) || \ |
mbed_official | 573:ad23fe03a082 | 1465 | ((__BASE__) == TIM_DMABASE_SR) || \ |
mbed_official | 573:ad23fe03a082 | 1466 | ((__BASE__) == TIM_DMABASE_EGR) || \ |
mbed_official | 573:ad23fe03a082 | 1467 | ((__BASE__) == TIM_DMABASE_CCMR1) || \ |
mbed_official | 573:ad23fe03a082 | 1468 | ((__BASE__) == TIM_DMABASE_CCMR2) || \ |
mbed_official | 573:ad23fe03a082 | 1469 | ((__BASE__) == TIM_DMABASE_CCER) || \ |
mbed_official | 573:ad23fe03a082 | 1470 | ((__BASE__) == TIM_DMABASE_CNT) || \ |
mbed_official | 573:ad23fe03a082 | 1471 | ((__BASE__) == TIM_DMABASE_PSC) || \ |
mbed_official | 573:ad23fe03a082 | 1472 | ((__BASE__) == TIM_DMABASE_ARR) || \ |
mbed_official | 573:ad23fe03a082 | 1473 | ((__BASE__) == TIM_DMABASE_RCR) || \ |
mbed_official | 573:ad23fe03a082 | 1474 | ((__BASE__) == TIM_DMABASE_CCR1) || \ |
mbed_official | 573:ad23fe03a082 | 1475 | ((__BASE__) == TIM_DMABASE_CCR2) || \ |
mbed_official | 573:ad23fe03a082 | 1476 | ((__BASE__) == TIM_DMABASE_CCR3) || \ |
mbed_official | 573:ad23fe03a082 | 1477 | ((__BASE__) == TIM_DMABASE_CCR4) || \ |
mbed_official | 573:ad23fe03a082 | 1478 | ((__BASE__) == TIM_DMABASE_BDTR) || \ |
mbed_official | 573:ad23fe03a082 | 1479 | ((__BASE__) == TIM_DMABASE_DCR) || \ |
mbed_official | 573:ad23fe03a082 | 1480 | ((__BASE__) == TIM_DMABASE_OR)) |
mbed_official | 573:ad23fe03a082 | 1481 | |
mbed_official | 573:ad23fe03a082 | 1482 | #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ |
mbed_official | 573:ad23fe03a082 | 1483 | ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ |
mbed_official | 573:ad23fe03a082 | 1484 | ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ |
mbed_official | 573:ad23fe03a082 | 1485 | ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ |
mbed_official | 573:ad23fe03a082 | 1486 | ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ |
mbed_official | 573:ad23fe03a082 | 1487 | ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ |
mbed_official | 573:ad23fe03a082 | 1488 | ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ |
mbed_official | 573:ad23fe03a082 | 1489 | ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ |
mbed_official | 573:ad23fe03a082 | 1490 | ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ |
mbed_official | 573:ad23fe03a082 | 1491 | ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ |
mbed_official | 573:ad23fe03a082 | 1492 | ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ |
mbed_official | 573:ad23fe03a082 | 1493 | ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ |
mbed_official | 573:ad23fe03a082 | 1494 | ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ |
mbed_official | 573:ad23fe03a082 | 1495 | ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ |
mbed_official | 573:ad23fe03a082 | 1496 | ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ |
mbed_official | 573:ad23fe03a082 | 1497 | ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ |
mbed_official | 573:ad23fe03a082 | 1498 | ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ |
mbed_official | 573:ad23fe03a082 | 1499 | ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) |
mbed_official | 573:ad23fe03a082 | 1500 | |
mbed_official | 573:ad23fe03a082 | 1501 | #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) |
mbed_official | 573:ad23fe03a082 | 1502 | |
mbed_official | 573:ad23fe03a082 | 1503 | |
mbed_official | 573:ad23fe03a082 | 1504 | /** |
mbed_official | 573:ad23fe03a082 | 1505 | * @} |
mbed_official | 573:ad23fe03a082 | 1506 | */ |
mbed_official | 573:ad23fe03a082 | 1507 | |
mbed_official | 573:ad23fe03a082 | 1508 | /** |
mbed_official | 573:ad23fe03a082 | 1509 | * @} |
mbed_official | 573:ad23fe03a082 | 1510 | */ |
mbed_official | 573:ad23fe03a082 | 1511 | |
mbed_official | 573:ad23fe03a082 | 1512 | /* Private functions ---------------------------------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 1513 | /** @defgroup TIM_Private_Functions TIM Private Functions |
mbed_official | 573:ad23fe03a082 | 1514 | * @{ |
mbed_official | 573:ad23fe03a082 | 1515 | */ |
mbed_official | 573:ad23fe03a082 | 1516 | void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); |
mbed_official | 573:ad23fe03a082 | 1517 | void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); |
mbed_official | 573:ad23fe03a082 | 1518 | void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); |
mbed_official | 573:ad23fe03a082 | 1519 | void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); |
mbed_official | 573:ad23fe03a082 | 1520 | void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); |
mbed_official | 573:ad23fe03a082 | 1521 | void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); |
mbed_official | 573:ad23fe03a082 | 1522 | void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); |
mbed_official | 573:ad23fe03a082 | 1523 | |
mbed_official | 573:ad23fe03a082 | 1524 | void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); |
mbed_official | 573:ad23fe03a082 | 1525 | void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma); |
mbed_official | 573:ad23fe03a082 | 1526 | void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); |
mbed_official | 573:ad23fe03a082 | 1527 | void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState); |
mbed_official | 573:ad23fe03a082 | 1528 | /** |
mbed_official | 573:ad23fe03a082 | 1529 | * @} |
mbed_official | 573:ad23fe03a082 | 1530 | */ |
mbed_official | 573:ad23fe03a082 | 1531 | |
mbed_official | 573:ad23fe03a082 | 1532 | /** |
mbed_official | 573:ad23fe03a082 | 1533 | * @} |
mbed_official | 573:ad23fe03a082 | 1534 | */ |
mbed_official | 573:ad23fe03a082 | 1535 | |
mbed_official | 573:ad23fe03a082 | 1536 | /** |
mbed_official | 573:ad23fe03a082 | 1537 | * @} |
mbed_official | 573:ad23fe03a082 | 1538 | */ |
mbed_official | 573:ad23fe03a082 | 1539 | |
mbed_official | 573:ad23fe03a082 | 1540 | #ifdef __cplusplus |
mbed_official | 573:ad23fe03a082 | 1541 | } |
mbed_official | 573:ad23fe03a082 | 1542 | #endif |
mbed_official | 573:ad23fe03a082 | 1543 | |
mbed_official | 573:ad23fe03a082 | 1544 | #endif /* __STM32F7xx_HAL_TIM_H */ |
mbed_official | 573:ad23fe03a082 | 1545 | |
mbed_official | 573:ad23fe03a082 | 1546 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |