marcus chiou
mbed library sources
Fork of
mbed-src
by 
mbed official
targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_dma.h@600:7d17ca308cd1, 2015-07-31 (annotated)
- Committer:
- mbed_official
- Date:
- Fri Jul 31 14:15:09 2015 +0100
- Revision:
- 600:7d17ca308cd1
- Parent:
- 489:119543c9f674
Synchronized with git revision e4cd8bbd3e05b68e5a7f466c74035a85743d45e0
Full URL: https://github.com/mbedmicro/mbed/commit/e4cd8bbd3e05b68e5a7f466c74035a85743d45e0/
Enable LPC8xx usart when configuring it
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 489:119543c9f674 | 1 | /** |
| mbed_official | 489:119543c9f674 | 2 | ****************************************************************************** |
| mbed_official | 489:119543c9f674 | 3 | * @file stm32f1xx_hal_dma.h |
| mbed_official | 489:119543c9f674 | 4 | * @author MCD Application Team |
| mbed_official | 489:119543c9f674 | 5 | * @version V1.0.0 |
| mbed_official | 489:119543c9f674 | 6 | * @date 15-December-2014 |
| mbed_official | 489:119543c9f674 | 7 | * @brief Header file of DMA HAL module. |
| mbed_official | 489:119543c9f674 | 8 | ****************************************************************************** |
| mbed_official | 489:119543c9f674 | 9 | * @attention |
| mbed_official | 489:119543c9f674 | 10 | * |
| mbed_official | 489:119543c9f674 | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| mbed_official | 489:119543c9f674 | 12 | * |
| mbed_official | 489:119543c9f674 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 489:119543c9f674 | 14 | * are permitted provided that the following conditions are met: |
| mbed_official | 489:119543c9f674 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 489:119543c9f674 | 16 | * this list of conditions and the following disclaimer. |
| mbed_official | 489:119543c9f674 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 489:119543c9f674 | 18 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 489:119543c9f674 | 19 | * and/or other materials provided with the distribution. |
| mbed_official | 489:119543c9f674 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 489:119543c9f674 | 21 | * may be used to endorse or promote products derived from this software |
| mbed_official | 489:119543c9f674 | 22 | * without specific prior written permission. |
| mbed_official | 489:119543c9f674 | 23 | * |
| mbed_official | 489:119543c9f674 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 489:119543c9f674 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 489:119543c9f674 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 489:119543c9f674 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 489:119543c9f674 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 489:119543c9f674 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 489:119543c9f674 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 489:119543c9f674 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 489:119543c9f674 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 489:119543c9f674 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 489:119543c9f674 | 34 | * |
| mbed_official | 489:119543c9f674 | 35 | ****************************************************************************** |
| mbed_official | 489:119543c9f674 | 36 | */ |
| mbed_official | 489:119543c9f674 | 37 | |
| mbed_official | 489:119543c9f674 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| mbed_official | 489:119543c9f674 | 39 | #ifndef __STM32F1xx_HAL_DMA_H |
| mbed_official | 489:119543c9f674 | 40 | #define __STM32F1xx_HAL_DMA_H |
| mbed_official | 489:119543c9f674 | 41 | |
| mbed_official | 489:119543c9f674 | 42 | #ifdef __cplusplus |
| mbed_official | 489:119543c9f674 | 43 | extern "C" { |
| mbed_official | 489:119543c9f674 | 44 | #endif |
| mbed_official | 489:119543c9f674 | 45 | |
| mbed_official | 489:119543c9f674 | 46 | /* Includes ------------------------------------------------------------------*/ |
| mbed_official | 489:119543c9f674 | 47 | #include "stm32f1xx_hal_def.h" |
| mbed_official | 489:119543c9f674 | 48 | |
| mbed_official | 489:119543c9f674 | 49 | /** @addtogroup STM32F1xx_HAL_Driver |
| mbed_official | 489:119543c9f674 | 50 | * @{ |
| mbed_official | 489:119543c9f674 | 51 | */ |
| mbed_official | 489:119543c9f674 | 52 | |
| mbed_official | 489:119543c9f674 | 53 | /** @addtogroup DMA |
| mbed_official | 489:119543c9f674 | 54 | * @{ |
| mbed_official | 489:119543c9f674 | 55 | */ |
| mbed_official | 489:119543c9f674 | 56 | |
| mbed_official | 489:119543c9f674 | 57 | /* Exported types ------------------------------------------------------------*/ |
| mbed_official | 489:119543c9f674 | 58 | /** @defgroup DMA_Exported_Types DMA Exported Types |
| mbed_official | 489:119543c9f674 | 59 | * @{ |
| mbed_official | 489:119543c9f674 | 60 | */ |
| mbed_official | 489:119543c9f674 | 61 | |
| mbed_official | 489:119543c9f674 | 62 | /** |
| mbed_official | 489:119543c9f674 | 63 | * @brief DMA Configuration Structure definition |
| mbed_official | 489:119543c9f674 | 64 | */ |
| mbed_official | 489:119543c9f674 | 65 | typedef struct |
| mbed_official | 489:119543c9f674 | 66 | { |
| mbed_official | 489:119543c9f674 | 67 | uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, |
| mbed_official | 489:119543c9f674 | 68 | from memory to memory or from peripheral to memory. |
| mbed_official | 489:119543c9f674 | 69 | This parameter can be a value of @ref DMA_Data_transfer_direction */ |
| mbed_official | 489:119543c9f674 | 70 | |
| mbed_official | 489:119543c9f674 | 71 | uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. |
| mbed_official | 489:119543c9f674 | 72 | This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ |
| mbed_official | 489:119543c9f674 | 73 | |
| mbed_official | 489:119543c9f674 | 74 | uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. |
| mbed_official | 489:119543c9f674 | 75 | This parameter can be a value of @ref DMA_Memory_incremented_mode */ |
| mbed_official | 489:119543c9f674 | 76 | |
| mbed_official | 489:119543c9f674 | 77 | uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. |
| mbed_official | 489:119543c9f674 | 78 | This parameter can be a value of @ref DMA_Peripheral_data_size */ |
| mbed_official | 489:119543c9f674 | 79 | |
| mbed_official | 489:119543c9f674 | 80 | uint32_t MemDataAlignment; /*!< Specifies the Memory data width. |
| mbed_official | 489:119543c9f674 | 81 | This parameter can be a value of @ref DMA_Memory_data_size */ |
| mbed_official | 489:119543c9f674 | 82 | |
| mbed_official | 489:119543c9f674 | 83 | uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. |
| mbed_official | 489:119543c9f674 | 84 | This parameter can be a value of @ref DMA_mode |
| mbed_official | 489:119543c9f674 | 85 | @note The circular buffer mode cannot be used if the memory-to-memory |
| mbed_official | 489:119543c9f674 | 86 | data transfer is configured on the selected Channel */ |
| mbed_official | 489:119543c9f674 | 87 | |
| mbed_official | 489:119543c9f674 | 88 | uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. |
| mbed_official | 489:119543c9f674 | 89 | This parameter can be a value of @ref DMA_Priority_level */ |
| mbed_official | 489:119543c9f674 | 90 | |
| mbed_official | 489:119543c9f674 | 91 | } DMA_InitTypeDef; |
| mbed_official | 489:119543c9f674 | 92 | |
| mbed_official | 489:119543c9f674 | 93 | /** |
| mbed_official | 489:119543c9f674 | 94 | * @brief DMA Configuration enumeration values definition |
| mbed_official | 489:119543c9f674 | 95 | */ |
| mbed_official | 489:119543c9f674 | 96 | typedef enum |
| mbed_official | 489:119543c9f674 | 97 | { |
| mbed_official | 489:119543c9f674 | 98 | DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */ |
| mbed_official | 489:119543c9f674 | 99 | DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */ |
| mbed_official | 489:119543c9f674 | 100 | |
| mbed_official | 489:119543c9f674 | 101 | } DMA_ControlTypeDef; |
| mbed_official | 489:119543c9f674 | 102 | |
| mbed_official | 489:119543c9f674 | 103 | /** |
| mbed_official | 489:119543c9f674 | 104 | * @brief HAL DMA State structures definition |
| mbed_official | 489:119543c9f674 | 105 | */ |
| mbed_official | 489:119543c9f674 | 106 | typedef enum |
| mbed_official | 489:119543c9f674 | 107 | { |
| mbed_official | 489:119543c9f674 | 108 | HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */ |
| mbed_official | 489:119543c9f674 | 109 | HAL_DMA_STATE_READY = 0x01, /*!< DMA process success and ready for use */ |
| mbed_official | 489:119543c9f674 | 110 | HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */ |
| mbed_official | 489:119543c9f674 | 111 | HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */ |
| mbed_official | 489:119543c9f674 | 112 | HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */ |
| mbed_official | 489:119543c9f674 | 113 | HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */ |
| mbed_official | 489:119543c9f674 | 114 | |
| mbed_official | 489:119543c9f674 | 115 | }HAL_DMA_StateTypeDef; |
| mbed_official | 489:119543c9f674 | 116 | |
| mbed_official | 489:119543c9f674 | 117 | /** |
| mbed_official | 489:119543c9f674 | 118 | * @brief HAL DMA Error Code structure definition |
| mbed_official | 489:119543c9f674 | 119 | */ |
| mbed_official | 489:119543c9f674 | 120 | typedef enum |
| mbed_official | 489:119543c9f674 | 121 | { |
| mbed_official | 489:119543c9f674 | 122 | HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */ |
| mbed_official | 489:119543c9f674 | 123 | HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */ |
| mbed_official | 489:119543c9f674 | 124 | |
| mbed_official | 489:119543c9f674 | 125 | }HAL_DMA_LevelCompleteTypeDef; |
| mbed_official | 489:119543c9f674 | 126 | |
| mbed_official | 489:119543c9f674 | 127 | /** |
| mbed_official | 489:119543c9f674 | 128 | * @brief DMA handle Structure definition |
| mbed_official | 489:119543c9f674 | 129 | */ |
| mbed_official | 489:119543c9f674 | 130 | typedef struct __DMA_HandleTypeDef |
| mbed_official | 489:119543c9f674 | 131 | { |
| mbed_official | 489:119543c9f674 | 132 | DMA_Channel_TypeDef *Instance; /*!< Register base address */ |
| mbed_official | 489:119543c9f674 | 133 | |
| mbed_official | 489:119543c9f674 | 134 | DMA_InitTypeDef Init; /*!< DMA communication parameters */ |
| mbed_official | 489:119543c9f674 | 135 | |
| mbed_official | 489:119543c9f674 | 136 | HAL_LockTypeDef Lock; /*!< DMA locking object */ |
| mbed_official | 489:119543c9f674 | 137 | |
| mbed_official | 489:119543c9f674 | 138 | HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ |
| mbed_official | 489:119543c9f674 | 139 | |
| mbed_official | 489:119543c9f674 | 140 | void *Parent; /*!< Parent object state */ |
| mbed_official | 489:119543c9f674 | 141 | |
| mbed_official | 489:119543c9f674 | 142 | void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ |
| mbed_official | 489:119543c9f674 | 143 | |
| mbed_official | 489:119543c9f674 | 144 | void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ |
| mbed_official | 489:119543c9f674 | 145 | |
| mbed_official | 489:119543c9f674 | 146 | void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ |
| mbed_official | 489:119543c9f674 | 147 | |
| mbed_official | 489:119543c9f674 | 148 | __IO uint32_t ErrorCode; /*!< DMA Error code */ |
| mbed_official | 489:119543c9f674 | 149 | |
| mbed_official | 489:119543c9f674 | 150 | } DMA_HandleTypeDef; |
| mbed_official | 489:119543c9f674 | 151 | /** |
| mbed_official | 489:119543c9f674 | 152 | * @} |
| mbed_official | 489:119543c9f674 | 153 | */ |
| mbed_official | 489:119543c9f674 | 154 | |
| mbed_official | 489:119543c9f674 | 155 | /* Exported constants --------------------------------------------------------*/ |
| mbed_official | 489:119543c9f674 | 156 | /** @defgroup DMA_Exported_Constants DMA Exported Constants |
| mbed_official | 489:119543c9f674 | 157 | * @{ |
| mbed_official | 489:119543c9f674 | 158 | */ |
| mbed_official | 489:119543c9f674 | 159 | |
| mbed_official | 489:119543c9f674 | 160 | /** @defgroup DMA_Error_Codes DMA Error Codes |
| mbed_official | 489:119543c9f674 | 161 | * @{ |
| mbed_official | 489:119543c9f674 | 162 | */ |
| mbed_official | 489:119543c9f674 | 163 | #define HAL_DMA_ERROR_NONE ((uint32_t)0x00) /*!< No error */ |
| mbed_official | 489:119543c9f674 | 164 | #define HAL_DMA_ERROR_TE ((uint32_t)0x01) /*!< Transfer error */ |
| mbed_official | 489:119543c9f674 | 165 | #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x20) /*!< Timeout error */ |
| mbed_official | 489:119543c9f674 | 166 | |
| mbed_official | 489:119543c9f674 | 167 | /** |
| mbed_official | 489:119543c9f674 | 168 | * @} |
| mbed_official | 489:119543c9f674 | 169 | */ |
| mbed_official | 489:119543c9f674 | 170 | |
| mbed_official | 489:119543c9f674 | 171 | |
| mbed_official | 489:119543c9f674 | 172 | |
| mbed_official | 489:119543c9f674 | 173 | /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction |
| mbed_official | 489:119543c9f674 | 174 | * @{ |
| mbed_official | 489:119543c9f674 | 175 | */ |
| mbed_official | 489:119543c9f674 | 176 | #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */ |
| mbed_official | 489:119543c9f674 | 177 | #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ |
| mbed_official | 489:119543c9f674 | 178 | #define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */ |
| mbed_official | 489:119543c9f674 | 179 | |
| mbed_official | 489:119543c9f674 | 180 | #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ |
| mbed_official | 489:119543c9f674 | 181 | ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ |
| mbed_official | 489:119543c9f674 | 182 | ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) |
| mbed_official | 489:119543c9f674 | 183 | /** |
| mbed_official | 489:119543c9f674 | 184 | * @} |
| mbed_official | 489:119543c9f674 | 185 | */ |
| mbed_official | 489:119543c9f674 | 186 | |
| mbed_official | 489:119543c9f674 | 187 | /** @defgroup DMA_Data_buffer_size DMA Data buffer size |
| mbed_official | 489:119543c9f674 | 188 | * @{ |
| mbed_official | 489:119543c9f674 | 189 | */ |
| mbed_official | 489:119543c9f674 | 190 | #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) |
| mbed_official | 489:119543c9f674 | 191 | /** |
| mbed_official | 489:119543c9f674 | 192 | * @} |
| mbed_official | 489:119543c9f674 | 193 | */ |
| mbed_official | 489:119543c9f674 | 194 | |
| mbed_official | 489:119543c9f674 | 195 | /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode |
| mbed_official | 489:119543c9f674 | 196 | * @{ |
| mbed_official | 489:119543c9f674 | 197 | */ |
| mbed_official | 489:119543c9f674 | 198 | #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ |
| mbed_official | 489:119543c9f674 | 199 | #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */ |
| mbed_official | 489:119543c9f674 | 200 | |
| mbed_official | 489:119543c9f674 | 201 | #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ |
| mbed_official | 489:119543c9f674 | 202 | ((STATE) == DMA_PINC_DISABLE)) |
| mbed_official | 489:119543c9f674 | 203 | /** |
| mbed_official | 489:119543c9f674 | 204 | * @} |
| mbed_official | 489:119543c9f674 | 205 | */ |
| mbed_official | 489:119543c9f674 | 206 | |
| mbed_official | 489:119543c9f674 | 207 | /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode |
| mbed_official | 489:119543c9f674 | 208 | * @{ |
| mbed_official | 489:119543c9f674 | 209 | */ |
| mbed_official | 489:119543c9f674 | 210 | #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ |
| mbed_official | 489:119543c9f674 | 211 | #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */ |
| mbed_official | 489:119543c9f674 | 212 | |
| mbed_official | 489:119543c9f674 | 213 | #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ |
| mbed_official | 489:119543c9f674 | 214 | ((STATE) == DMA_MINC_DISABLE)) |
| mbed_official | 489:119543c9f674 | 215 | /** |
| mbed_official | 489:119543c9f674 | 216 | * @} |
| mbed_official | 489:119543c9f674 | 217 | */ |
| mbed_official | 489:119543c9f674 | 218 | |
| mbed_official | 489:119543c9f674 | 219 | /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size |
| mbed_official | 489:119543c9f674 | 220 | * @{ |
| mbed_official | 489:119543c9f674 | 221 | */ |
| mbed_official | 489:119543c9f674 | 222 | #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */ |
| mbed_official | 489:119543c9f674 | 223 | #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */ |
| mbed_official | 489:119543c9f674 | 224 | #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */ |
| mbed_official | 489:119543c9f674 | 225 | |
| mbed_official | 489:119543c9f674 | 226 | #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ |
| mbed_official | 489:119543c9f674 | 227 | ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ |
| mbed_official | 489:119543c9f674 | 228 | ((SIZE) == DMA_PDATAALIGN_WORD)) |
| mbed_official | 489:119543c9f674 | 229 | /** |
| mbed_official | 489:119543c9f674 | 230 | * @} |
| mbed_official | 489:119543c9f674 | 231 | */ |
| mbed_official | 489:119543c9f674 | 232 | |
| mbed_official | 489:119543c9f674 | 233 | |
| mbed_official | 489:119543c9f674 | 234 | /** @defgroup DMA_Memory_data_size DMA Memory data size |
| mbed_official | 489:119543c9f674 | 235 | * @{ |
| mbed_official | 489:119543c9f674 | 236 | */ |
| mbed_official | 489:119543c9f674 | 237 | #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */ |
| mbed_official | 489:119543c9f674 | 238 | #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */ |
| mbed_official | 489:119543c9f674 | 239 | #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */ |
| mbed_official | 489:119543c9f674 | 240 | |
| mbed_official | 489:119543c9f674 | 241 | #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ |
| mbed_official | 489:119543c9f674 | 242 | ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ |
| mbed_official | 489:119543c9f674 | 243 | ((SIZE) == DMA_MDATAALIGN_WORD )) |
| mbed_official | 489:119543c9f674 | 244 | /** |
| mbed_official | 489:119543c9f674 | 245 | * @} |
| mbed_official | 489:119543c9f674 | 246 | */ |
| mbed_official | 489:119543c9f674 | 247 | |
| mbed_official | 489:119543c9f674 | 248 | /** @defgroup DMA_mode DMA mode |
| mbed_official | 489:119543c9f674 | 249 | * @{ |
| mbed_official | 489:119543c9f674 | 250 | */ |
| mbed_official | 489:119543c9f674 | 251 | #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */ |
| mbed_official | 489:119543c9f674 | 252 | #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */ |
| mbed_official | 489:119543c9f674 | 253 | |
| mbed_official | 489:119543c9f674 | 254 | #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ |
| mbed_official | 489:119543c9f674 | 255 | ((MODE) == DMA_CIRCULAR)) |
| mbed_official | 489:119543c9f674 | 256 | /** |
| mbed_official | 489:119543c9f674 | 257 | * @} |
| mbed_official | 489:119543c9f674 | 258 | */ |
| mbed_official | 489:119543c9f674 | 259 | |
| mbed_official | 489:119543c9f674 | 260 | /** @defgroup DMA_Priority_level DMA Priority level |
| mbed_official | 489:119543c9f674 | 261 | * @{ |
| mbed_official | 489:119543c9f674 | 262 | */ |
| mbed_official | 489:119543c9f674 | 263 | #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */ |
| mbed_official | 489:119543c9f674 | 264 | #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ |
| mbed_official | 489:119543c9f674 | 265 | #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ |
| mbed_official | 489:119543c9f674 | 266 | #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ |
| mbed_official | 489:119543c9f674 | 267 | |
| mbed_official | 489:119543c9f674 | 268 | #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ |
| mbed_official | 489:119543c9f674 | 269 | ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ |
| mbed_official | 489:119543c9f674 | 270 | ((PRIORITY) == DMA_PRIORITY_HIGH) || \ |
| mbed_official | 489:119543c9f674 | 271 | ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) |
| mbed_official | 489:119543c9f674 | 272 | /** |
| mbed_official | 489:119543c9f674 | 273 | * @} |
| mbed_official | 489:119543c9f674 | 274 | */ |
| mbed_official | 489:119543c9f674 | 275 | |
| mbed_official | 489:119543c9f674 | 276 | |
| mbed_official | 489:119543c9f674 | 277 | /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions |
| mbed_official | 489:119543c9f674 | 278 | * @{ |
| mbed_official | 489:119543c9f674 | 279 | */ |
| mbed_official | 489:119543c9f674 | 280 | |
| mbed_official | 489:119543c9f674 | 281 | #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) |
| mbed_official | 489:119543c9f674 | 282 | #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) |
| mbed_official | 489:119543c9f674 | 283 | #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) |
| mbed_official | 489:119543c9f674 | 284 | |
| mbed_official | 489:119543c9f674 | 285 | /** |
| mbed_official | 489:119543c9f674 | 286 | * @} |
| mbed_official | 489:119543c9f674 | 287 | */ |
| mbed_official | 489:119543c9f674 | 288 | |
| mbed_official | 489:119543c9f674 | 289 | /** @defgroup DMA_flag_definitions DMA flag definitions |
| mbed_official | 489:119543c9f674 | 290 | * @{ |
| mbed_official | 489:119543c9f674 | 291 | */ |
| mbed_official | 489:119543c9f674 | 292 | |
| mbed_official | 489:119543c9f674 | 293 | #define DMA_FLAG_GL1 ((uint32_t)0x00000001) |
| mbed_official | 489:119543c9f674 | 294 | #define DMA_FLAG_TC1 ((uint32_t)0x00000002) |
| mbed_official | 489:119543c9f674 | 295 | #define DMA_FLAG_HT1 ((uint32_t)0x00000004) |
| mbed_official | 489:119543c9f674 | 296 | #define DMA_FLAG_TE1 ((uint32_t)0x00000008) |
| mbed_official | 489:119543c9f674 | 297 | #define DMA_FLAG_GL2 ((uint32_t)0x00000010) |
| mbed_official | 489:119543c9f674 | 298 | #define DMA_FLAG_TC2 ((uint32_t)0x00000020) |
| mbed_official | 489:119543c9f674 | 299 | #define DMA_FLAG_HT2 ((uint32_t)0x00000040) |
| mbed_official | 489:119543c9f674 | 300 | #define DMA_FLAG_TE2 ((uint32_t)0x00000080) |
| mbed_official | 489:119543c9f674 | 301 | #define DMA_FLAG_GL3 ((uint32_t)0x00000100) |
| mbed_official | 489:119543c9f674 | 302 | #define DMA_FLAG_TC3 ((uint32_t)0x00000200) |
| mbed_official | 489:119543c9f674 | 303 | #define DMA_FLAG_HT3 ((uint32_t)0x00000400) |
| mbed_official | 489:119543c9f674 | 304 | #define DMA_FLAG_TE3 ((uint32_t)0x00000800) |
| mbed_official | 489:119543c9f674 | 305 | #define DMA_FLAG_GL4 ((uint32_t)0x00001000) |
| mbed_official | 489:119543c9f674 | 306 | #define DMA_FLAG_TC4 ((uint32_t)0x00002000) |
| mbed_official | 489:119543c9f674 | 307 | #define DMA_FLAG_HT4 ((uint32_t)0x00004000) |
| mbed_official | 489:119543c9f674 | 308 | #define DMA_FLAG_TE4 ((uint32_t)0x00008000) |
| mbed_official | 489:119543c9f674 | 309 | #define DMA_FLAG_GL5 ((uint32_t)0x00010000) |
| mbed_official | 489:119543c9f674 | 310 | #define DMA_FLAG_TC5 ((uint32_t)0x00020000) |
| mbed_official | 489:119543c9f674 | 311 | #define DMA_FLAG_HT5 ((uint32_t)0x00040000) |
| mbed_official | 489:119543c9f674 | 312 | #define DMA_FLAG_TE5 ((uint32_t)0x00080000) |
| mbed_official | 489:119543c9f674 | 313 | #define DMA_FLAG_GL6 ((uint32_t)0x00100000) |
| mbed_official | 489:119543c9f674 | 314 | #define DMA_FLAG_TC6 ((uint32_t)0x00200000) |
| mbed_official | 489:119543c9f674 | 315 | #define DMA_FLAG_HT6 ((uint32_t)0x00400000) |
| mbed_official | 489:119543c9f674 | 316 | #define DMA_FLAG_TE6 ((uint32_t)0x00800000) |
| mbed_official | 489:119543c9f674 | 317 | #define DMA_FLAG_GL7 ((uint32_t)0x01000000) |
| mbed_official | 489:119543c9f674 | 318 | #define DMA_FLAG_TC7 ((uint32_t)0x02000000) |
| mbed_official | 489:119543c9f674 | 319 | #define DMA_FLAG_HT7 ((uint32_t)0x04000000) |
| mbed_official | 489:119543c9f674 | 320 | #define DMA_FLAG_TE7 ((uint32_t)0x08000000) |
| mbed_official | 489:119543c9f674 | 321 | |
| mbed_official | 489:119543c9f674 | 322 | |
| mbed_official | 489:119543c9f674 | 323 | /** |
| mbed_official | 489:119543c9f674 | 324 | * @} |
| mbed_official | 489:119543c9f674 | 325 | */ |
| mbed_official | 489:119543c9f674 | 326 | |
| mbed_official | 489:119543c9f674 | 327 | /** |
| mbed_official | 489:119543c9f674 | 328 | * @} |
| mbed_official | 489:119543c9f674 | 329 | */ |
| mbed_official | 489:119543c9f674 | 330 | |
| mbed_official | 489:119543c9f674 | 331 | /* Exported macros -----------------------------------------------------------*/ |
| mbed_official | 489:119543c9f674 | 332 | /** @defgroup DMA_Exported_Macros DMA Exported Macros |
| mbed_official | 489:119543c9f674 | 333 | * @{ |
| mbed_official | 489:119543c9f674 | 334 | */ |
| mbed_official | 489:119543c9f674 | 335 | |
| mbed_official | 489:119543c9f674 | 336 | /** @brief Reset DMA handle state |
| mbed_official | 489:119543c9f674 | 337 | * @param __HANDLE__: DMA handle. |
| mbed_official | 489:119543c9f674 | 338 | * @retval None |
| mbed_official | 489:119543c9f674 | 339 | */ |
| mbed_official | 489:119543c9f674 | 340 | #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) |
| mbed_official | 489:119543c9f674 | 341 | |
| mbed_official | 489:119543c9f674 | 342 | /** |
| mbed_official | 489:119543c9f674 | 343 | * @brief Enable the specified DMA Channel. |
| mbed_official | 489:119543c9f674 | 344 | * @param __HANDLE__: DMA handle |
| mbed_official | 489:119543c9f674 | 345 | * @retval None. |
| mbed_official | 489:119543c9f674 | 346 | */ |
| mbed_official | 489:119543c9f674 | 347 | #define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) |
| mbed_official | 489:119543c9f674 | 348 | |
| mbed_official | 489:119543c9f674 | 349 | /** |
| mbed_official | 489:119543c9f674 | 350 | * @brief Disable the specified DMA Channel. |
| mbed_official | 489:119543c9f674 | 351 | * @param __HANDLE__: DMA handle |
| mbed_official | 489:119543c9f674 | 352 | * @retval None. |
| mbed_official | 489:119543c9f674 | 353 | */ |
| mbed_official | 489:119543c9f674 | 354 | #define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) |
| mbed_official | 489:119543c9f674 | 355 | |
| mbed_official | 489:119543c9f674 | 356 | |
| mbed_official | 489:119543c9f674 | 357 | /* Interrupt & Flag management */ |
| mbed_official | 489:119543c9f674 | 358 | |
| mbed_official | 489:119543c9f674 | 359 | /** |
| mbed_official | 489:119543c9f674 | 360 | * @brief Enables the specified DMA Channel interrupts. |
| mbed_official | 489:119543c9f674 | 361 | * @param __HANDLE__: DMA handle |
| mbed_official | 489:119543c9f674 | 362 | * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. |
| mbed_official | 489:119543c9f674 | 363 | * This parameter can be any combination of the following values: |
| mbed_official | 489:119543c9f674 | 364 | * @arg DMA_IT_TC: Transfer complete interrupt mask |
| mbed_official | 489:119543c9f674 | 365 | * @arg DMA_IT_HT: Half transfer complete interrupt mask |
| mbed_official | 489:119543c9f674 | 366 | * @arg DMA_IT_TE: Transfer error interrupt mask |
| mbed_official | 489:119543c9f674 | 367 | * @retval None |
| mbed_official | 489:119543c9f674 | 368 | */ |
| mbed_official | 489:119543c9f674 | 369 | #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__))) |
| mbed_official | 489:119543c9f674 | 370 | |
| mbed_official | 489:119543c9f674 | 371 | /** |
| mbed_official | 489:119543c9f674 | 372 | * @brief Disables the specified DMA Channel interrupts. |
| mbed_official | 489:119543c9f674 | 373 | * @param __HANDLE__: DMA handle |
| mbed_official | 489:119543c9f674 | 374 | * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. |
| mbed_official | 489:119543c9f674 | 375 | * This parameter can be any combination of the following values: |
| mbed_official | 489:119543c9f674 | 376 | * @arg DMA_IT_TC: Transfer complete interrupt mask |
| mbed_official | 489:119543c9f674 | 377 | * @arg DMA_IT_HT: Half transfer complete interrupt mask |
| mbed_official | 489:119543c9f674 | 378 | * @arg DMA_IT_TE: Transfer error interrupt mask |
| mbed_official | 489:119543c9f674 | 379 | * @retval None |
| mbed_official | 489:119543c9f674 | 380 | */ |
| mbed_official | 489:119543c9f674 | 381 | #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__))) |
| mbed_official | 489:119543c9f674 | 382 | |
| mbed_official | 489:119543c9f674 | 383 | /** |
| mbed_official | 489:119543c9f674 | 384 | * @brief Checks whether the specified DMA Channel interrupt has occurred or not. |
| mbed_official | 489:119543c9f674 | 385 | * @param __HANDLE__: DMA handle |
| mbed_official | 489:119543c9f674 | 386 | * @param __INTERRUPT__: specifies the DMA interrupt source to check. |
| mbed_official | 489:119543c9f674 | 387 | * This parameter can be one of the following values: |
| mbed_official | 489:119543c9f674 | 388 | * @arg DMA_IT_TC: Transfer complete interrupt mask |
| mbed_official | 489:119543c9f674 | 389 | * @arg DMA_IT_HT: Half transfer complete interrupt mask |
| mbed_official | 489:119543c9f674 | 390 | * @arg DMA_IT_TE: Transfer error interrupt mask |
| mbed_official | 489:119543c9f674 | 391 | * @retval The state of DMA_IT (SET or RESET). |
| mbed_official | 489:119543c9f674 | 392 | */ |
| mbed_official | 489:119543c9f674 | 393 | #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
| mbed_official | 489:119543c9f674 | 394 | |
| mbed_official | 489:119543c9f674 | 395 | /** |
| mbed_official | 489:119543c9f674 | 396 | * @} |
| mbed_official | 489:119543c9f674 | 397 | */ |
| mbed_official | 489:119543c9f674 | 398 | |
| mbed_official | 489:119543c9f674 | 399 | /* Include DMA HAL Extension module */ |
| mbed_official | 489:119543c9f674 | 400 | #include "stm32f1xx_hal_dma_ex.h" |
| mbed_official | 489:119543c9f674 | 401 | |
| mbed_official | 489:119543c9f674 | 402 | /* Exported functions --------------------------------------------------------*/ |
| mbed_official | 489:119543c9f674 | 403 | /** @addtogroup DMA_Exported_Functions DMA Exported Functions |
| mbed_official | 489:119543c9f674 | 404 | * @{ |
| mbed_official | 489:119543c9f674 | 405 | */ |
| mbed_official | 489:119543c9f674 | 406 | |
| mbed_official | 489:119543c9f674 | 407 | /** @addtogroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions |
| mbed_official | 489:119543c9f674 | 408 | * @{ |
| mbed_official | 489:119543c9f674 | 409 | */ |
| mbed_official | 489:119543c9f674 | 410 | /* Initialization and de-initialization functions *****************************/ |
| mbed_official | 489:119543c9f674 | 411 | HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); |
| mbed_official | 489:119543c9f674 | 412 | HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); |
| mbed_official | 489:119543c9f674 | 413 | /** |
| mbed_official | 489:119543c9f674 | 414 | * @} |
| mbed_official | 489:119543c9f674 | 415 | */ |
| mbed_official | 489:119543c9f674 | 416 | |
| mbed_official | 489:119543c9f674 | 417 | /** @addtogroup DMA_Exported_Functions_Group2 Input and Output operation functions |
| mbed_official | 489:119543c9f674 | 418 | * @{ |
| mbed_official | 489:119543c9f674 | 419 | */ |
| mbed_official | 489:119543c9f674 | 420 | /* IO operation functions *****************************************************/ |
| mbed_official | 489:119543c9f674 | 421 | HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
| mbed_official | 489:119543c9f674 | 422 | HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
| mbed_official | 489:119543c9f674 | 423 | HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); |
| mbed_official | 489:119543c9f674 | 424 | HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); |
| mbed_official | 489:119543c9f674 | 425 | void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); |
| mbed_official | 489:119543c9f674 | 426 | /** |
| mbed_official | 489:119543c9f674 | 427 | * @} |
| mbed_official | 489:119543c9f674 | 428 | */ |
| mbed_official | 489:119543c9f674 | 429 | |
| mbed_official | 489:119543c9f674 | 430 | /** @addtogroup DMA_Exported_Functions_Group3 Peripheral State functions |
| mbed_official | 489:119543c9f674 | 431 | * @{ |
| mbed_official | 489:119543c9f674 | 432 | */ |
| mbed_official | 489:119543c9f674 | 433 | /* Peripheral State and Error functions ***************************************/ |
| mbed_official | 489:119543c9f674 | 434 | HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); |
| mbed_official | 489:119543c9f674 | 435 | uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); |
| mbed_official | 489:119543c9f674 | 436 | /** |
| mbed_official | 489:119543c9f674 | 437 | * @} |
| mbed_official | 489:119543c9f674 | 438 | */ |
| mbed_official | 489:119543c9f674 | 439 | |
| mbed_official | 489:119543c9f674 | 440 | /** |
| mbed_official | 489:119543c9f674 | 441 | * @} |
| mbed_official | 489:119543c9f674 | 442 | */ |
| mbed_official | 489:119543c9f674 | 443 | |
| mbed_official | 489:119543c9f674 | 444 | /** |
| mbed_official | 489:119543c9f674 | 445 | * @} |
| mbed_official | 489:119543c9f674 | 446 | */ |
| mbed_official | 489:119543c9f674 | 447 | |
| mbed_official | 489:119543c9f674 | 448 | /** |
| mbed_official | 489:119543c9f674 | 449 | * @} |
| mbed_official | 489:119543c9f674 | 450 | */ |
| mbed_official | 489:119543c9f674 | 451 | |
| mbed_official | 489:119543c9f674 | 452 | #ifdef __cplusplus |
| mbed_official | 489:119543c9f674 | 453 | } |
| mbed_official | 489:119543c9f674 | 454 | #endif |
| mbed_official | 489:119543c9f674 | 455 | |
| mbed_official | 489:119543c9f674 | 456 | #endif /* __STM32F1xx_HAL_DMA_H */ |
| mbed_official | 489:119543c9f674 | 457 | |
| mbed_official | 489:119543c9f674 | 458 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |