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targets/cmsis/TARGET_Maxim/TARGET_MAX32610/adc_regs.h@600:7d17ca308cd1, 2015-07-31 (annotated)
- Committer:
- mbed_official
- Date:
- Fri Jul 31 14:15:09 2015 +0100
- Revision:
- 600:7d17ca308cd1
- Parent:
- 507:d4fc7603a669
Synchronized with git revision e4cd8bbd3e05b68e5a7f466c74035a85743d45e0
Full URL: https://github.com/mbedmicro/mbed/commit/e4cd8bbd3e05b68e5a7f466c74035a85743d45e0/
Enable LPC8xx usart when configuring it
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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mbed_official | 507:d4fc7603a669 | 1 | /******************************************************************************* |
mbed_official | 507:d4fc7603a669 | 2 | * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. |
mbed_official | 507:d4fc7603a669 | 3 | * |
mbed_official | 507:d4fc7603a669 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
mbed_official | 507:d4fc7603a669 | 5 | * copy of this software and associated documentation files (the "Software"), |
mbed_official | 507:d4fc7603a669 | 6 | * to deal in the Software without restriction, including without limitation |
mbed_official | 507:d4fc7603a669 | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
mbed_official | 507:d4fc7603a669 | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
mbed_official | 507:d4fc7603a669 | 9 | * Software is furnished to do so, subject to the following conditions: |
mbed_official | 507:d4fc7603a669 | 10 | * |
mbed_official | 507:d4fc7603a669 | 11 | * The above copyright notice and this permission notice shall be included |
mbed_official | 507:d4fc7603a669 | 12 | * in all copies or substantial portions of the Software. |
mbed_official | 507:d4fc7603a669 | 13 | * |
mbed_official | 507:d4fc7603a669 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
mbed_official | 507:d4fc7603a669 | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
mbed_official | 507:d4fc7603a669 | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
mbed_official | 507:d4fc7603a669 | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
mbed_official | 507:d4fc7603a669 | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
mbed_official | 507:d4fc7603a669 | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
mbed_official | 507:d4fc7603a669 | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
mbed_official | 507:d4fc7603a669 | 21 | * |
mbed_official | 507:d4fc7603a669 | 22 | * Except as contained in this notice, the name of Maxim Integrated |
mbed_official | 507:d4fc7603a669 | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
mbed_official | 507:d4fc7603a669 | 24 | * Products, Inc. Branding Policy. |
mbed_official | 507:d4fc7603a669 | 25 | * |
mbed_official | 507:d4fc7603a669 | 26 | * The mere transfer of this software does not imply any licenses |
mbed_official | 507:d4fc7603a669 | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
mbed_official | 507:d4fc7603a669 | 28 | * trademarks, maskwork rights, or any other form of intellectual |
mbed_official | 507:d4fc7603a669 | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
mbed_official | 507:d4fc7603a669 | 30 | * ownership rights. |
mbed_official | 507:d4fc7603a669 | 31 | ******************************************************************************* |
mbed_official | 507:d4fc7603a669 | 32 | */ |
mbed_official | 507:d4fc7603a669 | 33 | |
mbed_official | 507:d4fc7603a669 | 34 | #ifndef _MXC_ADC_REGS_H |
mbed_official | 507:d4fc7603a669 | 35 | #define _MXC_ADC_REGS_H |
mbed_official | 507:d4fc7603a669 | 36 | |
mbed_official | 507:d4fc7603a669 | 37 | #ifdef __cplusplus |
mbed_official | 507:d4fc7603a669 | 38 | extern "C" { |
mbed_official | 507:d4fc7603a669 | 39 | #endif |
mbed_official | 507:d4fc7603a669 | 40 | |
mbed_official | 507:d4fc7603a669 | 41 | #include <stdint.h> |
mbed_official | 507:d4fc7603a669 | 42 | |
mbed_official | 507:d4fc7603a669 | 43 | /** |
mbed_official | 507:d4fc7603a669 | 44 | * @file adc_regs.h |
mbed_official | 507:d4fc7603a669 | 45 | * @addtogroup adc ADC |
mbed_official | 507:d4fc7603a669 | 46 | * @{ |
mbed_official | 507:d4fc7603a669 | 47 | */ |
mbed_official | 507:d4fc7603a669 | 48 | |
mbed_official | 507:d4fc7603a669 | 49 | /** |
mbed_official | 507:d4fc7603a669 | 50 | * @brief Defines ADC Modes. |
mbed_official | 507:d4fc7603a669 | 51 | */ |
mbed_official | 507:d4fc7603a669 | 52 | typedef enum { |
mbed_official | 507:d4fc7603a669 | 53 | /** Single Mode Full Rate */ |
mbed_official | 507:d4fc7603a669 | 54 | MXC_E_ADC_MODE_SMPLCNT_FULL_RATE = 0, |
mbed_official | 507:d4fc7603a669 | 55 | /** Single Mode Low Power */ |
mbed_official | 507:d4fc7603a669 | 56 | MXC_E_ADC_MODE_SMPLCNT_LOW_POWER = 1, |
mbed_official | 507:d4fc7603a669 | 57 | /** Continuous Mode Full Rate */ |
mbed_official | 507:d4fc7603a669 | 58 | MXC_E_ADC_MODE_CONTINUOUS_FULL_RATE = 2, |
mbed_official | 507:d4fc7603a669 | 59 | /** Continuous Mode Low Power */ |
mbed_official | 507:d4fc7603a669 | 60 | MXC_E_ADC_MODE_CONTINUOUS_LOW_POWER = 3, |
mbed_official | 507:d4fc7603a669 | 61 | /** Single Mode Full Rate with Scan Enabled */ |
mbed_official | 507:d4fc7603a669 | 62 | MXC_E_ADC_MODE_SMPLCNT_SCAN_FULL_RATE = 8, |
mbed_official | 507:d4fc7603a669 | 63 | /** Single Mode Low Power with Scan Enabled */ |
mbed_official | 507:d4fc7603a669 | 64 | MXC_E_ADC_MODE_SMPLCNT_SCAN_LOW_POWER = 9, |
mbed_official | 507:d4fc7603a669 | 65 | /** Continuous Mode Full Rate with Scan Enabled */ |
mbed_official | 507:d4fc7603a669 | 66 | MXC_E_ADC_MODE_CONTINUOUS_SCAN_FULL_RATE = 10, |
mbed_official | 507:d4fc7603a669 | 67 | /** Continuous Mode Low Power with Scan Enabled */ |
mbed_official | 507:d4fc7603a669 | 68 | MXC_E_ADC_MODE_CONTINUOUS_SCAN_LOW_POWER = 11 |
mbed_official | 507:d4fc7603a669 | 69 | } mxc_adc_mode_t; |
mbed_official | 507:d4fc7603a669 | 70 | |
mbed_official | 507:d4fc7603a669 | 71 | /** |
mbed_official | 507:d4fc7603a669 | 72 | * @brief Defines ADC Range Control. |
mbed_official | 507:d4fc7603a669 | 73 | */ |
mbed_official | 507:d4fc7603a669 | 74 | typedef enum { |
mbed_official | 507:d4fc7603a669 | 75 | /** Bi-polar Operation (-Vref/2 -> Vref/2) */ |
mbed_official | 507:d4fc7603a669 | 76 | MXC_E_ADC_RANGE_HALF = 0, |
mbed_official | 507:d4fc7603a669 | 77 | /** Bi-polar Operation (-Vref -> Vref) */ |
mbed_official | 507:d4fc7603a669 | 78 | MXC_E_ADC_RANGE_FULL |
mbed_official | 507:d4fc7603a669 | 79 | } mxc_adc_range_t; |
mbed_official | 507:d4fc7603a669 | 80 | |
mbed_official | 507:d4fc7603a669 | 81 | /** |
mbed_official | 507:d4fc7603a669 | 82 | * @brief Defines ADC Bipolar operation. |
mbed_official | 507:d4fc7603a669 | 83 | */ |
mbed_official | 507:d4fc7603a669 | 84 | typedef enum { |
mbed_official | 507:d4fc7603a669 | 85 | /** Uni-polar operation (0 -> Vref) */ |
mbed_official | 507:d4fc7603a669 | 86 | MXC_E_ADC_BI_POL_UNIPOLAR = 0, |
mbed_official | 507:d4fc7603a669 | 87 | /** Bi-polar operation see ADC Range Control */ |
mbed_official | 507:d4fc7603a669 | 88 | MXC_E_ADC_BI_POL_BIPOLAR |
mbed_official | 507:d4fc7603a669 | 89 | } mxc_adc_bi_pol_t; |
mbed_official | 507:d4fc7603a669 | 90 | |
mbed_official | 507:d4fc7603a669 | 91 | /** |
mbed_official | 507:d4fc7603a669 | 92 | * @brief Defines Decimation Filter Modes. |
mbed_official | 507:d4fc7603a669 | 93 | */ |
mbed_official | 507:d4fc7603a669 | 94 | typedef enum { |
mbed_official | 507:d4fc7603a669 | 95 | /** Decimation Filter ByPassed */ |
mbed_official | 507:d4fc7603a669 | 96 | MXC_E_ADC_AVG_MODE_FILTER_BYPASS = 0, |
mbed_official | 507:d4fc7603a669 | 97 | /** Output Average Only*/ |
mbed_official | 507:d4fc7603a669 | 98 | MXC_E_ADC_AVG_MODE_FILTER_OUTPUT, |
mbed_official | 507:d4fc7603a669 | 99 | /** Output Average and Raw Data (Test Mode Only) */ |
mbed_official | 507:d4fc7603a669 | 100 | MXC_E_ADC_AVG_MODE_FILTER_OUTPUT_RAW |
mbed_official | 507:d4fc7603a669 | 101 | } mxc_adc_avg_mode_t; |
mbed_official | 507:d4fc7603a669 | 102 | |
mbed_official | 507:d4fc7603a669 | 103 | /** |
mbed_official | 507:d4fc7603a669 | 104 | * @brief Defines ADC StartMode Modes. |
mbed_official | 507:d4fc7603a669 | 105 | */ |
mbed_official | 507:d4fc7603a669 | 106 | typedef enum { |
mbed_official | 507:d4fc7603a669 | 107 | /** StarMode via Software */ |
mbed_official | 507:d4fc7603a669 | 108 | MXC_E_ADC_STRT_MODE_SOFTWARE = 0, |
mbed_official | 507:d4fc7603a669 | 109 | /** StarMode via PulseTrain */ |
mbed_official | 507:d4fc7603a669 | 110 | MXC_E_ADC_STRT_MODE_PULSETRAIN |
mbed_official | 507:d4fc7603a669 | 111 | } mxc_adc_strt_mode_t; |
mbed_official | 507:d4fc7603a669 | 112 | |
mbed_official | 507:d4fc7603a669 | 113 | /** |
mbed_official | 507:d4fc7603a669 | 114 | * @brief Defines Mux Channel Select for the Positive Input to the ADC. |
mbed_official | 507:d4fc7603a669 | 115 | */ |
mbed_official | 507:d4fc7603a669 | 116 | typedef enum { |
mbed_official | 507:d4fc7603a669 | 117 | /** Single Mode Input AIN0+; Diff Mode AIN0+/AIN8- */ |
mbed_official | 507:d4fc7603a669 | 118 | MXC_E_ADC_PGA_MUX_CH_SEL_AIN0 = 0, |
mbed_official | 507:d4fc7603a669 | 119 | /** Single Mode Input AIN1+; Diff Mode AIN1+/AIN9- */ |
mbed_official | 507:d4fc7603a669 | 120 | MXC_E_ADC_PGA_MUX_CH_SEL_AIN1 = 1, |
mbed_official | 507:d4fc7603a669 | 121 | /** Single Mode Input AIN2+; Diff Mode AIN2+/AIN10- */ |
mbed_official | 507:d4fc7603a669 | 122 | MXC_E_ADC_PGA_MUX_CH_SEL_AIN2 = 2, |
mbed_official | 507:d4fc7603a669 | 123 | /** Single Mode Input AIN3+; Diff Mode AIN3+/AIN11- */ |
mbed_official | 507:d4fc7603a669 | 124 | MXC_E_ADC_PGA_MUX_CH_SEL_AIN3 = 3, |
mbed_official | 507:d4fc7603a669 | 125 | /** Single Mode Input AIN4+; Diff Mode AIN4+/AIN12- */ |
mbed_official | 507:d4fc7603a669 | 126 | MXC_E_ADC_PGA_MUX_CH_SEL_AIN4 = 4, |
mbed_official | 507:d4fc7603a669 | 127 | /** Single Mode Input AIN5+; Diff Mode AIN5+/AIN13- */ |
mbed_official | 507:d4fc7603a669 | 128 | MXC_E_ADC_PGA_MUX_CH_SEL_AIN5 = 5, |
mbed_official | 507:d4fc7603a669 | 129 | /** Single Mode Input AIN6+; Diff Mode AIN6+/AIN14- */ |
mbed_official | 507:d4fc7603a669 | 130 | MXC_E_ADC_PGA_MUX_CH_SEL_AIN6 = 6, |
mbed_official | 507:d4fc7603a669 | 131 | /** Single Mode Input AIN7+; Diff Mode AIN7+/AIN15- */ |
mbed_official | 507:d4fc7603a669 | 132 | MXC_E_ADC_PGA_MUX_CH_SEL_AIN7 = 7, |
mbed_official | 507:d4fc7603a669 | 133 | /** Single Mode Input AIN8+ */ |
mbed_official | 507:d4fc7603a669 | 134 | MXC_E_ADC_PGA_MUX_CH_SEL_AIN8 = 8, |
mbed_official | 507:d4fc7603a669 | 135 | /** Single Mode Input AIN9+ */ |
mbed_official | 507:d4fc7603a669 | 136 | MXC_E_ADC_PGA_MUX_CH_SEL_AIN9 = 9, |
mbed_official | 507:d4fc7603a669 | 137 | /** Single Mode Input AIN10+ */ |
mbed_official | 507:d4fc7603a669 | 138 | MXC_E_ADC_PGA_MUX_CH_SEL_AIN10 = 10, |
mbed_official | 507:d4fc7603a669 | 139 | /** Single Mode Input AIN11+ */ |
mbed_official | 507:d4fc7603a669 | 140 | MXC_E_ADC_PGA_MUX_CH_SEL_AIN11 = 11, |
mbed_official | 507:d4fc7603a669 | 141 | /** Single Mode Input AIN12+ */ |
mbed_official | 507:d4fc7603a669 | 142 | MXC_E_ADC_PGA_MUX_CH_SEL_AIN12 = 12, |
mbed_official | 507:d4fc7603a669 | 143 | /** Single Mode Input AIN13+ */ |
mbed_official | 507:d4fc7603a669 | 144 | MXC_E_ADC_PGA_MUX_CH_SEL_AIN13 = 13, |
mbed_official | 507:d4fc7603a669 | 145 | /** Single Mode Input AIN14+ */ |
mbed_official | 507:d4fc7603a669 | 146 | MXC_E_ADC_PGA_MUX_CH_SEL_AIN14 = 14, |
mbed_official | 507:d4fc7603a669 | 147 | /** Single Mode Input AIN15+ */ |
mbed_official | 507:d4fc7603a669 | 148 | MXC_E_ADC_PGA_MUX_CH_SEL_AIN15 = 15, |
mbed_official | 507:d4fc7603a669 | 149 | /** Positive Input VSSADC */ |
mbed_official | 507:d4fc7603a669 | 150 | MXC_E_ADC_PGA_MUX_CH_SEL_VSSADC = 16, |
mbed_official | 507:d4fc7603a669 | 151 | /** Positive Input TMON_R */ |
mbed_official | 507:d4fc7603a669 | 152 | MXC_E_ADC_PGA_MUX_CH_SEL_TMON_R = 17, |
mbed_official | 507:d4fc7603a669 | 153 | /** Positive Input VDDA/4 */ |
mbed_official | 507:d4fc7603a669 | 154 | MXC_E_ADC_PGA_MUX_CH_SEL_VDDA4 = 18, |
mbed_official | 507:d4fc7603a669 | 155 | /** Positive Input PWRMAN_TST */ |
mbed_official | 507:d4fc7603a669 | 156 | MXC_E_ADC_PGA_MUX_CH_SEL_PWRMON_TST = 19, |
mbed_official | 507:d4fc7603a669 | 157 | /** Positive Input Ain0Div */ |
mbed_official | 507:d4fc7603a669 | 158 | MXC_E_ADC_PGA_MUX_CH_SEL_AIN0DIV = 20, |
mbed_official | 507:d4fc7603a669 | 159 | /** Positive Input OpAmp OUTA */ |
mbed_official | 507:d4fc7603a669 | 160 | MXC_E_ADC_PGA_MUX_CH_SEL_OUTA = 32, |
mbed_official | 507:d4fc7603a669 | 161 | /** Positive Input OpAmp OUTB */ |
mbed_official | 507:d4fc7603a669 | 162 | MXC_E_ADC_PGA_MUX_CH_SEL_OUTB = 33, |
mbed_official | 507:d4fc7603a669 | 163 | /** Positive Input OpAmp OUTC */ |
mbed_official | 507:d4fc7603a669 | 164 | MXC_E_ADC_PGA_MUX_CH_SEL_OUTC = 34, |
mbed_official | 507:d4fc7603a669 | 165 | /** Positive Input OpAmp OUTD */ |
mbed_official | 507:d4fc7603a669 | 166 | MXC_E_ADC_PGA_MUX_CH_SEL_OUTD = 35, |
mbed_official | 507:d4fc7603a669 | 167 | /** Positive INA+ */ |
mbed_official | 507:d4fc7603a669 | 168 | MXC_E_ADC_PGA_MUX_CH_SEL_INAPLUS = 36, |
mbed_official | 507:d4fc7603a669 | 169 | /** Positive SNO_or */ |
mbed_official | 507:d4fc7603a669 | 170 | MXC_E_ADC_PGA_MUX_CH_SEL_SNO_OR = 37, |
mbed_official | 507:d4fc7603a669 | 171 | /** Positive SCM_or */ |
mbed_official | 507:d4fc7603a669 | 172 | MXC_E_ADC_PGA_MUX_CH_SEL_SCM_OR = 38, |
mbed_official | 507:d4fc7603a669 | 173 | /** Positive TPROBE_sense */ |
mbed_official | 507:d4fc7603a669 | 174 | MXC_E_ADC_PGA_MUX_CH_SEL_TPROBE_SENSE = 48, |
mbed_official | 507:d4fc7603a669 | 175 | /** Positive VREFDAC */ |
mbed_official | 507:d4fc7603a669 | 176 | MXC_E_ADC_PGA_MUX_CH_SEL_VREFDAC = 49, |
mbed_official | 507:d4fc7603a669 | 177 | /** Positive VREFADJ */ |
mbed_official | 507:d4fc7603a669 | 178 | MXC_E_ADC_PGA_MUX_CH_SEL_VREFADJ = 50, |
mbed_official | 507:d4fc7603a669 | 179 | /** Positive Vdd3xtal */ |
mbed_official | 507:d4fc7603a669 | 180 | MXC_E_ADC_PGA_MUX_CH_SEL_VDD3XTAL = 51 |
mbed_official | 507:d4fc7603a669 | 181 | } mxc_adc_pga_mux_ch_sel_t; |
mbed_official | 507:d4fc7603a669 | 182 | |
mbed_official | 507:d4fc7603a669 | 183 | /** |
mbed_official | 507:d4fc7603a669 | 184 | * @brief Decoded with the MUX Channel Select to enable Differential Mode Input to the ADC. |
mbed_official | 507:d4fc7603a669 | 185 | */ |
mbed_official | 507:d4fc7603a669 | 186 | typedef enum { |
mbed_official | 507:d4fc7603a669 | 187 | /** Differential Mode Disabled */ |
mbed_official | 507:d4fc7603a669 | 188 | MXC_E_ADC_PGA_MUX_DIFF_DISABLE = 0, |
mbed_official | 507:d4fc7603a669 | 189 | /** Differential Mode Enabled */ |
mbed_official | 507:d4fc7603a669 | 190 | MXC_E_ADC_PGA_MUX_DIFF_ENABLE |
mbed_official | 507:d4fc7603a669 | 191 | } mxc_adc_pga_mux_diff_t; |
mbed_official | 507:d4fc7603a669 | 192 | |
mbed_official | 507:d4fc7603a669 | 193 | /** |
mbed_official | 507:d4fc7603a669 | 194 | * @brief Defines the PGA Gain Options. |
mbed_official | 507:d4fc7603a669 | 195 | */ |
mbed_official | 507:d4fc7603a669 | 196 | typedef enum { |
mbed_official | 507:d4fc7603a669 | 197 | /** PGA Gain = 1 */ |
mbed_official | 507:d4fc7603a669 | 198 | MXC_E_ADC_PGA_GAIN_1 = 0, |
mbed_official | 507:d4fc7603a669 | 199 | /** PGA Gain = 2 */ |
mbed_official | 507:d4fc7603a669 | 200 | MXC_E_ADC_PGA_GAIN_2, |
mbed_official | 507:d4fc7603a669 | 201 | /** PGA Gain = 4 */ |
mbed_official | 507:d4fc7603a669 | 202 | MXC_E_ADC_PGA_GAIN_4, |
mbed_official | 507:d4fc7603a669 | 203 | /** PGA Gain = 8 */ |
mbed_official | 507:d4fc7603a669 | 204 | MXC_E_ADC_PGA_GAIN_8, |
mbed_official | 507:d4fc7603a669 | 205 | } mxc_adc_pga_gain_t; |
mbed_official | 507:d4fc7603a669 | 206 | |
mbed_official | 507:d4fc7603a669 | 207 | /** |
mbed_official | 507:d4fc7603a669 | 208 | * @brief Defines the Switch Control Mode. |
mbed_official | 507:d4fc7603a669 | 209 | */ |
mbed_official | 507:d4fc7603a669 | 210 | typedef enum { |
mbed_official | 507:d4fc7603a669 | 211 | /** Switch Control Mode = Software */ |
mbed_official | 507:d4fc7603a669 | 212 | MXC_E_ADC_SPST_SW_CTRL_SOFTWARE = 0, |
mbed_official | 507:d4fc7603a669 | 213 | /** Switch Control Mode = Pulse Train */ |
mbed_official | 507:d4fc7603a669 | 214 | MXC_E_ADC_SPST_SW_CTRL_PULSETRAIN |
mbed_official | 507:d4fc7603a669 | 215 | } mxc_adc_spst_sw_ctrl_t; |
mbed_official | 507:d4fc7603a669 | 216 | |
mbed_official | 507:d4fc7603a669 | 217 | /** |
mbed_official | 507:d4fc7603a669 | 218 | * @brief Defines the number of channels to scan when Scan Mode is enabled. |
mbed_official | 507:d4fc7603a669 | 219 | */ |
mbed_official | 507:d4fc7603a669 | 220 | typedef enum { |
mbed_official | 507:d4fc7603a669 | 221 | /** Number of Channels to Scan = 1 */ |
mbed_official | 507:d4fc7603a669 | 222 | MXC_E_ADC_SCAN_CNT_1 = 0, |
mbed_official | 507:d4fc7603a669 | 223 | /** Number of Channels to Scan = 2 */ |
mbed_official | 507:d4fc7603a669 | 224 | MXC_E_ADC_SCAN_CNT_2, |
mbed_official | 507:d4fc7603a669 | 225 | /** Number of Channels to Scan = 3 */ |
mbed_official | 507:d4fc7603a669 | 226 | MXC_E_ADC_SCAN_CNT_3, |
mbed_official | 507:d4fc7603a669 | 227 | /** Number of Channels to Scan = 4 */ |
mbed_official | 507:d4fc7603a669 | 228 | MXC_E_ADC_SCAN_CNT_4, |
mbed_official | 507:d4fc7603a669 | 229 | /** Number of Channels to Scan = 5 */ |
mbed_official | 507:d4fc7603a669 | 230 | MXC_E_ADC_SCAN_CNT_5, |
mbed_official | 507:d4fc7603a669 | 231 | /** Number of Channels to Scan = 6 */ |
mbed_official | 507:d4fc7603a669 | 232 | MXC_E_ADC_SCAN_CNT_6, |
mbed_official | 507:d4fc7603a669 | 233 | /** Number of Channels to Scan = 7 */ |
mbed_official | 507:d4fc7603a669 | 234 | MXC_E_ADC_SCAN_CNT_7, |
mbed_official | 507:d4fc7603a669 | 235 | /** Number of Channels to Scan = 8 */ |
mbed_official | 507:d4fc7603a669 | 236 | MXC_E_ADC_SCAN_CNT_8, |
mbed_official | 507:d4fc7603a669 | 237 | } mxc_adc_scan_cnt_t; |
mbed_official | 507:d4fc7603a669 | 238 | |
mbed_official | 507:d4fc7603a669 | 239 | /* Offset Register Description |
mbed_official | 507:d4fc7603a669 | 240 | ====== =================================================== */ |
mbed_official | 507:d4fc7603a669 | 241 | typedef struct { |
mbed_official | 507:d4fc7603a669 | 242 | __IO uint32_t ctrl0; /* 0x0000 ADC Control Register 0 */ |
mbed_official | 507:d4fc7603a669 | 243 | __IO uint32_t pga_ctrl; /* 0x0004 PGA Control Register */ |
mbed_official | 507:d4fc7603a669 | 244 | __IO uint32_t tg_ctrl0; /* 0x0008 ADC Timing Generator Control 0 */ |
mbed_official | 507:d4fc7603a669 | 245 | __IO uint32_t tg_ctrl1; /* 0x000C ADC Timing Generator Control 1 */ |
mbed_official | 507:d4fc7603a669 | 246 | __IO uint32_t limit; /* 0x0010 ADC Limit Settings */ |
mbed_official | 507:d4fc7603a669 | 247 | __IO uint32_t intr; /* 0x0014 ADC Interrupt Flags and Enable/Disable Controls */ |
mbed_official | 507:d4fc7603a669 | 248 | __IO uint32_t out; /* 0x0018 ADC Output Register */ |
mbed_official | 507:d4fc7603a669 | 249 | } mxc_adc_regs_t; |
mbed_official | 507:d4fc7603a669 | 250 | |
mbed_official | 507:d4fc7603a669 | 251 | /* Offset Register Description |
mbed_official | 507:d4fc7603a669 | 252 | ====== =================================================== */ |
mbed_official | 507:d4fc7603a669 | 253 | typedef struct { |
mbed_official | 507:d4fc7603a669 | 254 | __IO uint32_t ctrl1; /* 0x0000 ADC Control Register 1 */ |
mbed_official | 507:d4fc7603a669 | 255 | __IO uint32_t scan1; /* 0x0004 ADC Auto-Scan Settings 1 */ |
mbed_official | 507:d4fc7603a669 | 256 | __IO uint32_t scan2; /* 0x0008 ADC Auto-Scan Settings 2 */ |
mbed_official | 507:d4fc7603a669 | 257 | __IO uint32_t ro_cal0; /* 0x000C ADC Ring Osc Calibration 0 */ |
mbed_official | 507:d4fc7603a669 | 258 | __IO uint32_t ro_cal1; /* 0x0010 ADC Ring Osc Calibration 1 */ |
mbed_official | 507:d4fc7603a669 | 259 | } mxc_adccfg_regs_t; |
mbed_official | 507:d4fc7603a669 | 260 | |
mbed_official | 507:d4fc7603a669 | 261 | typedef struct { |
mbed_official | 507:d4fc7603a669 | 262 | __IO uint16_t data; /* 0x0000 Read to pull sample data from ADC FIFO */ |
mbed_official | 507:d4fc7603a669 | 263 | } mxc_adc_fifo_regs_t; |
mbed_official | 507:d4fc7603a669 | 264 | |
mbed_official | 507:d4fc7603a669 | 265 | /* |
mbed_official | 507:d4fc7603a669 | 266 | Register offsets for module ADC, ADCCFG, ADC_FIFO |
mbed_official | 507:d4fc7603a669 | 267 | */ |
mbed_official | 507:d4fc7603a669 | 268 | #define MXC_R_ADC_OFFS_CTRL0 ((uint32_t)0x00000000UL) |
mbed_official | 507:d4fc7603a669 | 269 | #define MXC_R_ADC_OFFS_PGA_CTRL ((uint32_t)0x00000004UL) |
mbed_official | 507:d4fc7603a669 | 270 | #define MXC_R_ADC_OFFS_TG_CTRL0 ((uint32_t)0x00000008UL) |
mbed_official | 507:d4fc7603a669 | 271 | #define MXC_R_ADC_OFFS_TG_CTRL1 ((uint32_t)0x0000000CUL) |
mbed_official | 507:d4fc7603a669 | 272 | #define MXC_R_ADC_OFFS_LIMIT ((uint32_t)0x00000010UL) |
mbed_official | 507:d4fc7603a669 | 273 | #define MXC_R_ADC_OFFS_INTR ((uint32_t)0x00000014UL) |
mbed_official | 507:d4fc7603a669 | 274 | #define MXC_R_ADC_OFFS_OUT ((uint32_t)0x00000018UL) |
mbed_official | 507:d4fc7603a669 | 275 | |
mbed_official | 507:d4fc7603a669 | 276 | #define MXC_R_ADCCFG_OFFS_CTRL1 ((uint32_t)0x00000000UL) |
mbed_official | 507:d4fc7603a669 | 277 | #define MXC_R_ADCCFG_OFFS_SCAN1 ((uint32_t)0x00000004UL) |
mbed_official | 507:d4fc7603a669 | 278 | #define MXC_R_ADCCFG_OFFS_SCAN2 ((uint32_t)0x00000008UL) |
mbed_official | 507:d4fc7603a669 | 279 | #define MXC_R_ADCCFG_OFFS_RO_CAL0 ((uint32_t)0x0000000CUL) |
mbed_official | 507:d4fc7603a669 | 280 | #define MXC_R_ADCCFG_OFFS_RO_CAL1 ((uint32_t)0x00000010UL) |
mbed_official | 507:d4fc7603a669 | 281 | #define MXC_R_ADC_FIFO_OFFS_DATA ((uint32_t)0x00000000UL) |
mbed_official | 507:d4fc7603a669 | 282 | |
mbed_official | 507:d4fc7603a669 | 283 | /* |
mbed_official | 507:d4fc7603a669 | 284 | Field positions and masks for module ADC. |
mbed_official | 507:d4fc7603a669 | 285 | */ |
mbed_official | 507:d4fc7603a669 | 286 | #define MXC_F_ADC_CTRL0_ADC_WAKE_CNT_POS 0 |
mbed_official | 507:d4fc7603a669 | 287 | #define MXC_F_ADC_CTRL0_ADC_WAKE_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL0_ADC_WAKE_CNT_POS)) |
mbed_official | 507:d4fc7603a669 | 288 | #define MXC_F_ADC_CTRL0_ADC_STRT_MODE_POS 5 |
mbed_official | 507:d4fc7603a669 | 289 | #define MXC_F_ADC_CTRL0_ADC_STRT_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_STRT_MODE_POS)) |
mbed_official | 507:d4fc7603a669 | 290 | #define MXC_F_ADC_CTRL0_ADC_RANGE_POS 6 |
mbed_official | 507:d4fc7603a669 | 291 | #define MXC_F_ADC_CTRL0_ADC_RANGE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_RANGE_POS)) |
mbed_official | 507:d4fc7603a669 | 292 | #define MXC_F_ADC_CTRL0_ADC_BI_POL_POS 7 |
mbed_official | 507:d4fc7603a669 | 293 | #define MXC_F_ADC_CTRL0_ADC_BI_POL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_BI_POL_POS)) |
mbed_official | 507:d4fc7603a669 | 294 | #define MXC_F_ADC_CTRL0_ADC_DV_REG_POS 8 |
mbed_official | 507:d4fc7603a669 | 295 | #define MXC_F_ADC_CTRL0_ADC_DV_REG ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_DV_REG_POS)) |
mbed_official | 507:d4fc7603a669 | 296 | #define MXC_F_ADC_CTRL0_ADC_DV_POS 9 |
mbed_official | 507:d4fc7603a669 | 297 | #define MXC_F_ADC_CTRL0_ADC_DV ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_DV_POS)) |
mbed_official | 507:d4fc7603a669 | 298 | #define MXC_F_ADC_CTRL0_ADC_LMT_DMODE_POS 10 |
mbed_official | 507:d4fc7603a669 | 299 | #define MXC_F_ADC_CTRL0_ADC_LMT_DMODE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_LMT_DMODE_POS)) |
mbed_official | 507:d4fc7603a669 | 300 | #define MXC_F_ADC_CTRL0_ADC_SMP_EXT_POS 11 |
mbed_official | 507:d4fc7603a669 | 301 | #define MXC_F_ADC_CTRL0_ADC_SMP_EXT ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_SMP_EXT_POS)) |
mbed_official | 507:d4fc7603a669 | 302 | #define MXC_F_ADC_CTRL0_ADC_CLK_EN_POS 12 |
mbed_official | 507:d4fc7603a669 | 303 | #define MXC_F_ADC_CTRL0_ADC_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_CLK_EN_POS)) |
mbed_official | 507:d4fc7603a669 | 304 | #define MXC_F_ADC_CTRL0_CPU_ADC_RST_POS 13 |
mbed_official | 507:d4fc7603a669 | 305 | #define MXC_F_ADC_CTRL0_CPU_ADC_RST ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_RST_POS)) |
mbed_official | 507:d4fc7603a669 | 306 | #define MXC_F_ADC_CTRL0_CPU_ADC_START_POS 14 |
mbed_official | 507:d4fc7603a669 | 307 | #define MXC_F_ADC_CTRL0_CPU_ADC_START ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_START_POS)) |
mbed_official | 507:d4fc7603a669 | 308 | #define MXC_F_ADC_CTRL0_CPU_ADC_EN_POS 15 |
mbed_official | 507:d4fc7603a669 | 309 | #define MXC_F_ADC_CTRL0_CPU_ADC_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_EN_POS)) |
mbed_official | 507:d4fc7603a669 | 310 | #define MXC_F_ADC_CTRL0_ADC_FIFO_FULL_POS 18 |
mbed_official | 507:d4fc7603a669 | 311 | #define MXC_F_ADC_CTRL0_ADC_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_FIFO_FULL_POS)) |
mbed_official | 507:d4fc7603a669 | 312 | #define MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY_POS 19 |
mbed_official | 507:d4fc7603a669 | 313 | #define MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY_POS)) |
mbed_official | 507:d4fc7603a669 | 314 | #define MXC_F_ADC_CTRL0_AVG_MODE_POS 20 |
mbed_official | 507:d4fc7603a669 | 315 | #define MXC_F_ADC_CTRL0_AVG_MODE ((uint32_t)(0x00000003UL << MXC_F_ADC_CTRL0_AVG_MODE_POS)) |
mbed_official | 507:d4fc7603a669 | 316 | #define MXC_F_ADC_CTRL0_CPU_DAC_START_POS 22 |
mbed_official | 507:d4fc7603a669 | 317 | #define MXC_F_ADC_CTRL0_CPU_DAC_START ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_DAC_START_POS)) |
mbed_official | 507:d4fc7603a669 | 318 | #define MXC_F_ADC_CTRL0_ADC_CLK_MODE_POS 24 |
mbed_official | 507:d4fc7603a669 | 319 | #define MXC_F_ADC_CTRL0_ADC_CLK_MODE ((uint32_t)(0x00000007UL << MXC_F_ADC_CTRL0_ADC_CLK_MODE_POS)) |
mbed_official | 507:d4fc7603a669 | 320 | #define MXC_F_ADC_CTRL0_ADC_MODE_POS 28 |
mbed_official | 507:d4fc7603a669 | 321 | #define MXC_F_ADC_CTRL0_ADC_MODE ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL0_ADC_MODE_POS)) |
mbed_official | 507:d4fc7603a669 | 322 | |
mbed_official | 507:d4fc7603a669 | 323 | #define MXC_F_ADC_PGA_CTRL_PGA_GAIN_POS 0 |
mbed_official | 507:d4fc7603a669 | 324 | #define MXC_F_ADC_PGA_CTRL_PGA_GAIN ((uint32_t)(0x00000003UL << MXC_F_ADC_PGA_CTRL_PGA_GAIN_POS)) |
mbed_official | 507:d4fc7603a669 | 325 | #define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN_POS 2 |
mbed_official | 507:d4fc7603a669 | 326 | #define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN_POS)) |
mbed_official | 507:d4fc7603a669 | 327 | #define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_POS 3 |
mbed_official | 507:d4fc7603a669 | 328 | #define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_POS)) |
mbed_official | 507:d4fc7603a669 | 329 | #define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY_POS 4 |
mbed_official | 507:d4fc7603a669 | 330 | #define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY_POS)) |
mbed_official | 507:d4fc7603a669 | 331 | #define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_POS 5 |
mbed_official | 507:d4fc7603a669 | 332 | #define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_POS)) |
mbed_official | 507:d4fc7603a669 | 333 | #define MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS_POS 6 |
mbed_official | 507:d4fc7603a669 | 334 | #define MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS_POS)) |
mbed_official | 507:d4fc7603a669 | 335 | #define MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT_POS 8 |
mbed_official | 507:d4fc7603a669 | 336 | #define MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT ((uint32_t)(0x0000001FUL << MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT_POS)) |
mbed_official | 507:d4fc7603a669 | 337 | #define MXC_F_ADC_PGA_CTRL_MUX_SW_AIN_POS 13 |
mbed_official | 507:d4fc7603a669 | 338 | #define MXC_F_ADC_PGA_CTRL_MUX_SW_AIN ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_SW_AIN_POS)) |
mbed_official | 507:d4fc7603a669 | 339 | #define MXC_F_ADC_PGA_CTRL_MUX_DIFF_POS 14 |
mbed_official | 507:d4fc7603a669 | 340 | #define MXC_F_ADC_PGA_CTRL_MUX_DIFF ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_DIFF_POS)) |
mbed_official | 507:d4fc7603a669 | 341 | #define MXC_F_ADC_PGA_CTRL_MUX_MODE_POS 15 |
mbed_official | 507:d4fc7603a669 | 342 | #define MXC_F_ADC_PGA_CTRL_MUX_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_MODE_POS)) |
mbed_official | 507:d4fc7603a669 | 343 | #define MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT_POS 20 |
mbed_official | 507:d4fc7603a669 | 344 | #define MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT_POS)) |
mbed_official | 507:d4fc7603a669 | 345 | #define MXC_F_ADC_PGA_CTRL_MUX_CH_SEL_POS 24 |
mbed_official | 507:d4fc7603a669 | 346 | #define MXC_F_ADC_PGA_CTRL_MUX_CH_SEL ((uint32_t)(0x0000003FUL << MXC_F_ADC_PGA_CTRL_MUX_CH_SEL_POS)) |
mbed_official | 507:d4fc7603a669 | 347 | |
mbed_official | 507:d4fc7603a669 | 348 | #define MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT_POS 0 |
mbed_official | 507:d4fc7603a669 | 349 | #define MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT_POS)) |
mbed_official | 507:d4fc7603a669 | 350 | #define MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT_POS 16 |
mbed_official | 507:d4fc7603a669 | 351 | #define MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT_POS)) |
mbed_official | 507:d4fc7603a669 | 352 | |
mbed_official | 507:d4fc7603a669 | 353 | #define MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT_POS 0 |
mbed_official | 507:d4fc7603a669 | 354 | #define MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT_POS)) |
mbed_official | 507:d4fc7603a669 | 355 | #define MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT_POS 4 |
mbed_official | 507:d4fc7603a669 | 356 | #define MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT_POS)) |
mbed_official | 507:d4fc7603a669 | 357 | #define MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT_POS 8 |
mbed_official | 507:d4fc7603a669 | 358 | #define MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT ((uint32_t)(0x00000007UL << MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT_POS)) |
mbed_official | 507:d4fc7603a669 | 359 | #define MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT_POS 12 |
mbed_official | 507:d4fc7603a669 | 360 | #define MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT_POS)) |
mbed_official | 507:d4fc7603a669 | 361 | #define MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT_POS 16 |
mbed_official | 507:d4fc7603a669 | 362 | #define MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT_POS)) |
mbed_official | 507:d4fc7603a669 | 363 | |
mbed_official | 507:d4fc7603a669 | 364 | #define MXC_F_ADC_LIMIT_LO_LIMIT_POS 0 |
mbed_official | 507:d4fc7603a669 | 365 | #define MXC_F_ADC_LIMIT_LO_LIMIT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_LIMIT_LO_LIMIT_POS)) |
mbed_official | 507:d4fc7603a669 | 366 | #define MXC_F_ADC_LIMIT_HI_LIMIT_POS 16 |
mbed_official | 507:d4fc7603a669 | 367 | #define MXC_F_ADC_LIMIT_HI_LIMIT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_LIMIT_HI_LIMIT_POS)) |
mbed_official | 507:d4fc7603a669 | 368 | |
mbed_official | 507:d4fc7603a669 | 369 | #define MXC_F_ADC_INTR_FIFO_AF_POS 6 |
mbed_official | 507:d4fc7603a669 | 370 | #define MXC_F_ADC_INTR_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_AF_POS)) |
mbed_official | 507:d4fc7603a669 | 371 | #define MXC_F_ADC_INTR_OUT_RNG_IF_POS 7 |
mbed_official | 507:d4fc7603a669 | 372 | #define MXC_F_ADC_INTR_OUT_RNG_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_OUT_RNG_IF_POS)) |
mbed_official | 507:d4fc7603a669 | 373 | #define MXC_F_ADC_INTR_HI_RNG_IF_POS 8 |
mbed_official | 507:d4fc7603a669 | 374 | #define MXC_F_ADC_INTR_HI_RNG_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_HI_RNG_IF_POS)) |
mbed_official | 507:d4fc7603a669 | 375 | #define MXC_F_ADC_INTR_LO_RNG_IF_POS 9 |
mbed_official | 507:d4fc7603a669 | 376 | #define MXC_F_ADC_INTR_LO_RNG_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_LO_RNG_IF_POS)) |
mbed_official | 507:d4fc7603a669 | 377 | #define MXC_F_ADC_INTR_DONE_IF_POS 10 |
mbed_official | 507:d4fc7603a669 | 378 | #define MXC_F_ADC_INTR_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_DONE_IF_POS)) |
mbed_official | 507:d4fc7603a669 | 379 | #define MXC_F_ADC_INTR_FIFO_UF_IF_POS 11 |
mbed_official | 507:d4fc7603a669 | 380 | #define MXC_F_ADC_INTR_FIFO_UF_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_UF_IF_POS)) |
mbed_official | 507:d4fc7603a669 | 381 | #define MXC_F_ADC_INTR_FIFO_OF_IF_POS 12 |
mbed_official | 507:d4fc7603a669 | 382 | #define MXC_F_ADC_INTR_FIFO_OF_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_OF_IF_POS)) |
mbed_official | 507:d4fc7603a669 | 383 | #define MXC_F_ADC_INTR_FIFO_3Q_IF_POS 13 |
mbed_official | 507:d4fc7603a669 | 384 | #define MXC_F_ADC_INTR_FIFO_3Q_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_3Q_IF_POS)) |
mbed_official | 507:d4fc7603a669 | 385 | #define MXC_F_ADC_INTR_FIFO_2Q_IF_POS 14 |
mbed_official | 507:d4fc7603a669 | 386 | #define MXC_F_ADC_INTR_FIFO_2Q_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_2Q_IF_POS)) |
mbed_official | 507:d4fc7603a669 | 387 | #define MXC_F_ADC_INTR_FIFO_1Q_IF_POS 15 |
mbed_official | 507:d4fc7603a669 | 388 | #define MXC_F_ADC_INTR_FIFO_1Q_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_1Q_IF_POS)) |
mbed_official | 507:d4fc7603a669 | 389 | #define MXC_F_ADC_INTR_SPST0_CTRL_MODE_POS 16 |
mbed_official | 507:d4fc7603a669 | 390 | #define MXC_F_ADC_INTR_SPST0_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST0_CTRL_MODE_POS)) |
mbed_official | 507:d4fc7603a669 | 391 | #define MXC_F_ADC_INTR_SPST1_CTRL_MODE_POS 17 |
mbed_official | 507:d4fc7603a669 | 392 | #define MXC_F_ADC_INTR_SPST1_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST1_CTRL_MODE_POS)) |
mbed_official | 507:d4fc7603a669 | 393 | #define MXC_F_ADC_INTR_SPST2_CTRL_MODE_POS 18 |
mbed_official | 507:d4fc7603a669 | 394 | #define MXC_F_ADC_INTR_SPST2_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST2_CTRL_MODE_POS)) |
mbed_official | 507:d4fc7603a669 | 395 | #define MXC_F_ADC_INTR_SPST3_CTRL_MODE_POS 19 |
mbed_official | 507:d4fc7603a669 | 396 | #define MXC_F_ADC_INTR_SPST3_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST3_CTRL_MODE_POS)) |
mbed_official | 507:d4fc7603a669 | 397 | #define MXC_F_ADC_INTR_OUT_RNG_IE_POS 23 |
mbed_official | 507:d4fc7603a669 | 398 | #define MXC_F_ADC_INTR_OUT_RNG_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_OUT_RNG_IE_POS)) |
mbed_official | 507:d4fc7603a669 | 399 | #define MXC_F_ADC_INTR_HI_RNG_IE_POS 24 |
mbed_official | 507:d4fc7603a669 | 400 | #define MXC_F_ADC_INTR_HI_RNG_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_HI_RNG_IE_POS)) |
mbed_official | 507:d4fc7603a669 | 401 | #define MXC_F_ADC_INTR_LO_RNG_IE_POS 25 |
mbed_official | 507:d4fc7603a669 | 402 | #define MXC_F_ADC_INTR_LO_RNG_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_LO_RNG_IE_POS)) |
mbed_official | 507:d4fc7603a669 | 403 | #define MXC_F_ADC_INTR_DONE_IE_POS 26 |
mbed_official | 507:d4fc7603a669 | 404 | #define MXC_F_ADC_INTR_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_DONE_IE_POS)) |
mbed_official | 507:d4fc7603a669 | 405 | #define MXC_F_ADC_INTR_FIFO_UF_IE_POS 27 |
mbed_official | 507:d4fc7603a669 | 406 | #define MXC_F_ADC_INTR_FIFO_UF_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_UF_IE_POS)) |
mbed_official | 507:d4fc7603a669 | 407 | #define MXC_F_ADC_INTR_FIFO_OF_IE_POS 28 |
mbed_official | 507:d4fc7603a669 | 408 | #define MXC_F_ADC_INTR_FIFO_OF_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_OF_IE_POS)) |
mbed_official | 507:d4fc7603a669 | 409 | #define MXC_F_ADC_INTR_FIFO_3Q_IE_POS 29 |
mbed_official | 507:d4fc7603a669 | 410 | #define MXC_F_ADC_INTR_FIFO_3Q_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_3Q_IE_POS)) |
mbed_official | 507:d4fc7603a669 | 411 | #define MXC_F_ADC_INTR_FIFO_2Q_IE_POS 30 |
mbed_official | 507:d4fc7603a669 | 412 | #define MXC_F_ADC_INTR_FIFO_2Q_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_2Q_IE_POS)) |
mbed_official | 507:d4fc7603a669 | 413 | #define MXC_F_ADC_INTR_FIFO_1Q_IE_POS 31 |
mbed_official | 507:d4fc7603a669 | 414 | #define MXC_F_ADC_INTR_FIFO_1Q_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_1Q_IE_POS)) |
mbed_official | 507:d4fc7603a669 | 415 | |
mbed_official | 507:d4fc7603a669 | 416 | #define MXC_F_ADC_OUT_DATA_REG_POS 0 |
mbed_official | 507:d4fc7603a669 | 417 | #define MXC_F_ADC_OUT_DATA_REG ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_OUT_DATA_REG_POS)) |
mbed_official | 507:d4fc7603a669 | 418 | |
mbed_official | 507:d4fc7603a669 | 419 | #define MXC_F_ADC_CTRL1_ADC_SCAN_CNT_POS 16 |
mbed_official | 507:d4fc7603a669 | 420 | #define MXC_F_ADC_CTRL1_ADC_SCAN_CNT ((uint32_t)(0x00000007UL << MXC_F_ADC_CTRL1_ADC_SCAN_CNT_POS)) |
mbed_official | 507:d4fc7603a669 | 421 | |
mbed_official | 507:d4fc7603a669 | 422 | #define MXC_F_ADC_SCAN1_ADC_SCAN0_POS 0 |
mbed_official | 507:d4fc7603a669 | 423 | #define MXC_F_ADC_SCAN1_ADC_SCAN0 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN0_POS)) |
mbed_official | 507:d4fc7603a669 | 424 | #define MXC_F_ADC_SCAN1_ADC_SCAN1_POS 8 |
mbed_official | 507:d4fc7603a669 | 425 | #define MXC_F_ADC_SCAN1_ADC_SCAN1 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN1_POS)) |
mbed_official | 507:d4fc7603a669 | 426 | #define MXC_F_ADC_SCAN1_ADC_SCAN2_POS 16 |
mbed_official | 507:d4fc7603a669 | 427 | #define MXC_F_ADC_SCAN1_ADC_SCAN2 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN2_POS)) |
mbed_official | 507:d4fc7603a669 | 428 | #define MXC_F_ADC_SCAN1_ADC_SCAN3_POS 24 |
mbed_official | 507:d4fc7603a669 | 429 | #define MXC_F_ADC_SCAN1_ADC_SCAN3 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN3_POS)) |
mbed_official | 507:d4fc7603a669 | 430 | |
mbed_official | 507:d4fc7603a669 | 431 | #define MXC_F_ADC_SCAN2_ADC_SCAN4_POS 0 |
mbed_official | 507:d4fc7603a669 | 432 | #define MXC_F_ADC_SCAN2_ADC_SCAN4 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN4_POS)) |
mbed_official | 507:d4fc7603a669 | 433 | #define MXC_F_ADC_SCAN2_ADC_SCAN5_POS 8 |
mbed_official | 507:d4fc7603a669 | 434 | #define MXC_F_ADC_SCAN2_ADC_SCAN5 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN5_POS)) |
mbed_official | 507:d4fc7603a669 | 435 | #define MXC_F_ADC_SCAN2_ADC_SCAN6_POS 16 |
mbed_official | 507:d4fc7603a669 | 436 | #define MXC_F_ADC_SCAN2_ADC_SCAN6 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN6_POS)) |
mbed_official | 507:d4fc7603a669 | 437 | #define MXC_F_ADC_SCAN2_ADC_SCAN7_POS 24 |
mbed_official | 507:d4fc7603a669 | 438 | #define MXC_F_ADC_SCAN2_ADC_SCAN7 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN7_POS)) |
mbed_official | 507:d4fc7603a669 | 439 | |
mbed_official | 507:d4fc7603a669 | 440 | #define MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS 0 |
mbed_official | 507:d4fc7603a669 | 441 | #define MXC_F_ADC_RO_CAL0_RO_CAL_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS)) |
mbed_official | 507:d4fc7603a669 | 442 | #define MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS 1 |
mbed_official | 507:d4fc7603a669 | 443 | #define MXC_F_ADC_RO_CAL0_RO_CAL_RUN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS)) |
mbed_official | 507:d4fc7603a669 | 444 | #define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS 2 |
mbed_official | 507:d4fc7603a669 | 445 | #define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS)) |
mbed_official | 507:d4fc7603a669 | 446 | #define MXC_F_ADC_RO_CAL0_TRM_MU_POS 8 |
mbed_official | 507:d4fc7603a669 | 447 | #define MXC_F_ADC_RO_CAL0_TRM_MU ((uint32_t)(0x00000FFFUL << MXC_F_ADC_RO_CAL0_TRM_MU_POS)) |
mbed_official | 507:d4fc7603a669 | 448 | #define MXC_F_ADC_RO_CAL0_RO_TRM_POS 23 |
mbed_official | 507:d4fc7603a669 | 449 | #define MXC_F_ADC_RO_CAL0_RO_TRM ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL0_RO_TRM_POS)) |
mbed_official | 507:d4fc7603a669 | 450 | |
mbed_official | 507:d4fc7603a669 | 451 | #define MXC_F_ADC_RO_CAL1_TRM_INIT_POS 0 |
mbed_official | 507:d4fc7603a669 | 452 | #define MXC_F_ADC_RO_CAL1_TRM_INIT ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_INIT_POS)) |
mbed_official | 507:d4fc7603a669 | 453 | #define MXC_F_ADC_RO_CAL1_TRM_MIN_POS 10 |
mbed_official | 507:d4fc7603a669 | 454 | #define MXC_F_ADC_RO_CAL1_TRM_MIN ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MIN_POS)) |
mbed_official | 507:d4fc7603a669 | 455 | #define MXC_F_ADC_RO_CAL1_TRM_MAX_POS 20 |
mbed_official | 507:d4fc7603a669 | 456 | #define MXC_F_ADC_RO_CAL1_TRM_MAX ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MAX_POS)) |
mbed_official | 507:d4fc7603a669 | 457 | |
mbed_official | 507:d4fc7603a669 | 458 | #ifdef __cplusplus |
mbed_official | 507:d4fc7603a669 | 459 | } |
mbed_official | 507:d4fc7603a669 | 460 | #endif |
mbed_official | 507:d4fc7603a669 | 461 | |
mbed_official | 507:d4fc7603a669 | 462 | /** |
mbed_official | 507:d4fc7603a669 | 463 | * @} |
mbed_official | 507:d4fc7603a669 | 464 | */ |
mbed_official | 507:d4fc7603a669 | 465 | |
mbed_official | 507:d4fc7603a669 | 466 | #endif /* _MXC_ADC_REGS_H */ |