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targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rcc.h@489:119543c9f674, 2015-03-12 (annotated)

Committer:: mbed_official
Date:: Thu Mar 12 14:30:49 2015 +0000
Revision:: 489:119543c9f674

Synchronized with git revision 051854181516992fb498d51f9ee6e70cbad9e083

Full URL: https://github.com/mbedmicro/mbed/commit/051854181516992fb498d51f9ee6e70cbad9e083/

Fix ksdk mcu HAL - stopbit

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User	Revision	Line number	New contents of line
mbed_official	489:119543c9f674	1	/**
mbed_official	489:119543c9f674	2	******************************************************************************
mbed_official	489:119543c9f674	3	* @file stm32f1xx_hal_rcc.h
mbed_official	489:119543c9f674	4	* @author MCD Application Team
mbed_official	489:119543c9f674	5	* @version V1.0.0
mbed_official	489:119543c9f674	6	* @date 15-December-2014
mbed_official	489:119543c9f674	7	* @brief Header file of RCC HAL module.
mbed_official	489:119543c9f674	8	******************************************************************************
mbed_official	489:119543c9f674	9	* @attention
mbed_official	489:119543c9f674	10	*
mbed_official	489:119543c9f674	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	489:119543c9f674	12	*
mbed_official	489:119543c9f674	13	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	489:119543c9f674	14	* are permitted provided that the following conditions are met:
mbed_official	489:119543c9f674	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	489:119543c9f674	16	* this list of conditions and the following disclaimer.
mbed_official	489:119543c9f674	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	489:119543c9f674	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	489:119543c9f674	19	* and/or other materials provided with the distribution.
mbed_official	489:119543c9f674	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	489:119543c9f674	21	* may be used to endorse or promote products derived from this software
mbed_official	489:119543c9f674	22	* without specific prior written permission.
mbed_official	489:119543c9f674	23	*
mbed_official	489:119543c9f674	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	489:119543c9f674	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	489:119543c9f674	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	489:119543c9f674	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	489:119543c9f674	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	489:119543c9f674	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	489:119543c9f674	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	489:119543c9f674	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	489:119543c9f674	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	489:119543c9f674	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	489:119543c9f674	34	*
mbed_official	489:119543c9f674	35	******************************************************************************
mbed_official	489:119543c9f674	36	*/
mbed_official	489:119543c9f674	37
mbed_official	489:119543c9f674	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	489:119543c9f674	39	#ifndef __STM32F1xx_HAL_RCC_H
mbed_official	489:119543c9f674	40	#define __STM32F1xx_HAL_RCC_H
mbed_official	489:119543c9f674	41
mbed_official	489:119543c9f674	42	#ifdef __cplusplus
mbed_official	489:119543c9f674	43	extern "C" {
mbed_official	489:119543c9f674	44	#endif
mbed_official	489:119543c9f674	45
mbed_official	489:119543c9f674	46	/* Includes ------------------------------------------------------------------*/
mbed_official	489:119543c9f674	47	#include "stm32f1xx_hal_def.h"
mbed_official	489:119543c9f674	48
mbed_official	489:119543c9f674	49	/** @addtogroup STM32F1xx_HAL_Driver
mbed_official	489:119543c9f674	50	* @{
mbed_official	489:119543c9f674	51	*/
mbed_official	489:119543c9f674	52
mbed_official	489:119543c9f674	53	/** @addtogroup RCC
mbed_official	489:119543c9f674	54	* @{
mbed_official	489:119543c9f674	55	*/
mbed_official	489:119543c9f674	56
mbed_official	489:119543c9f674	57	/** @addtogroup RCC_Private_Constants
mbed_official	489:119543c9f674	58	* @{
mbed_official	489:119543c9f674	59	*/
mbed_official	489:119543c9f674	60
mbed_official	489:119543c9f674	61	#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)
mbed_official	489:119543c9f674	62	#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
mbed_official	489:119543c9f674	63	#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
mbed_official	489:119543c9f674	64	#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
mbed_official	489:119543c9f674	65	#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official	489:119543c9f674	66	#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official	489:119543c9f674	67	#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official	489:119543c9f674	68	#define LSI_VALUE ((uint32_t)40000) /* 40kHz */
mbed_official	489:119543c9f674	69
mbed_official	489:119543c9f674	70	/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
mbed_official	489:119543c9f674	71	* @brief RCC registers bit address in the alias region
mbed_official	489:119543c9f674	72	* @{
mbed_official	489:119543c9f674	73	*/
mbed_official	489:119543c9f674	74	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
mbed_official	489:119543c9f674	75	#define RCC_CR_OFFSET 0x00
mbed_official	489:119543c9f674	76	#define RCC_CFGR_OFFSET 0x04
mbed_official	489:119543c9f674	77	#define RCC_CIR_OFFSET 0x08
mbed_official	489:119543c9f674	78	#define RCC_BDCR_OFFSET 0x20
mbed_official	489:119543c9f674	79	#define RCC_CSR_OFFSET 0x24
mbed_official	489:119543c9f674	80	#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)
mbed_official	489:119543c9f674	81	#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)
mbed_official	489:119543c9f674	82	#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)
mbed_official	489:119543c9f674	83	#define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET)
mbed_official	489:119543c9f674	84	#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)
mbed_official	489:119543c9f674	85
mbed_official	489:119543c9f674	86	/* --- CR Register ---*/
mbed_official	489:119543c9f674	87	/* Alias word address of HSION bit */
mbed_official	489:119543c9f674	88	#define HSION_BITNUMBER POSITION_VAL(RCC_CR_HSION)
mbed_official	489:119543c9f674	89	#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (HSION_BITNUMBER * 4)))
mbed_official	489:119543c9f674	90	/* Alias word address of HSEON bit */
mbed_official	489:119543c9f674	91	#define HSEON_BITNUMBER POSITION_VAL(RCC_CR_HSEON)
mbed_official	489:119543c9f674	92	#define CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (HSEON_BITNUMBER * 4)))
mbed_official	489:119543c9f674	93	/* Alias word address of CSSON bit */
mbed_official	489:119543c9f674	94	#define CSSON_BITNUMBER POSITION_VAL(RCC_CR_CSSON)
mbed_official	489:119543c9f674	95	#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (CSSON_BITNUMBER * 4)))
mbed_official	489:119543c9f674	96	/* Alias word address of PLLON bit */
mbed_official	489:119543c9f674	97	#define PLLON_BITNUMBER POSITION_VAL(RCC_CR_PLLON)
mbed_official	489:119543c9f674	98	#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (PLLON_BITNUMBER * 4)))
mbed_official	489:119543c9f674	99
mbed_official	489:119543c9f674	100	/* --- CSR Register ---*/
mbed_official	489:119543c9f674	101	/* Alias word address of LSION bit */
mbed_official	489:119543c9f674	102	#define LSION_BITNUMBER POSITION_VAL(RCC_CSR_LSION)
mbed_official	489:119543c9f674	103	#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSION_BITNUMBER * 4)))
mbed_official	489:119543c9f674	104
mbed_official	489:119543c9f674	105	/* --- BDCR Register ---*/
mbed_official	489:119543c9f674	106	/* Alias word address of LSEON bit */
mbed_official	489:119543c9f674	107	#define LSEON_BITNUMBER POSITION_VAL(RCC_BDCR_LSEON)
mbed_official	489:119543c9f674	108	#define BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (LSEON_BITNUMBER * 4)))
mbed_official	489:119543c9f674	109
mbed_official	489:119543c9f674	110	/* Alias word address of LSEON bit */
mbed_official	489:119543c9f674	111	#define LSEBYP_BITNUMBER POSITION_VAL(RCC_BDCR_LSEBYP)
mbed_official	489:119543c9f674	112	#define BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (LSEBYP_BITNUMBER * 4)))
mbed_official	489:119543c9f674	113
mbed_official	489:119543c9f674	114	/* Alias word address of RTCEN bit */
mbed_official	489:119543c9f674	115	#define RTCEN_BITNUMBER POSITION_VAL(RCC_BDCR_RTCEN)
mbed_official	489:119543c9f674	116	#define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RTCEN_BITNUMBER * 4)))
mbed_official	489:119543c9f674	117
mbed_official	489:119543c9f674	118	/* Alias word address of BDRST bit */
mbed_official	489:119543c9f674	119	#define BDRST_BITNUMBER POSITION_VAL(RCC_BDCR_BDRST)
mbed_official	489:119543c9f674	120	#define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (BDRST_BITNUMBER * 4)))
mbed_official	489:119543c9f674	121
mbed_official	489:119543c9f674	122	/* CR register byte 2 (Bits[23:16]) base address */
mbed_official	489:119543c9f674	123	#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02))
mbed_official	489:119543c9f674	124
mbed_official	489:119543c9f674	125	/* CIR register byte 1 (Bits[15:8]) base address */
mbed_official	489:119543c9f674	126	#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01))
mbed_official	489:119543c9f674	127
mbed_official	489:119543c9f674	128	/* CIR register byte 2 (Bits[23:16]) base address */
mbed_official	489:119543c9f674	129	#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02))
mbed_official	489:119543c9f674	130
mbed_official	489:119543c9f674	131	/* Defines used for Flags */
mbed_official	489:119543c9f674	132	#define CR_REG_INDEX ((uint8_t)1)
mbed_official	489:119543c9f674	133	#define BDCR_REG_INDEX ((uint8_t)2)
mbed_official	489:119543c9f674	134	#define CSR_REG_INDEX ((uint8_t)3)
mbed_official	489:119543c9f674	135
mbed_official	489:119543c9f674	136	#define RCC_FLAG_MASK ((uint8_t)0x1F)
mbed_official	489:119543c9f674	137
mbed_official	489:119543c9f674	138	/**
mbed_official	489:119543c9f674	139	* @}
mbed_official	489:119543c9f674	140	*/
mbed_official	489:119543c9f674	141
mbed_official	489:119543c9f674	142	/** @addtogroup RCC_Private_Macros
mbed_official	489:119543c9f674	143	* @{
mbed_official	489:119543c9f674	144	*/
mbed_official	489:119543c9f674	145
mbed_official	489:119543c9f674	146	/** @defgroup RCC_Alias_For_Legacy Alias define maintained for legacy
mbed_official	489:119543c9f674	147	* @{
mbed_official	489:119543c9f674	148	*/
mbed_official	489:119543c9f674	149	#define __HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
mbed_official	489:119543c9f674	150	#define __HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
mbed_official	489:119543c9f674	151	#define __HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
mbed_official	489:119543c9f674	152	#define __HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
mbed_official	489:119543c9f674	153	/**
mbed_official	489:119543c9f674	154	* @}
mbed_official	489:119543c9f674	155	*/
mbed_official	489:119543c9f674	156
mbed_official	489:119543c9f674	157	#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) \|\| ((__HSI__) == RCC_HSI_ON))
mbed_official	489:119543c9f674	158
mbed_official	489:119543c9f674	159	#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
mbed_official	489:119543c9f674	160
mbed_official	489:119543c9f674	161	#define IS_RCC_CLOCKTYPE(__CLK__) ((1 <= (__CLK__)) && ((__CLK__) <= 15))
mbed_official	489:119543c9f674	162
mbed_official	489:119543c9f674	163	#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) \|\| ((__HSE__) == RCC_HSE_ON) \|\| \
mbed_official	489:119543c9f674	164	((__HSE__) == RCC_HSE_BYPASS))
mbed_official	489:119543c9f674	165
mbed_official	489:119543c9f674	166	#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) \|\| ((__LSE__) == RCC_LSE_ON) \|\| \
mbed_official	489:119543c9f674	167	((__LSE__) == RCC_LSE_BYPASS))
mbed_official	489:119543c9f674	168
mbed_official	489:119543c9f674	169	#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) \|\| \
mbed_official	489:119543c9f674	170	((__SOURCE__) == RCC_PLLSOURCE_HSE))
mbed_official	489:119543c9f674	171
mbed_official	489:119543c9f674	172	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) \|\| \
mbed_official	489:119543c9f674	173	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
mbed_official	489:119543c9f674	174	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
mbed_official	489:119543c9f674	175	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
mbed_official	489:119543c9f674	176	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
mbed_official	489:119543c9f674	177
mbed_official	489:119543c9f674	178	#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) \|\| ((__LSI__) == RCC_LSI_ON))
mbed_official	489:119543c9f674	179
mbed_official	489:119543c9f674	180	#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) \|\| ((__PLL__) == RCC_PLL_OFF) \|\| \
mbed_official	489:119543c9f674	181	((__PLL__) == RCC_PLL_ON))
mbed_official	489:119543c9f674	182
mbed_official	489:119543c9f674	183	#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) \|\| \
mbed_official	489:119543c9f674	184	((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) \|\| \
mbed_official	489:119543c9f674	185	((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
mbed_official	489:119543c9f674	186
mbed_official	489:119543c9f674	187	#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|\| \
mbed_official	489:119543c9f674	188	((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \
mbed_official	489:119543c9f674	189	((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \
mbed_official	489:119543c9f674	190	((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \
mbed_official	489:119543c9f674	191	((__HCLK__) == RCC_SYSCLK_DIV512))
mbed_official	489:119543c9f674	192
mbed_official	489:119543c9f674	193	#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) \|\| ((__PCLK__) == RCC_HCLK_DIV2) \|\| \
mbed_official	489:119543c9f674	194	((__PCLK__) == RCC_HCLK_DIV4) \|\| ((__PCLK__) == RCC_HCLK_DIV8) \|\| \
mbed_official	489:119543c9f674	195	((__PCLK__) == RCC_HCLK_DIV16))
mbed_official	489:119543c9f674	196
mbed_official	489:119543c9f674	197	#define IS_RCC_MCO(__MCO__) (((__MCO__) == RCC_MCO))
mbed_official	489:119543c9f674	198
mbed_official	489:119543c9f674	199	#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1))
mbed_official	489:119543c9f674	200
mbed_official	489:119543c9f674	201	/**
mbed_official	489:119543c9f674	202	* @}
mbed_official	489:119543c9f674	203	*/
mbed_official	489:119543c9f674	204
mbed_official	489:119543c9f674	205	/* Exported types ------------------------------------------------------------*/
mbed_official	489:119543c9f674	206
mbed_official	489:119543c9f674	207	/** @defgroup RCC_Exported_Types RCC Exported Types
mbed_official	489:119543c9f674	208	* @{
mbed_official	489:119543c9f674	209	*/
mbed_official	489:119543c9f674	210
mbed_official	489:119543c9f674	211	/**
mbed_official	489:119543c9f674	212	* @brief RCC PLL configuration structure definition
mbed_official	489:119543c9f674	213	*/
mbed_official	489:119543c9f674	214	typedef struct
mbed_official	489:119543c9f674	215	{
mbed_official	489:119543c9f674	216	uint32_t PLLState; /*!< The new state of the PLL.
mbed_official	489:119543c9f674	217	This parameter can be a value of @ref __HAL_RCC_PLL_CONFIG */
mbed_official	489:119543c9f674	218
mbed_official	489:119543c9f674	219	uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
mbed_official	489:119543c9f674	220	This parameter must be a value of @ref RCC_PLL_Clock_Source */
mbed_official	489:119543c9f674	221
mbed_official	489:119543c9f674	222	uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
mbed_official	489:119543c9f674	223	This parameter must be a value of @ref RCCEx_PLL_Multiplication_Factor */
mbed_official	489:119543c9f674	224	} RCC_PLLInitTypeDef;
mbed_official	489:119543c9f674	225
mbed_official	489:119543c9f674	226	/**
mbed_official	489:119543c9f674	227	* @brief RCC System, AHB and APB busses clock configuration structure definition
mbed_official	489:119543c9f674	228	*/
mbed_official	489:119543c9f674	229	typedef struct
mbed_official	489:119543c9f674	230	{
mbed_official	489:119543c9f674	231	uint32_t ClockType; /*!< The clock to be configured.
mbed_official	489:119543c9f674	232	This parameter can be a value of @ref RCC_System_Clock_Type */
mbed_official	489:119543c9f674	233
mbed_official	489:119543c9f674	234	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
mbed_official	489:119543c9f674	235	This parameter can be a value of @ref RCC_System_Clock_Source */
mbed_official	489:119543c9f674	236
mbed_official	489:119543c9f674	237	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
mbed_official	489:119543c9f674	238	This parameter can be a value of @ref RCC_AHB_Clock_Source */
mbed_official	489:119543c9f674	239
mbed_official	489:119543c9f674	240	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
mbed_official	489:119543c9f674	241	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
mbed_official	489:119543c9f674	242
mbed_official	489:119543c9f674	243	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
mbed_official	489:119543c9f674	244	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
mbed_official	489:119543c9f674	245
mbed_official	489:119543c9f674	246	} RCC_ClkInitTypeDef;
mbed_official	489:119543c9f674	247
mbed_official	489:119543c9f674	248	/**
mbed_official	489:119543c9f674	249	* @}
mbed_official	489:119543c9f674	250	*/
mbed_official	489:119543c9f674	251
mbed_official	489:119543c9f674	252	/**
mbed_official	489:119543c9f674	253	* @}
mbed_official	489:119543c9f674	254	*/
mbed_official	489:119543c9f674	255
mbed_official	489:119543c9f674	256	/* Exported constants --------------------------------------------------------*/
mbed_official	489:119543c9f674	257	/** @defgroup RCC_Exported_Constants RCC Exported Constants
mbed_official	489:119543c9f674	258	* @{
mbed_official	489:119543c9f674	259	*/
mbed_official	489:119543c9f674	260
mbed_official	489:119543c9f674	261	/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
mbed_official	489:119543c9f674	262	* @{
mbed_official	489:119543c9f674	263	*/
mbed_official	489:119543c9f674	264
mbed_official	489:119543c9f674	265	#define RCC_PLLSOURCE_HSI_DIV2 ((uint32_t)0x00000000) /!< HSI clock divided by 2 selected as PLL entry clock source /
mbed_official	489:119543c9f674	266	#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /!< HSE clock selected as PLL entry clock source /
mbed_official	489:119543c9f674	267
mbed_official	489:119543c9f674	268	/**
mbed_official	489:119543c9f674	269	* @}
mbed_official	489:119543c9f674	270	*/
mbed_official	489:119543c9f674	271
mbed_official	489:119543c9f674	272	/** @defgroup RCC_Oscillator_Type Oscillator Type
mbed_official	489:119543c9f674	273	* @{
mbed_official	489:119543c9f674	274	*/
mbed_official	489:119543c9f674	275	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
mbed_official	489:119543c9f674	276	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
mbed_official	489:119543c9f674	277	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
mbed_official	489:119543c9f674	278	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
mbed_official	489:119543c9f674	279	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
mbed_official	489:119543c9f674	280
mbed_official	489:119543c9f674	281	/**
mbed_official	489:119543c9f674	282	* @}
mbed_official	489:119543c9f674	283	*/
mbed_official	489:119543c9f674	284
mbed_official	489:119543c9f674	285	/** @defgroup __HAL_RCC_HSE_CONFIG HSE Config
mbed_official	489:119543c9f674	286	* @{
mbed_official	489:119543c9f674	287	*/
mbed_official	489:119543c9f674	288	#define RCC_HSE_OFF ((uint32_t)0x00000000) /!< HSE clock deactivation /
mbed_official	489:119543c9f674	289	#define RCC_HSE_ON ((uint32_t)0x00000001) /!< HSE clock activation /
mbed_official	489:119543c9f674	290	#define RCC_HSE_BYPASS ((uint32_t)0x00000005) /!< External clock source for HSE clock /
mbed_official	489:119543c9f674	291
mbed_official	489:119543c9f674	292	/**
mbed_official	489:119543c9f674	293	* @}
mbed_official	489:119543c9f674	294	*/
mbed_official	489:119543c9f674	295
mbed_official	489:119543c9f674	296	/** @defgroup __HAL_RCC_LSE_CONFIG LSE Config
mbed_official	489:119543c9f674	297	* @{
mbed_official	489:119543c9f674	298	*/
mbed_official	489:119543c9f674	299	#define RCC_LSE_OFF ((uint32_t)0x00000000) /!< LSE clock deactivation /
mbed_official	489:119543c9f674	300	#define RCC_LSE_ON ((uint32_t)0x00000001) /!< LSE clock activation /
mbed_official	489:119543c9f674	301	#define RCC_LSE_BYPASS ((uint32_t)0x00000005) /!< External clock source for LSE clock /
mbed_official	489:119543c9f674	302
mbed_official	489:119543c9f674	303	/**
mbed_official	489:119543c9f674	304	* @}
mbed_official	489:119543c9f674	305	*/
mbed_official	489:119543c9f674	306
mbed_official	489:119543c9f674	307	/** @defgroup RCC_HSI_Config HSI Config
mbed_official	489:119543c9f674	308	* @{
mbed_official	489:119543c9f674	309	*/
mbed_official	489:119543c9f674	310	#define RCC_HSI_OFF ((uint32_t)0x00000000) /!< HSI clock deactivation /
mbed_official	489:119543c9f674	311	#define RCC_HSI_ON RCC_CR_HSION /!< HSI clock activation /
mbed_official	489:119543c9f674	312
mbed_official	489:119543c9f674	313	#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
mbed_official	489:119543c9f674	314
mbed_official	489:119543c9f674	315	/**
mbed_official	489:119543c9f674	316	* @}
mbed_official	489:119543c9f674	317	*/
mbed_official	489:119543c9f674	318
mbed_official	489:119543c9f674	319	/** @defgroup RCC_LSI_Config LSI Config
mbed_official	489:119543c9f674	320	* @{
mbed_official	489:119543c9f674	321	*/
mbed_official	489:119543c9f674	322	#define RCC_LSI_OFF ((uint32_t)0x00000000) /!< LSI clock deactivation /
mbed_official	489:119543c9f674	323	#define RCC_LSI_ON RCC_CSR_LSION /!< LSI clock activation /
mbed_official	489:119543c9f674	324
mbed_official	489:119543c9f674	325	/**
mbed_official	489:119543c9f674	326	* @}
mbed_official	489:119543c9f674	327	*/
mbed_official	489:119543c9f674	328
mbed_official	489:119543c9f674	329	/** @defgroup __HAL_RCC_PLL_CONFIG PLL Config
mbed_official	489:119543c9f674	330	* @{
mbed_official	489:119543c9f674	331	*/
mbed_official	489:119543c9f674	332	#define RCC_PLL_NONE ((uint32_t)0x00000000) /!< PLL is not configured /
mbed_official	489:119543c9f674	333	#define RCC_PLL_OFF ((uint32_t)0x00000001) /!< PLL deactivation /
mbed_official	489:119543c9f674	334	#define RCC_PLL_ON ((uint32_t)0x00000002) /!< PLL activation /
mbed_official	489:119543c9f674	335
mbed_official	489:119543c9f674	336	/**
mbed_official	489:119543c9f674	337	* @}
mbed_official	489:119543c9f674	338	*/
mbed_official	489:119543c9f674	339
mbed_official	489:119543c9f674	340	/** @defgroup RCC_System_Clock_Type System Clock Type
mbed_official	489:119543c9f674	341	* @{
mbed_official	489:119543c9f674	342	*/
mbed_official	489:119543c9f674	343	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) /!< SYSCLK to configure /
mbed_official	489:119543c9f674	344	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) /!< HCLK to configure /
mbed_official	489:119543c9f674	345	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) /!< PCLK1 to configure /
mbed_official	489:119543c9f674	346	#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) /!< PCLK2 to configure /
mbed_official	489:119543c9f674	347
mbed_official	489:119543c9f674	348	/**
mbed_official	489:119543c9f674	349	* @}
mbed_official	489:119543c9f674	350	*/
mbed_official	489:119543c9f674	351
mbed_official	489:119543c9f674	352	/** @defgroup RCC_System_Clock_Source System Clock Source
mbed_official	489:119543c9f674	353	* @{
mbed_official	489:119543c9f674	354	*/
mbed_official	489:119543c9f674	355	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selected as system clock /
mbed_official	489:119543c9f674	356	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selected as system clock /
mbed_official	489:119543c9f674	357	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /!< PLL selected as system clock /
mbed_official	489:119543c9f674	358
mbed_official	489:119543c9f674	359	/**
mbed_official	489:119543c9f674	360	* @}
mbed_official	489:119543c9f674	361	*/
mbed_official	489:119543c9f674	362
mbed_official	489:119543c9f674	363	/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
mbed_official	489:119543c9f674	364	* @{
mbed_official	489:119543c9f674	365	*/
mbed_official	489:119543c9f674	366	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
mbed_official	489:119543c9f674	367	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
mbed_official	489:119543c9f674	368	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
mbed_official	489:119543c9f674	369
mbed_official	489:119543c9f674	370	/**
mbed_official	489:119543c9f674	371	* @}
mbed_official	489:119543c9f674	372	*/
mbed_official	489:119543c9f674	373
mbed_official	489:119543c9f674	374	/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
mbed_official	489:119543c9f674	375	* @{
mbed_official	489:119543c9f674	376	*/
mbed_official	489:119543c9f674	377	#define RCC_SYSCLK_DIV1 (RCC_CFGR_HPRE_DIV1) /!< SYSCLK not divided /
mbed_official	489:119543c9f674	378	#define RCC_SYSCLK_DIV2 (RCC_CFGR_HPRE_DIV2) /!< SYSCLK divided by 2 /
mbed_official	489:119543c9f674	379	#define RCC_SYSCLK_DIV4 (RCC_CFGR_HPRE_DIV4) /!< SYSCLK divided by 4 /
mbed_official	489:119543c9f674	380	#define RCC_SYSCLK_DIV8 (RCC_CFGR_HPRE_DIV8) /!< SYSCLK divided by 8 /
mbed_official	489:119543c9f674	381	#define RCC_SYSCLK_DIV16 (RCC_CFGR_HPRE_DIV16) /!< SYSCLK divided by 16 /
mbed_official	489:119543c9f674	382	#define RCC_SYSCLK_DIV64 (RCC_CFGR_HPRE_DIV64) /!< SYSCLK divided by 64 /
mbed_official	489:119543c9f674	383	#define RCC_SYSCLK_DIV128 (RCC_CFGR_HPRE_DIV128) /!< SYSCLK divided by 128 /
mbed_official	489:119543c9f674	384	#define RCC_SYSCLK_DIV256 (RCC_CFGR_HPRE_DIV256) /!< SYSCLK divided by 256 /
mbed_official	489:119543c9f674	385	#define RCC_SYSCLK_DIV512 (RCC_CFGR_HPRE_DIV512) /!< SYSCLK divided by 512 /
mbed_official	489:119543c9f674	386
mbed_official	489:119543c9f674	387	/**
mbed_official	489:119543c9f674	388	* @}
mbed_official	489:119543c9f674	389	*/
mbed_official	489:119543c9f674	390
mbed_official	489:119543c9f674	391	/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
mbed_official	489:119543c9f674	392	* @{
mbed_official	489:119543c9f674	393	*/
mbed_official	489:119543c9f674	394	#define RCC_HCLK_DIV1 (RCC_CFGR_PPRE1_DIV1) /!< HCLK not divided /
mbed_official	489:119543c9f674	395	#define RCC_HCLK_DIV2 (RCC_CFGR_PPRE1_DIV2) /!< HCLK divided by 2 /
mbed_official	489:119543c9f674	396	#define RCC_HCLK_DIV4 (RCC_CFGR_PPRE1_DIV4) /!< HCLK divided by 4 /
mbed_official	489:119543c9f674	397	#define RCC_HCLK_DIV8 (RCC_CFGR_PPRE1_DIV8) /!< HCLK divided by 8 /
mbed_official	489:119543c9f674	398	#define RCC_HCLK_DIV16 (RCC_CFGR_PPRE1_DIV16) /!< HCLK divided by 16 /
mbed_official	489:119543c9f674	399
mbed_official	489:119543c9f674	400	/**
mbed_official	489:119543c9f674	401	* @}
mbed_official	489:119543c9f674	402	*/
mbed_official	489:119543c9f674	403
mbed_official	489:119543c9f674	404	/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
mbed_official	489:119543c9f674	405	* @{
mbed_official	489:119543c9f674	406	*/
mbed_official	489:119543c9f674	407	#define RCC_RTCCLKSOURCE_LSE (RCC_BDCR_RTCSEL_LSE) /!< LSE oscillator clock used as RTC clock /
mbed_official	489:119543c9f674	408	#define RCC_RTCCLKSOURCE_LSI (RCC_BDCR_RTCSEL_LSI) /!< LSI oscillator clock used as RTC clock /
mbed_official	489:119543c9f674	409	#define RCC_RTCCLKSOURCE_HSE_DIV128 (RCC_BDCR_RTCSEL_HSE) /!< HSE oscillator clock divided by 128 used as RTC clock /
mbed_official	489:119543c9f674	410	/**
mbed_official	489:119543c9f674	411	* @}
mbed_official	489:119543c9f674	412	*/
mbed_official	489:119543c9f674	413
mbed_official	489:119543c9f674	414	/** @defgroup RCC_MCO_Index MCO Index
mbed_official	489:119543c9f674	415	* @{
mbed_official	489:119543c9f674	416	*/
mbed_official	489:119543c9f674	417	#define RCC_MCO1 ((uint32_t)0x00000000)
mbed_official	489:119543c9f674	418	#define RCC_MCO RCC_MCO1 /!< MCO1 to be compliant with other families with 2 MCOs/
mbed_official	489:119543c9f674	419
mbed_official	489:119543c9f674	420	/**
mbed_official	489:119543c9f674	421	* @}
mbed_official	489:119543c9f674	422	*/
mbed_official	489:119543c9f674	423
mbed_official	489:119543c9f674	424	/** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler
mbed_official	489:119543c9f674	425	* @{
mbed_official	489:119543c9f674	426	*/
mbed_official	489:119543c9f674	427	#define RCC_MCODIV_1 ((uint32_t)0x00000000)
mbed_official	489:119543c9f674	428
mbed_official	489:119543c9f674	429	/**
mbed_official	489:119543c9f674	430	* @}
mbed_official	489:119543c9f674	431	*/
mbed_official	489:119543c9f674	432
mbed_official	489:119543c9f674	433	/** @defgroup RCC_Interrupt Interrupts
mbed_official	489:119543c9f674	434	* @{
mbed_official	489:119543c9f674	435	*/
mbed_official	489:119543c9f674	436	#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /!< LSI Ready Interrupt flag /
mbed_official	489:119543c9f674	437	#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /!< LSE Ready Interrupt flag /
mbed_official	489:119543c9f674	438	#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /!< HSI Ready Interrupt flag /
mbed_official	489:119543c9f674	439	#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /!< HSE Ready Interrupt flag /
mbed_official	489:119543c9f674	440	#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /!< PLL Ready Interrupt flag /
mbed_official	489:119543c9f674	441	#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /!< Clock Security System Interrupt flag /
mbed_official	489:119543c9f674	442	/**
mbed_official	489:119543c9f674	443	* @}
mbed_official	489:119543c9f674	444	*/
mbed_official	489:119543c9f674	445
mbed_official	489:119543c9f674	446	/** @defgroup RCC_Flag Flags
mbed_official	489:119543c9f674	447	* Elements values convention: 0XXYYYYYb
mbed_official	489:119543c9f674	448	* - YYYYY : Flag position in the register
mbed_official	489:119543c9f674	449	* - XX : Register index
mbed_official	489:119543c9f674	450	* - 01: CR register
mbed_official	489:119543c9f674	451	* - 10: BDCR register
mbed_official	489:119543c9f674	452	* - 11: CSR register
mbed_official	489:119543c9f674	453	* @{
mbed_official	489:119543c9f674	454	*/
mbed_official	489:119543c9f674	455	/* Flags in the CR register */
mbed_official	489:119543c9f674	456	#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_HSIRDY))) /!< Internal High Speed clock ready flag /
mbed_official	489:119543c9f674	457	#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_HSERDY))) /!< External High Speed clock ready flag /
mbed_official	489:119543c9f674	458	#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_PLLRDY))) /!< PLL clock ready flag /
mbed_official	489:119543c9f674	459
mbed_official	489:119543c9f674	460	/* Flags in the BDCR register */
mbed_official	489:119543c9f674	461	#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5) \| POSITION_VAL(RCC_BDCR_LSERDY))) /!< External Low Speed oscillator Ready /
mbed_official	489:119543c9f674	462
mbed_official	489:119543c9f674	463	/* Flags in the CSR register */
mbed_official	489:119543c9f674	464	#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_LSIRDY))) /!< Internal Low Speed oscillator Ready /
mbed_official	489:119543c9f674	465	#define RCC_FLAG_RMV ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_RMVF))) /!< Remove reset flag /
mbed_official	489:119543c9f674	466	#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_PINRSTF))) /!< PIN reset flag /
mbed_official	489:119543c9f674	467	#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_PORRSTF))) /!< POR/PDR reset flag /
mbed_official	489:119543c9f674	468	#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_SFTRSTF))) /!< Software Reset flag /
mbed_official	489:119543c9f674	469	#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_IWDGRSTF))) /!< Independent Watchdog reset flag /
mbed_official	489:119543c9f674	470	#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_WWDGRSTF))) /!< Window watchdog reset flag /
mbed_official	489:119543c9f674	471	#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_LPWRRSTF))) /!< Low-Power reset flag /
mbed_official	489:119543c9f674	472
mbed_official	489:119543c9f674	473	/**
mbed_official	489:119543c9f674	474	* @}
mbed_official	489:119543c9f674	475	*/
mbed_official	489:119543c9f674	476
mbed_official	489:119543c9f674	477	/**
mbed_official	489:119543c9f674	478	* @}
mbed_official	489:119543c9f674	479	*/
mbed_official	489:119543c9f674	480
mbed_official	489:119543c9f674	481	/* Exported macro ------------------------------------------------------------*/
mbed_official	489:119543c9f674	482
mbed_official	489:119543c9f674	483	/** @defgroup RCC_Exported_Macros RCC Exported Macros
mbed_official	489:119543c9f674	484	* @{
mbed_official	489:119543c9f674	485	*/
mbed_official	489:119543c9f674	486
mbed_official	489:119543c9f674	487	/** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
mbed_official	489:119543c9f674	488	* @brief Enable or disable the AHB1 peripheral clock.
mbed_official	489:119543c9f674	489	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	489:119543c9f674	490	* is disabled and the application software has to enable this clock before
mbed_official	489:119543c9f674	491	* using it.
mbed_official	489:119543c9f674	492	* @{
mbed_official	489:119543c9f674	493	*/
mbed_official	489:119543c9f674	494	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	495	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	496	SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
mbed_official	489:119543c9f674	497	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	498	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
mbed_official	489:119543c9f674	499	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	500	} while(0)
mbed_official	489:119543c9f674	501
mbed_official	489:119543c9f674	502	#define __HAL_RCC_SRAM_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	503	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	504	SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
mbed_official	489:119543c9f674	505	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	506	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
mbed_official	489:119543c9f674	507	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	508	} while(0)
mbed_official	489:119543c9f674	509
mbed_official	489:119543c9f674	510	#define __HAL_RCC_FLITF_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	511	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	512	SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
mbed_official	489:119543c9f674	513	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	514	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
mbed_official	489:119543c9f674	515	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	516	} while(0)
mbed_official	489:119543c9f674	517
mbed_official	489:119543c9f674	518	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	519	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	520	SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
mbed_official	489:119543c9f674	521	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	522	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
mbed_official	489:119543c9f674	523	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	524	} while(0)
mbed_official	489:119543c9f674	525
mbed_official	489:119543c9f674	526	#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
mbed_official	489:119543c9f674	527	#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
mbed_official	489:119543c9f674	528	#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
mbed_official	489:119543c9f674	529	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
mbed_official	489:119543c9f674	530
mbed_official	489:119543c9f674	531	/**
mbed_official	489:119543c9f674	532	* @}
mbed_official	489:119543c9f674	533	*/
mbed_official	489:119543c9f674	534
mbed_official	489:119543c9f674	535	/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
mbed_official	489:119543c9f674	536	* @brief Get the enable or disable status of the AHB peripheral clock.
mbed_official	489:119543c9f674	537	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	489:119543c9f674	538	* is disabled and the application software has to enable this clock before
mbed_official	489:119543c9f674	539	* using it.
mbed_official	489:119543c9f674	540	* @{
mbed_official	489:119543c9f674	541	*/
mbed_official	489:119543c9f674	542
mbed_official	489:119543c9f674	543	#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
mbed_official	489:119543c9f674	544	#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
mbed_official	489:119543c9f674	545	#define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
mbed_official	489:119543c9f674	546	#define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
mbed_official	489:119543c9f674	547	#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
mbed_official	489:119543c9f674	548	#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
mbed_official	489:119543c9f674	549	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
mbed_official	489:119543c9f674	550	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
mbed_official	489:119543c9f674	551
mbed_official	489:119543c9f674	552	/**
mbed_official	489:119543c9f674	553	* @}
mbed_official	489:119543c9f674	554	*/
mbed_official	489:119543c9f674	555
mbed_official	489:119543c9f674	556	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
mbed_official	489:119543c9f674	557	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
mbed_official	489:119543c9f674	558	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	489:119543c9f674	559	* is disabled and the application software has to enable this clock before
mbed_official	489:119543c9f674	560	* using it.
mbed_official	489:119543c9f674	561	* @{
mbed_official	489:119543c9f674	562	*/
mbed_official	489:119543c9f674	563	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	564	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	565	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
mbed_official	489:119543c9f674	566	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	567	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
mbed_official	489:119543c9f674	568	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	569	} while(0)
mbed_official	489:119543c9f674	570
mbed_official	489:119543c9f674	571	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	572	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	573	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
mbed_official	489:119543c9f674	574	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	575	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
mbed_official	489:119543c9f674	576	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	577	} while(0)
mbed_official	489:119543c9f674	578
mbed_official	489:119543c9f674	579	#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	580	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	581	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
mbed_official	489:119543c9f674	582	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	583	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
mbed_official	489:119543c9f674	584	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	585	} while(0)
mbed_official	489:119543c9f674	586
mbed_official	489:119543c9f674	587	#define __HAL_RCC_USART2_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	588	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	589	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
mbed_official	489:119543c9f674	590	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	591	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
mbed_official	489:119543c9f674	592	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	593	} while(0)
mbed_official	489:119543c9f674	594
mbed_official	489:119543c9f674	595	#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	596	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	597	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
mbed_official	489:119543c9f674	598	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	599	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
mbed_official	489:119543c9f674	600	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	601	} while(0)
mbed_official	489:119543c9f674	602
mbed_official	489:119543c9f674	603	#define __HAL_RCC_BKP_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	604	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	605	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
mbed_official	489:119543c9f674	606	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	607	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
mbed_official	489:119543c9f674	608	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	609	} while(0)
mbed_official	489:119543c9f674	610
mbed_official	489:119543c9f674	611	#define __HAL_RCC_PWR_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	612	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	613	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
mbed_official	489:119543c9f674	614	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	615	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
mbed_official	489:119543c9f674	616	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	617	} while(0)
mbed_official	489:119543c9f674	618
mbed_official	489:119543c9f674	619	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
mbed_official	489:119543c9f674	620	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
mbed_official	489:119543c9f674	621	#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
mbed_official	489:119543c9f674	622	#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
mbed_official	489:119543c9f674	623	#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
mbed_official	489:119543c9f674	624
mbed_official	489:119543c9f674	625	#define __HAL_RCC_BKP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN))
mbed_official	489:119543c9f674	626	#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
mbed_official	489:119543c9f674	627
mbed_official	489:119543c9f674	628	/**
mbed_official	489:119543c9f674	629	* @}
mbed_official	489:119543c9f674	630	*/
mbed_official	489:119543c9f674	631
mbed_official	489:119543c9f674	632	/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
mbed_official	489:119543c9f674	633	* @brief Get the enable or disable status of the APB1 peripheral clock.
mbed_official	489:119543c9f674	634	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	489:119543c9f674	635	* is disabled and the application software has to enable this clock before
mbed_official	489:119543c9f674	636	* using it.
mbed_official	489:119543c9f674	637	* @{
mbed_official	489:119543c9f674	638	*/
mbed_official	489:119543c9f674	639
mbed_official	489:119543c9f674	640	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
mbed_official	489:119543c9f674	641	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
mbed_official	489:119543c9f674	642	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
mbed_official	489:119543c9f674	643	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
mbed_official	489:119543c9f674	644	#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
mbed_official	489:119543c9f674	645	#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
mbed_official	489:119543c9f674	646	#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
mbed_official	489:119543c9f674	647	#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
mbed_official	489:119543c9f674	648	#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
mbed_official	489:119543c9f674	649	#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
mbed_official	489:119543c9f674	650	#define __HAL_RCC_BKP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET)
mbed_official	489:119543c9f674	651	#define __HAL_RCC_BKP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET)
mbed_official	489:119543c9f674	652	#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
mbed_official	489:119543c9f674	653	#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
mbed_official	489:119543c9f674	654
mbed_official	489:119543c9f674	655	/**
mbed_official	489:119543c9f674	656	* @}
mbed_official	489:119543c9f674	657	*/
mbed_official	489:119543c9f674	658
mbed_official	489:119543c9f674	659	/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
mbed_official	489:119543c9f674	660	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
mbed_official	489:119543c9f674	661	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	489:119543c9f674	662	* is disabled and the application software has to enable this clock before
mbed_official	489:119543c9f674	663	* using it.
mbed_official	489:119543c9f674	664	* @{
mbed_official	489:119543c9f674	665	*/
mbed_official	489:119543c9f674	666	#define __HAL_RCC_AFIO_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	667	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	668	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
mbed_official	489:119543c9f674	669	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	670	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
mbed_official	489:119543c9f674	671	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	672	} while(0)
mbed_official	489:119543c9f674	673
mbed_official	489:119543c9f674	674	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	675	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	676	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
mbed_official	489:119543c9f674	677	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	678	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
mbed_official	489:119543c9f674	679	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	680	} while(0)
mbed_official	489:119543c9f674	681
mbed_official	489:119543c9f674	682	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	683	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	684	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
mbed_official	489:119543c9f674	685	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	686	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
mbed_official	489:119543c9f674	687	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	688	} while(0)
mbed_official	489:119543c9f674	689
mbed_official	489:119543c9f674	690	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	691	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	692	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
mbed_official	489:119543c9f674	693	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	694	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
mbed_official	489:119543c9f674	695	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	696	} while(0)
mbed_official	489:119543c9f674	697
mbed_official	489:119543c9f674	698	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	699	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	700	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
mbed_official	489:119543c9f674	701	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	702	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
mbed_official	489:119543c9f674	703	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	704	} while(0)
mbed_official	489:119543c9f674	705
mbed_official	489:119543c9f674	706	#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	707	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	708	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
mbed_official	489:119543c9f674	709	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	710	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
mbed_official	489:119543c9f674	711	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	712	} while(0)
mbed_official	489:119543c9f674	713
mbed_official	489:119543c9f674	714	#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	715	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	716	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
mbed_official	489:119543c9f674	717	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	718	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
mbed_official	489:119543c9f674	719	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	720	} while(0)
mbed_official	489:119543c9f674	721
mbed_official	489:119543c9f674	722	#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	723	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	724	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
mbed_official	489:119543c9f674	725	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	726	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
mbed_official	489:119543c9f674	727	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	728	} while(0)
mbed_official	489:119543c9f674	729
mbed_official	489:119543c9f674	730	#define __HAL_RCC_USART1_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	731	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	732	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
mbed_official	489:119543c9f674	733	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	734	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
mbed_official	489:119543c9f674	735	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	736	} while(0)
mbed_official	489:119543c9f674	737
mbed_official	489:119543c9f674	738	#define __HAL_RCC_AFIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN))
mbed_official	489:119543c9f674	739	#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN))
mbed_official	489:119543c9f674	740	#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN))
mbed_official	489:119543c9f674	741	#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN))
mbed_official	489:119543c9f674	742	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN))
mbed_official	489:119543c9f674	743	#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
mbed_official	489:119543c9f674	744
mbed_official	489:119543c9f674	745	#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
mbed_official	489:119543c9f674	746	#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
mbed_official	489:119543c9f674	747	#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
mbed_official	489:119543c9f674	748
mbed_official	489:119543c9f674	749	/**
mbed_official	489:119543c9f674	750	* @}
mbed_official	489:119543c9f674	751	*/
mbed_official	489:119543c9f674	752
mbed_official	489:119543c9f674	753	/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
mbed_official	489:119543c9f674	754	* @brief Get the enable or disable status of the APB2 peripheral clock.
mbed_official	489:119543c9f674	755	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	489:119543c9f674	756	* is disabled and the application software has to enable this clock before
mbed_official	489:119543c9f674	757	* using it.
mbed_official	489:119543c9f674	758	* @{
mbed_official	489:119543c9f674	759	*/
mbed_official	489:119543c9f674	760
mbed_official	489:119543c9f674	761	#define __HAL_RCC_AFIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET)
mbed_official	489:119543c9f674	762	#define __HAL_RCC_AFIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET)
mbed_official	489:119543c9f674	763	#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET)
mbed_official	489:119543c9f674	764	#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET)
mbed_official	489:119543c9f674	765	#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET)
mbed_official	489:119543c9f674	766	#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET)
mbed_official	489:119543c9f674	767	#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET)
mbed_official	489:119543c9f674	768	#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET)
mbed_official	489:119543c9f674	769	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET)
mbed_official	489:119543c9f674	770	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET)
mbed_official	489:119543c9f674	771	#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
mbed_official	489:119543c9f674	772	#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
mbed_official	489:119543c9f674	773	#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
mbed_official	489:119543c9f674	774	#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
mbed_official	489:119543c9f674	775	#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
mbed_official	489:119543c9f674	776	#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
mbed_official	489:119543c9f674	777	#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
mbed_official	489:119543c9f674	778	#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
mbed_official	489:119543c9f674	779
mbed_official	489:119543c9f674	780	/**
mbed_official	489:119543c9f674	781	* @}
mbed_official	489:119543c9f674	782	*/
mbed_official	489:119543c9f674	783
mbed_official	489:119543c9f674	784	/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
mbed_official	489:119543c9f674	785	* @brief Force or release APB1 peripheral reset.
mbed_official	489:119543c9f674	786	* @{
mbed_official	489:119543c9f674	787	*/
mbed_official	489:119543c9f674	788	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
mbed_official	489:119543c9f674	789	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
mbed_official	489:119543c9f674	790	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
mbed_official	489:119543c9f674	791	#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
mbed_official	489:119543c9f674	792	#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
mbed_official	489:119543c9f674	793	#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
mbed_official	489:119543c9f674	794
mbed_official	489:119543c9f674	795	#define __HAL_RCC_BKP_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_BKPRST))
mbed_official	489:119543c9f674	796	#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
mbed_official	489:119543c9f674	797
mbed_official	489:119543c9f674	798	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
mbed_official	489:119543c9f674	799	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
mbed_official	489:119543c9f674	800	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
mbed_official	489:119543c9f674	801	#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
mbed_official	489:119543c9f674	802	#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
mbed_official	489:119543c9f674	803	#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
mbed_official	489:119543c9f674	804
mbed_official	489:119543c9f674	805	#define __HAL_RCC_BKP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_BKPRST))
mbed_official	489:119543c9f674	806	#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
mbed_official	489:119543c9f674	807
mbed_official	489:119543c9f674	808	/**
mbed_official	489:119543c9f674	809	* @}
mbed_official	489:119543c9f674	810	*/
mbed_official	489:119543c9f674	811
mbed_official	489:119543c9f674	812	/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
mbed_official	489:119543c9f674	813	* @brief Force or release APB2 peripheral reset.
mbed_official	489:119543c9f674	814	* @{
mbed_official	489:119543c9f674	815	*/
mbed_official	489:119543c9f674	816	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
mbed_official	489:119543c9f674	817	#define __HAL_RCC_AFIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_AFIORST))
mbed_official	489:119543c9f674	818	#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPARST))
mbed_official	489:119543c9f674	819	#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPBRST))
mbed_official	489:119543c9f674	820	#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPCRST))
mbed_official	489:119543c9f674	821	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPDRST))
mbed_official	489:119543c9f674	822	#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADC1RST))
mbed_official	489:119543c9f674	823
mbed_official	489:119543c9f674	824	#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM1RST))
mbed_official	489:119543c9f674	825	#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
mbed_official	489:119543c9f674	826	#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
mbed_official	489:119543c9f674	827
mbed_official	489:119543c9f674	828	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
mbed_official	489:119543c9f674	829	#define __HAL_RCC_AFIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST))
mbed_official	489:119543c9f674	830	#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST))
mbed_official	489:119543c9f674	831	#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST))
mbed_official	489:119543c9f674	832	#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPCRST))
mbed_official	489:119543c9f674	833	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPDRST))
mbed_official	489:119543c9f674	834	#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
mbed_official	489:119543c9f674	835
mbed_official	489:119543c9f674	836	#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
mbed_official	489:119543c9f674	837	#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
mbed_official	489:119543c9f674	838	#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
mbed_official	489:119543c9f674	839
mbed_official	489:119543c9f674	840	/**
mbed_official	489:119543c9f674	841	* @}
mbed_official	489:119543c9f674	842	*/
mbed_official	489:119543c9f674	843
mbed_official	489:119543c9f674	844	/** @defgroup RCC_HSI_Configuration HSI Configuration
mbed_official	489:119543c9f674	845	* @{
mbed_official	489:119543c9f674	846	*/
mbed_official	489:119543c9f674	847
mbed_official	489:119543c9f674	848	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
mbed_official	489:119543c9f674	849	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	489:119543c9f674	850	* @note HSI can not be stopped if it is used as system clock source. In this case,
mbed_official	489:119543c9f674	851	* you have to select another source of the system clock then stop the HSI.
mbed_official	489:119543c9f674	852	* @note After enabling the HSI, the application software should wait on HSIRDY
mbed_official	489:119543c9f674	853	* flag to be set indicating that HSI clock is stable and can be used as
mbed_official	489:119543c9f674	854	* system clock source.
mbed_official	489:119543c9f674	855	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
mbed_official	489:119543c9f674	856	* clock cycles.
mbed_official	489:119543c9f674	857	*/
mbed_official	489:119543c9f674	858	#define __HAL_RCC_HSI_ENABLE() ((__IO uint32_t ) RCC_CR_HSION_BB = ENABLE)
mbed_official	489:119543c9f674	859	#define __HAL_RCC_HSI_DISABLE() ((__IO uint32_t ) RCC_CR_HSION_BB = DISABLE)
mbed_official	489:119543c9f674	860
mbed_official	489:119543c9f674	861	/** @brief macro to adjust the Internal High Speed oscillator (HSI) calibration value.
mbed_official	489:119543c9f674	862	* @note The calibration is used to compensate for the variations in voltage
mbed_official	489:119543c9f674	863	* and temperature that influence the frequency of the internal HSI RC.
mbed_official	489:119543c9f674	864	* @param _HSICALIBRATIONVALUE_: specifies the calibration trimming value.
mbed_official	489:119543c9f674	865	* (default is RCC_HSICALIBRATION_DEFAULT).
mbed_official	489:119543c9f674	866	* This parameter must be a number between 0 and 0x1F.
mbed_official	489:119543c9f674	867	*/
mbed_official	489:119543c9f674	868	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
mbed_official	489:119543c9f674	869	(MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_CR_HSITRIM)))
mbed_official	489:119543c9f674	870
mbed_official	489:119543c9f674	871	/**
mbed_official	489:119543c9f674	872	* @}
mbed_official	489:119543c9f674	873	*/
mbed_official	489:119543c9f674	874
mbed_official	489:119543c9f674	875	/** @defgroup RCC_LSI_Configuration LSI Configuration
mbed_official	489:119543c9f674	876	* @{
mbed_official	489:119543c9f674	877	*/
mbed_official	489:119543c9f674	878
mbed_official	489:119543c9f674	879	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
mbed_official	489:119543c9f674	880	* @note After enabling the LSI, the application software should wait on
mbed_official	489:119543c9f674	881	* LSIRDY flag to be set indicating that LSI clock is stable and can
mbed_official	489:119543c9f674	882	* be used to clock the IWDG and/or the RTC.
mbed_official	489:119543c9f674	883	* @note LSI can not be disabled if the IWDG is running.
mbed_official	489:119543c9f674	884	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
mbed_official	489:119543c9f674	885	* clock cycles.
mbed_official	489:119543c9f674	886	*/
mbed_official	489:119543c9f674	887	#define __HAL_RCC_LSI_ENABLE() ((__IO uint32_t ) RCC_CSR_LSION_BB = ENABLE)
mbed_official	489:119543c9f674	888	#define __HAL_RCC_LSI_DISABLE() ((__IO uint32_t ) RCC_CSR_LSION_BB = DISABLE)
mbed_official	489:119543c9f674	889
mbed_official	489:119543c9f674	890	/**
mbed_official	489:119543c9f674	891	* @}
mbed_official	489:119543c9f674	892	*/
mbed_official	489:119543c9f674	893
mbed_official	489:119543c9f674	894	/** @defgroup RCC_HSE_Configuration HSE Configuration
mbed_official	489:119543c9f674	895	* @{
mbed_official	489:119543c9f674	896	*/
mbed_official	489:119543c9f674	897
mbed_official	489:119543c9f674	898	/**
mbed_official	489:119543c9f674	899	* @brief Macro to configure the External High Speed oscillator (HSE).
mbed_official	489:119543c9f674	900	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
mbed_official	489:119543c9f674	901	* software should wait on HSERDY flag to be set indicating that HSE clock
mbed_official	489:119543c9f674	902	* is stable and can be used to clock the PLL and/or system clock.
mbed_official	489:119543c9f674	903	* @note HSE state can not be changed if it is used directly or through the
mbed_official	489:119543c9f674	904	* PLL as system clock. In this case, you have to select another source
mbed_official	489:119543c9f674	905	* of the system clock then change the HSE state (ex. disable it).
mbed_official	489:119543c9f674	906	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	489:119543c9f674	907	* @note This function reset the CSSON bit, so if the Clock security system(CSS)
mbed_official	489:119543c9f674	908	* was previously enabled you have to enable it again after calling this
mbed_official	489:119543c9f674	909	* function.
mbed_official	489:119543c9f674	910	* @param __STATE__: specifies the new state of the HSE.
mbed_official	489:119543c9f674	911	* This parameter can be one of the following values:
mbed_official	489:119543c9f674	912	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
mbed_official	489:119543c9f674	913	* 6 HSE oscillator clock cycles.
mbed_official	489:119543c9f674	914	* @arg RCC_HSE_ON: turn ON the HSE oscillator
mbed_official	489:119543c9f674	915	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock
mbed_official	489:119543c9f674	916	*/
mbed_official	489:119543c9f674	917	#define __HAL_RCC_HSE_CONFIG(__STATE__) \
mbed_official	489:119543c9f674	918	do { \
mbed_official	489:119543c9f674	919	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
mbed_official	489:119543c9f674	920	if((__STATE__) == RCC_HSE_ON) \
mbed_official	489:119543c9f674	921	{ \
mbed_official	489:119543c9f674	922	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
mbed_official	489:119543c9f674	923	SET_BIT(RCC->CR, RCC_CR_HSEON); \
mbed_official	489:119543c9f674	924	} \
mbed_official	489:119543c9f674	925	else if((__STATE__) == RCC_HSE_BYPASS) \
mbed_official	489:119543c9f674	926	{ \
mbed_official	489:119543c9f674	927	((__IO uint8_t ) RCC_CR_BYTE2_ADDRESS = (__STATE__)); \
mbed_official	489:119543c9f674	928	} \
mbed_official	489:119543c9f674	929	else \
mbed_official	489:119543c9f674	930	{ \
mbed_official	489:119543c9f674	931	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
mbed_official	489:119543c9f674	932	} \
mbed_official	489:119543c9f674	933	} while(0)
mbed_official	489:119543c9f674	934
mbed_official	489:119543c9f674	935	/**
mbed_official	489:119543c9f674	936	* @}
mbed_official	489:119543c9f674	937	*/
mbed_official	489:119543c9f674	938
mbed_official	489:119543c9f674	939	/** @defgroup RCC_LSE_Configuration LSE Configuration
mbed_official	489:119543c9f674	940	* @{
mbed_official	489:119543c9f674	941	*/
mbed_official	489:119543c9f674	942
mbed_official	489:119543c9f674	943	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSE).
mbed_official	489:119543c9f674	944	*/
mbed_official	489:119543c9f674	945	#define __HAL_RCC_LSE_CONFIG(__LSE_STATE__) \
mbed_official	489:119543c9f674	946	do{ \
mbed_official	489:119543c9f674	947	if ((__LSE_STATE__) == RCC_LSE_OFF) \
mbed_official	489:119543c9f674	948	{ \
mbed_official	489:119543c9f674	949	(__IO uint32_t ) BDCR_LSEON_BB = DISABLE; \
mbed_official	489:119543c9f674	950	(__IO uint32_t ) BDCR_LSEBYP_BB = DISABLE; \
mbed_official	489:119543c9f674	951	} \
mbed_official	489:119543c9f674	952	else if ((__LSE_STATE__) == RCC_LSE_ON) \
mbed_official	489:119543c9f674	953	{ \
mbed_official	489:119543c9f674	954	(__IO uint32_t ) BDCR_LSEBYP_BB = DISABLE; \
mbed_official	489:119543c9f674	955	(__IO uint32_t ) BDCR_LSEON_BB = ENABLE; \
mbed_official	489:119543c9f674	956	} \
mbed_official	489:119543c9f674	957	else \
mbed_official	489:119543c9f674	958	{ \
mbed_official	489:119543c9f674	959	(__IO uint32_t ) BDCR_LSEON_BB = DISABLE; \
mbed_official	489:119543c9f674	960	(__IO uint32_t ) BDCR_LSEBYP_BB = ENABLE; \
mbed_official	489:119543c9f674	961	} \
mbed_official	489:119543c9f674	962	}while(0)
mbed_official	489:119543c9f674	963
mbed_official	489:119543c9f674	964
mbed_official	489:119543c9f674	965	/**
mbed_official	489:119543c9f674	966	* @}
mbed_official	489:119543c9f674	967	*/
mbed_official	489:119543c9f674	968
mbed_official	489:119543c9f674	969	/** @defgroup RCC_PLL_Configuration PLL Configuration
mbed_official	489:119543c9f674	970	* @{
mbed_official	489:119543c9f674	971	*/
mbed_official	489:119543c9f674	972
mbed_official	489:119543c9f674	973	/** @brief Macros to enable the main PLL.
mbed_official	489:119543c9f674	974	* @note After enabling the main PLL, the application software should wait on
mbed_official	489:119543c9f674	975	* PLLRDY flag to be set indicating that PLL clock is stable and can
mbed_official	489:119543c9f674	976	* be used as system clock source.
mbed_official	489:119543c9f674	977	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
mbed_official	489:119543c9f674	978	*/
mbed_official	489:119543c9f674	979	#define __HAL_RCC_PLL_ENABLE() ((__IO uint32_t ) RCC_CR_PLLON_BB = ENABLE)
mbed_official	489:119543c9f674	980
mbed_official	489:119543c9f674	981	/** @brief Macros to disable the main PLL.
mbed_official	489:119543c9f674	982	* @note The main PLL can not be disabled if it is used as system clock source
mbed_official	489:119543c9f674	983	*/
mbed_official	489:119543c9f674	984	#define __HAL_RCC_PLL_DISABLE() ((__IO uint32_t ) RCC_CR_PLLON_BB = DISABLE)
mbed_official	489:119543c9f674	985
mbed_official	489:119543c9f674	986	/** @brief macros to configure the main PLL clock source and multiplication factors.
mbed_official	489:119543c9f674	987	* @note This function must be used only when the main PLL is disabled.
mbed_official	489:119543c9f674	988	*
mbed_official	489:119543c9f674	989	* @param __RCC_PLLSOURCE__: specifies the PLL entry clock source.
mbed_official	489:119543c9f674	990	* This parameter can be one of the following values:
mbed_official	489:119543c9f674	991	* @arg RCC_PLLSOURCE_HSI_DIV2: HSI oscillator clock selected as PLL clock entry
mbed_official	489:119543c9f674	992	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
mbed_official	489:119543c9f674	993	* @param __PLLMUL__: specifies the multiplication factor for PLL VCO output clock
mbed_official	489:119543c9f674	994	* This parameter can be one of the following values:
mbed_official	489:119543c9f674	995	* @arg RCC_PLL_MUL2: PLLVCO = PLL clock entry x 2 (*)
mbed_official	489:119543c9f674	996	* @arg RCC_PLL_MUL3: PLLVCO = PLL clock entry x 3 (*)
mbed_official	489:119543c9f674	997	* @arg RCC_PLL_MUL4: PLLVCO = PLL clock entry x 4
mbed_official	489:119543c9f674	998	* @arg RCC_PLL_MUL6: PLLVCO = PLL clock entry x 6
mbed_official	489:119543c9f674	999	* @arg RCC_PLL_MUL6_5: PLLVCO = PLL clock entry x 6.5 (**)
mbed_official	489:119543c9f674	1000	* @arg RCC_PLL_MUL8: PLLVCO = PLL clock entry x 8
mbed_official	489:119543c9f674	1001	* @arg RCC_PLL_MUL9: PLLVCO = PLL clock entry x 9
mbed_official	489:119543c9f674	1002	* @arg RCC_PLL_MUL10: PLLVCO = PLL clock entry x 10 (*)
mbed_official	489:119543c9f674	1003	* @arg RCC_PLL_MUL11: PLLVCO = PLL clock entry x 11 (*)
mbed_official	489:119543c9f674	1004	* @arg RCC_PLL_MUL12: PLLVCO = PLL clock entry x 12 (*)
mbed_official	489:119543c9f674	1005	* @arg RCC_PLL_MUL13: PLLVCO = PLL clock entry x 13 (*)
mbed_official	489:119543c9f674	1006	* @arg RCC_PLL_MUL14: PLLVCO = PLL clock entry x 14 (*)
mbed_official	489:119543c9f674	1007	* @arg RCC_PLL_MUL15: PLLVCO = PLL clock entry x 15 (*)
mbed_official	489:119543c9f674	1008	* @arg RCC_PLL_MUL16: PLLVCO = PLL clock entry x 16 (*)
mbed_official	489:119543c9f674	1009	* @note (*) These values are not available in STM32F105xx & STM32F107xx devices.
mbed_official	489:119543c9f674	1010	* @note (**) This value is available in STM32F105xx & STM32F107xx devices only.
mbed_official	489:119543c9f674	1011	*
mbed_official	489:119543c9f674	1012	*/
mbed_official	489:119543c9f674	1013	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\
mbed_official	489:119543c9f674	1014	MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC \| RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) \| (__PLLMUL__) ))
mbed_official	489:119543c9f674	1015	/**
mbed_official	489:119543c9f674	1016	* @}
mbed_official	489:119543c9f674	1017	*/
mbed_official	489:119543c9f674	1018
mbed_official	489:119543c9f674	1019	/** @defgroup RCC_Get_Clock_source Get Clock source
mbed_official	489:119543c9f674	1020	* @{
mbed_official	489:119543c9f674	1021	*/
mbed_official	489:119543c9f674	1022
mbed_official	489:119543c9f674	1023	/** @brief Macro to get the clock source used as system clock.
mbed_official	489:119543c9f674	1024	* @retval The clock source used as system clock. The returned value can be one
mbed_official	489:119543c9f674	1025	* of the following:
mbed_official	489:119543c9f674	1026	* @arg RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock
mbed_official	489:119543c9f674	1027	* @arg RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock
mbed_official	489:119543c9f674	1028	* @arg RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock
mbed_official	489:119543c9f674	1029	*/
mbed_official	489:119543c9f674	1030	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
mbed_official	489:119543c9f674	1031
mbed_official	489:119543c9f674	1032	/** @brief Get oscillator clock selected as PLL input clock
mbed_official	489:119543c9f674	1033	* @retval The clock source used for PLL entry. The returned value can be one
mbed_official	489:119543c9f674	1034	* of the following:
mbed_official	489:119543c9f674	1035	* @arg RCC_PLLSOURCE_HSI_DIV2: HSI oscillator clock selected as PLL input clock
mbed_official	489:119543c9f674	1036	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL input clock
mbed_official	489:119543c9f674	1037	*/
mbed_official	489:119543c9f674	1038	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((RCC->CFGR & RCC_CFGR_PLLSRC))
mbed_official	489:119543c9f674	1039
mbed_official	489:119543c9f674	1040	/**
mbed_official	489:119543c9f674	1041	* @}
mbed_official	489:119543c9f674	1042	*/
mbed_official	489:119543c9f674	1043	/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
mbed_official	489:119543c9f674	1044	* @{
mbed_official	489:119543c9f674	1045	*/
mbed_official	489:119543c9f674	1046
mbed_official	489:119543c9f674	1047	/** @brief Macro to configures the RTC clock (RTCCLK).
mbed_official	489:119543c9f674	1048	* @note As the RTC clock configuration bits are in the Backup domain and write
mbed_official	489:119543c9f674	1049	* access is denied to this domain after reset, you have to enable write
mbed_official	489:119543c9f674	1050	* access using the Power Backup Access macro before to configure
mbed_official	489:119543c9f674	1051	* the RTC clock source (to be done once after reset).
mbed_official	489:119543c9f674	1052	* @note Once the RTC clock is configured it can't be changed unless the
mbed_official	489:119543c9f674	1053	* Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
mbed_official	489:119543c9f674	1054	* a Power On Reset (POR).
mbed_official	489:119543c9f674	1055	*
mbed_official	489:119543c9f674	1056	* @param __RTC_CLKSOURCE__: specifies the RTC clock source.
mbed_official	489:119543c9f674	1057	* This parameter can be one of the following values:
mbed_official	489:119543c9f674	1058	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
mbed_official	489:119543c9f674	1059	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
mbed_official	489:119543c9f674	1060	* @arg RCC_RTCCLKSOURCE_HSE_DIV128: HSE divided by 128 selected as RTC clock
mbed_official	489:119543c9f674	1061	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
mbed_official	489:119543c9f674	1062	* work in STOP and STANDBY modes, and can be used as wakeup source.
mbed_official	489:119543c9f674	1063	* However, when the HSE clock is used as RTC clock source, the RTC
mbed_official	489:119543c9f674	1064	* cannot be used in STOP and STANDBY modes.
mbed_official	489:119543c9f674	1065	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
mbed_official	489:119543c9f674	1066	* RTC clock source).
mbed_official	489:119543c9f674	1067	*/
mbed_official	489:119543c9f674	1068	#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
mbed_official	489:119543c9f674	1069
mbed_official	489:119543c9f674	1070
mbed_official	489:119543c9f674	1071	/** @brief macros to get the RTC clock source.
mbed_official	489:119543c9f674	1072	*/
mbed_official	489:119543c9f674	1073	#define __HAL_RCC_GET_RTC_SOURCE() READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)
mbed_official	489:119543c9f674	1074
mbed_official	489:119543c9f674	1075	/** @brief Macros to enable the the RTC clock.
mbed_official	489:119543c9f674	1076	* @note These macros must be used only after the RTC clock source was selected.
mbed_official	489:119543c9f674	1077	*/
mbed_official	489:119543c9f674	1078	#define __HAL_RCC_RTC_ENABLE() ((__IO uint32_t ) RCC_BDCR_RTCEN_BB = ENABLE)
mbed_official	489:119543c9f674	1079
mbed_official	489:119543c9f674	1080	/** @brief Macros to disable the the RTC clock.
mbed_official	489:119543c9f674	1081	* @note These macros must be used only after the RTC clock source was selected.
mbed_official	489:119543c9f674	1082	*/
mbed_official	489:119543c9f674	1083	#define __HAL_RCC_RTC_DISABLE() ((__IO uint32_t ) RCC_BDCR_RTCEN_BB = DISABLE)
mbed_official	489:119543c9f674	1084
mbed_official	489:119543c9f674	1085	/** @brief Macros to force the Backup domain reset.
mbed_official	489:119543c9f674	1086	* @note This function resets the entire Backup domain.
mbed_official	489:119543c9f674	1087	*/
mbed_official	489:119543c9f674	1088	#define __HAL_RCC_BACKUPRESET_FORCE() ((__IO uint32_t ) RCC_BDCR_BDRST_BB = ENABLE)
mbed_official	489:119543c9f674	1089
mbed_official	489:119543c9f674	1090	/** @brief Macros to release the Backup domain reset.
mbed_official	489:119543c9f674	1091	*/
mbed_official	489:119543c9f674	1092	#define __HAL_RCC_BACKUPRESET_RELEASE() ((__IO uint32_t ) RCC_BDCR_BDRST_BB = DISABLE)
mbed_official	489:119543c9f674	1093
mbed_official	489:119543c9f674	1094
mbed_official	489:119543c9f674	1095	/**
mbed_official	489:119543c9f674	1096	* @}
mbed_official	489:119543c9f674	1097	*/
mbed_official	489:119543c9f674	1098
mbed_official	489:119543c9f674	1099	/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
mbed_official	489:119543c9f674	1100	* @brief macros to manage the specified RCC Flags and interrupts.
mbed_official	489:119543c9f674	1101	* @{
mbed_official	489:119543c9f674	1102	*/
mbed_official	489:119543c9f674	1103
mbed_official	489:119543c9f674	1104	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
mbed_official	489:119543c9f674	1105	* the selected interrupts.).
mbed_official	489:119543c9f674	1106	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
mbed_official	489:119543c9f674	1107	* This parameter can be any combination of the following values:
mbed_official	489:119543c9f674	1108	* @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official	489:119543c9f674	1109	* @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official	489:119543c9f674	1110	* @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official	489:119543c9f674	1111	* @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official	489:119543c9f674	1112	* @arg RCC_IT_PLLRDY: main PLL ready interrupt
mbed_official	489:119543c9f674	1113	* @arg RCC_IT_PLL2RDY: Main PLL2 ready interrupt.(*)
mbed_official	489:119543c9f674	1114	* @arg RCC_IT_PLLI2S2RDY: Main PLLI2S ready interrupt.(*)
mbed_official	489:119543c9f674	1115	* @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
mbed_official	489:119543c9f674	1116	*/
mbed_official	489:119543c9f674	1117	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS \|= (__INTERRUPT__))
mbed_official	489:119543c9f674	1118
mbed_official	489:119543c9f674	1119	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
mbed_official	489:119543c9f674	1120	* the selected interrupts).
mbed_official	489:119543c9f674	1121	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
mbed_official	489:119543c9f674	1122	* This parameter can be any combination of the following values:
mbed_official	489:119543c9f674	1123	* @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official	489:119543c9f674	1124	* @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official	489:119543c9f674	1125	* @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official	489:119543c9f674	1126	* @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official	489:119543c9f674	1127	* @arg RCC_IT_PLLRDY: main PLL ready interrupt
mbed_official	489:119543c9f674	1128	* @arg RCC_IT_PLL2RDY: Main PLL2 ready interrupt.(*)
mbed_official	489:119543c9f674	1129	* @arg RCC_IT_PLLI2S2RDY: Main PLLI2S ready interrupt.(*)
mbed_official	489:119543c9f674	1130	* @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
mbed_official	489:119543c9f674	1131	*/
mbed_official	489:119543c9f674	1132	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
mbed_official	489:119543c9f674	1133
mbed_official	489:119543c9f674	1134	/** @brief Clear the RCC's interrupt pending bits ( Perform Byte access to RCC_CIR[23:16]
mbed_official	489:119543c9f674	1135	* bits to clear the selected interrupt pending bits.
mbed_official	489:119543c9f674	1136	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
mbed_official	489:119543c9f674	1137	* This parameter can be any combination of the following values:
mbed_official	489:119543c9f674	1138	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
mbed_official	489:119543c9f674	1139	* @arg RCC_IT_LSERDY: LSE ready interrupt.
mbed_official	489:119543c9f674	1140	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
mbed_official	489:119543c9f674	1141	* @arg RCC_IT_HSERDY: HSE ready interrupt.
mbed_official	489:119543c9f674	1142	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
mbed_official	489:119543c9f674	1143	* @arg RCC_IT_PLL2RDY: Main PLL2 ready interrupt.(*)
mbed_official	489:119543c9f674	1144	* @arg RCC_IT_PLLI2S2RDY: Main PLLI2S ready interrupt.(*)
mbed_official	489:119543c9f674	1145	* @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
mbed_official	489:119543c9f674	1146	* @arg RCC_IT_CSS: Clock Security System interrupt
mbed_official	489:119543c9f674	1147	*/
mbed_official	489:119543c9f674	1148	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
mbed_official	489:119543c9f674	1149
mbed_official	489:119543c9f674	1150	/** @brief Check the RCC's interrupt has occurred or not.
mbed_official	489:119543c9f674	1151	* @param __INTERRUPT__: specifies the RCC interrupt source to check.
mbed_official	489:119543c9f674	1152	* This parameter can be one of the following values:
mbed_official	489:119543c9f674	1153	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
mbed_official	489:119543c9f674	1154	* @arg RCC_IT_LSERDY: LSE ready interrupt.
mbed_official	489:119543c9f674	1155	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
mbed_official	489:119543c9f674	1156	* @arg RCC_IT_HSERDY: HSE ready interrupt.
mbed_official	489:119543c9f674	1157	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
mbed_official	489:119543c9f674	1158	* @arg RCC_IT_PLL2RDY: Main PLL2 ready interrupt.(*)
mbed_official	489:119543c9f674	1159	* @arg RCC_IT_PLLI2S2RDY: Main PLLI2S ready interrupt.(*)
mbed_official	489:119543c9f674	1160	* @arg RCC_IT_CSS: Clock Security System interrupt
mbed_official	489:119543c9f674	1161	* @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
mbed_official	489:119543c9f674	1162	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
mbed_official	489:119543c9f674	1163	*/
mbed_official	489:119543c9f674	1164	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
mbed_official	489:119543c9f674	1165
mbed_official	489:119543c9f674	1166	/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
mbed_official	489:119543c9f674	1167	* RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
mbed_official	489:119543c9f674	1168	*/
mbed_official	489:119543c9f674	1169	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
mbed_official	489:119543c9f674	1170
mbed_official	489:119543c9f674	1171	/** @brief Check RCC flag is set or not.
mbed_official	489:119543c9f674	1172	* @param __FLAG__: specifies the flag to check.
mbed_official	489:119543c9f674	1173	* This parameter can be one of the following values:
mbed_official	489:119543c9f674	1174	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
mbed_official	489:119543c9f674	1175	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
mbed_official	489:119543c9f674	1176	* @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
mbed_official	489:119543c9f674	1177	* @arg RCC_FLAG_PLL2RDY: Main PLL2 clock ready.(*)
mbed_official	489:119543c9f674	1178	* @arg RCC_FLAG_PLLI2SRDY: Main PLLI2S clock ready.(*)
mbed_official	489:119543c9f674	1179	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
mbed_official	489:119543c9f674	1180	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
mbed_official	489:119543c9f674	1181	* @arg RCC_FLAG_PINRST: Pin reset.
mbed_official	489:119543c9f674	1182	* @arg RCC_FLAG_PORRST: POR/PDR reset.
mbed_official	489:119543c9f674	1183	* @arg RCC_FLAG_SFTRST: Software reset.
mbed_official	489:119543c9f674	1184	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
mbed_official	489:119543c9f674	1185	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
mbed_official	489:119543c9f674	1186	* @arg RCC_FLAG_LPWRRST: Low Power reset.
mbed_official	489:119543c9f674	1187	* @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
mbed_official	489:119543c9f674	1188	* @retval The new state of __FLAG__ (TRUE or FALSE).
mbed_official	489:119543c9f674	1189	*/
mbed_official	489:119543c9f674	1190	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR :((((__FLAG__) >> 5) == BDCR_REG_INDEX)? RCC->BDCR : RCC->CSR)) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))
mbed_official	489:119543c9f674	1191	/**
mbed_official	489:119543c9f674	1192	* @}
mbed_official	489:119543c9f674	1193	*/
mbed_official	489:119543c9f674	1194
mbed_official	489:119543c9f674	1195	/**
mbed_official	489:119543c9f674	1196	* @}
mbed_official	489:119543c9f674	1197	*/
mbed_official	489:119543c9f674	1198
mbed_official	489:119543c9f674	1199	/* Include RCC HAL Extension module */
mbed_official	489:119543c9f674	1200	#include "stm32f1xx_hal_rcc_ex.h"
mbed_official	489:119543c9f674	1201
mbed_official	489:119543c9f674	1202	/* Exported functions --------------------------------------------------------*/
mbed_official	489:119543c9f674	1203	/** @addtogroup RCC_Exported_Functions
mbed_official	489:119543c9f674	1204	* @{
mbed_official	489:119543c9f674	1205	*/
mbed_official	489:119543c9f674	1206
mbed_official	489:119543c9f674	1207	/** @addtogroup RCC_Exported_Functions_Group1
mbed_official	489:119543c9f674	1208	* @{
mbed_official	489:119543c9f674	1209	*/
mbed_official	489:119543c9f674	1210
mbed_official	489:119543c9f674	1211	/* Initialization and de-initialization functions ******************************/
mbed_official	489:119543c9f674	1212	void HAL_RCC_DeInit(void);
mbed_official	489:119543c9f674	1213	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
mbed_official	489:119543c9f674	1214	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
mbed_official	489:119543c9f674	1215
mbed_official	489:119543c9f674	1216	/**
mbed_official	489:119543c9f674	1217	* @}
mbed_official	489:119543c9f674	1218	*/
mbed_official	489:119543c9f674	1219
mbed_official	489:119543c9f674	1220	/** @addtogroup RCC_Exported_Functions_Group2
mbed_official	489:119543c9f674	1221	* @{
mbed_official	489:119543c9f674	1222	*/
mbed_official	489:119543c9f674	1223
mbed_official	489:119543c9f674	1224	/* Peripheral Control functions ************************************************/
mbed_official	489:119543c9f674	1225	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
mbed_official	489:119543c9f674	1226	void HAL_RCC_EnableCSS(void);
mbed_official	489:119543c9f674	1227	void HAL_RCC_DisableCSS(void);
mbed_official	489:119543c9f674	1228	uint32_t HAL_RCC_GetSysClockFreq(void);
mbed_official	489:119543c9f674	1229	uint32_t HAL_RCC_GetHCLKFreq(void);
mbed_official	489:119543c9f674	1230	uint32_t HAL_RCC_GetPCLK1Freq(void);
mbed_official	489:119543c9f674	1231	uint32_t HAL_RCC_GetPCLK2Freq(void);
mbed_official	489:119543c9f674	1232	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
mbed_official	489:119543c9f674	1233	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
mbed_official	489:119543c9f674	1234
mbed_official	489:119543c9f674	1235	/* CSS NMI IRQ handler */
mbed_official	489:119543c9f674	1236	void HAL_RCC_NMI_IRQHandler(void);
mbed_official	489:119543c9f674	1237
mbed_official	489:119543c9f674	1238	/* User Callbacks in non blocking mode (IT mode) */
mbed_official	489:119543c9f674	1239	void HAL_RCC_CSSCallback(void);
mbed_official	489:119543c9f674	1240
mbed_official	489:119543c9f674	1241	/**
mbed_official	489:119543c9f674	1242	* @}
mbed_official	489:119543c9f674	1243	*/
mbed_official	489:119543c9f674	1244
mbed_official	489:119543c9f674	1245	/**
mbed_official	489:119543c9f674	1246	* @}
mbed_official	489:119543c9f674	1247	*/
mbed_official	489:119543c9f674	1248
mbed_official	489:119543c9f674	1249	/**
mbed_official	489:119543c9f674	1250	* @}
mbed_official	489:119543c9f674	1251	*/
mbed_official	489:119543c9f674	1252
mbed_official	489:119543c9f674	1253	/**
mbed_official	489:119543c9f674	1254	* @}
mbed_official	489:119543c9f674	1255	*/
mbed_official	489:119543c9f674	1256
mbed_official	489:119543c9f674	1257	#ifdef __cplusplus
mbed_official	489:119543c9f674	1258	}
mbed_official	489:119543c9f674	1259	#endif
mbed_official	489:119543c9f674	1260
mbed_official	489:119543c9f674	1261	#endif /* __STM32F1xx_HAL_RCC_H */
mbed_official	489:119543c9f674	1262
mbed_official	489:119543c9f674	1263	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	27 Oct 2015
Imports:	0
Forks:	0
Commits:	637
Dependents:	0
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rcc.h@489:119543c9f674, 2015-03-12 (annotated)

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