marcus chiou / mbed-src

mbed library sources

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targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/mbed_overrides.c@505:0be0981777d7, 2015-04-08 (annotated)

Committer:
mbed_official
Date:
Wed Apr 08 07:15:07 2015 +0100
Revision:
505:0be0981777d7
Parent:
472:7bbab527289d
Child:
553:063b9f2f393c
Synchronized with git revision 331dc0725ddd63483e057688dfd2f70d628f7c29



Full URL: https://github.com/mbedmicro/mbed/commit/331dc0725ddd63483e057688dfd2f70d628f7c29/



Delta target - add RTC, bugfixes in mbed_overrides and pinnames

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 459:397407b8d9f7 1 /* mbed Microcontroller Library
mbed_official 472:7bbab527289d 2 * Copyright (c) 2006-2013 ARM Limited
mbed_official 472:7bbab527289d 3 *
mbed_official 472:7bbab527289d 4 * Licensed under the Apache License, Version 2.0 (the "License");
mbed_official 472:7bbab527289d 5 * you may not use this file except in compliance with the License.
mbed_official 472:7bbab527289d 6 * You may obtain a copy of the License at
mbed_official 472:7bbab527289d 7 *
mbed_official 472:7bbab527289d 8 * http://www.apache.org/licenses/LICENSE-2.0
mbed_official 472:7bbab527289d 9 *
mbed_official 472:7bbab527289d 10 * Unless required by applicable law or agreed to in writing, software
mbed_official 472:7bbab527289d 11 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 472:7bbab527289d 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 472:7bbab527289d 13 * See the License for the specific language governing permissions and
mbed_official 472:7bbab527289d 14 * limitations under the License.
mbed_official 459:397407b8d9f7 15 */
mbed_official 505:0be0981777d7 16
mbed_official 459:397407b8d9f7 17 #include "cmsis.h"
mbed_official 459:397407b8d9f7 18
mbed_official 505:0be0981777d7 19
mbed_official 505:0be0981777d7 20 #define SPIM1_SCK_PIN 11u /**< SPI clock GPIO pin number. */
mbed_official 505:0be0981777d7 21 #define SPIM1_MOSI_PIN 15u /**< SPI Master Out Slave In GPIO pin number. */
mbed_official 505:0be0981777d7 22 #define SPIM1_MISO_PIN 9u /**< SPI Master In Slave Out GPIO pin number. */
mbed_official 505:0be0981777d7 23 #define SPIM1_SS_PIN 28u /**< SPI Slave Select GPIO pin number. */
mbed_official 505:0be0981777d7 24
mbed_official 505:0be0981777d7 25 #define CMD_POWER_UP (0xAB)
mbed_official 505:0be0981777d7 26 #define CMD_POWER_DOWN (0xB9)
mbed_official 505:0be0981777d7 27
mbed_official 505:0be0981777d7 28 void spi_flash_init(void)
mbed_official 505:0be0981777d7 29 {
mbed_official 505:0be0981777d7 30 NRF_GPIO->PIN_CNF[SPIM1_MOSI_PIN] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
mbed_official 505:0be0981777d7 31 | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
mbed_official 505:0be0981777d7 32 | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
mbed_official 505:0be0981777d7 33 | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
mbed_official 505:0be0981777d7 34 | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
mbed_official 505:0be0981777d7 35 NRF_GPIO->PIN_CNF[SPIM1_MISO_PIN] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
mbed_official 505:0be0981777d7 36 | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
mbed_official 505:0be0981777d7 37 | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
mbed_official 505:0be0981777d7 38 | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
mbed_official 505:0be0981777d7 39 | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
mbed_official 505:0be0981777d7 40 NRF_GPIO->PIN_CNF[SPIM1_SCK_PIN] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
mbed_official 505:0be0981777d7 41 | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
mbed_official 505:0be0981777d7 42 | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
mbed_official 505:0be0981777d7 43 | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
mbed_official 505:0be0981777d7 44 | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
mbed_official 505:0be0981777d7 45
mbed_official 505:0be0981777d7 46 NRF_GPIO->PIN_CNF[SPIM1_SS_PIN] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
mbed_official 505:0be0981777d7 47 | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
mbed_official 505:0be0981777d7 48 | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
mbed_official 505:0be0981777d7 49 | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
mbed_official 505:0be0981777d7 50 | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
mbed_official 505:0be0981777d7 51 //cs = 1;
mbed_official 505:0be0981777d7 52 NRF_GPIO->OUTSET = (GPIO_OUTSET_PIN28_High << GPIO_OUTSET_PIN28_Pos);
mbed_official 505:0be0981777d7 53
mbed_official 505:0be0981777d7 54 NRF_SPI1->ENABLE = 1;
mbed_official 505:0be0981777d7 55 NRF_SPI1->PSELSCK = SPIM1_SCK_PIN;
mbed_official 505:0be0981777d7 56 NRF_SPI1->PSELMOSI = SPIM1_MISO_PIN;
mbed_official 505:0be0981777d7 57 NRF_SPI1->PSELMISO = SPIM1_MOSI_PIN;
mbed_official 505:0be0981777d7 58 //spi.frequency(1000000);
mbed_official 505:0be0981777d7 59 NRF_SPI1->FREQUENCY = 0x10000000; //1MHz
mbed_official 505:0be0981777d7 60
mbed_official 505:0be0981777d7 61 //spi.format(8,0);
mbed_official 505:0be0981777d7 62 uint32_t config_mode = 0;
mbed_official 505:0be0981777d7 63 config_mode = (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos); //mode 0
mbed_official 505:0be0981777d7 64 NRF_SPI1->CONFIG = (config_mode | (SPI_CONFIG_ORDER_MsbFirst << SPI_CONFIG_ORDER_Pos));
mbed_official 505:0be0981777d7 65 //cs = 0;
mbed_official 505:0be0981777d7 66 NRF_GPIO->OUTCLR = (GPIO_OUTCLR_PIN28_Clear << GPIO_OUTCLR_PIN28_Pos);
mbed_official 505:0be0981777d7 67 //spi.write(CMD_POWER_UP);
mbed_official 505:0be0981777d7 68 while (!NRF_SPI1->EVENTS_READY == 0) {
mbed_official 505:0be0981777d7 69 }
mbed_official 505:0be0981777d7 70 NRF_SPI1->TXD = (uint32_t)CMD_POWER_UP;
mbed_official 505:0be0981777d7 71 while (!NRF_SPI1->EVENTS_READY == 1) {
mbed_official 505:0be0981777d7 72 }
mbed_official 505:0be0981777d7 73 NRF_SPI1->EVENTS_READY = 0;
mbed_official 505:0be0981777d7 74 NRF_SPI1->RXD;
mbed_official 505:0be0981777d7 75 //wait_ms(30);
mbed_official 505:0be0981777d7 76 // Deselect the device
mbed_official 505:0be0981777d7 77 //cs = 1;
mbed_official 505:0be0981777d7 78 NRF_GPIO->OUTSET = (GPIO_OUTSET_PIN28_High << GPIO_OUTSET_PIN28_Pos);
mbed_official 505:0be0981777d7 79
mbed_official 505:0be0981777d7 80 }
mbed_official 505:0be0981777d7 81
mbed_official 505:0be0981777d7 82 void spi_flash_powerDown(void)
mbed_official 505:0be0981777d7 83 {
mbed_official 505:0be0981777d7 84 NRF_GPIO->OUTCLR = (GPIO_OUTCLR_PIN28_Clear << GPIO_OUTCLR_PIN28_Pos);
mbed_official 505:0be0981777d7 85 //spi.write(CMD_POWER_DOWN);
mbed_official 505:0be0981777d7 86 while (!NRF_SPI1->EVENTS_READY == 0) {
mbed_official 505:0be0981777d7 87 }
mbed_official 505:0be0981777d7 88 NRF_SPI1->TXD = (uint32_t)CMD_POWER_DOWN;
mbed_official 505:0be0981777d7 89 while (!NRF_SPI1->EVENTS_READY == 1) {
mbed_official 505:0be0981777d7 90 }
mbed_official 505:0be0981777d7 91 NRF_SPI1->EVENTS_READY = 0;
mbed_official 505:0be0981777d7 92 NRF_SPI1->RXD;
mbed_official 505:0be0981777d7 93 NRF_GPIO->OUTSET = (GPIO_OUTSET_PIN28_High << GPIO_OUTSET_PIN28_Pos);
mbed_official 505:0be0981777d7 94
mbed_official 505:0be0981777d7 95 //wait for sleep
mbed_official 505:0be0981777d7 96 //wait_us(3);
mbed_official 505:0be0981777d7 97 }
mbed_official 505:0be0981777d7 98
mbed_official 459:397407b8d9f7 99 void mbed_sdk_init()
mbed_official 459:397407b8d9f7 100 {
mbed_official 472:7bbab527289d 101 // Default SWIO setting, pull SWIO(p19) to low for turning antenna switch to BLE radiated path
mbed_official 459:397407b8d9f7 102 NRF_GPIO->PIN_CNF[19] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
mbed_official 459:397407b8d9f7 103 | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
mbed_official 459:397407b8d9f7 104 | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
mbed_official 459:397407b8d9f7 105 | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos)
mbed_official 459:397407b8d9f7 106 | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
mbed_official 459:397407b8d9f7 107
mbed_official 459:397407b8d9f7 108 NRF_GPIO->OUTCLR = (GPIO_OUTCLR_PIN19_Clear << GPIO_OUTCLR_PIN19_Pos);
mbed_official 472:7bbab527289d 109
mbed_official 472:7bbab527289d 110 // Config External Crystal to 32MHz
mbed_official 472:7bbab527289d 111 NRF_CLOCK->XTALFREQ = 0x00;
mbed_official 472:7bbab527289d 112 NRF_CLOCK->EVENTS_HFCLKSTARTED = 0;
mbed_official 472:7bbab527289d 113 NRF_CLOCK->TASKS_HFCLKSTART = 1;
mbed_official 472:7bbab527289d 114 while (NRF_CLOCK->EVENTS_HFCLKSTARTED == 0)
mbed_official 472:7bbab527289d 115 {// Do nothing.
mbed_official 472:7bbab527289d 116 }
mbed_official 505:0be0981777d7 117
mbed_official 505:0be0981777d7 118 spi_flash_init();
mbed_official 505:0be0981777d7 119
mbed_official 505:0be0981777d7 120 //nrf_delay_ms(10);
mbed_official 505:0be0981777d7 121 spi_flash_powerDown();
mbed_official 505:0be0981777d7 122
mbed_official 459:397407b8d9f7 123 }