Marek Trojan / mbed-dev

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_NXP/TARGET_LPC81X/sleep.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/hal/TARGET_NXP/TARGET_LPC81X/sleep.c@144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2013 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 #include "sleep_api.h"
<> 144:ef7eb2e8f9f7 17 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 18
<> 144:ef7eb2e8f9f7 19
<> 144:ef7eb2e8f9f7 20 //#define DEEPSLEEP
<> 144:ef7eb2e8f9f7 21 #define POWERDOWN
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 void sleep(void) {
<> 144:ef7eb2e8f9f7 24 //Normal sleep mode for PCON:
<> 144:ef7eb2e8f9f7 25 LPC_PMU->PCON &= ~0x03;
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27 //Normal sleep mode for ARM core:
<> 144:ef7eb2e8f9f7 28 SCB->SCR = 0;
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30 //And go to sleep
<> 144:ef7eb2e8f9f7 31 __WFI();
<> 144:ef7eb2e8f9f7 32 }
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 //Deepsleep/powerdown modes assume the device is configured to use its internal RC oscillator directly
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 #ifdef DEEPSLEEP
<> 144:ef7eb2e8f9f7 39 void deepsleep(void) {
<> 144:ef7eb2e8f9f7 40 //Deep sleep in PCON
<> 144:ef7eb2e8f9f7 41 LPC_PMU->PCON &= ~0x03;
<> 144:ef7eb2e8f9f7 42 LPC_PMU->PCON |= 0x01;
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 //If brownout detection and WDT are enabled, keep them enabled during sleep
<> 144:ef7eb2e8f9f7 45 LPC_SYSCON->PDSLEEPCFG = LPC_SYSCON->PDRUNCFG;
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 //After wakeup same stuff as currently enabled:
<> 144:ef7eb2e8f9f7 48 LPC_SYSCON->PDAWAKECFG = LPC_SYSCON->PDRUNCFG;
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 //All interrupts may wake up:
<> 144:ef7eb2e8f9f7 51 LPC_SYSCON->STARTERP0 = 0xFF;
<> 144:ef7eb2e8f9f7 52 LPC_SYSCON->STARTERP1 = 0xFFFF;
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 //Deep sleep for ARM core:
<> 144:ef7eb2e8f9f7 55 SCB->SCR = 1<<2;
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 __WFI();
<> 144:ef7eb2e8f9f7 58 }
<> 144:ef7eb2e8f9f7 59 #endif
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 #ifdef POWERDOWN
<> 144:ef7eb2e8f9f7 62 void deepsleep(void) {
<> 144:ef7eb2e8f9f7 63 //Powerdown in PCON
<> 144:ef7eb2e8f9f7 64 LPC_PMU->PCON &= ~0x03;
<> 144:ef7eb2e8f9f7 65 LPC_PMU->PCON |= 0x02;
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 //If brownout detection and WDT are enabled, keep them enabled during sleep
<> 144:ef7eb2e8f9f7 68 LPC_SYSCON->PDSLEEPCFG = LPC_SYSCON->PDRUNCFG;
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 //After wakeup same stuff as currently enabled:
<> 144:ef7eb2e8f9f7 71 LPC_SYSCON->PDAWAKECFG = LPC_SYSCON->PDRUNCFG;
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 //All interrupts may wake up:
<> 144:ef7eb2e8f9f7 74 LPC_SYSCON->STARTERP0 = 0xFF;
<> 144:ef7eb2e8f9f7 75 LPC_SYSCON->STARTERP1 = 0xFFFF;
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 //Deep sleep for ARM core:
<> 144:ef7eb2e8f9f7 78 SCB->SCR = 1<<2;
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 __WFI();
<> 144:ef7eb2e8f9f7 81 }
<> 144:ef7eb2e8f9f7 82 #endif