Marco Zecchini / Mbed OS Example_RTOS

Rtos API example

mbed-os/targets/TARGET_STM/gpio_api.c@0:9fca2b23d0ba, 2019-02-23 (annotated)

Committer:
marcozecchini
Date:
Sat Feb 23 12:13:36 2019 +0000
Revision:
0:9fca2b23d0ba
final commit

Who changed what in which revision?

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marcozecchini 0:9fca2b23d0ba 1 /* mbed Microcontroller Library
marcozecchini 0:9fca2b23d0ba 2 *******************************************************************************
marcozecchini 0:9fca2b23d0ba 3 * Copyright (c) 2015, STMicroelectronics
marcozecchini 0:9fca2b23d0ba 4 * All rights reserved.
marcozecchini 0:9fca2b23d0ba 5 *
marcozecchini 0:9fca2b23d0ba 6 * Redistribution and use in source and binary forms, with or without
marcozecchini 0:9fca2b23d0ba 7 * modification, are permitted provided that the following conditions are met:
marcozecchini 0:9fca2b23d0ba 8 *
marcozecchini 0:9fca2b23d0ba 9 * 1. Redistributions of source code must retain the above copyright notice,
marcozecchini 0:9fca2b23d0ba 10 * this list of conditions and the following disclaimer.
marcozecchini 0:9fca2b23d0ba 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
marcozecchini 0:9fca2b23d0ba 12 * this list of conditions and the following disclaimer in the documentation
marcozecchini 0:9fca2b23d0ba 13 * and/or other materials provided with the distribution.
marcozecchini 0:9fca2b23d0ba 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
marcozecchini 0:9fca2b23d0ba 15 * may be used to endorse or promote products derived from this software
marcozecchini 0:9fca2b23d0ba 16 * without specific prior written permission.
marcozecchini 0:9fca2b23d0ba 17 *
marcozecchini 0:9fca2b23d0ba 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
marcozecchini 0:9fca2b23d0ba 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
marcozecchini 0:9fca2b23d0ba 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
marcozecchini 0:9fca2b23d0ba 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
marcozecchini 0:9fca2b23d0ba 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
marcozecchini 0:9fca2b23d0ba 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
marcozecchini 0:9fca2b23d0ba 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
marcozecchini 0:9fca2b23d0ba 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
marcozecchini 0:9fca2b23d0ba 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
marcozecchini 0:9fca2b23d0ba 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
marcozecchini 0:9fca2b23d0ba 28 *******************************************************************************
marcozecchini 0:9fca2b23d0ba 29 */
marcozecchini 0:9fca2b23d0ba 30 #include "mbed_assert.h"
marcozecchini 0:9fca2b23d0ba 31 #include "gpio_api.h"
marcozecchini 0:9fca2b23d0ba 32 #include "pinmap.h"
marcozecchini 0:9fca2b23d0ba 33 #include "mbed_error.h"
marcozecchini 0:9fca2b23d0ba 34 #include "pin_device.h"
marcozecchini 0:9fca2b23d0ba 35
marcozecchini 0:9fca2b23d0ba 36 extern const uint32_t ll_pin_defines[16];
marcozecchini 0:9fca2b23d0ba 37
marcozecchini 0:9fca2b23d0ba 38 // Enable GPIO clock and return GPIO base address
marcozecchini 0:9fca2b23d0ba 39 GPIO_TypeDef *Set_GPIO_Clock(uint32_t port_idx) {
marcozecchini 0:9fca2b23d0ba 40 uint32_t gpio_add = 0;
marcozecchini 0:9fca2b23d0ba 41 switch (port_idx) {
marcozecchini 0:9fca2b23d0ba 42 case PortA:
marcozecchini 0:9fca2b23d0ba 43 gpio_add = GPIOA_BASE;
marcozecchini 0:9fca2b23d0ba 44 __HAL_RCC_GPIOA_CLK_ENABLE();
marcozecchini 0:9fca2b23d0ba 45 break;
marcozecchini 0:9fca2b23d0ba 46 case PortB:
marcozecchini 0:9fca2b23d0ba 47 gpio_add = GPIOB_BASE;
marcozecchini 0:9fca2b23d0ba 48 __HAL_RCC_GPIOB_CLK_ENABLE();
marcozecchini 0:9fca2b23d0ba 49 break;
marcozecchini 0:9fca2b23d0ba 50 #if defined(GPIOC_BASE)
marcozecchini 0:9fca2b23d0ba 51 case PortC:
marcozecchini 0:9fca2b23d0ba 52 gpio_add = GPIOC_BASE;
marcozecchini 0:9fca2b23d0ba 53 __HAL_RCC_GPIOC_CLK_ENABLE();
marcozecchini 0:9fca2b23d0ba 54 break;
marcozecchini 0:9fca2b23d0ba 55 #endif
marcozecchini 0:9fca2b23d0ba 56 #if defined GPIOD_BASE
marcozecchini 0:9fca2b23d0ba 57 case PortD:
marcozecchini 0:9fca2b23d0ba 58 gpio_add = GPIOD_BASE;
marcozecchini 0:9fca2b23d0ba 59 __HAL_RCC_GPIOD_CLK_ENABLE();
marcozecchini 0:9fca2b23d0ba 60 break;
marcozecchini 0:9fca2b23d0ba 61 #endif
marcozecchini 0:9fca2b23d0ba 62 #if defined GPIOE_BASE
marcozecchini 0:9fca2b23d0ba 63 case PortE:
marcozecchini 0:9fca2b23d0ba 64 gpio_add = GPIOE_BASE;
marcozecchini 0:9fca2b23d0ba 65 __HAL_RCC_GPIOE_CLK_ENABLE();
marcozecchini 0:9fca2b23d0ba 66 break;
marcozecchini 0:9fca2b23d0ba 67 #endif
marcozecchini 0:9fca2b23d0ba 68 #if defined GPIOF_BASE
marcozecchini 0:9fca2b23d0ba 69 case PortF:
marcozecchini 0:9fca2b23d0ba 70 gpio_add = GPIOF_BASE;
marcozecchini 0:9fca2b23d0ba 71 __HAL_RCC_GPIOF_CLK_ENABLE();
marcozecchini 0:9fca2b23d0ba 72 break;
marcozecchini 0:9fca2b23d0ba 73 #endif
marcozecchini 0:9fca2b23d0ba 74 #if defined GPIOG_BASE
marcozecchini 0:9fca2b23d0ba 75 case PortG:
marcozecchini 0:9fca2b23d0ba 76 #if defined TARGET_STM32L4
marcozecchini 0:9fca2b23d0ba 77 __HAL_RCC_PWR_CLK_ENABLE();
marcozecchini 0:9fca2b23d0ba 78 HAL_PWREx_EnableVddIO2();
marcozecchini 0:9fca2b23d0ba 79 #endif
marcozecchini 0:9fca2b23d0ba 80 gpio_add = GPIOG_BASE;
marcozecchini 0:9fca2b23d0ba 81 __HAL_RCC_GPIOG_CLK_ENABLE();
marcozecchini 0:9fca2b23d0ba 82 break;
marcozecchini 0:9fca2b23d0ba 83 #endif
marcozecchini 0:9fca2b23d0ba 84 #if defined GPIOH_BASE
marcozecchini 0:9fca2b23d0ba 85 case PortH:
marcozecchini 0:9fca2b23d0ba 86 gpio_add = GPIOH_BASE;
marcozecchini 0:9fca2b23d0ba 87 __HAL_RCC_GPIOH_CLK_ENABLE();
marcozecchini 0:9fca2b23d0ba 88 break;
marcozecchini 0:9fca2b23d0ba 89 #endif
marcozecchini 0:9fca2b23d0ba 90 #if defined GPIOI_BASE
marcozecchini 0:9fca2b23d0ba 91 case PortI:
marcozecchini 0:9fca2b23d0ba 92 gpio_add = GPIOI_BASE;
marcozecchini 0:9fca2b23d0ba 93 __HAL_RCC_GPIOI_CLK_ENABLE();
marcozecchini 0:9fca2b23d0ba 94 break;
marcozecchini 0:9fca2b23d0ba 95 #endif
marcozecchini 0:9fca2b23d0ba 96 #if defined GPIOJ_BASE
marcozecchini 0:9fca2b23d0ba 97 case PortJ:
marcozecchini 0:9fca2b23d0ba 98 gpio_add = GPIOJ_BASE;
marcozecchini 0:9fca2b23d0ba 99 __HAL_RCC_GPIOJ_CLK_ENABLE();
marcozecchini 0:9fca2b23d0ba 100 break;
marcozecchini 0:9fca2b23d0ba 101 #endif
marcozecchini 0:9fca2b23d0ba 102 #if defined GPIOK_BASE
marcozecchini 0:9fca2b23d0ba 103 case PortK:
marcozecchini 0:9fca2b23d0ba 104 gpio_add = GPIOK_BASE;
marcozecchini 0:9fca2b23d0ba 105 __HAL_RCC_GPIOK_CLK_ENABLE();
marcozecchini 0:9fca2b23d0ba 106 break;
marcozecchini 0:9fca2b23d0ba 107 #endif
marcozecchini 0:9fca2b23d0ba 108 default:
marcozecchini 0:9fca2b23d0ba 109 error("Pinmap error: wrong port number.");
marcozecchini 0:9fca2b23d0ba 110 break;
marcozecchini 0:9fca2b23d0ba 111 }
marcozecchini 0:9fca2b23d0ba 112 return (GPIO_TypeDef *) gpio_add;
marcozecchini 0:9fca2b23d0ba 113 }
marcozecchini 0:9fca2b23d0ba 114
marcozecchini 0:9fca2b23d0ba 115 uint32_t gpio_set(PinName pin) {
marcozecchini 0:9fca2b23d0ba 116 MBED_ASSERT(pin != (PinName)NC);
marcozecchini 0:9fca2b23d0ba 117
marcozecchini 0:9fca2b23d0ba 118 pin_function(pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
marcozecchini 0:9fca2b23d0ba 119
marcozecchini 0:9fca2b23d0ba 120 return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask
marcozecchini 0:9fca2b23d0ba 121 }
marcozecchini 0:9fca2b23d0ba 122
marcozecchini 0:9fca2b23d0ba 123
marcozecchini 0:9fca2b23d0ba 124 void gpio_init(gpio_t *obj, PinName pin) {
marcozecchini 0:9fca2b23d0ba 125 obj->pin = pin;
marcozecchini 0:9fca2b23d0ba 126 if (pin == (PinName)NC) {
marcozecchini 0:9fca2b23d0ba 127 return;
marcozecchini 0:9fca2b23d0ba 128 }
marcozecchini 0:9fca2b23d0ba 129
marcozecchini 0:9fca2b23d0ba 130 uint32_t port_index = STM_PORT(pin);
marcozecchini 0:9fca2b23d0ba 131
marcozecchini 0:9fca2b23d0ba 132 // Enable GPIO clock
marcozecchini 0:9fca2b23d0ba 133 GPIO_TypeDef *gpio = Set_GPIO_Clock(port_index);
marcozecchini 0:9fca2b23d0ba 134
marcozecchini 0:9fca2b23d0ba 135 // Fill GPIO object structure for future use
marcozecchini 0:9fca2b23d0ba 136 obj->mask = gpio_set(pin);
marcozecchini 0:9fca2b23d0ba 137 obj->gpio = gpio;
marcozecchini 0:9fca2b23d0ba 138 obj->ll_pin = ll_pin_defines[STM_PIN(obj->pin)];
marcozecchini 0:9fca2b23d0ba 139 obj->reg_in = &gpio->IDR;
marcozecchini 0:9fca2b23d0ba 140 obj->reg_set = &gpio->BSRR;
marcozecchini 0:9fca2b23d0ba 141 #ifdef GPIO_IP_WITHOUT_BRR
marcozecchini 0:9fca2b23d0ba 142 obj->reg_clr = &gpio->BSRR;
marcozecchini 0:9fca2b23d0ba 143 #else
marcozecchini 0:9fca2b23d0ba 144 obj->reg_clr = &gpio->BRR;
marcozecchini 0:9fca2b23d0ba 145 #endif
marcozecchini 0:9fca2b23d0ba 146 }
marcozecchini 0:9fca2b23d0ba 147
marcozecchini 0:9fca2b23d0ba 148 void gpio_mode(gpio_t *obj, PinMode mode) {
marcozecchini 0:9fca2b23d0ba 149 pin_mode(obj->pin, mode);
marcozecchini 0:9fca2b23d0ba 150 }
marcozecchini 0:9fca2b23d0ba 151
marcozecchini 0:9fca2b23d0ba 152 inline void gpio_dir(gpio_t *obj, PinDirection direction) {
marcozecchini 0:9fca2b23d0ba 153 if (direction == PIN_INPUT) {
marcozecchini 0:9fca2b23d0ba 154 LL_GPIO_SetPinMode(obj->gpio, obj->ll_pin, LL_GPIO_MODE_INPUT);
marcozecchini 0:9fca2b23d0ba 155 } else {
marcozecchini 0:9fca2b23d0ba 156 LL_GPIO_SetPinMode(obj->gpio, obj->ll_pin, LL_GPIO_MODE_OUTPUT);
marcozecchini 0:9fca2b23d0ba 157 }
marcozecchini 0:9fca2b23d0ba 158 }
marcozecchini 0:9fca2b23d0ba 159