Marco Zecchini / Mbed OS Example_RTOS

Rtos API example

mbed-os/targets/TARGET_STM/i2c_api.c@0:9fca2b23d0ba, 2019-02-23 (annotated)

Committer:
marcozecchini
Date:
Sat Feb 23 12:13:36 2019 +0000
Revision:
0:9fca2b23d0ba
final commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
marcozecchini 0:9fca2b23d0ba 1 /* mbed Microcontroller Library
marcozecchini 0:9fca2b23d0ba 2 *******************************************************************************
marcozecchini 0:9fca2b23d0ba 3 * Copyright (c) 2015, STMicroelectronics
marcozecchini 0:9fca2b23d0ba 4 * All rights reserved.
marcozecchini 0:9fca2b23d0ba 5 *
marcozecchini 0:9fca2b23d0ba 6 * Redistribution and use in source and binary forms, with or without
marcozecchini 0:9fca2b23d0ba 7 * modification, are permitted provided that the following conditions are met:
marcozecchini 0:9fca2b23d0ba 8 *
marcozecchini 0:9fca2b23d0ba 9 * 1. Redistributions of source code must retain the above copyright notice,
marcozecchini 0:9fca2b23d0ba 10 * this list of conditions and the following disclaimer.
marcozecchini 0:9fca2b23d0ba 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
marcozecchini 0:9fca2b23d0ba 12 * this list of conditions and the following disclaimer in the documentation
marcozecchini 0:9fca2b23d0ba 13 * and/or other materials provided with the distribution.
marcozecchini 0:9fca2b23d0ba 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
marcozecchini 0:9fca2b23d0ba 15 * may be used to endorse or promote products derived from this software
marcozecchini 0:9fca2b23d0ba 16 * without specific prior written permission.
marcozecchini 0:9fca2b23d0ba 17 *
marcozecchini 0:9fca2b23d0ba 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
marcozecchini 0:9fca2b23d0ba 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
marcozecchini 0:9fca2b23d0ba 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
marcozecchini 0:9fca2b23d0ba 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
marcozecchini 0:9fca2b23d0ba 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
marcozecchini 0:9fca2b23d0ba 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
marcozecchini 0:9fca2b23d0ba 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
marcozecchini 0:9fca2b23d0ba 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
marcozecchini 0:9fca2b23d0ba 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
marcozecchini 0:9fca2b23d0ba 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
marcozecchini 0:9fca2b23d0ba 28 *******************************************************************************
marcozecchini 0:9fca2b23d0ba 29 */
marcozecchini 0:9fca2b23d0ba 30
marcozecchini 0:9fca2b23d0ba 31
marcozecchini 0:9fca2b23d0ba 32 #include "mbed_assert.h"
marcozecchini 0:9fca2b23d0ba 33 #include "i2c_api.h"
marcozecchini 0:9fca2b23d0ba 34 #include "platform/mbed_wait_api.h"
marcozecchini 0:9fca2b23d0ba 35
marcozecchini 0:9fca2b23d0ba 36 #if DEVICE_I2C
marcozecchini 0:9fca2b23d0ba 37
marcozecchini 0:9fca2b23d0ba 38 #include "cmsis.h"
marcozecchini 0:9fca2b23d0ba 39 #include "pinmap.h"
marcozecchini 0:9fca2b23d0ba 40 #include "PeripheralPins.h"
marcozecchini 0:9fca2b23d0ba 41 #include "i2c_device.h" // family specific defines
marcozecchini 0:9fca2b23d0ba 42
marcozecchini 0:9fca2b23d0ba 43 #ifndef DEBUG_STDIO
marcozecchini 0:9fca2b23d0ba 44 # define DEBUG_STDIO 0
marcozecchini 0:9fca2b23d0ba 45 #endif
marcozecchini 0:9fca2b23d0ba 46
marcozecchini 0:9fca2b23d0ba 47 #if DEBUG_STDIO
marcozecchini 0:9fca2b23d0ba 48 # include <stdio.h>
marcozecchini 0:9fca2b23d0ba 49 # define DEBUG_PRINTF(...) do { printf(__VA_ARGS__); } while(0)
marcozecchini 0:9fca2b23d0ba 50 #else
marcozecchini 0:9fca2b23d0ba 51 # define DEBUG_PRINTF(...) {}
marcozecchini 0:9fca2b23d0ba 52 #endif
marcozecchini 0:9fca2b23d0ba 53
marcozecchini 0:9fca2b23d0ba 54 #if DEVICE_I2C_ASYNCH
marcozecchini 0:9fca2b23d0ba 55 #define I2C_S(obj) (struct i2c_s *) (&((obj)->i2c))
marcozecchini 0:9fca2b23d0ba 56 #else
marcozecchini 0:9fca2b23d0ba 57 #define I2C_S(obj) (struct i2c_s *) (obj)
marcozecchini 0:9fca2b23d0ba 58 #endif
marcozecchini 0:9fca2b23d0ba 59
marcozecchini 0:9fca2b23d0ba 60 /* Family specific description for I2C */
marcozecchini 0:9fca2b23d0ba 61 #define I2C_NUM (5)
marcozecchini 0:9fca2b23d0ba 62 static I2C_HandleTypeDef* i2c_handles[I2C_NUM];
marcozecchini 0:9fca2b23d0ba 63
marcozecchini 0:9fca2b23d0ba 64 /* Timeout values are based on core clock and I2C clock.
marcozecchini 0:9fca2b23d0ba 65 The BYTE_TIMEOUT is computed as twice the number of cycles it would
marcozecchini 0:9fca2b23d0ba 66 take to send 10 bits over I2C. Most Flags should take less than that.
marcozecchini 0:9fca2b23d0ba 67 This is for immediate FLAG or ACK check.
marcozecchini 0:9fca2b23d0ba 68 */
marcozecchini 0:9fca2b23d0ba 69 #define BYTE_TIMEOUT ((SystemCoreClock / obj_s->hz) * 2 * 10)
marcozecchini 0:9fca2b23d0ba 70 /* Timeout values based on I2C clock.
marcozecchini 0:9fca2b23d0ba 71 The BYTE_TIMEOUT_US is computed as 3x the time in us it would
marcozecchini 0:9fca2b23d0ba 72 take to send 10 bits over I2C. Most Flags should take less than that.
marcozecchini 0:9fca2b23d0ba 73 This is for complete transfers check.
marcozecchini 0:9fca2b23d0ba 74 */
marcozecchini 0:9fca2b23d0ba 75 #define BYTE_TIMEOUT_US ((SystemCoreClock / obj_s->hz) * 3 * 10)
marcozecchini 0:9fca2b23d0ba 76 /* Timeout values for flags and events waiting loops. These timeouts are
marcozecchini 0:9fca2b23d0ba 77 not based on accurate values, they just guarantee that the application will
marcozecchini 0:9fca2b23d0ba 78 not remain stuck if the I2C communication is corrupted.
marcozecchini 0:9fca2b23d0ba 79 */
marcozecchini 0:9fca2b23d0ba 80 #define FLAG_TIMEOUT ((int)0x1000)
marcozecchini 0:9fca2b23d0ba 81
marcozecchini 0:9fca2b23d0ba 82 /* GENERIC INIT and HELPERS FUNCTIONS */
marcozecchini 0:9fca2b23d0ba 83
marcozecchini 0:9fca2b23d0ba 84 #if defined(I2C1_BASE)
marcozecchini 0:9fca2b23d0ba 85 static void i2c1_irq(void)
marcozecchini 0:9fca2b23d0ba 86 {
marcozecchini 0:9fca2b23d0ba 87 I2C_HandleTypeDef * handle = i2c_handles[0];
marcozecchini 0:9fca2b23d0ba 88 HAL_I2C_EV_IRQHandler(handle);
marcozecchini 0:9fca2b23d0ba 89 HAL_I2C_ER_IRQHandler(handle);
marcozecchini 0:9fca2b23d0ba 90 }
marcozecchini 0:9fca2b23d0ba 91 #endif
marcozecchini 0:9fca2b23d0ba 92 #if defined(I2C2_BASE)
marcozecchini 0:9fca2b23d0ba 93 static void i2c2_irq(void)
marcozecchini 0:9fca2b23d0ba 94 {
marcozecchini 0:9fca2b23d0ba 95 I2C_HandleTypeDef * handle = i2c_handles[1];
marcozecchini 0:9fca2b23d0ba 96 HAL_I2C_EV_IRQHandler(handle);
marcozecchini 0:9fca2b23d0ba 97 HAL_I2C_ER_IRQHandler(handle);
marcozecchini 0:9fca2b23d0ba 98 }
marcozecchini 0:9fca2b23d0ba 99 #endif
marcozecchini 0:9fca2b23d0ba 100 #if defined(I2C3_BASE)
marcozecchini 0:9fca2b23d0ba 101 static void i2c3_irq(void)
marcozecchini 0:9fca2b23d0ba 102 {
marcozecchini 0:9fca2b23d0ba 103 I2C_HandleTypeDef * handle = i2c_handles[2];
marcozecchini 0:9fca2b23d0ba 104 HAL_I2C_EV_IRQHandler(handle);
marcozecchini 0:9fca2b23d0ba 105 HAL_I2C_ER_IRQHandler(handle);
marcozecchini 0:9fca2b23d0ba 106 }
marcozecchini 0:9fca2b23d0ba 107 #endif
marcozecchini 0:9fca2b23d0ba 108 #if defined(I2C4_BASE)
marcozecchini 0:9fca2b23d0ba 109 static void i2c4_irq(void)
marcozecchini 0:9fca2b23d0ba 110 {
marcozecchini 0:9fca2b23d0ba 111 I2C_HandleTypeDef * handle = i2c_handles[3];
marcozecchini 0:9fca2b23d0ba 112 HAL_I2C_EV_IRQHandler(handle);
marcozecchini 0:9fca2b23d0ba 113 HAL_I2C_ER_IRQHandler(handle);
marcozecchini 0:9fca2b23d0ba 114 }
marcozecchini 0:9fca2b23d0ba 115 #endif
marcozecchini 0:9fca2b23d0ba 116 #if defined(FMPI2C1_BASE)
marcozecchini 0:9fca2b23d0ba 117 static void i2c5_irq(void)
marcozecchini 0:9fca2b23d0ba 118 {
marcozecchini 0:9fca2b23d0ba 119 I2C_HandleTypeDef * handle = i2c_handles[4];
marcozecchini 0:9fca2b23d0ba 120 HAL_I2C_EV_IRQHandler(handle);
marcozecchini 0:9fca2b23d0ba 121 HAL_I2C_ER_IRQHandler(handle);
marcozecchini 0:9fca2b23d0ba 122 }
marcozecchini 0:9fca2b23d0ba 123 #endif
marcozecchini 0:9fca2b23d0ba 124
marcozecchini 0:9fca2b23d0ba 125 void i2c_ev_err_enable(i2c_t *obj, uint32_t handler) {
marcozecchini 0:9fca2b23d0ba 126 struct i2c_s *obj_s = I2C_S(obj);
marcozecchini 0:9fca2b23d0ba 127 IRQn_Type irq_event_n = obj_s->event_i2cIRQ;
marcozecchini 0:9fca2b23d0ba 128 IRQn_Type irq_error_n = obj_s->error_i2cIRQ;
marcozecchini 0:9fca2b23d0ba 129 /* default prio in master case is set to 2 */
marcozecchini 0:9fca2b23d0ba 130 uint32_t prio = 2;
marcozecchini 0:9fca2b23d0ba 131
marcozecchini 0:9fca2b23d0ba 132 /* Set up ITs using IRQ and handler tables */
marcozecchini 0:9fca2b23d0ba 133 NVIC_SetVector(irq_event_n, handler);
marcozecchini 0:9fca2b23d0ba 134 NVIC_SetVector(irq_error_n, handler);
marcozecchini 0:9fca2b23d0ba 135
marcozecchini 0:9fca2b23d0ba 136 #if DEVICE_I2CSLAVE
marcozecchini 0:9fca2b23d0ba 137 /* Set higher priority to slave device than master.
marcozecchini 0:9fca2b23d0ba 138 * In case a device makes use of both master and slave, the
marcozecchini 0:9fca2b23d0ba 139 * slave needs higher responsiveness.
marcozecchini 0:9fca2b23d0ba 140 */
marcozecchini 0:9fca2b23d0ba 141 if (obj_s->slave) {
marcozecchini 0:9fca2b23d0ba 142 prio = 1;
marcozecchini 0:9fca2b23d0ba 143 }
marcozecchini 0:9fca2b23d0ba 144 #endif
marcozecchini 0:9fca2b23d0ba 145
marcozecchini 0:9fca2b23d0ba 146 NVIC_SetPriority(irq_event_n, prio);
marcozecchini 0:9fca2b23d0ba 147 NVIC_SetPriority(irq_error_n, prio);
marcozecchini 0:9fca2b23d0ba 148 NVIC_EnableIRQ(irq_event_n);
marcozecchini 0:9fca2b23d0ba 149 NVIC_EnableIRQ(irq_error_n);
marcozecchini 0:9fca2b23d0ba 150 }
marcozecchini 0:9fca2b23d0ba 151
marcozecchini 0:9fca2b23d0ba 152 void i2c_ev_err_disable(i2c_t *obj) {
marcozecchini 0:9fca2b23d0ba 153 struct i2c_s *obj_s = I2C_S(obj);
marcozecchini 0:9fca2b23d0ba 154 IRQn_Type irq_event_n = obj_s->event_i2cIRQ;
marcozecchini 0:9fca2b23d0ba 155 IRQn_Type irq_error_n = obj_s->error_i2cIRQ;
marcozecchini 0:9fca2b23d0ba 156
marcozecchini 0:9fca2b23d0ba 157 HAL_NVIC_DisableIRQ(irq_event_n);
marcozecchini 0:9fca2b23d0ba 158 HAL_NVIC_DisableIRQ(irq_error_n);
marcozecchini 0:9fca2b23d0ba 159 }
marcozecchini 0:9fca2b23d0ba 160
marcozecchini 0:9fca2b23d0ba 161 uint32_t i2c_get_irq_handler(i2c_t *obj)
marcozecchini 0:9fca2b23d0ba 162 {
marcozecchini 0:9fca2b23d0ba 163 struct i2c_s *obj_s = I2C_S(obj);
marcozecchini 0:9fca2b23d0ba 164 I2C_HandleTypeDef *handle = &(obj_s->handle);
marcozecchini 0:9fca2b23d0ba 165 uint32_t handler = 0;
marcozecchini 0:9fca2b23d0ba 166
marcozecchini 0:9fca2b23d0ba 167 switch (obj_s->index) {
marcozecchini 0:9fca2b23d0ba 168 #if defined(I2C1_BASE)
marcozecchini 0:9fca2b23d0ba 169 case 0:
marcozecchini 0:9fca2b23d0ba 170 handler = (uint32_t)&i2c1_irq;
marcozecchini 0:9fca2b23d0ba 171 break;
marcozecchini 0:9fca2b23d0ba 172 #endif
marcozecchini 0:9fca2b23d0ba 173 #if defined(I2C2_BASE)
marcozecchini 0:9fca2b23d0ba 174 case 1:
marcozecchini 0:9fca2b23d0ba 175 handler = (uint32_t)&i2c2_irq;
marcozecchini 0:9fca2b23d0ba 176 break;
marcozecchini 0:9fca2b23d0ba 177 #endif
marcozecchini 0:9fca2b23d0ba 178 #if defined(I2C3_BASE)
marcozecchini 0:9fca2b23d0ba 179 case 2:
marcozecchini 0:9fca2b23d0ba 180 handler = (uint32_t)&i2c3_irq;
marcozecchini 0:9fca2b23d0ba 181 break;
marcozecchini 0:9fca2b23d0ba 182 #endif
marcozecchini 0:9fca2b23d0ba 183 #if defined(I2C4_BASE)
marcozecchini 0:9fca2b23d0ba 184 case 3:
marcozecchini 0:9fca2b23d0ba 185 handler = (uint32_t)&i2c4_irq;
marcozecchini 0:9fca2b23d0ba 186 break;
marcozecchini 0:9fca2b23d0ba 187 #endif
marcozecchini 0:9fca2b23d0ba 188 #if defined(FMPI2C1_BASE)
marcozecchini 0:9fca2b23d0ba 189 case 4:
marcozecchini 0:9fca2b23d0ba 190 handler = (uint32_t)&i2c5_irq;
marcozecchini 0:9fca2b23d0ba 191 break;
marcozecchini 0:9fca2b23d0ba 192 #endif
marcozecchini 0:9fca2b23d0ba 193 }
marcozecchini 0:9fca2b23d0ba 194
marcozecchini 0:9fca2b23d0ba 195 i2c_handles[obj_s->index] = handle;
marcozecchini 0:9fca2b23d0ba 196 return handler;
marcozecchini 0:9fca2b23d0ba 197 }
marcozecchini 0:9fca2b23d0ba 198
marcozecchini 0:9fca2b23d0ba 199 void i2c_hw_reset(i2c_t *obj) {
marcozecchini 0:9fca2b23d0ba 200 int timeout;
marcozecchini 0:9fca2b23d0ba 201 struct i2c_s *obj_s = I2C_S(obj);
marcozecchini 0:9fca2b23d0ba 202 I2C_HandleTypeDef *handle = &(obj_s->handle);
marcozecchini 0:9fca2b23d0ba 203
marcozecchini 0:9fca2b23d0ba 204 handle->Instance = (I2C_TypeDef *)(obj_s->i2c);
marcozecchini 0:9fca2b23d0ba 205
marcozecchini 0:9fca2b23d0ba 206 // wait before reset
marcozecchini 0:9fca2b23d0ba 207 timeout = BYTE_TIMEOUT;
marcozecchini 0:9fca2b23d0ba 208 while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BUSY)) && (--timeout != 0));
marcozecchini 0:9fca2b23d0ba 209 #if defined I2C1_BASE
marcozecchini 0:9fca2b23d0ba 210 if (obj_s->i2c == I2C_1) {
marcozecchini 0:9fca2b23d0ba 211 __HAL_RCC_I2C1_FORCE_RESET();
marcozecchini 0:9fca2b23d0ba 212 __HAL_RCC_I2C1_RELEASE_RESET();
marcozecchini 0:9fca2b23d0ba 213 }
marcozecchini 0:9fca2b23d0ba 214 #endif
marcozecchini 0:9fca2b23d0ba 215 #if defined I2C2_BASE
marcozecchini 0:9fca2b23d0ba 216 if (obj_s->i2c == I2C_2) {
marcozecchini 0:9fca2b23d0ba 217 __HAL_RCC_I2C2_FORCE_RESET();
marcozecchini 0:9fca2b23d0ba 218 __HAL_RCC_I2C2_RELEASE_RESET();
marcozecchini 0:9fca2b23d0ba 219 }
marcozecchini 0:9fca2b23d0ba 220 #endif
marcozecchini 0:9fca2b23d0ba 221 #if defined I2C3_BASE
marcozecchini 0:9fca2b23d0ba 222 if (obj_s->i2c == I2C_3) {
marcozecchini 0:9fca2b23d0ba 223 __HAL_RCC_I2C3_FORCE_RESET();
marcozecchini 0:9fca2b23d0ba 224 __HAL_RCC_I2C3_RELEASE_RESET();
marcozecchini 0:9fca2b23d0ba 225 }
marcozecchini 0:9fca2b23d0ba 226 #endif
marcozecchini 0:9fca2b23d0ba 227 #if defined I2C4_BASE
marcozecchini 0:9fca2b23d0ba 228 if (obj_s->i2c == I2C_4) {
marcozecchini 0:9fca2b23d0ba 229 __HAL_RCC_I2C4_FORCE_RESET();
marcozecchini 0:9fca2b23d0ba 230 __HAL_RCC_I2C4_RELEASE_RESET();
marcozecchini 0:9fca2b23d0ba 231 }
marcozecchini 0:9fca2b23d0ba 232 #endif
marcozecchini 0:9fca2b23d0ba 233 #if defined FMPI2C1_BASE
marcozecchini 0:9fca2b23d0ba 234 if (obj_s->i2c == FMPI2C_1) {
marcozecchini 0:9fca2b23d0ba 235 __HAL_RCC_FMPI2C1_FORCE_RESET();
marcozecchini 0:9fca2b23d0ba 236 __HAL_RCC_FMPI2C1_RELEASE_RESET();
marcozecchini 0:9fca2b23d0ba 237 }
marcozecchini 0:9fca2b23d0ba 238 #endif
marcozecchini 0:9fca2b23d0ba 239 }
marcozecchini 0:9fca2b23d0ba 240
marcozecchini 0:9fca2b23d0ba 241 void i2c_sw_reset(i2c_t *obj)
marcozecchini 0:9fca2b23d0ba 242 {
marcozecchini 0:9fca2b23d0ba 243 struct i2c_s *obj_s = I2C_S(obj);
marcozecchini 0:9fca2b23d0ba 244 I2C_HandleTypeDef *handle = &(obj_s->handle);
marcozecchini 0:9fca2b23d0ba 245 /* SW reset procedure:
marcozecchini 0:9fca2b23d0ba 246 * PE must be kept low during at least 3 APB clock cycles
marcozecchini 0:9fca2b23d0ba 247 * in order to perform the software reset.
marcozecchini 0:9fca2b23d0ba 248 * This is ensured by writing the following software sequence:
marcozecchini 0:9fca2b23d0ba 249 * - Write PE=0
marcozecchini 0:9fca2b23d0ba 250 * - Check PE=0
marcozecchini 0:9fca2b23d0ba 251 * - Write PE=1.
marcozecchini 0:9fca2b23d0ba 252 */
marcozecchini 0:9fca2b23d0ba 253 handle->Instance->CR1 &= ~I2C_CR1_PE;
marcozecchini 0:9fca2b23d0ba 254 while(handle->Instance->CR1 & I2C_CR1_PE);
marcozecchini 0:9fca2b23d0ba 255 handle->Instance->CR1 |= I2C_CR1_PE;
marcozecchini 0:9fca2b23d0ba 256 }
marcozecchini 0:9fca2b23d0ba 257
marcozecchini 0:9fca2b23d0ba 258 void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
marcozecchini 0:9fca2b23d0ba 259
marcozecchini 0:9fca2b23d0ba 260 struct i2c_s *obj_s = I2C_S(obj);
marcozecchini 0:9fca2b23d0ba 261
marcozecchini 0:9fca2b23d0ba 262 // Determine the I2C to use
marcozecchini 0:9fca2b23d0ba 263 I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
marcozecchini 0:9fca2b23d0ba 264 I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
marcozecchini 0:9fca2b23d0ba 265 obj_s->sda = sda;
marcozecchini 0:9fca2b23d0ba 266 obj_s->scl = scl;
marcozecchini 0:9fca2b23d0ba 267
marcozecchini 0:9fca2b23d0ba 268 obj_s->i2c = (I2CName)pinmap_merge(i2c_sda, i2c_scl);
marcozecchini 0:9fca2b23d0ba 269 MBED_ASSERT(obj_s->i2c != (I2CName)NC);
marcozecchini 0:9fca2b23d0ba 270
marcozecchini 0:9fca2b23d0ba 271 #if defined I2C1_BASE
marcozecchini 0:9fca2b23d0ba 272 // Enable I2C1 clock and pinout if not done
marcozecchini 0:9fca2b23d0ba 273 if (obj_s->i2c == I2C_1) {
marcozecchini 0:9fca2b23d0ba 274 obj_s->index = 0;
marcozecchini 0:9fca2b23d0ba 275 __HAL_RCC_I2C1_CLK_ENABLE();
marcozecchini 0:9fca2b23d0ba 276 // Configure I2C pins
marcozecchini 0:9fca2b23d0ba 277 obj_s->event_i2cIRQ = I2C1_EV_IRQn;
marcozecchini 0:9fca2b23d0ba 278 obj_s->error_i2cIRQ = I2C1_ER_IRQn;
marcozecchini 0:9fca2b23d0ba 279 }
marcozecchini 0:9fca2b23d0ba 280 #endif
marcozecchini 0:9fca2b23d0ba 281 #if defined I2C2_BASE
marcozecchini 0:9fca2b23d0ba 282 // Enable I2C2 clock and pinout if not done
marcozecchini 0:9fca2b23d0ba 283 if (obj_s->i2c == I2C_2) {
marcozecchini 0:9fca2b23d0ba 284 obj_s->index = 1;
marcozecchini 0:9fca2b23d0ba 285 __HAL_RCC_I2C2_CLK_ENABLE();
marcozecchini 0:9fca2b23d0ba 286 obj_s->event_i2cIRQ = I2C2_EV_IRQn;
marcozecchini 0:9fca2b23d0ba 287 obj_s->error_i2cIRQ = I2C2_ER_IRQn;
marcozecchini 0:9fca2b23d0ba 288 }
marcozecchini 0:9fca2b23d0ba 289 #endif
marcozecchini 0:9fca2b23d0ba 290 #if defined I2C3_BASE
marcozecchini 0:9fca2b23d0ba 291 // Enable I2C3 clock and pinout if not done
marcozecchini 0:9fca2b23d0ba 292 if (obj_s->i2c == I2C_3) {
marcozecchini 0:9fca2b23d0ba 293 obj_s->index = 2;
marcozecchini 0:9fca2b23d0ba 294 __HAL_RCC_I2C3_CLK_ENABLE();
marcozecchini 0:9fca2b23d0ba 295 obj_s->event_i2cIRQ = I2C3_EV_IRQn;
marcozecchini 0:9fca2b23d0ba 296 obj_s->error_i2cIRQ = I2C3_ER_IRQn;
marcozecchini 0:9fca2b23d0ba 297 }
marcozecchini 0:9fca2b23d0ba 298 #endif
marcozecchini 0:9fca2b23d0ba 299 #if defined I2C4_BASE
marcozecchini 0:9fca2b23d0ba 300 // Enable I2C3 clock and pinout if not done
marcozecchini 0:9fca2b23d0ba 301 if (obj_s->i2c == I2C_4) {
marcozecchini 0:9fca2b23d0ba 302 obj_s->index = 3;
marcozecchini 0:9fca2b23d0ba 303 __HAL_RCC_I2C4_CLK_ENABLE();
marcozecchini 0:9fca2b23d0ba 304 obj_s->event_i2cIRQ = I2C4_EV_IRQn;
marcozecchini 0:9fca2b23d0ba 305 obj_s->error_i2cIRQ = I2C4_ER_IRQn;
marcozecchini 0:9fca2b23d0ba 306 }
marcozecchini 0:9fca2b23d0ba 307 #endif
marcozecchini 0:9fca2b23d0ba 308 #if defined FMPI2C1_BASE
marcozecchini 0:9fca2b23d0ba 309 // Enable I2C3 clock and pinout if not done
marcozecchini 0:9fca2b23d0ba 310 if (obj_s->i2c == FMPI2C_1) {
marcozecchini 0:9fca2b23d0ba 311 obj_s->index = 4;
marcozecchini 0:9fca2b23d0ba 312 __HAL_RCC_FMPI2C1_CLK_ENABLE();
marcozecchini 0:9fca2b23d0ba 313 obj_s->event_i2cIRQ = FMPI2C1_EV_IRQn;
marcozecchini 0:9fca2b23d0ba 314 obj_s->error_i2cIRQ = FMPI2C1_ER_IRQn;
marcozecchini 0:9fca2b23d0ba 315 }
marcozecchini 0:9fca2b23d0ba 316 #endif
marcozecchini 0:9fca2b23d0ba 317
marcozecchini 0:9fca2b23d0ba 318 // Configure I2C pins
marcozecchini 0:9fca2b23d0ba 319 pinmap_pinout(sda, PinMap_I2C_SDA);
marcozecchini 0:9fca2b23d0ba 320 pinmap_pinout(scl, PinMap_I2C_SCL);
marcozecchini 0:9fca2b23d0ba 321 pin_mode(sda, OpenDrainNoPull);
marcozecchini 0:9fca2b23d0ba 322 pin_mode(scl, OpenDrainNoPull);
marcozecchini 0:9fca2b23d0ba 323
marcozecchini 0:9fca2b23d0ba 324 // I2C configuration
marcozecchini 0:9fca2b23d0ba 325 // Default hz value used for timeout computation
marcozecchini 0:9fca2b23d0ba 326 if(!obj_s->hz)
marcozecchini 0:9fca2b23d0ba 327 obj_s->hz = 100000; // 100 kHz per default
marcozecchini 0:9fca2b23d0ba 328
marcozecchini 0:9fca2b23d0ba 329 // Reset to clear pending flags if any
marcozecchini 0:9fca2b23d0ba 330 i2c_hw_reset(obj);
marcozecchini 0:9fca2b23d0ba 331 i2c_frequency(obj, obj_s->hz );
marcozecchini 0:9fca2b23d0ba 332
marcozecchini 0:9fca2b23d0ba 333 #if DEVICE_I2CSLAVE
marcozecchini 0:9fca2b23d0ba 334 // I2C master by default
marcozecchini 0:9fca2b23d0ba 335 obj_s->slave = 0;
marcozecchini 0:9fca2b23d0ba 336 obj_s->pending_slave_tx_master_rx = 0;
marcozecchini 0:9fca2b23d0ba 337 obj_s->pending_slave_rx_maxter_tx = 0;
marcozecchini 0:9fca2b23d0ba 338 #endif
marcozecchini 0:9fca2b23d0ba 339
marcozecchini 0:9fca2b23d0ba 340 // I2C Xfer operation init
marcozecchini 0:9fca2b23d0ba 341 obj_s->event = 0;
marcozecchini 0:9fca2b23d0ba 342 obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME;
marcozecchini 0:9fca2b23d0ba 343 #ifdef I2C_IP_VERSION_V2
marcozecchini 0:9fca2b23d0ba 344 obj_s->pending_start = 0;
marcozecchini 0:9fca2b23d0ba 345 #endif
marcozecchini 0:9fca2b23d0ba 346 }
marcozecchini 0:9fca2b23d0ba 347
marcozecchini 0:9fca2b23d0ba 348 void i2c_frequency(i2c_t *obj, int hz)
marcozecchini 0:9fca2b23d0ba 349 {
marcozecchini 0:9fca2b23d0ba 350 int timeout;
marcozecchini 0:9fca2b23d0ba 351 struct i2c_s *obj_s = I2C_S(obj);
marcozecchini 0:9fca2b23d0ba 352 I2C_HandleTypeDef *handle = &(obj_s->handle);
marcozecchini 0:9fca2b23d0ba 353
marcozecchini 0:9fca2b23d0ba 354 // wait before init
marcozecchini 0:9fca2b23d0ba 355 timeout = BYTE_TIMEOUT;
marcozecchini 0:9fca2b23d0ba 356 while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BUSY)) && (--timeout != 0));
marcozecchini 0:9fca2b23d0ba 357
marcozecchini 0:9fca2b23d0ba 358 #ifdef I2C_IP_VERSION_V1
marcozecchini 0:9fca2b23d0ba 359 handle->Init.ClockSpeed = hz;
marcozecchini 0:9fca2b23d0ba 360 handle->Init.DutyCycle = I2C_DUTYCYCLE_2;
marcozecchini 0:9fca2b23d0ba 361 #endif
marcozecchini 0:9fca2b23d0ba 362 #ifdef I2C_IP_VERSION_V2
marcozecchini 0:9fca2b23d0ba 363 /* Only predefined timing for below frequencies are supported */
marcozecchini 0:9fca2b23d0ba 364 MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000));
marcozecchini 0:9fca2b23d0ba 365 handle->Init.Timing = get_i2c_timing(hz);
marcozecchini 0:9fca2b23d0ba 366
marcozecchini 0:9fca2b23d0ba 367 // Enable the Fast Mode Plus capability
marcozecchini 0:9fca2b23d0ba 368 if (hz == 1000000) {
marcozecchini 0:9fca2b23d0ba 369 #if defined(I2C1_BASE) && defined(__HAL_SYSCFG_FASTMODEPLUS_ENABLE) && defined (I2C_FASTMODEPLUS_I2C1)
marcozecchini 0:9fca2b23d0ba 370 if (obj_s->i2c == I2C_1) {
marcozecchini 0:9fca2b23d0ba 371 HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C1);
marcozecchini 0:9fca2b23d0ba 372 }
marcozecchini 0:9fca2b23d0ba 373 #endif
marcozecchini 0:9fca2b23d0ba 374 #if defined(I2C2_BASE) && defined(__HAL_SYSCFG_FASTMODEPLUS_ENABLE) && defined (I2C_FASTMODEPLUS_I2C2)
marcozecchini 0:9fca2b23d0ba 375 if (obj_s->i2c == I2C_2) {
marcozecchini 0:9fca2b23d0ba 376 HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C2);
marcozecchini 0:9fca2b23d0ba 377 }
marcozecchini 0:9fca2b23d0ba 378 #endif
marcozecchini 0:9fca2b23d0ba 379 #if defined(I2C3_BASE) && defined(__HAL_SYSCFG_FASTMODEPLUS_ENABLE) && defined (I2C_FASTMODEPLUS_I2C3)
marcozecchini 0:9fca2b23d0ba 380 if (obj_s->i2c == I2C_3) {
marcozecchini 0:9fca2b23d0ba 381 HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C3);
marcozecchini 0:9fca2b23d0ba 382 }
marcozecchini 0:9fca2b23d0ba 383 #endif
marcozecchini 0:9fca2b23d0ba 384 #if defined(I2C4_BASE) && defined(__HAL_SYSCFG_FASTMODEPLUS_ENABLE) && defined (I2C_FASTMODEPLUS_I2C4)
marcozecchini 0:9fca2b23d0ba 385 if (obj_s->i2c == I2C_4) {
marcozecchini 0:9fca2b23d0ba 386 HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C4);
marcozecchini 0:9fca2b23d0ba 387 }
marcozecchini 0:9fca2b23d0ba 388 #endif
marcozecchini 0:9fca2b23d0ba 389 }
marcozecchini 0:9fca2b23d0ba 390 #endif //I2C_IP_VERSION_V2
marcozecchini 0:9fca2b23d0ba 391
marcozecchini 0:9fca2b23d0ba 392 /*##-1- Configure the I2C clock source. The clock is derived from the SYSCLK #*/
marcozecchini 0:9fca2b23d0ba 393 #if defined(I2C1_BASE) && defined (__HAL_RCC_I2C1_CONFIG)
marcozecchini 0:9fca2b23d0ba 394 if (obj_s->i2c == I2C_1) {
marcozecchini 0:9fca2b23d0ba 395 __HAL_RCC_I2C1_CONFIG(I2CAPI_I2C1_CLKSRC);
marcozecchini 0:9fca2b23d0ba 396 }
marcozecchini 0:9fca2b23d0ba 397 #endif
marcozecchini 0:9fca2b23d0ba 398 #if defined(I2C2_BASE) && defined(__HAL_RCC_I2C2_CONFIG)
marcozecchini 0:9fca2b23d0ba 399 if (obj_s->i2c == I2C_2) {
marcozecchini 0:9fca2b23d0ba 400 __HAL_RCC_I2C2_CONFIG(I2CAPI_I2C2_CLKSRC);
marcozecchini 0:9fca2b23d0ba 401 }
marcozecchini 0:9fca2b23d0ba 402 #endif
marcozecchini 0:9fca2b23d0ba 403 #if defined(I2C3_BASE) && defined(__HAL_RCC_I2C3_CONFIG)
marcozecchini 0:9fca2b23d0ba 404 if (obj_s->i2c == I2C_3) {
marcozecchini 0:9fca2b23d0ba 405 __HAL_RCC_I2C3_CONFIG(I2CAPI_I2C3_CLKSRC);
marcozecchini 0:9fca2b23d0ba 406 }
marcozecchini 0:9fca2b23d0ba 407 #endif
marcozecchini 0:9fca2b23d0ba 408 #if defined(I2C4_BASE) && defined(__HAL_RCC_I2C4_CONFIG)
marcozecchini 0:9fca2b23d0ba 409 if (obj_s->i2c == I2C_4) {
marcozecchini 0:9fca2b23d0ba 410 __HAL_RCC_I2C4_CONFIG(I2CAPI_I2C4_CLKSRC);
marcozecchini 0:9fca2b23d0ba 411 }
marcozecchini 0:9fca2b23d0ba 412 #endif
marcozecchini 0:9fca2b23d0ba 413
marcozecchini 0:9fca2b23d0ba 414 #ifdef I2C_ANALOGFILTER_ENABLE
marcozecchini 0:9fca2b23d0ba 415 /* Enable the Analog I2C Filter */
marcozecchini 0:9fca2b23d0ba 416 HAL_I2CEx_AnalogFilter_Config(handle,I2C_ANALOGFILTER_ENABLE);
marcozecchini 0:9fca2b23d0ba 417 #endif
marcozecchini 0:9fca2b23d0ba 418
marcozecchini 0:9fca2b23d0ba 419 // I2C configuration
marcozecchini 0:9fca2b23d0ba 420 handle->Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
marcozecchini 0:9fca2b23d0ba 421 handle->Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
marcozecchini 0:9fca2b23d0ba 422 handle->Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
marcozecchini 0:9fca2b23d0ba 423 handle->Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
marcozecchini 0:9fca2b23d0ba 424 handle->Init.OwnAddress1 = 0;
marcozecchini 0:9fca2b23d0ba 425 handle->Init.OwnAddress2 = 0;
marcozecchini 0:9fca2b23d0ba 426 HAL_I2C_Init(handle);
marcozecchini 0:9fca2b23d0ba 427
marcozecchini 0:9fca2b23d0ba 428 /* store frequency for timeout computation */
marcozecchini 0:9fca2b23d0ba 429 obj_s->hz = hz;
marcozecchini 0:9fca2b23d0ba 430 }
marcozecchini 0:9fca2b23d0ba 431
marcozecchini 0:9fca2b23d0ba 432 i2c_t *get_i2c_obj(I2C_HandleTypeDef *hi2c){
marcozecchini 0:9fca2b23d0ba 433 /* Aim of the function is to get i2c_s pointer using hi2c pointer */
marcozecchini 0:9fca2b23d0ba 434 /* Highly inspired from magical linux kernel's "container_of" */
marcozecchini 0:9fca2b23d0ba 435 /* (which was not directly used since not compatible with IAR toolchain) */
marcozecchini 0:9fca2b23d0ba 436 struct i2c_s *obj_s;
marcozecchini 0:9fca2b23d0ba 437 i2c_t *obj;
marcozecchini 0:9fca2b23d0ba 438
marcozecchini 0:9fca2b23d0ba 439 obj_s = (struct i2c_s *)( (char *)hi2c - offsetof(struct i2c_s,handle));
marcozecchini 0:9fca2b23d0ba 440 obj = (i2c_t *)( (char *)obj_s - offsetof(i2c_t,i2c));
marcozecchini 0:9fca2b23d0ba 441
marcozecchini 0:9fca2b23d0ba 442 return (obj);
marcozecchini 0:9fca2b23d0ba 443 }
marcozecchini 0:9fca2b23d0ba 444
marcozecchini 0:9fca2b23d0ba 445 void i2c_reset(i2c_t *obj) {
marcozecchini 0:9fca2b23d0ba 446 struct i2c_s *obj_s = I2C_S(obj);
marcozecchini 0:9fca2b23d0ba 447 /* As recommended in i2c_api.h, mainly send stop */
marcozecchini 0:9fca2b23d0ba 448 i2c_stop(obj);
marcozecchini 0:9fca2b23d0ba 449 /* then re-init */
marcozecchini 0:9fca2b23d0ba 450 i2c_init(obj, obj_s->sda, obj_s->scl);
marcozecchini 0:9fca2b23d0ba 451 }
marcozecchini 0:9fca2b23d0ba 452
marcozecchini 0:9fca2b23d0ba 453 /*
marcozecchini 0:9fca2b23d0ba 454 * UNITARY APIS.
marcozecchini 0:9fca2b23d0ba 455 * For very basic operations, direct registers access is needed
marcozecchini 0:9fca2b23d0ba 456 * There are 2 different IPs version that need to be supported
marcozecchini 0:9fca2b23d0ba 457 */
marcozecchini 0:9fca2b23d0ba 458 #ifdef I2C_IP_VERSION_V1
marcozecchini 0:9fca2b23d0ba 459 int i2c_start(i2c_t *obj) {
marcozecchini 0:9fca2b23d0ba 460
marcozecchini 0:9fca2b23d0ba 461 int timeout;
marcozecchini 0:9fca2b23d0ba 462 struct i2c_s *obj_s = I2C_S(obj);
marcozecchini 0:9fca2b23d0ba 463 I2C_HandleTypeDef *handle = &(obj_s->handle);
marcozecchini 0:9fca2b23d0ba 464
marcozecchini 0:9fca2b23d0ba 465 // Clear Acknowledge failure flag
marcozecchini 0:9fca2b23d0ba 466 __HAL_I2C_CLEAR_FLAG(handle, I2C_FLAG_AF);
marcozecchini 0:9fca2b23d0ba 467
marcozecchini 0:9fca2b23d0ba 468 // Wait the STOP condition has been previously correctly sent
marcozecchini 0:9fca2b23d0ba 469 // This timeout can be avoid in some specific cases by simply clearing the STOP bit
marcozecchini 0:9fca2b23d0ba 470 timeout = FLAG_TIMEOUT;
marcozecchini 0:9fca2b23d0ba 471 while ((handle->Instance->CR1 & I2C_CR1_STOP) == I2C_CR1_STOP) {
marcozecchini 0:9fca2b23d0ba 472 if ((timeout--) == 0) {
marcozecchini 0:9fca2b23d0ba 473 return 1;
marcozecchini 0:9fca2b23d0ba 474 }
marcozecchini 0:9fca2b23d0ba 475 }
marcozecchini 0:9fca2b23d0ba 476
marcozecchini 0:9fca2b23d0ba 477 // Generate the START condition
marcozecchini 0:9fca2b23d0ba 478 handle->Instance->CR1 |= I2C_CR1_START;
marcozecchini 0:9fca2b23d0ba 479
marcozecchini 0:9fca2b23d0ba 480 // Wait the START condition has been correctly sent
marcozecchini 0:9fca2b23d0ba 481 timeout = FLAG_TIMEOUT;
marcozecchini 0:9fca2b23d0ba 482 while (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_SB) == RESET) {
marcozecchini 0:9fca2b23d0ba 483 if ((timeout--) == 0) {
marcozecchini 0:9fca2b23d0ba 484 return 1;
marcozecchini 0:9fca2b23d0ba 485 }
marcozecchini 0:9fca2b23d0ba 486 }
marcozecchini 0:9fca2b23d0ba 487
marcozecchini 0:9fca2b23d0ba 488 return 0;
marcozecchini 0:9fca2b23d0ba 489 }
marcozecchini 0:9fca2b23d0ba 490
marcozecchini 0:9fca2b23d0ba 491 int i2c_stop(i2c_t *obj) {
marcozecchini 0:9fca2b23d0ba 492 struct i2c_s *obj_s = I2C_S(obj);
marcozecchini 0:9fca2b23d0ba 493 I2C_TypeDef *i2c = (I2C_TypeDef *)obj_s->i2c;
marcozecchini 0:9fca2b23d0ba 494
marcozecchini 0:9fca2b23d0ba 495 // Generate the STOP condition
marcozecchini 0:9fca2b23d0ba 496 i2c->CR1 |= I2C_CR1_STOP;
marcozecchini 0:9fca2b23d0ba 497
marcozecchini 0:9fca2b23d0ba 498 /* In case of mixed usage of the APIs (unitary + SYNC)
marcozecchini 0:9fca2b23d0ba 499 * re-init HAL state
marcozecchini 0:9fca2b23d0ba 500 */
marcozecchini 0:9fca2b23d0ba 501 if(obj_s->XferOperation != I2C_FIRST_AND_LAST_FRAME)
marcozecchini 0:9fca2b23d0ba 502 i2c_init(obj, obj_s->sda, obj_s->scl);
marcozecchini 0:9fca2b23d0ba 503
marcozecchini 0:9fca2b23d0ba 504 return 0;
marcozecchini 0:9fca2b23d0ba 505 }
marcozecchini 0:9fca2b23d0ba 506
marcozecchini 0:9fca2b23d0ba 507 int i2c_byte_read(i2c_t *obj, int last) {
marcozecchini 0:9fca2b23d0ba 508
marcozecchini 0:9fca2b23d0ba 509 int timeout;
marcozecchini 0:9fca2b23d0ba 510 struct i2c_s *obj_s = I2C_S(obj);
marcozecchini 0:9fca2b23d0ba 511 I2C_HandleTypeDef *handle = &(obj_s->handle);
marcozecchini 0:9fca2b23d0ba 512
marcozecchini 0:9fca2b23d0ba 513 if (last) {
marcozecchini 0:9fca2b23d0ba 514 // Don't acknowledge the last byte
marcozecchini 0:9fca2b23d0ba 515 handle->Instance->CR1 &= ~I2C_CR1_ACK;
marcozecchini 0:9fca2b23d0ba 516 } else {
marcozecchini 0:9fca2b23d0ba 517 // Acknowledge the byte
marcozecchini 0:9fca2b23d0ba 518 handle->Instance->CR1 |= I2C_CR1_ACK;
marcozecchini 0:9fca2b23d0ba 519 }
marcozecchini 0:9fca2b23d0ba 520
marcozecchini 0:9fca2b23d0ba 521 // Wait until the byte is received
marcozecchini 0:9fca2b23d0ba 522 timeout = FLAG_TIMEOUT;
marcozecchini 0:9fca2b23d0ba 523 while (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_RXNE) == RESET) {
marcozecchini 0:9fca2b23d0ba 524 if ((timeout--) == 0) {
marcozecchini 0:9fca2b23d0ba 525 return -1;
marcozecchini 0:9fca2b23d0ba 526 }
marcozecchini 0:9fca2b23d0ba 527 }
marcozecchini 0:9fca2b23d0ba 528
marcozecchini 0:9fca2b23d0ba 529 return (int)handle->Instance->DR;
marcozecchini 0:9fca2b23d0ba 530 }
marcozecchini 0:9fca2b23d0ba 531
marcozecchini 0:9fca2b23d0ba 532 int i2c_byte_write(i2c_t *obj, int data) {
marcozecchini 0:9fca2b23d0ba 533
marcozecchini 0:9fca2b23d0ba 534 int timeout;
marcozecchini 0:9fca2b23d0ba 535 struct i2c_s *obj_s = I2C_S(obj);
marcozecchini 0:9fca2b23d0ba 536 I2C_HandleTypeDef *handle = &(obj_s->handle);
marcozecchini 0:9fca2b23d0ba 537
marcozecchini 0:9fca2b23d0ba 538 handle->Instance->DR = (uint8_t)data;
marcozecchini 0:9fca2b23d0ba 539
marcozecchini 0:9fca2b23d0ba 540 // Wait until the byte (might be the address) is transmitted
marcozecchini 0:9fca2b23d0ba 541 timeout = FLAG_TIMEOUT;
marcozecchini 0:9fca2b23d0ba 542 while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_TXE) == RESET) &&
marcozecchini 0:9fca2b23d0ba 543 (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BTF) == RESET) &&
marcozecchini 0:9fca2b23d0ba 544 (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_ADDR) == RESET)) {
marcozecchini 0:9fca2b23d0ba 545 if ((timeout--) == 0) {
marcozecchini 0:9fca2b23d0ba 546 return 2;
marcozecchini 0:9fca2b23d0ba 547 }
marcozecchini 0:9fca2b23d0ba 548 }
marcozecchini 0:9fca2b23d0ba 549
marcozecchini 0:9fca2b23d0ba 550 if (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_ADDR) != RESET)
marcozecchini 0:9fca2b23d0ba 551 {
marcozecchini 0:9fca2b23d0ba 552 __HAL_I2C_CLEAR_ADDRFLAG(handle);
marcozecchini 0:9fca2b23d0ba 553 }
marcozecchini 0:9fca2b23d0ba 554
marcozecchini 0:9fca2b23d0ba 555 return 1;
marcozecchini 0:9fca2b23d0ba 556 }
marcozecchini 0:9fca2b23d0ba 557 #endif //I2C_IP_VERSION_V1
marcozecchini 0:9fca2b23d0ba 558 #ifdef I2C_IP_VERSION_V2
marcozecchini 0:9fca2b23d0ba 559
marcozecchini 0:9fca2b23d0ba 560 int i2c_start(i2c_t *obj) {
marcozecchini 0:9fca2b23d0ba 561 struct i2c_s *obj_s = I2C_S(obj);
marcozecchini 0:9fca2b23d0ba 562 /* This I2C IP doesn't */
marcozecchini 0:9fca2b23d0ba 563 obj_s->pending_start = 1;
marcozecchini 0:9fca2b23d0ba 564 return 0;
marcozecchini 0:9fca2b23d0ba 565 }
marcozecchini 0:9fca2b23d0ba 566
marcozecchini 0:9fca2b23d0ba 567 int i2c_stop(i2c_t *obj) {
marcozecchini 0:9fca2b23d0ba 568 struct i2c_s *obj_s = I2C_S(obj);
marcozecchini 0:9fca2b23d0ba 569 I2C_HandleTypeDef *handle = &(obj_s->handle);
marcozecchini 0:9fca2b23d0ba 570 int timeout = FLAG_TIMEOUT;
marcozecchini 0:9fca2b23d0ba 571 #if DEVICE_I2CSLAVE
marcozecchini 0:9fca2b23d0ba 572 if (obj_s->slave) {
marcozecchini 0:9fca2b23d0ba 573 /* re-init slave when stop is requested */
marcozecchini 0:9fca2b23d0ba 574 i2c_init(obj, obj_s->sda, obj_s->scl);
marcozecchini 0:9fca2b23d0ba 575 return 0;
marcozecchini 0:9fca2b23d0ba 576 }
marcozecchini 0:9fca2b23d0ba 577 #endif
marcozecchini 0:9fca2b23d0ba 578 // Disable reload mode
marcozecchini 0:9fca2b23d0ba 579 handle->Instance->CR2 &= (uint32_t)~I2C_CR2_RELOAD;
marcozecchini 0:9fca2b23d0ba 580 // Generate the STOP condition
marcozecchini 0:9fca2b23d0ba 581 handle->Instance->CR2 |= I2C_CR2_STOP;
marcozecchini 0:9fca2b23d0ba 582
marcozecchini 0:9fca2b23d0ba 583 timeout = FLAG_TIMEOUT;
marcozecchini 0:9fca2b23d0ba 584 while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_STOPF)) {
marcozecchini 0:9fca2b23d0ba 585 if ((timeout--) == 0) {
marcozecchini 0:9fca2b23d0ba 586 return I2C_ERROR_BUS_BUSY;
marcozecchini 0:9fca2b23d0ba 587 }
marcozecchini 0:9fca2b23d0ba 588 }
marcozecchini 0:9fca2b23d0ba 589
marcozecchini 0:9fca2b23d0ba 590 /* Clear STOP Flag */
marcozecchini 0:9fca2b23d0ba 591 __HAL_I2C_CLEAR_FLAG(handle, I2C_FLAG_STOPF);
marcozecchini 0:9fca2b23d0ba 592
marcozecchini 0:9fca2b23d0ba 593 /* Erase slave address, this wiil be used as a marker
marcozecchini 0:9fca2b23d0ba 594 * to know when we need to prepare next start */
marcozecchini 0:9fca2b23d0ba 595 handle->Instance->CR2 &= ~I2C_CR2_SADD;
marcozecchini 0:9fca2b23d0ba 596
marcozecchini 0:9fca2b23d0ba 597 /*
marcozecchini 0:9fca2b23d0ba 598 * V2 IP is meant for automatic STOP, not user STOP
marcozecchini 0:9fca2b23d0ba 599 * SW reset the IP state machine before next transaction
marcozecchini 0:9fca2b23d0ba 600 */
marcozecchini 0:9fca2b23d0ba 601 i2c_sw_reset(obj);
marcozecchini 0:9fca2b23d0ba 602
marcozecchini 0:9fca2b23d0ba 603 /* In case of mixed usage of the APIs (unitary + SYNC)
marcozecchini 0:9fca2b23d0ba 604 * re-init HAL state */
marcozecchini 0:9fca2b23d0ba 605 if (obj_s->XferOperation != I2C_FIRST_AND_LAST_FRAME) {
marcozecchini 0:9fca2b23d0ba 606 i2c_init(obj, obj_s->sda, obj_s->scl);
marcozecchini 0:9fca2b23d0ba 607 }
marcozecchini 0:9fca2b23d0ba 608
marcozecchini 0:9fca2b23d0ba 609 return 0;
marcozecchini 0:9fca2b23d0ba 610 }
marcozecchini 0:9fca2b23d0ba 611
marcozecchini 0:9fca2b23d0ba 612 int i2c_byte_read(i2c_t *obj, int last) {
marcozecchini 0:9fca2b23d0ba 613 struct i2c_s *obj_s = I2C_S(obj);
marcozecchini 0:9fca2b23d0ba 614 I2C_HandleTypeDef *handle = &(obj_s->handle);
marcozecchini 0:9fca2b23d0ba 615 int timeout = FLAG_TIMEOUT;
marcozecchini 0:9fca2b23d0ba 616 uint32_t tmpreg = handle->Instance->CR2;
marcozecchini 0:9fca2b23d0ba 617 char data;
marcozecchini 0:9fca2b23d0ba 618 #if DEVICE_I2CSLAVE
marcozecchini 0:9fca2b23d0ba 619 if (obj_s->slave) {
marcozecchini 0:9fca2b23d0ba 620 return i2c_slave_read(obj, &data, 1);
marcozecchini 0:9fca2b23d0ba 621 }
marcozecchini 0:9fca2b23d0ba 622 #endif
marcozecchini 0:9fca2b23d0ba 623 /* Then send data when there's room in the TX fifo */
marcozecchini 0:9fca2b23d0ba 624 if ((tmpreg & I2C_CR2_RELOAD) != 0) {
marcozecchini 0:9fca2b23d0ba 625 while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_TCR)) {
marcozecchini 0:9fca2b23d0ba 626 if ((timeout--) == 0) {
marcozecchini 0:9fca2b23d0ba 627 DEBUG_PRINTF("timeout in byte_read\r\n");
marcozecchini 0:9fca2b23d0ba 628 return -1;
marcozecchini 0:9fca2b23d0ba 629 }
marcozecchini 0:9fca2b23d0ba 630 }
marcozecchini 0:9fca2b23d0ba 631 }
marcozecchini 0:9fca2b23d0ba 632
marcozecchini 0:9fca2b23d0ba 633 /* Enable reload mode as we don't know how many bytes will be sent */
marcozecchini 0:9fca2b23d0ba 634 /* and set transfer size to 1 */
marcozecchini 0:9fca2b23d0ba 635 tmpreg |= I2C_CR2_RELOAD | (I2C_CR2_NBYTES & (1 << 16));
marcozecchini 0:9fca2b23d0ba 636 /* Set the prepared configuration */
marcozecchini 0:9fca2b23d0ba 637 handle->Instance->CR2 = tmpreg;
marcozecchini 0:9fca2b23d0ba 638
marcozecchini 0:9fca2b23d0ba 639 timeout = FLAG_TIMEOUT;
marcozecchini 0:9fca2b23d0ba 640 while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_RXNE)) {
marcozecchini 0:9fca2b23d0ba 641 if ((timeout--) == 0) {
marcozecchini 0:9fca2b23d0ba 642 return -1;
marcozecchini 0:9fca2b23d0ba 643 }
marcozecchini 0:9fca2b23d0ba 644 }
marcozecchini 0:9fca2b23d0ba 645
marcozecchini 0:9fca2b23d0ba 646 /* Then Get Byte */
marcozecchini 0:9fca2b23d0ba 647 data = handle->Instance->RXDR;
marcozecchini 0:9fca2b23d0ba 648
marcozecchini 0:9fca2b23d0ba 649 if (last) {
marcozecchini 0:9fca2b23d0ba 650 /* Disable Address Acknowledge */
marcozecchini 0:9fca2b23d0ba 651 handle->Instance->CR2 |= I2C_CR2_NACK;
marcozecchini 0:9fca2b23d0ba 652 }
marcozecchini 0:9fca2b23d0ba 653
marcozecchini 0:9fca2b23d0ba 654 return data;
marcozecchini 0:9fca2b23d0ba 655 }
marcozecchini 0:9fca2b23d0ba 656
marcozecchini 0:9fca2b23d0ba 657 int i2c_byte_write(i2c_t *obj, int data) {
marcozecchini 0:9fca2b23d0ba 658 struct i2c_s *obj_s = I2C_S(obj);
marcozecchini 0:9fca2b23d0ba 659 I2C_HandleTypeDef *handle = &(obj_s->handle);
marcozecchini 0:9fca2b23d0ba 660 int timeout = FLAG_TIMEOUT;
marcozecchini 0:9fca2b23d0ba 661 uint32_t tmpreg = handle->Instance->CR2;
marcozecchini 0:9fca2b23d0ba 662 #if DEVICE_I2CSLAVE
marcozecchini 0:9fca2b23d0ba 663 if (obj_s->slave) {
marcozecchini 0:9fca2b23d0ba 664 return i2c_slave_write(obj, (char *) &data, 1);
marcozecchini 0:9fca2b23d0ba 665 }
marcozecchini 0:9fca2b23d0ba 666 #endif
marcozecchini 0:9fca2b23d0ba 667 if (obj_s->pending_start) {
marcozecchini 0:9fca2b23d0ba 668 obj_s->pending_start = 0;
marcozecchini 0:9fca2b23d0ba 669 //* First byte after the start is the address */
marcozecchini 0:9fca2b23d0ba 670 tmpreg |= (uint32_t)((uint32_t)data & I2C_CR2_SADD);
marcozecchini 0:9fca2b23d0ba 671 if (data & 0x01) {
marcozecchini 0:9fca2b23d0ba 672 tmpreg |= I2C_CR2_START | I2C_CR2_RD_WRN;
marcozecchini 0:9fca2b23d0ba 673 } else {
marcozecchini 0:9fca2b23d0ba 674 tmpreg |= I2C_CR2_START;
marcozecchini 0:9fca2b23d0ba 675 tmpreg &= ~I2C_CR2_RD_WRN;
marcozecchini 0:9fca2b23d0ba 676 }
marcozecchini 0:9fca2b23d0ba 677 /* Disable reload first to use it later */
marcozecchini 0:9fca2b23d0ba 678 tmpreg &= ~I2C_CR2_RELOAD;
marcozecchini 0:9fca2b23d0ba 679 /* Disable Autoend */
marcozecchini 0:9fca2b23d0ba 680 tmpreg &= ~I2C_CR2_AUTOEND;
marcozecchini 0:9fca2b23d0ba 681 /* Do not set any transfer size for now */
marcozecchini 0:9fca2b23d0ba 682 tmpreg |= (I2C_CR2_NBYTES & (1 << 16));
marcozecchini 0:9fca2b23d0ba 683 /* Set the prepared configuration */
marcozecchini 0:9fca2b23d0ba 684 handle->Instance->CR2 = tmpreg;
marcozecchini 0:9fca2b23d0ba 685 } else {
marcozecchini 0:9fca2b23d0ba 686 /* Set the prepared configuration */
marcozecchini 0:9fca2b23d0ba 687 tmpreg = handle->Instance->CR2;
marcozecchini 0:9fca2b23d0ba 688
marcozecchini 0:9fca2b23d0ba 689 /* Then send data when there's room in the TX fifo */
marcozecchini 0:9fca2b23d0ba 690 if ((tmpreg & I2C_CR2_RELOAD) != 0) {
marcozecchini 0:9fca2b23d0ba 691 while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_TCR)) {
marcozecchini 0:9fca2b23d0ba 692 if ((timeout--) == 0) {
marcozecchini 0:9fca2b23d0ba 693 DEBUG_PRINTF("timeout in byte_write\r\n");
marcozecchini 0:9fca2b23d0ba 694 return 2;
marcozecchini 0:9fca2b23d0ba 695 }
marcozecchini 0:9fca2b23d0ba 696 }
marcozecchini 0:9fca2b23d0ba 697 }
marcozecchini 0:9fca2b23d0ba 698 /* Enable reload mode as we don't know how many bytes will eb sent */
marcozecchini 0:9fca2b23d0ba 699 tmpreg |= I2C_CR2_RELOAD;
marcozecchini 0:9fca2b23d0ba 700 /* Set transfer size to 1 */
marcozecchini 0:9fca2b23d0ba 701 tmpreg |= (I2C_CR2_NBYTES & (1 << 16));
marcozecchini 0:9fca2b23d0ba 702 /* Set the prepared configuration */
marcozecchini 0:9fca2b23d0ba 703 handle->Instance->CR2 = tmpreg;
marcozecchini 0:9fca2b23d0ba 704 /* Prepare next write */
marcozecchini 0:9fca2b23d0ba 705 timeout = FLAG_TIMEOUT;
marcozecchini 0:9fca2b23d0ba 706 while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_TXE)) {
marcozecchini 0:9fca2b23d0ba 707 if ((timeout--) == 0) {
marcozecchini 0:9fca2b23d0ba 708 return 2;
marcozecchini 0:9fca2b23d0ba 709 }
marcozecchini 0:9fca2b23d0ba 710 }
marcozecchini 0:9fca2b23d0ba 711 /* Write byte */
marcozecchini 0:9fca2b23d0ba 712 handle->Instance->TXDR = data;
marcozecchini 0:9fca2b23d0ba 713 }
marcozecchini 0:9fca2b23d0ba 714
marcozecchini 0:9fca2b23d0ba 715 return 1;
marcozecchini 0:9fca2b23d0ba 716 }
marcozecchini 0:9fca2b23d0ba 717 #endif //I2C_IP_VERSION_V2
marcozecchini 0:9fca2b23d0ba 718
marcozecchini 0:9fca2b23d0ba 719 /*
marcozecchini 0:9fca2b23d0ba 720 * SYNC APIS
marcozecchini 0:9fca2b23d0ba 721 */
marcozecchini 0:9fca2b23d0ba 722 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
marcozecchini 0:9fca2b23d0ba 723 struct i2c_s *obj_s = I2C_S(obj);
marcozecchini 0:9fca2b23d0ba 724 I2C_HandleTypeDef *handle = &(obj_s->handle);
marcozecchini 0:9fca2b23d0ba 725 int count = I2C_ERROR_BUS_BUSY, ret = 0;
marcozecchini 0:9fca2b23d0ba 726 uint32_t timeout = 0;
marcozecchini 0:9fca2b23d0ba 727
marcozecchini 0:9fca2b23d0ba 728 // Trick to remove compiler warning "left and right operands are identical" in some cases
marcozecchini 0:9fca2b23d0ba 729 uint32_t op1 = I2C_FIRST_AND_LAST_FRAME;
marcozecchini 0:9fca2b23d0ba 730 uint32_t op2 = I2C_LAST_FRAME;
marcozecchini 0:9fca2b23d0ba 731 if ((obj_s->XferOperation == op1) || (obj_s->XferOperation == op2)) {
marcozecchini 0:9fca2b23d0ba 732 if (stop)
marcozecchini 0:9fca2b23d0ba 733 obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME;
marcozecchini 0:9fca2b23d0ba 734 else
marcozecchini 0:9fca2b23d0ba 735 obj_s->XferOperation = I2C_FIRST_FRAME;
marcozecchini 0:9fca2b23d0ba 736 } else if ((obj_s->XferOperation == I2C_FIRST_FRAME) ||
marcozecchini 0:9fca2b23d0ba 737 (obj_s->XferOperation == I2C_NEXT_FRAME)) {
marcozecchini 0:9fca2b23d0ba 738 if (stop)
marcozecchini 0:9fca2b23d0ba 739 obj_s->XferOperation = I2C_LAST_FRAME;
marcozecchini 0:9fca2b23d0ba 740 else
marcozecchini 0:9fca2b23d0ba 741 obj_s->XferOperation = I2C_NEXT_FRAME;
marcozecchini 0:9fca2b23d0ba 742 }
marcozecchini 0:9fca2b23d0ba 743
marcozecchini 0:9fca2b23d0ba 744 obj_s->event = 0;
marcozecchini 0:9fca2b23d0ba 745
marcozecchini 0:9fca2b23d0ba 746 /* Activate default IRQ handlers for sync mode
marcozecchini 0:9fca2b23d0ba 747 * which would be overwritten in async mode
marcozecchini 0:9fca2b23d0ba 748 */
marcozecchini 0:9fca2b23d0ba 749 i2c_ev_err_enable(obj, i2c_get_irq_handler(obj));
marcozecchini 0:9fca2b23d0ba 750
marcozecchini 0:9fca2b23d0ba 751 ret = HAL_I2C_Master_Sequential_Receive_IT(handle, address, (uint8_t *) data, length, obj_s->XferOperation);
marcozecchini 0:9fca2b23d0ba 752
marcozecchini 0:9fca2b23d0ba 753 if(ret == HAL_OK) {
marcozecchini 0:9fca2b23d0ba 754 timeout = BYTE_TIMEOUT_US * (length + 1);
marcozecchini 0:9fca2b23d0ba 755 /* transfer started : wait completion or timeout */
marcozecchini 0:9fca2b23d0ba 756 while(!(obj_s->event & I2C_EVENT_ALL) && (--timeout != 0)) {
marcozecchini 0:9fca2b23d0ba 757 wait_us(1);
marcozecchini 0:9fca2b23d0ba 758 }
marcozecchini 0:9fca2b23d0ba 759
marcozecchini 0:9fca2b23d0ba 760 i2c_ev_err_disable(obj);
marcozecchini 0:9fca2b23d0ba 761
marcozecchini 0:9fca2b23d0ba 762 if((timeout == 0) || (obj_s->event != I2C_EVENT_TRANSFER_COMPLETE)) {
marcozecchini 0:9fca2b23d0ba 763 DEBUG_PRINTF(" TIMEOUT or error in i2c_read\r\n");
marcozecchini 0:9fca2b23d0ba 764 /* re-init IP to try and get back in a working state */
marcozecchini 0:9fca2b23d0ba 765 i2c_init(obj, obj_s->sda, obj_s->scl);
marcozecchini 0:9fca2b23d0ba 766 } else {
marcozecchini 0:9fca2b23d0ba 767 count = length;
marcozecchini 0:9fca2b23d0ba 768 }
marcozecchini 0:9fca2b23d0ba 769 } else {
marcozecchini 0:9fca2b23d0ba 770 DEBUG_PRINTF("ERROR in i2c_read:%d\r\n", ret);
marcozecchini 0:9fca2b23d0ba 771 }
marcozecchini 0:9fca2b23d0ba 772
marcozecchini 0:9fca2b23d0ba 773 return count;
marcozecchini 0:9fca2b23d0ba 774 }
marcozecchini 0:9fca2b23d0ba 775
marcozecchini 0:9fca2b23d0ba 776 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
marcozecchini 0:9fca2b23d0ba 777 struct i2c_s *obj_s = I2C_S(obj);
marcozecchini 0:9fca2b23d0ba 778 I2C_HandleTypeDef *handle = &(obj_s->handle);
marcozecchini 0:9fca2b23d0ba 779 int count = I2C_ERROR_BUS_BUSY, ret = 0;
marcozecchini 0:9fca2b23d0ba 780 uint32_t timeout = 0;
marcozecchini 0:9fca2b23d0ba 781
marcozecchini 0:9fca2b23d0ba 782 // Trick to remove compiler warning "left and right operands are identical" in some cases
marcozecchini 0:9fca2b23d0ba 783 uint32_t op1 = I2C_FIRST_AND_LAST_FRAME;
marcozecchini 0:9fca2b23d0ba 784 uint32_t op2 = I2C_LAST_FRAME;
marcozecchini 0:9fca2b23d0ba 785 if ((obj_s->XferOperation == op1) || (obj_s->XferOperation == op2)) {
marcozecchini 0:9fca2b23d0ba 786 if (stop)
marcozecchini 0:9fca2b23d0ba 787 obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME;
marcozecchini 0:9fca2b23d0ba 788 else
marcozecchini 0:9fca2b23d0ba 789 obj_s->XferOperation = I2C_FIRST_FRAME;
marcozecchini 0:9fca2b23d0ba 790 } else if ((obj_s->XferOperation == I2C_FIRST_FRAME) ||
marcozecchini 0:9fca2b23d0ba 791 (obj_s->XferOperation == I2C_NEXT_FRAME)) {
marcozecchini 0:9fca2b23d0ba 792 if (stop)
marcozecchini 0:9fca2b23d0ba 793 obj_s->XferOperation = I2C_LAST_FRAME;
marcozecchini 0:9fca2b23d0ba 794 else
marcozecchini 0:9fca2b23d0ba 795 obj_s->XferOperation = I2C_NEXT_FRAME;
marcozecchini 0:9fca2b23d0ba 796 }
marcozecchini 0:9fca2b23d0ba 797
marcozecchini 0:9fca2b23d0ba 798 obj_s->event = 0;
marcozecchini 0:9fca2b23d0ba 799
marcozecchini 0:9fca2b23d0ba 800 i2c_ev_err_enable(obj, i2c_get_irq_handler(obj));
marcozecchini 0:9fca2b23d0ba 801
marcozecchini 0:9fca2b23d0ba 802 ret = HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t *) data, length, obj_s->XferOperation);
marcozecchini 0:9fca2b23d0ba 803
marcozecchini 0:9fca2b23d0ba 804 if(ret == HAL_OK) {
marcozecchini 0:9fca2b23d0ba 805 timeout = BYTE_TIMEOUT_US * (length + 1);
marcozecchini 0:9fca2b23d0ba 806 /* transfer started : wait completion or timeout */
marcozecchini 0:9fca2b23d0ba 807 while(!(obj_s->event & I2C_EVENT_ALL) && (--timeout != 0)) {
marcozecchini 0:9fca2b23d0ba 808 wait_us(1);
marcozecchini 0:9fca2b23d0ba 809 }
marcozecchini 0:9fca2b23d0ba 810
marcozecchini 0:9fca2b23d0ba 811 i2c_ev_err_disable(obj);
marcozecchini 0:9fca2b23d0ba 812
marcozecchini 0:9fca2b23d0ba 813 if((timeout == 0) || (obj_s->event != I2C_EVENT_TRANSFER_COMPLETE)) {
marcozecchini 0:9fca2b23d0ba 814 DEBUG_PRINTF(" TIMEOUT or error in i2c_write\r\n");
marcozecchini 0:9fca2b23d0ba 815 /* re-init IP to try and get back in a working state */
marcozecchini 0:9fca2b23d0ba 816 i2c_init(obj, obj_s->sda, obj_s->scl);
marcozecchini 0:9fca2b23d0ba 817 } else {
marcozecchini 0:9fca2b23d0ba 818 count = length;
marcozecchini 0:9fca2b23d0ba 819 }
marcozecchini 0:9fca2b23d0ba 820 } else {
marcozecchini 0:9fca2b23d0ba 821 DEBUG_PRINTF("ERROR in i2c_read\r\n");
marcozecchini 0:9fca2b23d0ba 822 }
marcozecchini 0:9fca2b23d0ba 823
marcozecchini 0:9fca2b23d0ba 824 return count;
marcozecchini 0:9fca2b23d0ba 825 }
marcozecchini 0:9fca2b23d0ba 826
marcozecchini 0:9fca2b23d0ba 827 void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c){
marcozecchini 0:9fca2b23d0ba 828 /* Get object ptr based on handler ptr */
marcozecchini 0:9fca2b23d0ba 829 i2c_t *obj = get_i2c_obj(hi2c);
marcozecchini 0:9fca2b23d0ba 830 struct i2c_s *obj_s = I2C_S(obj);
marcozecchini 0:9fca2b23d0ba 831
marcozecchini 0:9fca2b23d0ba 832 #if DEVICE_I2C_ASYNCH
marcozecchini 0:9fca2b23d0ba 833 /* Handle potential Tx/Rx use case */
marcozecchini 0:9fca2b23d0ba 834 if ((obj->tx_buff.length) && (obj->rx_buff.length)) {
marcozecchini 0:9fca2b23d0ba 835 if (obj_s->stop) {
marcozecchini 0:9fca2b23d0ba 836 obj_s->XferOperation = I2C_LAST_FRAME;
marcozecchini 0:9fca2b23d0ba 837 } else {
marcozecchini 0:9fca2b23d0ba 838 obj_s->XferOperation = I2C_NEXT_FRAME;
marcozecchini 0:9fca2b23d0ba 839 }
marcozecchini 0:9fca2b23d0ba 840
marcozecchini 0:9fca2b23d0ba 841 HAL_I2C_Master_Sequential_Receive_IT(hi2c, obj_s->address, (uint8_t*)obj->rx_buff.buffer , obj->rx_buff.length, obj_s->XferOperation);
marcozecchini 0:9fca2b23d0ba 842 }
marcozecchini 0:9fca2b23d0ba 843 else
marcozecchini 0:9fca2b23d0ba 844 #endif
marcozecchini 0:9fca2b23d0ba 845 {
marcozecchini 0:9fca2b23d0ba 846 /* Set event flag */
marcozecchini 0:9fca2b23d0ba 847 obj_s->event = I2C_EVENT_TRANSFER_COMPLETE;
marcozecchini 0:9fca2b23d0ba 848 }
marcozecchini 0:9fca2b23d0ba 849 }
marcozecchini 0:9fca2b23d0ba 850
marcozecchini 0:9fca2b23d0ba 851 void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c){
marcozecchini 0:9fca2b23d0ba 852 /* Get object ptr based on handler ptr */
marcozecchini 0:9fca2b23d0ba 853 i2c_t *obj = get_i2c_obj(hi2c);
marcozecchini 0:9fca2b23d0ba 854 struct i2c_s *obj_s = I2C_S(obj);
marcozecchini 0:9fca2b23d0ba 855
marcozecchini 0:9fca2b23d0ba 856 /* Set event flag */
marcozecchini 0:9fca2b23d0ba 857 obj_s->event = I2C_EVENT_TRANSFER_COMPLETE;
marcozecchini 0:9fca2b23d0ba 858 }
marcozecchini 0:9fca2b23d0ba 859
marcozecchini 0:9fca2b23d0ba 860 void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c){
marcozecchini 0:9fca2b23d0ba 861 /* Get object ptr based on handler ptr */
marcozecchini 0:9fca2b23d0ba 862 i2c_t *obj = get_i2c_obj(hi2c);
marcozecchini 0:9fca2b23d0ba 863 struct i2c_s *obj_s = I2C_S(obj);
marcozecchini 0:9fca2b23d0ba 864 #if DEVICE_I2CSLAVE
marcozecchini 0:9fca2b23d0ba 865 I2C_HandleTypeDef *handle = &(obj_s->handle);
marcozecchini 0:9fca2b23d0ba 866 uint32_t address = 0;
marcozecchini 0:9fca2b23d0ba 867 /* Store address to handle it after reset */
marcozecchini 0:9fca2b23d0ba 868 if(obj_s->slave)
marcozecchini 0:9fca2b23d0ba 869 address = handle->Init.OwnAddress1;
marcozecchini 0:9fca2b23d0ba 870 #endif
marcozecchini 0:9fca2b23d0ba 871
marcozecchini 0:9fca2b23d0ba 872 DEBUG_PRINTF("HAL_I2C_ErrorCallback:%d, index=%d\r\n", (int) hi2c->ErrorCode, obj_s->index);
marcozecchini 0:9fca2b23d0ba 873
marcozecchini 0:9fca2b23d0ba 874 /* re-init IP to try and get back in a working state */
marcozecchini 0:9fca2b23d0ba 875 i2c_init(obj, obj_s->sda, obj_s->scl);
marcozecchini 0:9fca2b23d0ba 876
marcozecchini 0:9fca2b23d0ba 877 #if DEVICE_I2CSLAVE
marcozecchini 0:9fca2b23d0ba 878 /* restore slave address */
marcozecchini 0:9fca2b23d0ba 879 if (address != 0) {
marcozecchini 0:9fca2b23d0ba 880 obj_s->slave = 1;
marcozecchini 0:9fca2b23d0ba 881 i2c_slave_address(obj, 0, address, 0);
marcozecchini 0:9fca2b23d0ba 882 }
marcozecchini 0:9fca2b23d0ba 883 #endif
marcozecchini 0:9fca2b23d0ba 884
marcozecchini 0:9fca2b23d0ba 885 /* Keep Set event flag */
marcozecchini 0:9fca2b23d0ba 886 obj_s->event = I2C_EVENT_ERROR;
marcozecchini 0:9fca2b23d0ba 887 }
marcozecchini 0:9fca2b23d0ba 888
marcozecchini 0:9fca2b23d0ba 889 #if DEVICE_I2CSLAVE
marcozecchini 0:9fca2b23d0ba 890 /* SLAVE API FUNCTIONS */
marcozecchini 0:9fca2b23d0ba 891 void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
marcozecchini 0:9fca2b23d0ba 892 struct i2c_s *obj_s = I2C_S(obj);
marcozecchini 0:9fca2b23d0ba 893 I2C_HandleTypeDef *handle = &(obj_s->handle);
marcozecchini 0:9fca2b23d0ba 894
marcozecchini 0:9fca2b23d0ba 895 // I2C configuration
marcozecchini 0:9fca2b23d0ba 896 handle->Init.OwnAddress1 = address;
marcozecchini 0:9fca2b23d0ba 897 HAL_I2C_Init(handle);
marcozecchini 0:9fca2b23d0ba 898
marcozecchini 0:9fca2b23d0ba 899 i2c_ev_err_enable(obj, i2c_get_irq_handler(obj));
marcozecchini 0:9fca2b23d0ba 900
marcozecchini 0:9fca2b23d0ba 901 HAL_I2C_EnableListen_IT(handle);
marcozecchini 0:9fca2b23d0ba 902 }
marcozecchini 0:9fca2b23d0ba 903
marcozecchini 0:9fca2b23d0ba 904 void i2c_slave_mode(i2c_t *obj, int enable_slave) {
marcozecchini 0:9fca2b23d0ba 905
marcozecchini 0:9fca2b23d0ba 906 struct i2c_s *obj_s = I2C_S(obj);
marcozecchini 0:9fca2b23d0ba 907 I2C_HandleTypeDef *handle = &(obj_s->handle);
marcozecchini 0:9fca2b23d0ba 908
marcozecchini 0:9fca2b23d0ba 909 if (enable_slave) {
marcozecchini 0:9fca2b23d0ba 910 obj_s->slave = 1;
marcozecchini 0:9fca2b23d0ba 911 HAL_I2C_EnableListen_IT(handle);
marcozecchini 0:9fca2b23d0ba 912 } else {
marcozecchini 0:9fca2b23d0ba 913 obj_s->slave = 0;
marcozecchini 0:9fca2b23d0ba 914 HAL_I2C_DisableListen_IT(handle);
marcozecchini 0:9fca2b23d0ba 915 }
marcozecchini 0:9fca2b23d0ba 916 }
marcozecchini 0:9fca2b23d0ba 917
marcozecchini 0:9fca2b23d0ba 918 // See I2CSlave.h
marcozecchini 0:9fca2b23d0ba 919 #define NoData 0 // the slave has not been addressed
marcozecchini 0:9fca2b23d0ba 920 #define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter)
marcozecchini 0:9fca2b23d0ba 921 #define WriteGeneral 2 // the master is writing to all slave
marcozecchini 0:9fca2b23d0ba 922 #define WriteAddressed 3 // the master is writing to this slave (slave = receiver)
marcozecchini 0:9fca2b23d0ba 923
marcozecchini 0:9fca2b23d0ba 924
marcozecchini 0:9fca2b23d0ba 925 void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) {
marcozecchini 0:9fca2b23d0ba 926 /* Get object ptr based on handler ptr */
marcozecchini 0:9fca2b23d0ba 927 i2c_t *obj = get_i2c_obj(hi2c);
marcozecchini 0:9fca2b23d0ba 928 struct i2c_s *obj_s = I2C_S(obj);
marcozecchini 0:9fca2b23d0ba 929
marcozecchini 0:9fca2b23d0ba 930 /* Transfer direction in HAL is from Master point of view */
marcozecchini 0:9fca2b23d0ba 931 if(TransferDirection == I2C_DIRECTION_RECEIVE) {
marcozecchini 0:9fca2b23d0ba 932 obj_s->pending_slave_tx_master_rx = 1;
marcozecchini 0:9fca2b23d0ba 933 }
marcozecchini 0:9fca2b23d0ba 934
marcozecchini 0:9fca2b23d0ba 935 if(TransferDirection == I2C_DIRECTION_TRANSMIT) {
marcozecchini 0:9fca2b23d0ba 936 obj_s->pending_slave_rx_maxter_tx = 1;
marcozecchini 0:9fca2b23d0ba 937 }
marcozecchini 0:9fca2b23d0ba 938 }
marcozecchini 0:9fca2b23d0ba 939
marcozecchini 0:9fca2b23d0ba 940 void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *I2cHandle){
marcozecchini 0:9fca2b23d0ba 941 /* Get object ptr based on handler ptr */
marcozecchini 0:9fca2b23d0ba 942 i2c_t *obj = get_i2c_obj(I2cHandle);
marcozecchini 0:9fca2b23d0ba 943 struct i2c_s *obj_s = I2C_S(obj);
marcozecchini 0:9fca2b23d0ba 944 obj_s->pending_slave_tx_master_rx = 0;
marcozecchini 0:9fca2b23d0ba 945 }
marcozecchini 0:9fca2b23d0ba 946
marcozecchini 0:9fca2b23d0ba 947 void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *I2cHandle){
marcozecchini 0:9fca2b23d0ba 948 /* Get object ptr based on handler ptr */
marcozecchini 0:9fca2b23d0ba 949 i2c_t *obj = get_i2c_obj(I2cHandle);
marcozecchini 0:9fca2b23d0ba 950 struct i2c_s *obj_s = I2C_S(obj);
marcozecchini 0:9fca2b23d0ba 951 obj_s->pending_slave_rx_maxter_tx = 0;
marcozecchini 0:9fca2b23d0ba 952 }
marcozecchini 0:9fca2b23d0ba 953
marcozecchini 0:9fca2b23d0ba 954 void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
marcozecchini 0:9fca2b23d0ba 955 {
marcozecchini 0:9fca2b23d0ba 956 /* restart listening for master requests */
marcozecchini 0:9fca2b23d0ba 957 HAL_I2C_EnableListen_IT(hi2c);
marcozecchini 0:9fca2b23d0ba 958 }
marcozecchini 0:9fca2b23d0ba 959
marcozecchini 0:9fca2b23d0ba 960 int i2c_slave_receive(i2c_t *obj) {
marcozecchini 0:9fca2b23d0ba 961
marcozecchini 0:9fca2b23d0ba 962 struct i2c_s *obj_s = I2C_S(obj);
marcozecchini 0:9fca2b23d0ba 963 int retValue = NoData;
marcozecchini 0:9fca2b23d0ba 964
marcozecchini 0:9fca2b23d0ba 965 if(obj_s->pending_slave_rx_maxter_tx) {
marcozecchini 0:9fca2b23d0ba 966 retValue = WriteAddressed;
marcozecchini 0:9fca2b23d0ba 967 }
marcozecchini 0:9fca2b23d0ba 968
marcozecchini 0:9fca2b23d0ba 969 if(obj_s->pending_slave_tx_master_rx) {
marcozecchini 0:9fca2b23d0ba 970 retValue = ReadAddressed;
marcozecchini 0:9fca2b23d0ba 971 }
marcozecchini 0:9fca2b23d0ba 972
marcozecchini 0:9fca2b23d0ba 973 return (retValue);
marcozecchini 0:9fca2b23d0ba 974 }
marcozecchini 0:9fca2b23d0ba 975
marcozecchini 0:9fca2b23d0ba 976 int i2c_slave_read(i2c_t *obj, char *data, int length) {
marcozecchini 0:9fca2b23d0ba 977 struct i2c_s *obj_s = I2C_S(obj);
marcozecchini 0:9fca2b23d0ba 978 I2C_HandleTypeDef *handle = &(obj_s->handle);
marcozecchini 0:9fca2b23d0ba 979 int count = 0;
marcozecchini 0:9fca2b23d0ba 980 int ret = 0;
marcozecchini 0:9fca2b23d0ba 981 uint32_t timeout = 0;
marcozecchini 0:9fca2b23d0ba 982
marcozecchini 0:9fca2b23d0ba 983 /* Always use I2C_NEXT_FRAME as slave will just adapt to master requests */
marcozecchini 0:9fca2b23d0ba 984 ret = HAL_I2C_Slave_Sequential_Receive_IT(handle, (uint8_t *) data, length, I2C_NEXT_FRAME);
marcozecchini 0:9fca2b23d0ba 985
marcozecchini 0:9fca2b23d0ba 986 if(ret == HAL_OK) {
marcozecchini 0:9fca2b23d0ba 987 timeout = BYTE_TIMEOUT_US * (length + 1);
marcozecchini 0:9fca2b23d0ba 988 while(obj_s->pending_slave_rx_maxter_tx && (--timeout != 0)) {
marcozecchini 0:9fca2b23d0ba 989 wait_us(1);
marcozecchini 0:9fca2b23d0ba 990 }
marcozecchini 0:9fca2b23d0ba 991
marcozecchini 0:9fca2b23d0ba 992 if(timeout != 0) {
marcozecchini 0:9fca2b23d0ba 993 count = length;
marcozecchini 0:9fca2b23d0ba 994 } else {
marcozecchini 0:9fca2b23d0ba 995 DEBUG_PRINTF("TIMEOUT or error in i2c_slave_read\r\n");
marcozecchini 0:9fca2b23d0ba 996 }
marcozecchini 0:9fca2b23d0ba 997 }
marcozecchini 0:9fca2b23d0ba 998 return count;
marcozecchini 0:9fca2b23d0ba 999 }
marcozecchini 0:9fca2b23d0ba 1000
marcozecchini 0:9fca2b23d0ba 1001 int i2c_slave_write(i2c_t *obj, const char *data, int length) {
marcozecchini 0:9fca2b23d0ba 1002 struct i2c_s *obj_s = I2C_S(obj);
marcozecchini 0:9fca2b23d0ba 1003 I2C_HandleTypeDef *handle = &(obj_s->handle);
marcozecchini 0:9fca2b23d0ba 1004 int count = 0;
marcozecchini 0:9fca2b23d0ba 1005 int ret = 0;
marcozecchini 0:9fca2b23d0ba 1006 uint32_t timeout = 0;
marcozecchini 0:9fca2b23d0ba 1007
marcozecchini 0:9fca2b23d0ba 1008 /* Always use I2C_NEXT_FRAME as slave will just adapt to master requests */
marcozecchini 0:9fca2b23d0ba 1009 ret = HAL_I2C_Slave_Sequential_Transmit_IT(handle, (uint8_t *) data, length, I2C_NEXT_FRAME);
marcozecchini 0:9fca2b23d0ba 1010
marcozecchini 0:9fca2b23d0ba 1011 if(ret == HAL_OK) {
marcozecchini 0:9fca2b23d0ba 1012 timeout = BYTE_TIMEOUT_US * (length + 1);
marcozecchini 0:9fca2b23d0ba 1013 while(obj_s->pending_slave_tx_master_rx && (--timeout != 0)) {
marcozecchini 0:9fca2b23d0ba 1014 wait_us(1);
marcozecchini 0:9fca2b23d0ba 1015 }
marcozecchini 0:9fca2b23d0ba 1016
marcozecchini 0:9fca2b23d0ba 1017 if(timeout != 0) {
marcozecchini 0:9fca2b23d0ba 1018 count = length;
marcozecchini 0:9fca2b23d0ba 1019 } else {
marcozecchini 0:9fca2b23d0ba 1020 DEBUG_PRINTF("TIMEOUT or error in i2c_slave_write\r\n");
marcozecchini 0:9fca2b23d0ba 1021 }
marcozecchini 0:9fca2b23d0ba 1022 }
marcozecchini 0:9fca2b23d0ba 1023
marcozecchini 0:9fca2b23d0ba 1024 return count;
marcozecchini 0:9fca2b23d0ba 1025 }
marcozecchini 0:9fca2b23d0ba 1026 #endif // DEVICE_I2CSLAVE
marcozecchini 0:9fca2b23d0ba 1027
marcozecchini 0:9fca2b23d0ba 1028 #if DEVICE_I2C_ASYNCH
marcozecchini 0:9fca2b23d0ba 1029 /* ASYNCH MASTER API FUNCTIONS */
marcozecchini 0:9fca2b23d0ba 1030 void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c){
marcozecchini 0:9fca2b23d0ba 1031 /* Get object ptr based on handler ptr */
marcozecchini 0:9fca2b23d0ba 1032 i2c_t *obj = get_i2c_obj(hi2c);
marcozecchini 0:9fca2b23d0ba 1033 struct i2c_s *obj_s = I2C_S(obj);
marcozecchini 0:9fca2b23d0ba 1034 I2C_HandleTypeDef *handle = &(obj_s->handle);
marcozecchini 0:9fca2b23d0ba 1035
marcozecchini 0:9fca2b23d0ba 1036 /* Disable IT. Not always done before calling macro */
marcozecchini 0:9fca2b23d0ba 1037 __HAL_I2C_DISABLE_IT(handle, I2C_IT_ALL);
marcozecchini 0:9fca2b23d0ba 1038 i2c_ev_err_disable(obj);
marcozecchini 0:9fca2b23d0ba 1039
marcozecchini 0:9fca2b23d0ba 1040 /* Set event flag */
marcozecchini 0:9fca2b23d0ba 1041 obj_s->event = I2C_EVENT_ERROR;
marcozecchini 0:9fca2b23d0ba 1042 }
marcozecchini 0:9fca2b23d0ba 1043
marcozecchini 0:9fca2b23d0ba 1044 void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint) {
marcozecchini 0:9fca2b23d0ba 1045
marcozecchini 0:9fca2b23d0ba 1046 // TODO: DMA usage is currently ignored by this way
marcozecchini 0:9fca2b23d0ba 1047 (void) hint;
marcozecchini 0:9fca2b23d0ba 1048
marcozecchini 0:9fca2b23d0ba 1049 struct i2c_s *obj_s = I2C_S(obj);
marcozecchini 0:9fca2b23d0ba 1050 I2C_HandleTypeDef *handle = &(obj_s->handle);
marcozecchini 0:9fca2b23d0ba 1051
marcozecchini 0:9fca2b23d0ba 1052 /* Update object */
marcozecchini 0:9fca2b23d0ba 1053 obj->tx_buff.buffer = (void *)tx;
marcozecchini 0:9fca2b23d0ba 1054 obj->tx_buff.length = tx_length;
marcozecchini 0:9fca2b23d0ba 1055 obj->tx_buff.pos = 0;
marcozecchini 0:9fca2b23d0ba 1056 obj->tx_buff.width = 8;
marcozecchini 0:9fca2b23d0ba 1057
marcozecchini 0:9fca2b23d0ba 1058 obj->rx_buff.buffer = (void *)rx;
marcozecchini 0:9fca2b23d0ba 1059 obj->rx_buff.length = rx_length;
marcozecchini 0:9fca2b23d0ba 1060 obj->rx_buff.pos = SIZE_MAX;
marcozecchini 0:9fca2b23d0ba 1061 obj->rx_buff.width = 8;
marcozecchini 0:9fca2b23d0ba 1062
marcozecchini 0:9fca2b23d0ba 1063 obj_s->available_events = event;
marcozecchini 0:9fca2b23d0ba 1064 obj_s->event = 0;
marcozecchini 0:9fca2b23d0ba 1065 obj_s->address = address;
marcozecchini 0:9fca2b23d0ba 1066 obj_s->stop = stop;
marcozecchini 0:9fca2b23d0ba 1067
marcozecchini 0:9fca2b23d0ba 1068 i2c_ev_err_enable(obj, handler);
marcozecchini 0:9fca2b23d0ba 1069
marcozecchini 0:9fca2b23d0ba 1070 /* Set operation step depending if stop sending required or not */
marcozecchini 0:9fca2b23d0ba 1071 if ((tx_length && !rx_length) || (!tx_length && rx_length)) {
marcozecchini 0:9fca2b23d0ba 1072 // Trick to remove compiler warning "left and right operands are identical" in some cases
marcozecchini 0:9fca2b23d0ba 1073 uint32_t op1 = I2C_FIRST_AND_LAST_FRAME;
marcozecchini 0:9fca2b23d0ba 1074 uint32_t op2 = I2C_LAST_FRAME;
marcozecchini 0:9fca2b23d0ba 1075 if ((obj_s->XferOperation == op1) || (obj_s->XferOperation == op2)) {
marcozecchini 0:9fca2b23d0ba 1076 if (stop)
marcozecchini 0:9fca2b23d0ba 1077 obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME;
marcozecchini 0:9fca2b23d0ba 1078 else
marcozecchini 0:9fca2b23d0ba 1079 obj_s->XferOperation = I2C_FIRST_FRAME;
marcozecchini 0:9fca2b23d0ba 1080 } else if ((obj_s->XferOperation == I2C_FIRST_FRAME) ||
marcozecchini 0:9fca2b23d0ba 1081 (obj_s->XferOperation == I2C_NEXT_FRAME)) {
marcozecchini 0:9fca2b23d0ba 1082 if (stop)
marcozecchini 0:9fca2b23d0ba 1083 obj_s->XferOperation = I2C_LAST_FRAME;
marcozecchini 0:9fca2b23d0ba 1084 else
marcozecchini 0:9fca2b23d0ba 1085 obj_s->XferOperation = I2C_NEXT_FRAME;
marcozecchini 0:9fca2b23d0ba 1086 }
marcozecchini 0:9fca2b23d0ba 1087
marcozecchini 0:9fca2b23d0ba 1088 if (tx_length > 0) {
marcozecchini 0:9fca2b23d0ba 1089 HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t*)tx, tx_length, obj_s->XferOperation);
marcozecchini 0:9fca2b23d0ba 1090 }
marcozecchini 0:9fca2b23d0ba 1091 if (rx_length > 0) {
marcozecchini 0:9fca2b23d0ba 1092 HAL_I2C_Master_Sequential_Receive_IT(handle, address, (uint8_t*)rx, rx_length, obj_s->XferOperation);
marcozecchini 0:9fca2b23d0ba 1093 }
marcozecchini 0:9fca2b23d0ba 1094 }
marcozecchini 0:9fca2b23d0ba 1095 else if (tx_length && rx_length) {
marcozecchini 0:9fca2b23d0ba 1096 /* Two steps operation, don't modify XferOperation, keep it for next step */
marcozecchini 0:9fca2b23d0ba 1097 // Trick to remove compiler warning "left and right operands are identical" in some cases
marcozecchini 0:9fca2b23d0ba 1098 uint32_t op1 = I2C_FIRST_AND_LAST_FRAME;
marcozecchini 0:9fca2b23d0ba 1099 uint32_t op2 = I2C_LAST_FRAME;
marcozecchini 0:9fca2b23d0ba 1100 if ((obj_s->XferOperation == op1) || (obj_s->XferOperation == op2)) {
marcozecchini 0:9fca2b23d0ba 1101 HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t*)tx, tx_length, I2C_FIRST_FRAME);
marcozecchini 0:9fca2b23d0ba 1102 } else if ((obj_s->XferOperation == I2C_FIRST_FRAME) ||
marcozecchini 0:9fca2b23d0ba 1103 (obj_s->XferOperation == I2C_NEXT_FRAME)) {
marcozecchini 0:9fca2b23d0ba 1104 HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t*)tx, tx_length, I2C_NEXT_FRAME);
marcozecchini 0:9fca2b23d0ba 1105 }
marcozecchini 0:9fca2b23d0ba 1106 }
marcozecchini 0:9fca2b23d0ba 1107 }
marcozecchini 0:9fca2b23d0ba 1108
marcozecchini 0:9fca2b23d0ba 1109
marcozecchini 0:9fca2b23d0ba 1110 uint32_t i2c_irq_handler_asynch(i2c_t *obj) {
marcozecchini 0:9fca2b23d0ba 1111
marcozecchini 0:9fca2b23d0ba 1112 struct i2c_s *obj_s = I2C_S(obj);
marcozecchini 0:9fca2b23d0ba 1113 I2C_HandleTypeDef *handle = &(obj_s->handle);
marcozecchini 0:9fca2b23d0ba 1114
marcozecchini 0:9fca2b23d0ba 1115 HAL_I2C_EV_IRQHandler(handle);
marcozecchini 0:9fca2b23d0ba 1116 HAL_I2C_ER_IRQHandler(handle);
marcozecchini 0:9fca2b23d0ba 1117
marcozecchini 0:9fca2b23d0ba 1118 /* Return I2C event status */
marcozecchini 0:9fca2b23d0ba 1119 return (obj_s->event & obj_s->available_events);
marcozecchini 0:9fca2b23d0ba 1120 }
marcozecchini 0:9fca2b23d0ba 1121
marcozecchini 0:9fca2b23d0ba 1122 uint8_t i2c_active(i2c_t *obj) {
marcozecchini 0:9fca2b23d0ba 1123
marcozecchini 0:9fca2b23d0ba 1124 struct i2c_s *obj_s = I2C_S(obj);
marcozecchini 0:9fca2b23d0ba 1125 I2C_HandleTypeDef *handle = &(obj_s->handle);
marcozecchini 0:9fca2b23d0ba 1126
marcozecchini 0:9fca2b23d0ba 1127 if (handle->State == HAL_I2C_STATE_READY) {
marcozecchini 0:9fca2b23d0ba 1128 return 0;
marcozecchini 0:9fca2b23d0ba 1129 }
marcozecchini 0:9fca2b23d0ba 1130 else {
marcozecchini 0:9fca2b23d0ba 1131 return 1;
marcozecchini 0:9fca2b23d0ba 1132 }
marcozecchini 0:9fca2b23d0ba 1133 }
marcozecchini 0:9fca2b23d0ba 1134
marcozecchini 0:9fca2b23d0ba 1135 void i2c_abort_asynch(i2c_t *obj) {
marcozecchini 0:9fca2b23d0ba 1136
marcozecchini 0:9fca2b23d0ba 1137 struct i2c_s *obj_s = I2C_S(obj);
marcozecchini 0:9fca2b23d0ba 1138 I2C_HandleTypeDef *handle = &(obj_s->handle);
marcozecchini 0:9fca2b23d0ba 1139
marcozecchini 0:9fca2b23d0ba 1140 /* Abort HAL requires DevAddress, but is not used. Use Dummy */
marcozecchini 0:9fca2b23d0ba 1141 uint16_t Dummy_DevAddress = 0x00;
marcozecchini 0:9fca2b23d0ba 1142
marcozecchini 0:9fca2b23d0ba 1143 HAL_I2C_Master_Abort_IT(handle, Dummy_DevAddress);
marcozecchini 0:9fca2b23d0ba 1144 }
marcozecchini 0:9fca2b23d0ba 1145
marcozecchini 0:9fca2b23d0ba 1146 #endif // DEVICE_I2C_ASYNCH
marcozecchini 0:9fca2b23d0ba 1147
marcozecchini 0:9fca2b23d0ba 1148 #endif // DEVICE_I2C