Marco Zecchini / Mbed OS Example_RTOS

Rtos API example

mbed-os/targets/TARGET_STM/can_api.c@0:9fca2b23d0ba, 2019-02-23 (annotated)

Committer:
marcozecchini
Date:
Sat Feb 23 12:13:36 2019 +0000
Revision:
0:9fca2b23d0ba
final commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
marcozecchini 0:9fca2b23d0ba 1 /* mbed Microcontroller Library
marcozecchini 0:9fca2b23d0ba 2 * Copyright (c) 2006-2017 ARM Limited
marcozecchini 0:9fca2b23d0ba 3 *
marcozecchini 0:9fca2b23d0ba 4 * Licensed under the Apache License, Version 2.0 (the "License");
marcozecchini 0:9fca2b23d0ba 5 * you may not use this file except in compliance with the License.
marcozecchini 0:9fca2b23d0ba 6 * You may obtain a copy of the License at
marcozecchini 0:9fca2b23d0ba 7 *
marcozecchini 0:9fca2b23d0ba 8 * http://www.apache.org/licenses/LICENSE-2.0
marcozecchini 0:9fca2b23d0ba 9 *
marcozecchini 0:9fca2b23d0ba 10 * Unless required by applicable law or agreed to in writing, software
marcozecchini 0:9fca2b23d0ba 11 * distributed under the License is distributed on an "AS IS" BASIS,
marcozecchini 0:9fca2b23d0ba 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
marcozecchini 0:9fca2b23d0ba 13 * See the License for the specific language governing permissions and
marcozecchini 0:9fca2b23d0ba 14 * limitations under the License.
marcozecchini 0:9fca2b23d0ba 15 */
marcozecchini 0:9fca2b23d0ba 16 #include "can_api.h"
marcozecchini 0:9fca2b23d0ba 17
marcozecchini 0:9fca2b23d0ba 18 #if DEVICE_CAN
marcozecchini 0:9fca2b23d0ba 19
marcozecchini 0:9fca2b23d0ba 20 #include "cmsis.h"
marcozecchini 0:9fca2b23d0ba 21 #include "pinmap.h"
marcozecchini 0:9fca2b23d0ba 22 #include "PeripheralPins.h"
marcozecchini 0:9fca2b23d0ba 23 #include "mbed_error.h"
marcozecchini 0:9fca2b23d0ba 24 #include "can_device.h" // Specific to STM32 serie
marcozecchini 0:9fca2b23d0ba 25 #include <math.h>
marcozecchini 0:9fca2b23d0ba 26 #include <string.h>
marcozecchini 0:9fca2b23d0ba 27
marcozecchini 0:9fca2b23d0ba 28 static uint32_t can_irq_ids[CAN_NUM] = {0};
marcozecchini 0:9fca2b23d0ba 29 static can_irq_handler irq_handler;
marcozecchini 0:9fca2b23d0ba 30
marcozecchini 0:9fca2b23d0ba 31 static void can_registers_init(can_t *obj)
marcozecchini 0:9fca2b23d0ba 32 {
marcozecchini 0:9fca2b23d0ba 33 if (HAL_CAN_Init(&obj->CanHandle) != HAL_OK) {
marcozecchini 0:9fca2b23d0ba 34 error("Cannot initialize CAN");
marcozecchini 0:9fca2b23d0ba 35 }
marcozecchini 0:9fca2b23d0ba 36
marcozecchini 0:9fca2b23d0ba 37 // Set initial CAN frequency to specified frequency
marcozecchini 0:9fca2b23d0ba 38 if (can_frequency(obj, obj->hz) != 1) {
marcozecchini 0:9fca2b23d0ba 39 error("Can frequency could not be set\n");
marcozecchini 0:9fca2b23d0ba 40 }
marcozecchini 0:9fca2b23d0ba 41 }
marcozecchini 0:9fca2b23d0ba 42
marcozecchini 0:9fca2b23d0ba 43 void can_init(can_t *obj, PinName rd, PinName td)
marcozecchini 0:9fca2b23d0ba 44 {
marcozecchini 0:9fca2b23d0ba 45 can_init_freq(obj, rd, td, 100000);
marcozecchini 0:9fca2b23d0ba 46 }
marcozecchini 0:9fca2b23d0ba 47
marcozecchini 0:9fca2b23d0ba 48 void can_init_freq (can_t *obj, PinName rd, PinName td, int hz)
marcozecchini 0:9fca2b23d0ba 49 {
marcozecchini 0:9fca2b23d0ba 50 CANName can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RD);
marcozecchini 0:9fca2b23d0ba 51 CANName can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TD);
marcozecchini 0:9fca2b23d0ba 52 CANName can = (CANName)pinmap_merge(can_rd, can_td);
marcozecchini 0:9fca2b23d0ba 53
marcozecchini 0:9fca2b23d0ba 54 MBED_ASSERT((int)can != NC);
marcozecchini 0:9fca2b23d0ba 55
marcozecchini 0:9fca2b23d0ba 56 if (can == CAN_1) {
marcozecchini 0:9fca2b23d0ba 57 __HAL_RCC_CAN1_CLK_ENABLE();
marcozecchini 0:9fca2b23d0ba 58 obj->index = 0;
marcozecchini 0:9fca2b23d0ba 59 }
marcozecchini 0:9fca2b23d0ba 60 #if defined(CAN2_BASE) && defined(CAN_2)
marcozecchini 0:9fca2b23d0ba 61 else if (can == CAN_2) {
marcozecchini 0:9fca2b23d0ba 62 __HAL_RCC_CAN1_CLK_ENABLE(); // needed to set filters
marcozecchini 0:9fca2b23d0ba 63 __HAL_RCC_CAN2_CLK_ENABLE();
marcozecchini 0:9fca2b23d0ba 64 obj->index = 1;
marcozecchini 0:9fca2b23d0ba 65 }
marcozecchini 0:9fca2b23d0ba 66 #endif
marcozecchini 0:9fca2b23d0ba 67 #if defined(CAN3_BASE) && defined(CAN_3)
marcozecchini 0:9fca2b23d0ba 68 else if (can == CAN_3) {
marcozecchini 0:9fca2b23d0ba 69 __HAL_RCC_CAN3_CLK_ENABLE();
marcozecchini 0:9fca2b23d0ba 70 obj->index = 2;
marcozecchini 0:9fca2b23d0ba 71 }
marcozecchini 0:9fca2b23d0ba 72 #endif
marcozecchini 0:9fca2b23d0ba 73 else {
marcozecchini 0:9fca2b23d0ba 74 return;
marcozecchini 0:9fca2b23d0ba 75 }
marcozecchini 0:9fca2b23d0ba 76
marcozecchini 0:9fca2b23d0ba 77 // Configure the CAN pins
marcozecchini 0:9fca2b23d0ba 78 pinmap_pinout(rd, PinMap_CAN_RD);
marcozecchini 0:9fca2b23d0ba 79 pinmap_pinout(td, PinMap_CAN_TD);
marcozecchini 0:9fca2b23d0ba 80 if (rd != NC) {
marcozecchini 0:9fca2b23d0ba 81 pin_mode(rd, PullUp);
marcozecchini 0:9fca2b23d0ba 82 }
marcozecchini 0:9fca2b23d0ba 83 if (td != NC) {
marcozecchini 0:9fca2b23d0ba 84 pin_mode(td, PullUp);
marcozecchini 0:9fca2b23d0ba 85 }
marcozecchini 0:9fca2b23d0ba 86
marcozecchini 0:9fca2b23d0ba 87 /* Use default values for rist init */
marcozecchini 0:9fca2b23d0ba 88 obj->CanHandle.Instance = (CAN_TypeDef *)can;
marcozecchini 0:9fca2b23d0ba 89 obj->CanHandle.Init.TTCM = DISABLE;
marcozecchini 0:9fca2b23d0ba 90 obj->CanHandle.Init.ABOM = DISABLE;
marcozecchini 0:9fca2b23d0ba 91 obj->CanHandle.Init.AWUM = DISABLE;
marcozecchini 0:9fca2b23d0ba 92 obj->CanHandle.Init.NART = DISABLE;
marcozecchini 0:9fca2b23d0ba 93 obj->CanHandle.Init.RFLM = DISABLE;
marcozecchini 0:9fca2b23d0ba 94 obj->CanHandle.Init.TXFP = DISABLE;
marcozecchini 0:9fca2b23d0ba 95 obj->CanHandle.Init.Mode = CAN_MODE_NORMAL;
marcozecchini 0:9fca2b23d0ba 96 obj->CanHandle.Init.SJW = CAN_SJW_1TQ;
marcozecchini 0:9fca2b23d0ba 97 obj->CanHandle.Init.BS1 = CAN_BS1_6TQ;
marcozecchini 0:9fca2b23d0ba 98 obj->CanHandle.Init.BS2 = CAN_BS2_8TQ;
marcozecchini 0:9fca2b23d0ba 99 obj->CanHandle.Init.Prescaler = 2;
marcozecchini 0:9fca2b23d0ba 100
marcozecchini 0:9fca2b23d0ba 101 /* Store frequency to be restored in case of reset */
marcozecchini 0:9fca2b23d0ba 102 obj->hz = hz;
marcozecchini 0:9fca2b23d0ba 103
marcozecchini 0:9fca2b23d0ba 104 can_registers_init(obj);
marcozecchini 0:9fca2b23d0ba 105
marcozecchini 0:9fca2b23d0ba 106 uint32_t filter_number = (can == CAN_1) ? 0 : 14;
marcozecchini 0:9fca2b23d0ba 107 can_filter(obj, 0, 0, CANStandard, filter_number);
marcozecchini 0:9fca2b23d0ba 108 }
marcozecchini 0:9fca2b23d0ba 109
marcozecchini 0:9fca2b23d0ba 110
marcozecchini 0:9fca2b23d0ba 111 void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id)
marcozecchini 0:9fca2b23d0ba 112 {
marcozecchini 0:9fca2b23d0ba 113 irq_handler = handler;
marcozecchini 0:9fca2b23d0ba 114 can_irq_ids[obj->index] = id;
marcozecchini 0:9fca2b23d0ba 115 }
marcozecchini 0:9fca2b23d0ba 116
marcozecchini 0:9fca2b23d0ba 117 void can_irq_free(can_t *obj)
marcozecchini 0:9fca2b23d0ba 118 {
marcozecchini 0:9fca2b23d0ba 119 CAN_TypeDef *can = obj->CanHandle.Instance;
marcozecchini 0:9fca2b23d0ba 120
marcozecchini 0:9fca2b23d0ba 121 can->IER &= ~(CAN_IT_FMP0 | CAN_IT_FMP1 | CAN_IT_TME | \
marcozecchini 0:9fca2b23d0ba 122 CAN_IT_ERR | CAN_IT_EPV | CAN_IT_BOF);
marcozecchini 0:9fca2b23d0ba 123 can_irq_ids[obj->index] = 0;
marcozecchini 0:9fca2b23d0ba 124 }
marcozecchini 0:9fca2b23d0ba 125
marcozecchini 0:9fca2b23d0ba 126 void can_free(can_t *obj)
marcozecchini 0:9fca2b23d0ba 127 {
marcozecchini 0:9fca2b23d0ba 128 CANName can = (CANName) obj->CanHandle.Instance;
marcozecchini 0:9fca2b23d0ba 129 // Reset CAN and disable clock
marcozecchini 0:9fca2b23d0ba 130 if (can == CAN_1) {
marcozecchini 0:9fca2b23d0ba 131 __HAL_RCC_CAN1_FORCE_RESET();
marcozecchini 0:9fca2b23d0ba 132 __HAL_RCC_CAN1_RELEASE_RESET();
marcozecchini 0:9fca2b23d0ba 133 __HAL_RCC_CAN1_CLK_DISABLE();
marcozecchini 0:9fca2b23d0ba 134 }
marcozecchini 0:9fca2b23d0ba 135 #if defined(CAN2_BASE) && defined(CAN_2)
marcozecchini 0:9fca2b23d0ba 136 if (can == CAN_2) {
marcozecchini 0:9fca2b23d0ba 137 __HAL_RCC_CAN2_FORCE_RESET();
marcozecchini 0:9fca2b23d0ba 138 __HAL_RCC_CAN2_RELEASE_RESET();
marcozecchini 0:9fca2b23d0ba 139 __HAL_RCC_CAN2_CLK_DISABLE();
marcozecchini 0:9fca2b23d0ba 140 }
marcozecchini 0:9fca2b23d0ba 141 #endif
marcozecchini 0:9fca2b23d0ba 142 #if defined(CAN3_BASE) && defined(CAN_3)
marcozecchini 0:9fca2b23d0ba 143 if (can == CAN_3) {
marcozecchini 0:9fca2b23d0ba 144 __HAL_RCC_CAN3_FORCE_RESET();
marcozecchini 0:9fca2b23d0ba 145 __HAL_RCC_CAN3_RELEASE_RESET();
marcozecchini 0:9fca2b23d0ba 146 __HAL_RCC_CAN3_CLK_DISABLE();
marcozecchini 0:9fca2b23d0ba 147 }
marcozecchini 0:9fca2b23d0ba 148 #endif
marcozecchini 0:9fca2b23d0ba 149 }
marcozecchini 0:9fca2b23d0ba 150
marcozecchini 0:9fca2b23d0ba 151 // The following table is used to program bit_timing. It is an adjustment of the sample
marcozecchini 0:9fca2b23d0ba 152 // point by synchronizing on the start-bit edge and resynchronizing on the following edges.
marcozecchini 0:9fca2b23d0ba 153 // This table has the sampling points as close to 75% as possible (most commonly used).
marcozecchini 0:9fca2b23d0ba 154 // The first value is TSEG1, the second TSEG2.
marcozecchini 0:9fca2b23d0ba 155 static const int timing_pts[23][2] = {
marcozecchini 0:9fca2b23d0ba 156 {0x0, 0x0}, // 2, 50%
marcozecchini 0:9fca2b23d0ba 157 {0x1, 0x0}, // 3, 67%
marcozecchini 0:9fca2b23d0ba 158 {0x2, 0x0}, // 4, 75%
marcozecchini 0:9fca2b23d0ba 159 {0x3, 0x0}, // 5, 80%
marcozecchini 0:9fca2b23d0ba 160 {0x3, 0x1}, // 6, 67%
marcozecchini 0:9fca2b23d0ba 161 {0x4, 0x1}, // 7, 71%
marcozecchini 0:9fca2b23d0ba 162 {0x5, 0x1}, // 8, 75%
marcozecchini 0:9fca2b23d0ba 163 {0x6, 0x1}, // 9, 78%
marcozecchini 0:9fca2b23d0ba 164 {0x6, 0x2}, // 10, 70%
marcozecchini 0:9fca2b23d0ba 165 {0x7, 0x2}, // 11, 73%
marcozecchini 0:9fca2b23d0ba 166 {0x8, 0x2}, // 12, 75%
marcozecchini 0:9fca2b23d0ba 167 {0x9, 0x2}, // 13, 77%
marcozecchini 0:9fca2b23d0ba 168 {0x9, 0x3}, // 14, 71%
marcozecchini 0:9fca2b23d0ba 169 {0xA, 0x3}, // 15, 73%
marcozecchini 0:9fca2b23d0ba 170 {0xB, 0x3}, // 16, 75%
marcozecchini 0:9fca2b23d0ba 171 {0xC, 0x3}, // 17, 76%
marcozecchini 0:9fca2b23d0ba 172 {0xD, 0x3}, // 18, 78%
marcozecchini 0:9fca2b23d0ba 173 {0xD, 0x4}, // 19, 74%
marcozecchini 0:9fca2b23d0ba 174 {0xE, 0x4}, // 20, 75%
marcozecchini 0:9fca2b23d0ba 175 {0xF, 0x4}, // 21, 76%
marcozecchini 0:9fca2b23d0ba 176 {0xF, 0x5}, // 22, 73%
marcozecchini 0:9fca2b23d0ba 177 {0xF, 0x6}, // 23, 70%
marcozecchini 0:9fca2b23d0ba 178 {0xF, 0x7}, // 24, 67%
marcozecchini 0:9fca2b23d0ba 179 };
marcozecchini 0:9fca2b23d0ba 180
marcozecchini 0:9fca2b23d0ba 181 static unsigned int can_speed(unsigned int pclk, unsigned int cclk, unsigned char psjw)
marcozecchini 0:9fca2b23d0ba 182 {
marcozecchini 0:9fca2b23d0ba 183 uint32_t btr;
marcozecchini 0:9fca2b23d0ba 184 uint16_t brp = 0;
marcozecchini 0:9fca2b23d0ba 185 uint32_t calcbit;
marcozecchini 0:9fca2b23d0ba 186 uint32_t bitwidth;
marcozecchini 0:9fca2b23d0ba 187 int hit = 0;
marcozecchini 0:9fca2b23d0ba 188 int bits;
marcozecchini 0:9fca2b23d0ba 189
marcozecchini 0:9fca2b23d0ba 190 bitwidth = (pclk / cclk);
marcozecchini 0:9fca2b23d0ba 191
marcozecchini 0:9fca2b23d0ba 192 brp = bitwidth / 0x18;
marcozecchini 0:9fca2b23d0ba 193 while ((!hit) && (brp < bitwidth / 4)) {
marcozecchini 0:9fca2b23d0ba 194 brp++;
marcozecchini 0:9fca2b23d0ba 195 for (bits = 22; bits > 0; bits--) {
marcozecchini 0:9fca2b23d0ba 196 calcbit = (bits + 3) * (brp + 1);
marcozecchini 0:9fca2b23d0ba 197 if (calcbit == bitwidth) {
marcozecchini 0:9fca2b23d0ba 198 hit = 1;
marcozecchini 0:9fca2b23d0ba 199 break;
marcozecchini 0:9fca2b23d0ba 200 }
marcozecchini 0:9fca2b23d0ba 201 }
marcozecchini 0:9fca2b23d0ba 202 }
marcozecchini 0:9fca2b23d0ba 203
marcozecchini 0:9fca2b23d0ba 204 if (hit) {
marcozecchini 0:9fca2b23d0ba 205 btr = ((timing_pts[bits][1] << CAN_BTR_TS2_Pos) & CAN_BTR_TS2) |
marcozecchini 0:9fca2b23d0ba 206 ((timing_pts[bits][0] << CAN_BTR_TS1_Pos) & CAN_BTR_TS1) |
marcozecchini 0:9fca2b23d0ba 207 ((psjw << CAN_BTR_SJW_Pos) & CAN_BTR_SJW) |
marcozecchini 0:9fca2b23d0ba 208 ((brp << CAN_BTR_BRP_Pos) & CAN_BTR_BRP);
marcozecchini 0:9fca2b23d0ba 209 } else {
marcozecchini 0:9fca2b23d0ba 210 btr = 0xFFFFFFFF;
marcozecchini 0:9fca2b23d0ba 211 }
marcozecchini 0:9fca2b23d0ba 212
marcozecchini 0:9fca2b23d0ba 213 return btr;
marcozecchini 0:9fca2b23d0ba 214
marcozecchini 0:9fca2b23d0ba 215 }
marcozecchini 0:9fca2b23d0ba 216
marcozecchini 0:9fca2b23d0ba 217 int can_frequency(can_t *obj, int f)
marcozecchini 0:9fca2b23d0ba 218 {
marcozecchini 0:9fca2b23d0ba 219 int pclk = HAL_RCC_GetPCLK1Freq();
marcozecchini 0:9fca2b23d0ba 220 int btr = can_speed(pclk, (unsigned int)f, 1);
marcozecchini 0:9fca2b23d0ba 221 CAN_TypeDef *can = obj->CanHandle.Instance;
marcozecchini 0:9fca2b23d0ba 222 uint32_t tickstart = 0;
marcozecchini 0:9fca2b23d0ba 223 int status = 1;
marcozecchini 0:9fca2b23d0ba 224
marcozecchini 0:9fca2b23d0ba 225 if (btr > 0) {
marcozecchini 0:9fca2b23d0ba 226 can->MCR |= CAN_MCR_INRQ ;
marcozecchini 0:9fca2b23d0ba 227 /* Get tick */
marcozecchini 0:9fca2b23d0ba 228 tickstart = HAL_GetTick();
marcozecchini 0:9fca2b23d0ba 229 while ((can->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) {
marcozecchini 0:9fca2b23d0ba 230 if ((HAL_GetTick() - tickstart) > 2) {
marcozecchini 0:9fca2b23d0ba 231 status = 0;
marcozecchini 0:9fca2b23d0ba 232 break;
marcozecchini 0:9fca2b23d0ba 233 }
marcozecchini 0:9fca2b23d0ba 234 }
marcozecchini 0:9fca2b23d0ba 235 if (status != 0) {
marcozecchini 0:9fca2b23d0ba 236 /* Do not erase all BTR registers (e.g. silent mode), only the
marcozecchini 0:9fca2b23d0ba 237 * ones calculated in can_speed */
marcozecchini 0:9fca2b23d0ba 238 can->BTR &= ~(CAN_BTR_TS2 | CAN_BTR_TS1 | CAN_BTR_SJW | CAN_BTR_BRP);
marcozecchini 0:9fca2b23d0ba 239 can->BTR |= btr;
marcozecchini 0:9fca2b23d0ba 240
marcozecchini 0:9fca2b23d0ba 241 can->MCR &= ~(uint32_t)CAN_MCR_INRQ;
marcozecchini 0:9fca2b23d0ba 242 /* Get tick */
marcozecchini 0:9fca2b23d0ba 243 tickstart = HAL_GetTick();
marcozecchini 0:9fca2b23d0ba 244 while ((can->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) {
marcozecchini 0:9fca2b23d0ba 245 if ((HAL_GetTick() - tickstart) > 2) {
marcozecchini 0:9fca2b23d0ba 246 status = 0;
marcozecchini 0:9fca2b23d0ba 247 break;
marcozecchini 0:9fca2b23d0ba 248 }
marcozecchini 0:9fca2b23d0ba 249 }
marcozecchini 0:9fca2b23d0ba 250 if (status == 0) {
marcozecchini 0:9fca2b23d0ba 251 error("can ESR 0x%04x.%04x + timeout status %d", (can->ESR & 0xFFFF0000) >> 16, (can->ESR & 0xFFFF), status);
marcozecchini 0:9fca2b23d0ba 252 }
marcozecchini 0:9fca2b23d0ba 253 } else {
marcozecchini 0:9fca2b23d0ba 254 error("can init request timeout\n");
marcozecchini 0:9fca2b23d0ba 255 }
marcozecchini 0:9fca2b23d0ba 256 } else {
marcozecchini 0:9fca2b23d0ba 257 status = 0;
marcozecchini 0:9fca2b23d0ba 258 }
marcozecchini 0:9fca2b23d0ba 259 return status;
marcozecchini 0:9fca2b23d0ba 260 }
marcozecchini 0:9fca2b23d0ba 261
marcozecchini 0:9fca2b23d0ba 262 int can_write(can_t *obj, CAN_Message msg, int cc)
marcozecchini 0:9fca2b23d0ba 263 {
marcozecchini 0:9fca2b23d0ba 264 uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
marcozecchini 0:9fca2b23d0ba 265 CAN_TypeDef *can = obj->CanHandle.Instance;
marcozecchini 0:9fca2b23d0ba 266
marcozecchini 0:9fca2b23d0ba 267 /* Select one empty transmit mailbox */
marcozecchini 0:9fca2b23d0ba 268 if ((can->TSR & CAN_TSR_TME0) == CAN_TSR_TME0) {
marcozecchini 0:9fca2b23d0ba 269 transmitmailbox = 0;
marcozecchini 0:9fca2b23d0ba 270 } else if ((can->TSR & CAN_TSR_TME1) == CAN_TSR_TME1) {
marcozecchini 0:9fca2b23d0ba 271 transmitmailbox = 1;
marcozecchini 0:9fca2b23d0ba 272 } else if ((can->TSR & CAN_TSR_TME2) == CAN_TSR_TME2) {
marcozecchini 0:9fca2b23d0ba 273 transmitmailbox = 2;
marcozecchini 0:9fca2b23d0ba 274 } else {
marcozecchini 0:9fca2b23d0ba 275 return 0;
marcozecchini 0:9fca2b23d0ba 276 }
marcozecchini 0:9fca2b23d0ba 277
marcozecchini 0:9fca2b23d0ba 278 can->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
marcozecchini 0:9fca2b23d0ba 279 if (!(msg.format)) {
marcozecchini 0:9fca2b23d0ba 280 can->sTxMailBox[transmitmailbox].TIR |= ((msg.id << 21) | msg.type);
marcozecchini 0:9fca2b23d0ba 281 } else {
marcozecchini 0:9fca2b23d0ba 282 can->sTxMailBox[transmitmailbox].TIR |= ((msg.id << 3) | CAN_ID_EXT | msg.type);
marcozecchini 0:9fca2b23d0ba 283 }
marcozecchini 0:9fca2b23d0ba 284
marcozecchini 0:9fca2b23d0ba 285 /* Set up the DLC */
marcozecchini 0:9fca2b23d0ba 286 can->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0;
marcozecchini 0:9fca2b23d0ba 287 can->sTxMailBox[transmitmailbox].TDTR |= (msg.len & (uint8_t)0x0000000F);
marcozecchini 0:9fca2b23d0ba 288
marcozecchini 0:9fca2b23d0ba 289 /* Set up the data field */
marcozecchini 0:9fca2b23d0ba 290 can->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)msg.data[3] << 24) |
marcozecchini 0:9fca2b23d0ba 291 ((uint32_t)msg.data[2] << 16) |
marcozecchini 0:9fca2b23d0ba 292 ((uint32_t)msg.data[1] << 8) |
marcozecchini 0:9fca2b23d0ba 293 ((uint32_t)msg.data[0]));
marcozecchini 0:9fca2b23d0ba 294 can->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)msg.data[7] << 24) |
marcozecchini 0:9fca2b23d0ba 295 ((uint32_t)msg.data[6] << 16) |
marcozecchini 0:9fca2b23d0ba 296 ((uint32_t)msg.data[5] << 8) |
marcozecchini 0:9fca2b23d0ba 297 ((uint32_t)msg.data[4]));
marcozecchini 0:9fca2b23d0ba 298 /* Request transmission */
marcozecchini 0:9fca2b23d0ba 299 can->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
marcozecchini 0:9fca2b23d0ba 300
marcozecchini 0:9fca2b23d0ba 301 return 1;
marcozecchini 0:9fca2b23d0ba 302 }
marcozecchini 0:9fca2b23d0ba 303
marcozecchini 0:9fca2b23d0ba 304 int can_read(can_t *obj, CAN_Message *msg, int handle)
marcozecchini 0:9fca2b23d0ba 305 {
marcozecchini 0:9fca2b23d0ba 306 //handle is the FIFO number
marcozecchini 0:9fca2b23d0ba 307
marcozecchini 0:9fca2b23d0ba 308 CAN_TypeDef *can = obj->CanHandle.Instance;
marcozecchini 0:9fca2b23d0ba 309
marcozecchini 0:9fca2b23d0ba 310 // check FPM0 which holds the pending message count in FIFO 0
marcozecchini 0:9fca2b23d0ba 311 // if no message is pending, return 0
marcozecchini 0:9fca2b23d0ba 312 if ((can->RF0R & CAN_RF0R_FMP0) == 0) {
marcozecchini 0:9fca2b23d0ba 313 return 0;
marcozecchini 0:9fca2b23d0ba 314 }
marcozecchini 0:9fca2b23d0ba 315
marcozecchini 0:9fca2b23d0ba 316 /* Get the Id */
marcozecchini 0:9fca2b23d0ba 317 msg->format = (CANFormat)(((uint8_t)0x04 & can->sFIFOMailBox[handle].RIR) >> 2);
marcozecchini 0:9fca2b23d0ba 318 if (!msg->format) {
marcozecchini 0:9fca2b23d0ba 319 msg->id = (uint32_t)0x000007FF & (can->sFIFOMailBox[handle].RIR >> 21);
marcozecchini 0:9fca2b23d0ba 320 } else {
marcozecchini 0:9fca2b23d0ba 321 msg->id = (uint32_t)0x1FFFFFFF & (can->sFIFOMailBox[handle].RIR >> 3);
marcozecchini 0:9fca2b23d0ba 322 }
marcozecchini 0:9fca2b23d0ba 323
marcozecchini 0:9fca2b23d0ba 324 msg->type = (CANType)(((uint8_t)0x02 & can->sFIFOMailBox[handle].RIR) >> 1);
marcozecchini 0:9fca2b23d0ba 325 /* Get the DLC */
marcozecchini 0:9fca2b23d0ba 326 msg->len = (uint8_t)0x0F & can->sFIFOMailBox[handle].RDTR;
marcozecchini 0:9fca2b23d0ba 327 /* Get the FMI */
marcozecchini 0:9fca2b23d0ba 328 // msg->FMI = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDTR >> 8);
marcozecchini 0:9fca2b23d0ba 329 /* Get the data field */
marcozecchini 0:9fca2b23d0ba 330 msg->data[0] = (uint8_t)0xFF & can->sFIFOMailBox[handle].RDLR;
marcozecchini 0:9fca2b23d0ba 331 msg->data[1] = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDLR >> 8);
marcozecchini 0:9fca2b23d0ba 332 msg->data[2] = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDLR >> 16);
marcozecchini 0:9fca2b23d0ba 333 msg->data[3] = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDLR >> 24);
marcozecchini 0:9fca2b23d0ba 334 msg->data[4] = (uint8_t)0xFF & can->sFIFOMailBox[handle].RDHR;
marcozecchini 0:9fca2b23d0ba 335 msg->data[5] = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDHR >> 8);
marcozecchini 0:9fca2b23d0ba 336 msg->data[6] = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDHR >> 16);
marcozecchini 0:9fca2b23d0ba 337 msg->data[7] = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDHR >> 24);
marcozecchini 0:9fca2b23d0ba 338
marcozecchini 0:9fca2b23d0ba 339 /* Release the FIFO */
marcozecchini 0:9fca2b23d0ba 340 if (handle == CAN_FIFO0) {
marcozecchini 0:9fca2b23d0ba 341 /* Release FIFO0 */
marcozecchini 0:9fca2b23d0ba 342 can->RF0R |= CAN_RF0R_RFOM0;
marcozecchini 0:9fca2b23d0ba 343 } else { /* FIFONumber == CAN_FIFO1 */
marcozecchini 0:9fca2b23d0ba 344 /* Release FIFO1 */
marcozecchini 0:9fca2b23d0ba 345 can->RF1R |= CAN_RF1R_RFOM1;
marcozecchini 0:9fca2b23d0ba 346 }
marcozecchini 0:9fca2b23d0ba 347
marcozecchini 0:9fca2b23d0ba 348 return 1;
marcozecchini 0:9fca2b23d0ba 349 }
marcozecchini 0:9fca2b23d0ba 350
marcozecchini 0:9fca2b23d0ba 351 void can_reset(can_t *obj)
marcozecchini 0:9fca2b23d0ba 352 {
marcozecchini 0:9fca2b23d0ba 353 CAN_TypeDef *can = obj->CanHandle.Instance;
marcozecchini 0:9fca2b23d0ba 354
marcozecchini 0:9fca2b23d0ba 355 /* Reset IP and delete errors */
marcozecchini 0:9fca2b23d0ba 356 can->MCR |= CAN_MCR_RESET;
marcozecchini 0:9fca2b23d0ba 357 can->ESR = 0x0;
marcozecchini 0:9fca2b23d0ba 358
marcozecchini 0:9fca2b23d0ba 359 /* restore registers state as saved in obj context */
marcozecchini 0:9fca2b23d0ba 360 can_registers_init(obj);
marcozecchini 0:9fca2b23d0ba 361 }
marcozecchini 0:9fca2b23d0ba 362
marcozecchini 0:9fca2b23d0ba 363 unsigned char can_rderror(can_t *obj)
marcozecchini 0:9fca2b23d0ba 364 {
marcozecchini 0:9fca2b23d0ba 365 CAN_TypeDef *can = obj->CanHandle.Instance;
marcozecchini 0:9fca2b23d0ba 366 return (can->ESR >> 24) & 0xFF;
marcozecchini 0:9fca2b23d0ba 367 }
marcozecchini 0:9fca2b23d0ba 368
marcozecchini 0:9fca2b23d0ba 369 unsigned char can_tderror(can_t *obj)
marcozecchini 0:9fca2b23d0ba 370 {
marcozecchini 0:9fca2b23d0ba 371 CAN_TypeDef *can = obj->CanHandle.Instance;
marcozecchini 0:9fca2b23d0ba 372 return (can->ESR >> 16) & 0xFF;
marcozecchini 0:9fca2b23d0ba 373 }
marcozecchini 0:9fca2b23d0ba 374
marcozecchini 0:9fca2b23d0ba 375 void can_monitor(can_t *obj, int silent)
marcozecchini 0:9fca2b23d0ba 376 {
marcozecchini 0:9fca2b23d0ba 377 CanMode mode = MODE_NORMAL;
marcozecchini 0:9fca2b23d0ba 378 /* Update current state w/ or w/o silent */
marcozecchini 0:9fca2b23d0ba 379 if(silent) {
marcozecchini 0:9fca2b23d0ba 380 switch (obj->CanHandle.Init.Mode) {
marcozecchini 0:9fca2b23d0ba 381 case CAN_MODE_LOOPBACK:
marcozecchini 0:9fca2b23d0ba 382 case CAN_MODE_SILENT_LOOPBACK:
marcozecchini 0:9fca2b23d0ba 383 mode = MODE_TEST_SILENT;
marcozecchini 0:9fca2b23d0ba 384 break;
marcozecchini 0:9fca2b23d0ba 385 default:
marcozecchini 0:9fca2b23d0ba 386 mode = MODE_SILENT;
marcozecchini 0:9fca2b23d0ba 387 break;
marcozecchini 0:9fca2b23d0ba 388 }
marcozecchini 0:9fca2b23d0ba 389 } else {
marcozecchini 0:9fca2b23d0ba 390 switch (obj->CanHandle.Init.Mode) {
marcozecchini 0:9fca2b23d0ba 391 case CAN_MODE_LOOPBACK:
marcozecchini 0:9fca2b23d0ba 392 case CAN_MODE_SILENT_LOOPBACK:
marcozecchini 0:9fca2b23d0ba 393 mode = MODE_TEST_LOCAL;
marcozecchini 0:9fca2b23d0ba 394 break;
marcozecchini 0:9fca2b23d0ba 395 default:
marcozecchini 0:9fca2b23d0ba 396 mode = MODE_NORMAL;
marcozecchini 0:9fca2b23d0ba 397 break;
marcozecchini 0:9fca2b23d0ba 398 }
marcozecchini 0:9fca2b23d0ba 399 }
marcozecchini 0:9fca2b23d0ba 400
marcozecchini 0:9fca2b23d0ba 401 can_mode(obj, mode);
marcozecchini 0:9fca2b23d0ba 402 }
marcozecchini 0:9fca2b23d0ba 403
marcozecchini 0:9fca2b23d0ba 404 int can_mode(can_t *obj, CanMode mode)
marcozecchini 0:9fca2b23d0ba 405 {
marcozecchini 0:9fca2b23d0ba 406 int success = 0;
marcozecchini 0:9fca2b23d0ba 407 CAN_TypeDef *can = obj->CanHandle.Instance;
marcozecchini 0:9fca2b23d0ba 408
marcozecchini 0:9fca2b23d0ba 409 can->MCR |= CAN_MCR_INRQ ;
marcozecchini 0:9fca2b23d0ba 410 while ((can->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) {
marcozecchini 0:9fca2b23d0ba 411 }
marcozecchini 0:9fca2b23d0ba 412
marcozecchini 0:9fca2b23d0ba 413 switch (mode) {
marcozecchini 0:9fca2b23d0ba 414 case MODE_NORMAL:
marcozecchini 0:9fca2b23d0ba 415 obj->CanHandle.Init.Mode = CAN_MODE_NORMAL;
marcozecchini 0:9fca2b23d0ba 416 can->BTR &= ~(CAN_BTR_SILM | CAN_BTR_LBKM);
marcozecchini 0:9fca2b23d0ba 417 success = 1;
marcozecchini 0:9fca2b23d0ba 418 break;
marcozecchini 0:9fca2b23d0ba 419 case MODE_SILENT:
marcozecchini 0:9fca2b23d0ba 420 obj->CanHandle.Init.Mode = CAN_MODE_SILENT;
marcozecchini 0:9fca2b23d0ba 421 can->BTR |= CAN_BTR_SILM;
marcozecchini 0:9fca2b23d0ba 422 can->BTR &= ~CAN_BTR_LBKM;
marcozecchini 0:9fca2b23d0ba 423 success = 1;
marcozecchini 0:9fca2b23d0ba 424 break;
marcozecchini 0:9fca2b23d0ba 425 case MODE_TEST_GLOBAL:
marcozecchini 0:9fca2b23d0ba 426 case MODE_TEST_LOCAL:
marcozecchini 0:9fca2b23d0ba 427 obj->CanHandle.Init.Mode = CAN_MODE_LOOPBACK;
marcozecchini 0:9fca2b23d0ba 428 can->BTR |= CAN_BTR_LBKM;
marcozecchini 0:9fca2b23d0ba 429 can->BTR &= ~CAN_BTR_SILM;
marcozecchini 0:9fca2b23d0ba 430 success = 1;
marcozecchini 0:9fca2b23d0ba 431 break;
marcozecchini 0:9fca2b23d0ba 432 case MODE_TEST_SILENT:
marcozecchini 0:9fca2b23d0ba 433 obj->CanHandle.Init.Mode = CAN_MODE_SILENT_LOOPBACK;
marcozecchini 0:9fca2b23d0ba 434 can->BTR |= (CAN_BTR_SILM | CAN_BTR_LBKM);
marcozecchini 0:9fca2b23d0ba 435 success = 1;
marcozecchini 0:9fca2b23d0ba 436 break;
marcozecchini 0:9fca2b23d0ba 437 default:
marcozecchini 0:9fca2b23d0ba 438 success = 0;
marcozecchini 0:9fca2b23d0ba 439 break;
marcozecchini 0:9fca2b23d0ba 440 }
marcozecchini 0:9fca2b23d0ba 441
marcozecchini 0:9fca2b23d0ba 442 can->MCR &= ~(uint32_t)CAN_MCR_INRQ;
marcozecchini 0:9fca2b23d0ba 443 while ((can->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) {
marcozecchini 0:9fca2b23d0ba 444 }
marcozecchini 0:9fca2b23d0ba 445
marcozecchini 0:9fca2b23d0ba 446 return success;
marcozecchini 0:9fca2b23d0ba 447 }
marcozecchini 0:9fca2b23d0ba 448
marcozecchini 0:9fca2b23d0ba 449 int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle)
marcozecchini 0:9fca2b23d0ba 450 {
marcozecchini 0:9fca2b23d0ba 451 int retval = 0;
marcozecchini 0:9fca2b23d0ba 452
marcozecchini 0:9fca2b23d0ba 453 // filter for CANAny format cannot be configured for STM32
marcozecchini 0:9fca2b23d0ba 454 if ((format == CANStandard) || (format == CANExtended)) {
marcozecchini 0:9fca2b23d0ba 455 CAN_FilterConfTypeDef sFilterConfig;
marcozecchini 0:9fca2b23d0ba 456 sFilterConfig.FilterNumber = handle;
marcozecchini 0:9fca2b23d0ba 457 sFilterConfig.FilterMode = CAN_FILTERMODE_IDMASK;
marcozecchini 0:9fca2b23d0ba 458 sFilterConfig.FilterScale = CAN_FILTERSCALE_32BIT;
marcozecchini 0:9fca2b23d0ba 459
marcozecchini 0:9fca2b23d0ba 460 if (format == CANStandard) {
marcozecchini 0:9fca2b23d0ba 461 sFilterConfig.FilterIdHigh = id << 5;
marcozecchini 0:9fca2b23d0ba 462 sFilterConfig.FilterIdLow = 0x0;
marcozecchini 0:9fca2b23d0ba 463 sFilterConfig.FilterMaskIdHigh = mask << 5;
marcozecchini 0:9fca2b23d0ba 464 sFilterConfig.FilterMaskIdLow = 0x0; // allows both remote and data frames
marcozecchini 0:9fca2b23d0ba 465 } else if (format == CANExtended) {
marcozecchini 0:9fca2b23d0ba 466 sFilterConfig.FilterIdHigh = id >> 13; // EXTID[28:13]
marcozecchini 0:9fca2b23d0ba 467 sFilterConfig.FilterIdLow = (0x00FF & (id << 3)) | (1 << 2); // EXTID[12:0]
marcozecchini 0:9fca2b23d0ba 468 sFilterConfig.FilterMaskIdHigh = mask >> 13;
marcozecchini 0:9fca2b23d0ba 469 sFilterConfig.FilterMaskIdLow = (0x00FF & (mask << 3)) | (1 << 2);
marcozecchini 0:9fca2b23d0ba 470 }
marcozecchini 0:9fca2b23d0ba 471
marcozecchini 0:9fca2b23d0ba 472 sFilterConfig.FilterFIFOAssignment = 0;
marcozecchini 0:9fca2b23d0ba 473 sFilterConfig.FilterActivation = ENABLE;
marcozecchini 0:9fca2b23d0ba 474 sFilterConfig.BankNumber = 14 + handle;
marcozecchini 0:9fca2b23d0ba 475
marcozecchini 0:9fca2b23d0ba 476 HAL_CAN_ConfigFilter(&obj->CanHandle, &sFilterConfig);
marcozecchini 0:9fca2b23d0ba 477 retval = handle;
marcozecchini 0:9fca2b23d0ba 478 }
marcozecchini 0:9fca2b23d0ba 479 return retval;
marcozecchini 0:9fca2b23d0ba 480 }
marcozecchini 0:9fca2b23d0ba 481
marcozecchini 0:9fca2b23d0ba 482 static void can_irq(CANName name, int id)
marcozecchini 0:9fca2b23d0ba 483 {
marcozecchini 0:9fca2b23d0ba 484 uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0;
marcozecchini 0:9fca2b23d0ba 485 CAN_HandleTypeDef CanHandle;
marcozecchini 0:9fca2b23d0ba 486 CanHandle.Instance = (CAN_TypeDef *)name;
marcozecchini 0:9fca2b23d0ba 487
marcozecchini 0:9fca2b23d0ba 488 if (__HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_TME)) {
marcozecchini 0:9fca2b23d0ba 489 tmp1 = __HAL_CAN_TRANSMIT_STATUS(&CanHandle, CAN_TXMAILBOX_0);
marcozecchini 0:9fca2b23d0ba 490 tmp2 = __HAL_CAN_TRANSMIT_STATUS(&CanHandle, CAN_TXMAILBOX_1);
marcozecchini 0:9fca2b23d0ba 491 tmp3 = __HAL_CAN_TRANSMIT_STATUS(&CanHandle, CAN_TXMAILBOX_2);
marcozecchini 0:9fca2b23d0ba 492 if (tmp1) {
marcozecchini 0:9fca2b23d0ba 493 __HAL_CAN_CLEAR_FLAG(&CanHandle, CAN_FLAG_RQCP0);
marcozecchini 0:9fca2b23d0ba 494 }
marcozecchini 0:9fca2b23d0ba 495 if (tmp2) {
marcozecchini 0:9fca2b23d0ba 496 __HAL_CAN_CLEAR_FLAG(&CanHandle, CAN_FLAG_RQCP1);
marcozecchini 0:9fca2b23d0ba 497 }
marcozecchini 0:9fca2b23d0ba 498 if (tmp3) {
marcozecchini 0:9fca2b23d0ba 499 __HAL_CAN_CLEAR_FLAG(&CanHandle, CAN_FLAG_RQCP2);
marcozecchini 0:9fca2b23d0ba 500 }
marcozecchini 0:9fca2b23d0ba 501 if (tmp1 || tmp2 || tmp3) {
marcozecchini 0:9fca2b23d0ba 502 irq_handler(can_irq_ids[id], IRQ_TX);
marcozecchini 0:9fca2b23d0ba 503 }
marcozecchini 0:9fca2b23d0ba 504 }
marcozecchini 0:9fca2b23d0ba 505
marcozecchini 0:9fca2b23d0ba 506 tmp1 = __HAL_CAN_MSG_PENDING(&CanHandle, CAN_FIFO0);
marcozecchini 0:9fca2b23d0ba 507 tmp2 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_FMP0);
marcozecchini 0:9fca2b23d0ba 508
marcozecchini 0:9fca2b23d0ba 509 if ((tmp1 != 0) && tmp2) {
marcozecchini 0:9fca2b23d0ba 510 irq_handler(can_irq_ids[id], IRQ_RX);
marcozecchini 0:9fca2b23d0ba 511 }
marcozecchini 0:9fca2b23d0ba 512
marcozecchini 0:9fca2b23d0ba 513 tmp1 = __HAL_CAN_GET_FLAG(&CanHandle, CAN_FLAG_EPV);
marcozecchini 0:9fca2b23d0ba 514 tmp2 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_EPV);
marcozecchini 0:9fca2b23d0ba 515 tmp3 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_ERR);
marcozecchini 0:9fca2b23d0ba 516
marcozecchini 0:9fca2b23d0ba 517 if (tmp1 && tmp2 && tmp3) {
marcozecchini 0:9fca2b23d0ba 518 irq_handler(can_irq_ids[id], IRQ_PASSIVE);
marcozecchini 0:9fca2b23d0ba 519 }
marcozecchini 0:9fca2b23d0ba 520
marcozecchini 0:9fca2b23d0ba 521 tmp1 = __HAL_CAN_GET_FLAG(&CanHandle, CAN_FLAG_BOF);
marcozecchini 0:9fca2b23d0ba 522 tmp2 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_BOF);
marcozecchini 0:9fca2b23d0ba 523 tmp3 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_ERR);
marcozecchini 0:9fca2b23d0ba 524 if (tmp1 && tmp2 && tmp3) {
marcozecchini 0:9fca2b23d0ba 525 irq_handler(can_irq_ids[id], IRQ_BUS);
marcozecchini 0:9fca2b23d0ba 526 }
marcozecchini 0:9fca2b23d0ba 527
marcozecchini 0:9fca2b23d0ba 528 tmp3 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_ERR);
marcozecchini 0:9fca2b23d0ba 529 if (tmp1 && tmp2 && tmp3) {
marcozecchini 0:9fca2b23d0ba 530 irq_handler(can_irq_ids[id], IRQ_ERROR);
marcozecchini 0:9fca2b23d0ba 531 }
marcozecchini 0:9fca2b23d0ba 532 }
marcozecchini 0:9fca2b23d0ba 533
marcozecchini 0:9fca2b23d0ba 534 #if defined(TARGET_STM32F0)
marcozecchini 0:9fca2b23d0ba 535 void CAN_IRQHandler(void)
marcozecchini 0:9fca2b23d0ba 536 {
marcozecchini 0:9fca2b23d0ba 537 can_irq(CAN_1, 0);
marcozecchini 0:9fca2b23d0ba 538 }
marcozecchini 0:9fca2b23d0ba 539 #elif defined(TARGET_STM32F3)
marcozecchini 0:9fca2b23d0ba 540 void CAN_RX0_IRQHandler(void)
marcozecchini 0:9fca2b23d0ba 541 {
marcozecchini 0:9fca2b23d0ba 542 can_irq(CAN_1, 0);
marcozecchini 0:9fca2b23d0ba 543 }
marcozecchini 0:9fca2b23d0ba 544 void CAN_TX_IRQHandler(void)
marcozecchini 0:9fca2b23d0ba 545 {
marcozecchini 0:9fca2b23d0ba 546 can_irq(CAN_1, 0);
marcozecchini 0:9fca2b23d0ba 547 }
marcozecchini 0:9fca2b23d0ba 548 void CAN_SCE_IRQHandler(void)
marcozecchini 0:9fca2b23d0ba 549 {
marcozecchini 0:9fca2b23d0ba 550 can_irq(CAN_1, 0);
marcozecchini 0:9fca2b23d0ba 551 }
marcozecchini 0:9fca2b23d0ba 552 #else
marcozecchini 0:9fca2b23d0ba 553 void CAN1_RX0_IRQHandler(void)
marcozecchini 0:9fca2b23d0ba 554 {
marcozecchini 0:9fca2b23d0ba 555 can_irq(CAN_1, 0);
marcozecchini 0:9fca2b23d0ba 556 }
marcozecchini 0:9fca2b23d0ba 557 void CAN1_TX_IRQHandler(void)
marcozecchini 0:9fca2b23d0ba 558 {
marcozecchini 0:9fca2b23d0ba 559 can_irq(CAN_1, 0);
marcozecchini 0:9fca2b23d0ba 560 }
marcozecchini 0:9fca2b23d0ba 561 void CAN1_SCE_IRQHandler(void)
marcozecchini 0:9fca2b23d0ba 562 {
marcozecchini 0:9fca2b23d0ba 563 can_irq(CAN_1, 0);
marcozecchini 0:9fca2b23d0ba 564 }
marcozecchini 0:9fca2b23d0ba 565 #if defined(CAN2_BASE) && defined(CAN_2)
marcozecchini 0:9fca2b23d0ba 566 void CAN2_RX0_IRQHandler(void)
marcozecchini 0:9fca2b23d0ba 567 {
marcozecchini 0:9fca2b23d0ba 568 can_irq(CAN_2, 1);
marcozecchini 0:9fca2b23d0ba 569 }
marcozecchini 0:9fca2b23d0ba 570 void CAN2_TX_IRQHandler(void)
marcozecchini 0:9fca2b23d0ba 571 {
marcozecchini 0:9fca2b23d0ba 572 can_irq(CAN_2, 1);
marcozecchini 0:9fca2b23d0ba 573 }
marcozecchini 0:9fca2b23d0ba 574 void CAN2_SCE_IRQHandler(void)
marcozecchini 0:9fca2b23d0ba 575 {
marcozecchini 0:9fca2b23d0ba 576 can_irq(CAN_2, 1);
marcozecchini 0:9fca2b23d0ba 577 }
marcozecchini 0:9fca2b23d0ba 578 #endif
marcozecchini 0:9fca2b23d0ba 579 #if defined(CAN3_BASE) && defined(CAN_3)
marcozecchini 0:9fca2b23d0ba 580 void CAN3_RX0_IRQHandler(void)
marcozecchini 0:9fca2b23d0ba 581 {
marcozecchini 0:9fca2b23d0ba 582 can_irq(CAN_3, 1);
marcozecchini 0:9fca2b23d0ba 583 }
marcozecchini 0:9fca2b23d0ba 584 void CAN3_TX_IRQHandler(void)
marcozecchini 0:9fca2b23d0ba 585 {
marcozecchini 0:9fca2b23d0ba 586 can_irq(CAN_3, 1);
marcozecchini 0:9fca2b23d0ba 587 }
marcozecchini 0:9fca2b23d0ba 588 void CAN3_SCE_IRQHandler(void)
marcozecchini 0:9fca2b23d0ba 589 {
marcozecchini 0:9fca2b23d0ba 590 can_irq(CAN_3, 1);
marcozecchini 0:9fca2b23d0ba 591 }
marcozecchini 0:9fca2b23d0ba 592 #endif
marcozecchini 0:9fca2b23d0ba 593 #endif // else
marcozecchini 0:9fca2b23d0ba 594
marcozecchini 0:9fca2b23d0ba 595 void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable)
marcozecchini 0:9fca2b23d0ba 596 {
marcozecchini 0:9fca2b23d0ba 597 CAN_TypeDef *can = obj->CanHandle.Instance;
marcozecchini 0:9fca2b23d0ba 598 IRQn_Type irq_n = (IRQn_Type)0;
marcozecchini 0:9fca2b23d0ba 599 uint32_t vector = 0;
marcozecchini 0:9fca2b23d0ba 600 uint32_t ier;
marcozecchini 0:9fca2b23d0ba 601
marcozecchini 0:9fca2b23d0ba 602 if ((CANName) can == CAN_1) {
marcozecchini 0:9fca2b23d0ba 603 switch (type) {
marcozecchini 0:9fca2b23d0ba 604 case IRQ_RX:
marcozecchini 0:9fca2b23d0ba 605 ier = CAN_IT_FMP0;
marcozecchini 0:9fca2b23d0ba 606 irq_n = CAN1_IRQ_RX_IRQN;
marcozecchini 0:9fca2b23d0ba 607 vector = (uint32_t)&CAN1_IRQ_RX_VECT;
marcozecchini 0:9fca2b23d0ba 608 break;
marcozecchini 0:9fca2b23d0ba 609 case IRQ_TX:
marcozecchini 0:9fca2b23d0ba 610 ier = CAN_IT_TME;
marcozecchini 0:9fca2b23d0ba 611 irq_n = CAN1_IRQ_TX_IRQN;
marcozecchini 0:9fca2b23d0ba 612 vector = (uint32_t)&CAN1_IRQ_TX_VECT;
marcozecchini 0:9fca2b23d0ba 613 break;
marcozecchini 0:9fca2b23d0ba 614 case IRQ_ERROR:
marcozecchini 0:9fca2b23d0ba 615 ier = CAN_IT_ERR;
marcozecchini 0:9fca2b23d0ba 616 irq_n = CAN1_IRQ_ERROR_IRQN;
marcozecchini 0:9fca2b23d0ba 617 vector = (uint32_t)&CAN1_IRQ_ERROR_VECT;
marcozecchini 0:9fca2b23d0ba 618 break;
marcozecchini 0:9fca2b23d0ba 619 case IRQ_PASSIVE:
marcozecchini 0:9fca2b23d0ba 620 ier = CAN_IT_EPV;
marcozecchini 0:9fca2b23d0ba 621 irq_n = CAN1_IRQ_PASSIVE_IRQN;
marcozecchini 0:9fca2b23d0ba 622 vector = (uint32_t)&CAN1_IRQ_PASSIVE_VECT;
marcozecchini 0:9fca2b23d0ba 623 break;
marcozecchini 0:9fca2b23d0ba 624 case IRQ_BUS:
marcozecchini 0:9fca2b23d0ba 625 ier = CAN_IT_BOF;
marcozecchini 0:9fca2b23d0ba 626 irq_n = CAN1_IRQ_BUS_IRQN;
marcozecchini 0:9fca2b23d0ba 627 vector = (uint32_t)&CAN1_IRQ_BUS_VECT;
marcozecchini 0:9fca2b23d0ba 628 break;
marcozecchini 0:9fca2b23d0ba 629 default:
marcozecchini 0:9fca2b23d0ba 630 return;
marcozecchini 0:9fca2b23d0ba 631 }
marcozecchini 0:9fca2b23d0ba 632 }
marcozecchini 0:9fca2b23d0ba 633 #if defined(CAN2_BASE) && defined(CAN_2)
marcozecchini 0:9fca2b23d0ba 634 else if ((CANName) can == CAN_2) {
marcozecchini 0:9fca2b23d0ba 635 switch (type) {
marcozecchini 0:9fca2b23d0ba 636 case IRQ_RX:
marcozecchini 0:9fca2b23d0ba 637 ier = CAN_IT_FMP0;
marcozecchini 0:9fca2b23d0ba 638 irq_n = CAN2_IRQ_RX_IRQN;
marcozecchini 0:9fca2b23d0ba 639 vector = (uint32_t)&CAN2_IRQ_RX_VECT;
marcozecchini 0:9fca2b23d0ba 640 break;
marcozecchini 0:9fca2b23d0ba 641 case IRQ_TX:
marcozecchini 0:9fca2b23d0ba 642 ier = CAN_IT_TME;
marcozecchini 0:9fca2b23d0ba 643 irq_n = CAN2_IRQ_TX_IRQN;
marcozecchini 0:9fca2b23d0ba 644 vector = (uint32_t)&CAN2_IRQ_TX_VECT;
marcozecchini 0:9fca2b23d0ba 645 break;
marcozecchini 0:9fca2b23d0ba 646 case IRQ_ERROR:
marcozecchini 0:9fca2b23d0ba 647 ier = CAN_IT_ERR;
marcozecchini 0:9fca2b23d0ba 648 irq_n = CAN2_IRQ_ERROR_IRQN;
marcozecchini 0:9fca2b23d0ba 649 vector = (uint32_t)&CAN2_IRQ_ERROR_VECT;
marcozecchini 0:9fca2b23d0ba 650 break;
marcozecchini 0:9fca2b23d0ba 651 case IRQ_PASSIVE:
marcozecchini 0:9fca2b23d0ba 652 ier = CAN_IT_EPV;
marcozecchini 0:9fca2b23d0ba 653 irq_n = CAN2_IRQ_PASSIVE_IRQN;
marcozecchini 0:9fca2b23d0ba 654 vector = (uint32_t)&CAN2_IRQ_PASSIVE_VECT;
marcozecchini 0:9fca2b23d0ba 655 break;
marcozecchini 0:9fca2b23d0ba 656 case IRQ_BUS:
marcozecchini 0:9fca2b23d0ba 657 ier = CAN_IT_BOF;
marcozecchini 0:9fca2b23d0ba 658 irq_n = CAN2_IRQ_BUS_IRQN;
marcozecchini 0:9fca2b23d0ba 659 vector = (uint32_t)&CAN2_IRQ_BUS_VECT;
marcozecchini 0:9fca2b23d0ba 660 break;
marcozecchini 0:9fca2b23d0ba 661 default:
marcozecchini 0:9fca2b23d0ba 662 return;
marcozecchini 0:9fca2b23d0ba 663 }
marcozecchini 0:9fca2b23d0ba 664 }
marcozecchini 0:9fca2b23d0ba 665 #endif
marcozecchini 0:9fca2b23d0ba 666 #if defined(CAN3_BASE) && defined(CAN_3)
marcozecchini 0:9fca2b23d0ba 667 else if ((CANName) can == CAN_3) {
marcozecchini 0:9fca2b23d0ba 668 switch (type) {
marcozecchini 0:9fca2b23d0ba 669 case IRQ_RX:
marcozecchini 0:9fca2b23d0ba 670 ier = CAN_IT_FMP0;
marcozecchini 0:9fca2b23d0ba 671 irq_n = CAN3_IRQ_RX_IRQN;
marcozecchini 0:9fca2b23d0ba 672 vector = (uint32_t)&CAN3_IRQ_RX_VECT;
marcozecchini 0:9fca2b23d0ba 673 break;
marcozecchini 0:9fca2b23d0ba 674 case IRQ_TX:
marcozecchini 0:9fca2b23d0ba 675 ier = CAN_IT_TME;
marcozecchini 0:9fca2b23d0ba 676 irq_n = CAN3_IRQ_TX_IRQN;
marcozecchini 0:9fca2b23d0ba 677 vector = (uint32_t)&CAN3_IRQ_TX_VECT;
marcozecchini 0:9fca2b23d0ba 678 break;
marcozecchini 0:9fca2b23d0ba 679 case IRQ_ERROR:
marcozecchini 0:9fca2b23d0ba 680 ier = CAN_IT_ERR;
marcozecchini 0:9fca2b23d0ba 681 irq_n = CAN3_IRQ_ERROR_IRQN;
marcozecchini 0:9fca2b23d0ba 682 vector = (uint32_t)&CAN3_IRQ_ERROR_VECT;
marcozecchini 0:9fca2b23d0ba 683 break;
marcozecchini 0:9fca2b23d0ba 684 case IRQ_PASSIVE:
marcozecchini 0:9fca2b23d0ba 685 ier = CAN_IT_EPV;
marcozecchini 0:9fca2b23d0ba 686 irq_n = CAN3_IRQ_PASSIVE_IRQN;
marcozecchini 0:9fca2b23d0ba 687 vector = (uint32_t)&CAN3_IRQ_PASSIVE_VECT;
marcozecchini 0:9fca2b23d0ba 688 break;
marcozecchini 0:9fca2b23d0ba 689 case IRQ_BUS:
marcozecchini 0:9fca2b23d0ba 690 ier = CAN_IT_BOF;
marcozecchini 0:9fca2b23d0ba 691 irq_n = CAN3_IRQ_BUS_IRQN;
marcozecchini 0:9fca2b23d0ba 692 vector = (uint32_t)&CAN3_IRQ_BUS_VECT;
marcozecchini 0:9fca2b23d0ba 693 break;
marcozecchini 0:9fca2b23d0ba 694 default:
marcozecchini 0:9fca2b23d0ba 695 return;
marcozecchini 0:9fca2b23d0ba 696 }
marcozecchini 0:9fca2b23d0ba 697 }
marcozecchini 0:9fca2b23d0ba 698 #endif
marcozecchini 0:9fca2b23d0ba 699 else {
marcozecchini 0:9fca2b23d0ba 700 return;
marcozecchini 0:9fca2b23d0ba 701 }
marcozecchini 0:9fca2b23d0ba 702
marcozecchini 0:9fca2b23d0ba 703 if (enable) {
marcozecchini 0:9fca2b23d0ba 704 can->IER |= ier;
marcozecchini 0:9fca2b23d0ba 705 } else {
marcozecchini 0:9fca2b23d0ba 706 can->IER &= ~ier;
marcozecchini 0:9fca2b23d0ba 707 }
marcozecchini 0:9fca2b23d0ba 708
marcozecchini 0:9fca2b23d0ba 709 NVIC_SetVector(irq_n, vector);
marcozecchini 0:9fca2b23d0ba 710 NVIC_EnableIRQ(irq_n);
marcozecchini 0:9fca2b23d0ba 711 }
marcozecchini 0:9fca2b23d0ba 712
marcozecchini 0:9fca2b23d0ba 713 #endif // DEVICE_CAN
marcozecchini 0:9fca2b23d0ba 714