Diff: DW1000/DW1000.cpp

Revision:

37:40f94c634c3e

Parent:

36:883de6f9a73b

Child:

38:8ef3b8d8b908

--- a/DW1000/DW1000.cpp	Fri Feb 20 09:07:52 2015 +0000
+++ b/DW1000/DW1000.cpp	Fri Feb 20 13:21:06 2015 +0000
@@ -7,7 +7,7 @@
     spi.format(8,0);                    // Setup the spi for standard 8 bit data and SPI-Mode 0 (GPIO5, GPIO6 open circuit or ground on DW1000)
     spi.frequency(1000000);             // with a 1MHz clock rate (worked up to 49MHz in our Test)
     
-    //resetAll();                         // we do a soft reset of the DW1000 everytime the driver starts
+    resetAll();                         // we do a soft reset of the DW1000 everytime the driver starts
     loadLDE();                          // important everytime DW1000 initialises/awakes otherwise the LDE algorithm must be turned of or there's receiving malfunction see User Manual LDELOAD on p22 & p158
     
     // Configuration TODO: make method for that
@@ -83,10 +83,22 @@
     if (length >= 1021) length = 1021;                              // check for maximim length a frame can have            TODO: 127 Byte mode?
     writeRegister(DW1000_TX_BUFFER, 0, message, length);            // fill buffer
     
-    uint8_t backup = readRegister8(DW1000_TX_FCTRL, 1);             // put length of frame
-    length += 2;                                                    // including 2 CRC Bytes
-    length = ((backup & 0xFC) << 8) | (length & 0x03FF);
-    writeRegister16(DW1000_TX_FCTRL, 0, length);
+    #if 0 // switch draft for slower data rate and original working 6.8Mbps
+        uint8_t backup = readRegister8(DW1000_TX_FCTRL, 1);             // put length of frame
+        length += 2;                                                    // including 2 CRC Bytes
+        //length = ((backup & 0xFC) << 8) | (length & 0x03FF);
+        length = ((0xA0 & 0xFC) << 8) | (length & 0x03FF); // for slower data rate and therefore more range   TODO: put in a modular configuration not a fixed value
+        writeRegister16(DW1000_TX_FCTRL, 0, length);
+        
+        backup = readRegister8(DW1000_TX_FCTRL, 2); // change preamble length
+        uint8_t preamble_reg = (backup & 0xC0) | (0x29 & 0x3F); // for longer preamble to match slower data rate   TODO: put in a modular configuration not a fixed value
+        writeRegister8(DW1000_TX_FCTRL, 2, preamble_reg);
+    #else
+        uint8_t backup = readRegister8(DW1000_TX_FCTRL, 1);             // put length of frame
+        length += 2;                                                    // including 2 CRC Bytes
+        length = ((backup & 0xFC) << 8) | (length & 0x03FF);
+        writeRegister16(DW1000_TX_FCTRL, 0, length);
+    #endif
     
     stopTRX();                                                      // stop receiving
     writeRegister8(DW1000_SYS_CTRL, 0, 0x02);                       // trigger sending process by setting the TXSTRT bit