Manh Pham / Mbed OS Nucleo_rtos_basic_ir_controller

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mbed-os/cmsis/TARGET_CORTEX_A/core_ca.h@0:c8673aa96267, 2018-04-07 (annotated)

Committer:
manhpham
Date:
Sat Apr 07 09:22:54 2018 +0000
Revision:
0:c8673aa96267
Nucleo_rtos_basic_ir_controller

Who changed what in which revision?

UserRevisionLine numberNew contents of line
manhpham 0:c8673aa96267 1 /**************************************************************************//**
manhpham 0:c8673aa96267 2 * @file core_ca.h
manhpham 0:c8673aa96267 3 * @brief CMSIS Cortex-A Core Peripheral Access Layer Header File
manhpham 0:c8673aa96267 4 * @version V1.00
manhpham 0:c8673aa96267 5 * @date 22. Feb 2017
manhpham 0:c8673aa96267 6 ******************************************************************************/
manhpham 0:c8673aa96267 7 /*
manhpham 0:c8673aa96267 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
manhpham 0:c8673aa96267 9 *
manhpham 0:c8673aa96267 10 * SPDX-License-Identifier: Apache-2.0
manhpham 0:c8673aa96267 11 *
manhpham 0:c8673aa96267 12 * Licensed under the Apache License, Version 2.0 (the License); you may
manhpham 0:c8673aa96267 13 * not use this file except in compliance with the License.
manhpham 0:c8673aa96267 14 * You may obtain a copy of the License at
manhpham 0:c8673aa96267 15 *
manhpham 0:c8673aa96267 16 * www.apache.org/licenses/LICENSE-2.0
manhpham 0:c8673aa96267 17 *
manhpham 0:c8673aa96267 18 * Unless required by applicable law or agreed to in writing, software
manhpham 0:c8673aa96267 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
manhpham 0:c8673aa96267 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
manhpham 0:c8673aa96267 21 * See the License for the specific language governing permissions and
manhpham 0:c8673aa96267 22 * limitations under the License.
manhpham 0:c8673aa96267 23 */
manhpham 0:c8673aa96267 24
manhpham 0:c8673aa96267 25 #if defined ( __ICCARM__ )
manhpham 0:c8673aa96267 26 #pragma system_include /* treat file as system include file for MISRA check */
manhpham 0:c8673aa96267 27 #elif defined (__clang__)
manhpham 0:c8673aa96267 28 #pragma clang system_header /* treat file as system include file */
manhpham 0:c8673aa96267 29 #endif
manhpham 0:c8673aa96267 30
manhpham 0:c8673aa96267 31 #ifdef __cplusplus
manhpham 0:c8673aa96267 32 extern "C" {
manhpham 0:c8673aa96267 33 #endif
manhpham 0:c8673aa96267 34
manhpham 0:c8673aa96267 35 #ifndef __CORE_CA_H_GENERIC
manhpham 0:c8673aa96267 36 #define __CORE_CA_H_GENERIC
manhpham 0:c8673aa96267 37
manhpham 0:c8673aa96267 38
manhpham 0:c8673aa96267 39 /*******************************************************************************
manhpham 0:c8673aa96267 40 * CMSIS definitions
manhpham 0:c8673aa96267 41 ******************************************************************************/
manhpham 0:c8673aa96267 42
manhpham 0:c8673aa96267 43 /* CMSIS CA definitions */
manhpham 0:c8673aa96267 44 #define __CA_CMSIS_VERSION_MAIN (1U) /*!< \brief [31:16] CMSIS-Core(A) main version */
manhpham 0:c8673aa96267 45 #define __CA_CMSIS_VERSION_SUB (1U) /*!< \brief [15:0] CMSIS-Core(A) sub version */
manhpham 0:c8673aa96267 46 #define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \
manhpham 0:c8673aa96267 47 __CA_CMSIS_VERSION_SUB ) /*!< \brief CMSIS-Core(A) version number */
manhpham 0:c8673aa96267 48
manhpham 0:c8673aa96267 49 #if defined ( __CC_ARM )
manhpham 0:c8673aa96267 50 #if defined __TARGET_FPU_VFP
manhpham 0:c8673aa96267 51 #if (__FPU_PRESENT == 1)
manhpham 0:c8673aa96267 52 #define __FPU_USED 1U
manhpham 0:c8673aa96267 53 #else
manhpham 0:c8673aa96267 54 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
manhpham 0:c8673aa96267 55 #define __FPU_USED 0U
manhpham 0:c8673aa96267 56 #endif
manhpham 0:c8673aa96267 57 #else
manhpham 0:c8673aa96267 58 #define __FPU_USED 0U
manhpham 0:c8673aa96267 59 #endif
manhpham 0:c8673aa96267 60
manhpham 0:c8673aa96267 61 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
manhpham 0:c8673aa96267 62 #if defined __ARM_PCS_VFP
manhpham 0:c8673aa96267 63 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
manhpham 0:c8673aa96267 64 #define __FPU_USED 1U
manhpham 0:c8673aa96267 65 #else
manhpham 0:c8673aa96267 66 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
manhpham 0:c8673aa96267 67 #define __FPU_USED 0U
manhpham 0:c8673aa96267 68 #endif
manhpham 0:c8673aa96267 69 #else
manhpham 0:c8673aa96267 70 #define __FPU_USED 0U
manhpham 0:c8673aa96267 71 #endif
manhpham 0:c8673aa96267 72
manhpham 0:c8673aa96267 73 #elif defined ( __ICCARM__ )
manhpham 0:c8673aa96267 74 #if defined __ARMVFP__
manhpham 0:c8673aa96267 75 #if (__FPU_PRESENT == 1)
manhpham 0:c8673aa96267 76 #define __FPU_USED 1U
manhpham 0:c8673aa96267 77 #else
manhpham 0:c8673aa96267 78 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
manhpham 0:c8673aa96267 79 #define __FPU_USED 0U
manhpham 0:c8673aa96267 80 #endif
manhpham 0:c8673aa96267 81 #else
manhpham 0:c8673aa96267 82 #define __FPU_USED 0U
manhpham 0:c8673aa96267 83 #endif
manhpham 0:c8673aa96267 84
manhpham 0:c8673aa96267 85 #elif defined ( __TMS470__ )
manhpham 0:c8673aa96267 86 #if defined __TI_VFP_SUPPORT__
manhpham 0:c8673aa96267 87 #if (__FPU_PRESENT == 1)
manhpham 0:c8673aa96267 88 #define __FPU_USED 1U
manhpham 0:c8673aa96267 89 #else
manhpham 0:c8673aa96267 90 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
manhpham 0:c8673aa96267 91 #define __FPU_USED 0U
manhpham 0:c8673aa96267 92 #endif
manhpham 0:c8673aa96267 93 #else
manhpham 0:c8673aa96267 94 #define __FPU_USED 0U
manhpham 0:c8673aa96267 95 #endif
manhpham 0:c8673aa96267 96
manhpham 0:c8673aa96267 97 #elif defined ( __GNUC__ )
manhpham 0:c8673aa96267 98 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
manhpham 0:c8673aa96267 99 #if (__FPU_PRESENT == 1)
manhpham 0:c8673aa96267 100 #define __FPU_USED 1U
manhpham 0:c8673aa96267 101 #else
manhpham 0:c8673aa96267 102 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
manhpham 0:c8673aa96267 103 #define __FPU_USED 0U
manhpham 0:c8673aa96267 104 #endif
manhpham 0:c8673aa96267 105 #else
manhpham 0:c8673aa96267 106 #define __FPU_USED 0U
manhpham 0:c8673aa96267 107 #endif
manhpham 0:c8673aa96267 108
manhpham 0:c8673aa96267 109 #elif defined ( __TASKING__ )
manhpham 0:c8673aa96267 110 #if defined __FPU_VFP__
manhpham 0:c8673aa96267 111 #if (__FPU_PRESENT == 1)
manhpham 0:c8673aa96267 112 #define __FPU_USED 1U
manhpham 0:c8673aa96267 113 #else
manhpham 0:c8673aa96267 114 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
manhpham 0:c8673aa96267 115 #define __FPU_USED 0U
manhpham 0:c8673aa96267 116 #endif
manhpham 0:c8673aa96267 117 #else
manhpham 0:c8673aa96267 118 #define __FPU_USED 0U
manhpham 0:c8673aa96267 119 #endif
manhpham 0:c8673aa96267 120 #endif
manhpham 0:c8673aa96267 121
manhpham 0:c8673aa96267 122 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
manhpham 0:c8673aa96267 123
manhpham 0:c8673aa96267 124 #ifdef __cplusplus
manhpham 0:c8673aa96267 125 }
manhpham 0:c8673aa96267 126 #endif
manhpham 0:c8673aa96267 127
manhpham 0:c8673aa96267 128 #endif /* __CORE_CA_H_GENERIC */
manhpham 0:c8673aa96267 129
manhpham 0:c8673aa96267 130 #ifndef __CMSIS_GENERIC
manhpham 0:c8673aa96267 131
manhpham 0:c8673aa96267 132 #ifndef __CORE_CA_H_DEPENDANT
manhpham 0:c8673aa96267 133 #define __CORE_CA_H_DEPENDANT
manhpham 0:c8673aa96267 134
manhpham 0:c8673aa96267 135 #ifdef __cplusplus
manhpham 0:c8673aa96267 136 extern "C" {
manhpham 0:c8673aa96267 137 #endif
manhpham 0:c8673aa96267 138
manhpham 0:c8673aa96267 139 /* check device defines and use defaults */
manhpham 0:c8673aa96267 140 #if defined __CHECK_DEVICE_DEFINES
manhpham 0:c8673aa96267 141 #ifndef __CA_REV
manhpham 0:c8673aa96267 142 #define __CA_REV 0x0000U
manhpham 0:c8673aa96267 143 #warning "__CA_REV not defined in device header file; using default!"
manhpham 0:c8673aa96267 144 #endif
manhpham 0:c8673aa96267 145
manhpham 0:c8673aa96267 146 #ifndef __FPU_PRESENT
manhpham 0:c8673aa96267 147 #define __FPU_PRESENT 0U
manhpham 0:c8673aa96267 148 #warning "__FPU_PRESENT not defined in device header file; using default!"
manhpham 0:c8673aa96267 149 #endif
manhpham 0:c8673aa96267 150
manhpham 0:c8673aa96267 151 #ifndef __GIC_PRESENT
manhpham 0:c8673aa96267 152 #define __GIC_PRESENT 1U
manhpham 0:c8673aa96267 153 #warning "__GIC_PRESENT not defined in device header file; using default!"
manhpham 0:c8673aa96267 154 #endif
manhpham 0:c8673aa96267 155
manhpham 0:c8673aa96267 156 #ifndef __TIM_PRESENT
manhpham 0:c8673aa96267 157 #define __TIM_PRESENT 1U
manhpham 0:c8673aa96267 158 #warning "__TIM_PRESENT not defined in device header file; using default!"
manhpham 0:c8673aa96267 159 #endif
manhpham 0:c8673aa96267 160
manhpham 0:c8673aa96267 161 #ifndef __L2C_PRESENT
manhpham 0:c8673aa96267 162 #define __L2C_PRESENT 0U
manhpham 0:c8673aa96267 163 #warning "__L2C_PRESENT not defined in device header file; using default!"
manhpham 0:c8673aa96267 164 #endif
manhpham 0:c8673aa96267 165 #endif
manhpham 0:c8673aa96267 166
manhpham 0:c8673aa96267 167 /* IO definitions (access restrictions to peripheral registers) */
manhpham 0:c8673aa96267 168 #ifdef __cplusplus
manhpham 0:c8673aa96267 169 #define __I volatile /*!< \brief Defines 'read only' permissions */
manhpham 0:c8673aa96267 170 #else
manhpham 0:c8673aa96267 171 #define __I volatile const /*!< \brief Defines 'read only' permissions */
manhpham 0:c8673aa96267 172 #endif
manhpham 0:c8673aa96267 173 #define __O volatile /*!< \brief Defines 'write only' permissions */
manhpham 0:c8673aa96267 174 #define __IO volatile /*!< \brief Defines 'read / write' permissions */
manhpham 0:c8673aa96267 175
manhpham 0:c8673aa96267 176 /* following defines should be used for structure members */
manhpham 0:c8673aa96267 177 #define __IM volatile const /*!< \brief Defines 'read only' structure member permissions */
manhpham 0:c8673aa96267 178 #define __OM volatile /*!< \brief Defines 'write only' structure member permissions */
manhpham 0:c8673aa96267 179 #define __IOM volatile /*!< \brief Defines 'read / write' structure member permissions */
manhpham 0:c8673aa96267 180 #define RESERVED(N, T) T RESERVED##N; // placeholder struct members used for "reserved" areas
manhpham 0:c8673aa96267 181
manhpham 0:c8673aa96267 182 /*******************************************************************************
manhpham 0:c8673aa96267 183 * Register Abstraction
manhpham 0:c8673aa96267 184 Core Register contain:
manhpham 0:c8673aa96267 185 - CPSR
manhpham 0:c8673aa96267 186 - CP15 Registers
manhpham 0:c8673aa96267 187 - L2C-310 Cache Controller
manhpham 0:c8673aa96267 188 - Generic Interrupt Controller Distributor
manhpham 0:c8673aa96267 189 - Generic Interrupt Controller Interface
manhpham 0:c8673aa96267 190 ******************************************************************************/
manhpham 0:c8673aa96267 191
manhpham 0:c8673aa96267 192 /* Core Register CPSR */
manhpham 0:c8673aa96267 193 typedef union
manhpham 0:c8673aa96267 194 {
manhpham 0:c8673aa96267 195 struct
manhpham 0:c8673aa96267 196 {
manhpham 0:c8673aa96267 197 uint32_t M:5; /*!< \brief bit: 0.. 4 Mode field */
manhpham 0:c8673aa96267 198 uint32_t T:1; /*!< \brief bit: 5 Thumb execution state bit */
manhpham 0:c8673aa96267 199 uint32_t F:1; /*!< \brief bit: 6 FIQ mask bit */
manhpham 0:c8673aa96267 200 uint32_t I:1; /*!< \brief bit: 7 IRQ mask bit */
manhpham 0:c8673aa96267 201 uint32_t A:1; /*!< \brief bit: 8 Asynchronous abort mask bit */
manhpham 0:c8673aa96267 202 uint32_t E:1; /*!< \brief bit: 9 Endianness execution state bit */
manhpham 0:c8673aa96267 203 uint32_t IT1:6; /*!< \brief bit: 10..15 If-Then execution state bits 2-7 */
manhpham 0:c8673aa96267 204 uint32_t GE:4; /*!< \brief bit: 16..19 Greater than or Equal flags */
manhpham 0:c8673aa96267 205 RESERVED(0:4, uint32_t)
manhpham 0:c8673aa96267 206 uint32_t J:1; /*!< \brief bit: 24 Jazelle bit */
manhpham 0:c8673aa96267 207 uint32_t IT0:2; /*!< \brief bit: 25..26 If-Then execution state bits 0-1 */
manhpham 0:c8673aa96267 208 uint32_t Q:1; /*!< \brief bit: 27 Saturation condition flag */
manhpham 0:c8673aa96267 209 uint32_t V:1; /*!< \brief bit: 28 Overflow condition code flag */
manhpham 0:c8673aa96267 210 uint32_t C:1; /*!< \brief bit: 29 Carry condition code flag */
manhpham 0:c8673aa96267 211 uint32_t Z:1; /*!< \brief bit: 30 Zero condition code flag */
manhpham 0:c8673aa96267 212 uint32_t N:1; /*!< \brief bit: 31 Negative condition code flag */
manhpham 0:c8673aa96267 213 } b; /*!< \brief Structure used for bit access */
manhpham 0:c8673aa96267 214 uint32_t w; /*!< \brief Type used for word access */
manhpham 0:c8673aa96267 215 } CPSR_Type;
manhpham 0:c8673aa96267 216
manhpham 0:c8673aa96267 217
manhpham 0:c8673aa96267 218
manhpham 0:c8673aa96267 219 /* CPSR Register Definitions */
manhpham 0:c8673aa96267 220 #define CPSR_N_Pos 31U /*!< \brief CPSR: N Position */
manhpham 0:c8673aa96267 221 #define CPSR_N_Msk (1UL << CPSR_N_Pos) /*!< \brief CPSR: N Mask */
manhpham 0:c8673aa96267 222
manhpham 0:c8673aa96267 223 #define CPSR_Z_Pos 30U /*!< \brief CPSR: Z Position */
manhpham 0:c8673aa96267 224 #define CPSR_Z_Msk (1UL << CPSR_Z_Pos) /*!< \brief CPSR: Z Mask */
manhpham 0:c8673aa96267 225
manhpham 0:c8673aa96267 226 #define CPSR_C_Pos 29U /*!< \brief CPSR: C Position */
manhpham 0:c8673aa96267 227 #define CPSR_C_Msk (1UL << CPSR_C_Pos) /*!< \brief CPSR: C Mask */
manhpham 0:c8673aa96267 228
manhpham 0:c8673aa96267 229 #define CPSR_V_Pos 28U /*!< \brief CPSR: V Position */
manhpham 0:c8673aa96267 230 #define CPSR_V_Msk (1UL << CPSR_V_Pos) /*!< \brief CPSR: V Mask */
manhpham 0:c8673aa96267 231
manhpham 0:c8673aa96267 232 #define CPSR_Q_Pos 27U /*!< \brief CPSR: Q Position */
manhpham 0:c8673aa96267 233 #define CPSR_Q_Msk (1UL << CPSR_Q_Pos) /*!< \brief CPSR: Q Mask */
manhpham 0:c8673aa96267 234
manhpham 0:c8673aa96267 235 #define CPSR_IT0_Pos 25U /*!< \brief CPSR: IT0 Position */
manhpham 0:c8673aa96267 236 #define CPSR_IT0_Msk (3UL << CPSR_IT0_Pos) /*!< \brief CPSR: IT0 Mask */
manhpham 0:c8673aa96267 237
manhpham 0:c8673aa96267 238 #define CPSR_J_Pos 24U /*!< \brief CPSR: J Position */
manhpham 0:c8673aa96267 239 #define CPSR_J_Msk (1UL << CPSR_J_Pos) /*!< \brief CPSR: J Mask */
manhpham 0:c8673aa96267 240
manhpham 0:c8673aa96267 241 #define CPSR_GE_Pos 16U /*!< \brief CPSR: GE Position */
manhpham 0:c8673aa96267 242 #define CPSR_GE_Msk (0xFUL << CPSR_GE_Pos) /*!< \brief CPSR: GE Mask */
manhpham 0:c8673aa96267 243
manhpham 0:c8673aa96267 244 #define CPSR_IT1_Pos 10U /*!< \brief CPSR: IT1 Position */
manhpham 0:c8673aa96267 245 #define CPSR_IT1_Msk (0x3FUL << CPSR_IT1_Pos) /*!< \brief CPSR: IT1 Mask */
manhpham 0:c8673aa96267 246
manhpham 0:c8673aa96267 247 #define CPSR_E_Pos 9U /*!< \brief CPSR: E Position */
manhpham 0:c8673aa96267 248 #define CPSR_E_Msk (1UL << CPSR_E_Pos) /*!< \brief CPSR: E Mask */
manhpham 0:c8673aa96267 249
manhpham 0:c8673aa96267 250 #define CPSR_A_Pos 8U /*!< \brief CPSR: A Position */
manhpham 0:c8673aa96267 251 #define CPSR_A_Msk (1UL << CPSR_A_Pos) /*!< \brief CPSR: A Mask */
manhpham 0:c8673aa96267 252
manhpham 0:c8673aa96267 253 #define CPSR_I_Pos 7U /*!< \brief CPSR: I Position */
manhpham 0:c8673aa96267 254 #define CPSR_I_Msk (1UL << CPSR_I_Pos) /*!< \brief CPSR: I Mask */
manhpham 0:c8673aa96267 255
manhpham 0:c8673aa96267 256 #define CPSR_F_Pos 6U /*!< \brief CPSR: F Position */
manhpham 0:c8673aa96267 257 #define CPSR_F_Msk (1UL << CPSR_F_Pos) /*!< \brief CPSR: F Mask */
manhpham 0:c8673aa96267 258
manhpham 0:c8673aa96267 259 #define CPSR_T_Pos 5U /*!< \brief CPSR: T Position */
manhpham 0:c8673aa96267 260 #define CPSR_T_Msk (1UL << CPSR_T_Pos) /*!< \brief CPSR: T Mask */
manhpham 0:c8673aa96267 261
manhpham 0:c8673aa96267 262 #define CPSR_M_Pos 0U /*!< \brief CPSR: M Position */
manhpham 0:c8673aa96267 263 #define CPSR_M_Msk (0x1FUL << CPSR_M_Pos) /*!< \brief CPSR: M Mask */
manhpham 0:c8673aa96267 264
manhpham 0:c8673aa96267 265 #define CPSR_M_USR 0x10U /*!< \brief CPSR: M User mode (PL0) */
manhpham 0:c8673aa96267 266 #define CPSR_M_FIQ 0x11U /*!< \brief CPSR: M Fast Interrupt mode (PL1) */
manhpham 0:c8673aa96267 267 #define CPSR_M_IRQ 0x12U /*!< \brief CPSR: M Interrupt mode (PL1) */
manhpham 0:c8673aa96267 268 #define CPSR_M_SVC 0x13U /*!< \brief CPSR: M Supervisor mode (PL1) */
manhpham 0:c8673aa96267 269 #define CPSR_M_MON 0x16U /*!< \brief CPSR: M Monitor mode (PL1) */
manhpham 0:c8673aa96267 270 #define CPSR_M_ABT 0x17U /*!< \brief CPSR: M Abort mode (PL1) */
manhpham 0:c8673aa96267 271 #define CPSR_M_HYP 0x1AU /*!< \brief CPSR: M Hypervisor mode (PL2) */
manhpham 0:c8673aa96267 272 #define CPSR_M_UND 0x1BU /*!< \brief CPSR: M Undefined mode (PL1) */
manhpham 0:c8673aa96267 273 #define CPSR_M_SYS 0x1FU /*!< \brief CPSR: M System mode (PL1) */
manhpham 0:c8673aa96267 274
manhpham 0:c8673aa96267 275 /* CP15 Register SCTLR */
manhpham 0:c8673aa96267 276 typedef union
manhpham 0:c8673aa96267 277 {
manhpham 0:c8673aa96267 278 struct
manhpham 0:c8673aa96267 279 {
manhpham 0:c8673aa96267 280 uint32_t M:1; /*!< \brief bit: 0 MMU enable */
manhpham 0:c8673aa96267 281 uint32_t A:1; /*!< \brief bit: 1 Alignment check enable */
manhpham 0:c8673aa96267 282 uint32_t C:1; /*!< \brief bit: 2 Cache enable */
manhpham 0:c8673aa96267 283 RESERVED(0:2, uint32_t)
manhpham 0:c8673aa96267 284 uint32_t CP15BEN:1; /*!< \brief bit: 5 CP15 barrier enable */
manhpham 0:c8673aa96267 285 RESERVED(1:1, uint32_t)
manhpham 0:c8673aa96267 286 uint32_t B:1; /*!< \brief bit: 7 Endianness model */
manhpham 0:c8673aa96267 287 RESERVED(2:2, uint32_t)
manhpham 0:c8673aa96267 288 uint32_t SW:1; /*!< \brief bit: 10 SWP and SWPB enable */
manhpham 0:c8673aa96267 289 uint32_t Z:1; /*!< \brief bit: 11 Branch prediction enable */
manhpham 0:c8673aa96267 290 uint32_t I:1; /*!< \brief bit: 12 Instruction cache enable */
manhpham 0:c8673aa96267 291 uint32_t V:1; /*!< \brief bit: 13 Vectors bit */
manhpham 0:c8673aa96267 292 uint32_t RR:1; /*!< \brief bit: 14 Round Robin select */
manhpham 0:c8673aa96267 293 RESERVED(3:2, uint32_t)
manhpham 0:c8673aa96267 294 uint32_t HA:1; /*!< \brief bit: 17 Hardware Access flag enable */
manhpham 0:c8673aa96267 295 RESERVED(4:1, uint32_t)
manhpham 0:c8673aa96267 296 uint32_t WXN:1; /*!< \brief bit: 19 Write permission implies XN */
manhpham 0:c8673aa96267 297 uint32_t UWXN:1; /*!< \brief bit: 20 Unprivileged write permission implies PL1 XN */
manhpham 0:c8673aa96267 298 uint32_t FI:1; /*!< \brief bit: 21 Fast interrupts configuration enable */
manhpham 0:c8673aa96267 299 uint32_t U:1; /*!< \brief bit: 22 Alignment model */
manhpham 0:c8673aa96267 300 RESERVED(5:1, uint32_t)
manhpham 0:c8673aa96267 301 uint32_t VE:1; /*!< \brief bit: 24 Interrupt Vectors Enable */
manhpham 0:c8673aa96267 302 uint32_t EE:1; /*!< \brief bit: 25 Exception Endianness */
manhpham 0:c8673aa96267 303 RESERVED(6:1, uint32_t)
manhpham 0:c8673aa96267 304 uint32_t NMFI:1; /*!< \brief bit: 27 Non-maskable FIQ (NMFI) support */
manhpham 0:c8673aa96267 305 uint32_t TRE:1; /*!< \brief bit: 28 TEX remap enable. */
manhpham 0:c8673aa96267 306 uint32_t AFE:1; /*!< \brief bit: 29 Access flag enable */
manhpham 0:c8673aa96267 307 uint32_t TE:1; /*!< \brief bit: 30 Thumb Exception enable */
manhpham 0:c8673aa96267 308 RESERVED(7:1, uint32_t)
manhpham 0:c8673aa96267 309 } b; /*!< \brief Structure used for bit access */
manhpham 0:c8673aa96267 310 uint32_t w; /*!< \brief Type used for word access */
manhpham 0:c8673aa96267 311 } SCTLR_Type;
manhpham 0:c8673aa96267 312
manhpham 0:c8673aa96267 313 #define SCTLR_TE_Pos 30U /*!< \brief SCTLR: TE Position */
manhpham 0:c8673aa96267 314 #define SCTLR_TE_Msk (1UL << SCTLR_TE_Pos) /*!< \brief SCTLR: TE Mask */
manhpham 0:c8673aa96267 315
manhpham 0:c8673aa96267 316 #define SCTLR_AFE_Pos 29U /*!< \brief SCTLR: AFE Position */
manhpham 0:c8673aa96267 317 #define SCTLR_AFE_Msk (1UL << SCTLR_AFE_Pos) /*!< \brief SCTLR: AFE Mask */
manhpham 0:c8673aa96267 318
manhpham 0:c8673aa96267 319 #define SCTLR_TRE_Pos 28U /*!< \brief SCTLR: TRE Position */
manhpham 0:c8673aa96267 320 #define SCTLR_TRE_Msk (1UL << SCTLR_TRE_Pos) /*!< \brief SCTLR: TRE Mask */
manhpham 0:c8673aa96267 321
manhpham 0:c8673aa96267 322 #define SCTLR_NMFI_Pos 27U /*!< \brief SCTLR: NMFI Position */
manhpham 0:c8673aa96267 323 #define SCTLR_NMFI_Msk (1UL << SCTLR_NMFI_Pos) /*!< \brief SCTLR: NMFI Mask */
manhpham 0:c8673aa96267 324
manhpham 0:c8673aa96267 325 #define SCTLR_EE_Pos 25U /*!< \brief SCTLR: EE Position */
manhpham 0:c8673aa96267 326 #define SCTLR_EE_Msk (1UL << SCTLR_EE_Pos) /*!< \brief SCTLR: EE Mask */
manhpham 0:c8673aa96267 327
manhpham 0:c8673aa96267 328 #define SCTLR_VE_Pos 24U /*!< \brief SCTLR: VE Position */
manhpham 0:c8673aa96267 329 #define SCTLR_VE_Msk (1UL << SCTLR_VE_Pos) /*!< \brief SCTLR: VE Mask */
manhpham 0:c8673aa96267 330
manhpham 0:c8673aa96267 331 #define SCTLR_U_Pos 22U /*!< \brief SCTLR: U Position */
manhpham 0:c8673aa96267 332 #define SCTLR_U_Msk (1UL << SCTLR_U_Pos) /*!< \brief SCTLR: U Mask */
manhpham 0:c8673aa96267 333
manhpham 0:c8673aa96267 334 #define SCTLR_FI_Pos 21U /*!< \brief SCTLR: FI Position */
manhpham 0:c8673aa96267 335 #define SCTLR_FI_Msk (1UL << SCTLR_FI_Pos) /*!< \brief SCTLR: FI Mask */
manhpham 0:c8673aa96267 336
manhpham 0:c8673aa96267 337 #define SCTLR_UWXN_Pos 20U /*!< \brief SCTLR: UWXN Position */
manhpham 0:c8673aa96267 338 #define SCTLR_UWXN_Msk (1UL << SCTLR_UWXN_Pos) /*!< \brief SCTLR: UWXN Mask */
manhpham 0:c8673aa96267 339
manhpham 0:c8673aa96267 340 #define SCTLR_WXN_Pos 19U /*!< \brief SCTLR: WXN Position */
manhpham 0:c8673aa96267 341 #define SCTLR_WXN_Msk (1UL << SCTLR_WXN_Pos) /*!< \brief SCTLR: WXN Mask */
manhpham 0:c8673aa96267 342
manhpham 0:c8673aa96267 343 #define SCTLR_HA_Pos 17U /*!< \brief SCTLR: HA Position */
manhpham 0:c8673aa96267 344 #define SCTLR_HA_Msk (1UL << SCTLR_HA_Pos) /*!< \brief SCTLR: HA Mask */
manhpham 0:c8673aa96267 345
manhpham 0:c8673aa96267 346 #define SCTLR_RR_Pos 14U /*!< \brief SCTLR: RR Position */
manhpham 0:c8673aa96267 347 #define SCTLR_RR_Msk (1UL << SCTLR_RR_Pos) /*!< \brief SCTLR: RR Mask */
manhpham 0:c8673aa96267 348
manhpham 0:c8673aa96267 349 #define SCTLR_V_Pos 13U /*!< \brief SCTLR: V Position */
manhpham 0:c8673aa96267 350 #define SCTLR_V_Msk (1UL << SCTLR_V_Pos) /*!< \brief SCTLR: V Mask */
manhpham 0:c8673aa96267 351
manhpham 0:c8673aa96267 352 #define SCTLR_I_Pos 12U /*!< \brief SCTLR: I Position */
manhpham 0:c8673aa96267 353 #define SCTLR_I_Msk (1UL << SCTLR_I_Pos) /*!< \brief SCTLR: I Mask */
manhpham 0:c8673aa96267 354
manhpham 0:c8673aa96267 355 #define SCTLR_Z_Pos 11U /*!< \brief SCTLR: Z Position */
manhpham 0:c8673aa96267 356 #define SCTLR_Z_Msk (1UL << SCTLR_Z_Pos) /*!< \brief SCTLR: Z Mask */
manhpham 0:c8673aa96267 357
manhpham 0:c8673aa96267 358 #define SCTLR_SW_Pos 10U /*!< \brief SCTLR: SW Position */
manhpham 0:c8673aa96267 359 #define SCTLR_SW_Msk (1UL << SCTLR_SW_Pos) /*!< \brief SCTLR: SW Mask */
manhpham 0:c8673aa96267 360
manhpham 0:c8673aa96267 361 #define SCTLR_B_Pos 7U /*!< \brief SCTLR: B Position */
manhpham 0:c8673aa96267 362 #define SCTLR_B_Msk (1UL << SCTLR_B_Pos) /*!< \brief SCTLR: B Mask */
manhpham 0:c8673aa96267 363
manhpham 0:c8673aa96267 364 #define SCTLR_CP15BEN_Pos 5U /*!< \brief SCTLR: CP15BEN Position */
manhpham 0:c8673aa96267 365 #define SCTLR_CP15BEN_Msk (1UL << SCTLR_CP15BEN_Pos) /*!< \brief SCTLR: CP15BEN Mask */
manhpham 0:c8673aa96267 366
manhpham 0:c8673aa96267 367 #define SCTLR_C_Pos 2U /*!< \brief SCTLR: C Position */
manhpham 0:c8673aa96267 368 #define SCTLR_C_Msk (1UL << SCTLR_C_Pos) /*!< \brief SCTLR: C Mask */
manhpham 0:c8673aa96267 369
manhpham 0:c8673aa96267 370 #define SCTLR_A_Pos 1U /*!< \brief SCTLR: A Position */
manhpham 0:c8673aa96267 371 #define SCTLR_A_Msk (1UL << SCTLR_A_Pos) /*!< \brief SCTLR: A Mask */
manhpham 0:c8673aa96267 372
manhpham 0:c8673aa96267 373 #define SCTLR_M_Pos 0U /*!< \brief SCTLR: M Position */
manhpham 0:c8673aa96267 374 #define SCTLR_M_Msk (1UL << SCTLR_M_Pos) /*!< \brief SCTLR: M Mask */
manhpham 0:c8673aa96267 375
manhpham 0:c8673aa96267 376 /* CP15 Register ACTLR */
manhpham 0:c8673aa96267 377 typedef union
manhpham 0:c8673aa96267 378 {
manhpham 0:c8673aa96267 379 #if __CORTEX_A == 5 || defined(DOXYGEN)
manhpham 0:c8673aa96267 380 /** \brief Structure used for bit access on Cortex-A5 */
manhpham 0:c8673aa96267 381 struct
manhpham 0:c8673aa96267 382 {
manhpham 0:c8673aa96267 383 uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */
manhpham 0:c8673aa96267 384 RESERVED(0:5, uint32_t)
manhpham 0:c8673aa96267 385 uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */
manhpham 0:c8673aa96267 386 uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */
manhpham 0:c8673aa96267 387 RESERVED(1:2, uint32_t)
manhpham 0:c8673aa96267 388 uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */
manhpham 0:c8673aa96267 389 uint32_t DWBST:1; /*!< \brief bit: 11 AXI data write bursts to Normal memory */
manhpham 0:c8673aa96267 390 uint32_t RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */
manhpham 0:c8673aa96267 391 uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */
manhpham 0:c8673aa96267 392 uint32_t BP:2; /*!< \brief bit:16..15 Branch prediction policy */
manhpham 0:c8673aa96267 393 uint32_t RSDIS:1; /*!< \brief bit: 17 Disable return stack operation */
manhpham 0:c8673aa96267 394 uint32_t BTDIS:1; /*!< \brief bit: 18 Disable indirect Branch Target Address Cache (BTAC) */
manhpham 0:c8673aa96267 395 RESERVED(3:9, uint32_t)
manhpham 0:c8673aa96267 396 uint32_t DBDI:1; /*!< \brief bit: 28 Disable branch dual issue */
manhpham 0:c8673aa96267 397 RESERVED(7:3, uint32_t)
manhpham 0:c8673aa96267 398 } b;
manhpham 0:c8673aa96267 399 #endif
manhpham 0:c8673aa96267 400 #if __CORTEX_A == 7 || defined(DOXYGEN)
manhpham 0:c8673aa96267 401 /** \brief Structure used for bit access on Cortex-A7 */
manhpham 0:c8673aa96267 402 struct
manhpham 0:c8673aa96267 403 {
manhpham 0:c8673aa96267 404 RESERVED(0:6, uint32_t)
manhpham 0:c8673aa96267 405 uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */
manhpham 0:c8673aa96267 406 RESERVED(1:3, uint32_t)
manhpham 0:c8673aa96267 407 uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */
manhpham 0:c8673aa96267 408 uint32_t L2RADIS:1; /*!< \brief bit: 11 L2 Data Cache read-allocate mode disable */
manhpham 0:c8673aa96267 409 uint32_t L1RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */
manhpham 0:c8673aa96267 410 uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */
manhpham 0:c8673aa96267 411 uint32_t DDVM:1; /*!< \brief bit: 15 Disable Distributed Virtual Memory (DVM) transactions */
manhpham 0:c8673aa96267 412 RESERVED(3:12, uint32_t)
manhpham 0:c8673aa96267 413 uint32_t DDI:1; /*!< \brief bit: 28 Disable dual issue */
manhpham 0:c8673aa96267 414 RESERVED(7:3, uint32_t)
manhpham 0:c8673aa96267 415 } b;
manhpham 0:c8673aa96267 416 #endif
manhpham 0:c8673aa96267 417 #if __CORTEX_A == 9 || defined(DOXYGEN)
manhpham 0:c8673aa96267 418 /** \brief Structure used for bit access on Cortex-A9 */
manhpham 0:c8673aa96267 419 struct
manhpham 0:c8673aa96267 420 {
manhpham 0:c8673aa96267 421 uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */
manhpham 0:c8673aa96267 422 RESERVED(0:1, uint32_t)
manhpham 0:c8673aa96267 423 uint32_t L1PE:1; /*!< \brief bit: 2 Dside prefetch */
manhpham 0:c8673aa96267 424 uint32_t WFLZM:1; /*!< \brief bit: 3 Cache and TLB maintenance broadcast */
manhpham 0:c8673aa96267 425 RESERVED(1:2, uint32_t)
manhpham 0:c8673aa96267 426 uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */
manhpham 0:c8673aa96267 427 uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */
manhpham 0:c8673aa96267 428 uint32_t AOW:1; /*!< \brief bit: 8 Enable allocation in one cache way only */
manhpham 0:c8673aa96267 429 uint32_t PARITY:1; /*!< \brief bit: 9 Support for parity checking, if implemented */
manhpham 0:c8673aa96267 430 RESERVED(7:22, uint32_t)
manhpham 0:c8673aa96267 431 } b;
manhpham 0:c8673aa96267 432 #endif
manhpham 0:c8673aa96267 433 uint32_t w; /*!< \brief Type used for word access */
manhpham 0:c8673aa96267 434 } ACTLR_Type;
manhpham 0:c8673aa96267 435
manhpham 0:c8673aa96267 436 #define ACTLR_DDI_Pos 28U /*!< \brief ACTLR: DDI Position */
manhpham 0:c8673aa96267 437 #define ACTLR_DDI_Msk (1UL << ACTLR_DDI_Pos) /*!< \brief ACTLR: DDI Mask */
manhpham 0:c8673aa96267 438
manhpham 0:c8673aa96267 439 #define ACTLR_DBDI_Pos 28U /*!< \brief ACTLR: DBDI Position */
manhpham 0:c8673aa96267 440 #define ACTLR_DBDI_Msk (1UL << ACTLR_DBDI_Pos) /*!< \brief ACTLR: DBDI Mask */
manhpham 0:c8673aa96267 441
manhpham 0:c8673aa96267 442 #define ACTLR_BTDIS_Pos 18U /*!< \brief ACTLR: BTDIS Position */
manhpham 0:c8673aa96267 443 #define ACTLR_BTDIS_Msk (1UL << ACTLR_BTDIS_Pos) /*!< \brief ACTLR: BTDIS Mask */
manhpham 0:c8673aa96267 444
manhpham 0:c8673aa96267 445 #define ACTLR_RSDIS_Pos 17U /*!< \brief ACTLR: RSDIS Position */
manhpham 0:c8673aa96267 446 #define ACTLR_RSDIS_Msk (1UL << ACTLR_RSDIS_Pos) /*!< \brief ACTLR: RSDIS Mask */
manhpham 0:c8673aa96267 447
manhpham 0:c8673aa96267 448 #define ACTLR_BP_Pos 15U /*!< \brief ACTLR: BP Position */
manhpham 0:c8673aa96267 449 #define ACTLR_BP_Msk (3UL << ACTLR_BP_Pos) /*!< \brief ACTLR: BP Mask */
manhpham 0:c8673aa96267 450
manhpham 0:c8673aa96267 451 #define ACTLR_DDVM_Pos 15U /*!< \brief ACTLR: DDVM Position */
manhpham 0:c8673aa96267 452 #define ACTLR_DDVM_Msk (1UL << ACTLR_DDVM_Pos) /*!< \brief ACTLR: DDVM Mask */
manhpham 0:c8673aa96267 453
manhpham 0:c8673aa96267 454 #define ACTLR_L1PCTL_Pos 13U /*!< \brief ACTLR: L1PCTL Position */
manhpham 0:c8673aa96267 455 #define ACTLR_L1PCTL_Msk (3UL << ACTLR_L1PCTL_Pos) /*!< \brief ACTLR: L1PCTL Mask */
manhpham 0:c8673aa96267 456
manhpham 0:c8673aa96267 457 #define ACTLR_RADIS_Pos 12U /*!< \brief ACTLR: RADIS Position */
manhpham 0:c8673aa96267 458 #define ACTLR_RADIS_Msk (1UL << ACTLR_RADIS_Pos) /*!< \brief ACTLR: RADIS Mask */
manhpham 0:c8673aa96267 459
manhpham 0:c8673aa96267 460 #define ACTLR_L1RADIS_Pos 12U /*!< \brief ACTLR: L1RADIS Position */
manhpham 0:c8673aa96267 461 #define ACTLR_L1RADIS_Msk (1UL << ACTLR_L1RADIS_Pos) /*!< \brief ACTLR: L1RADIS Mask */
manhpham 0:c8673aa96267 462
manhpham 0:c8673aa96267 463 #define ACTLR_DWBST_Pos 11U /*!< \brief ACTLR: DWBST Position */
manhpham 0:c8673aa96267 464 #define ACTLR_DWBST_Msk (1UL << ACTLR_DWBST_Pos) /*!< \brief ACTLR: DWBST Mask */
manhpham 0:c8673aa96267 465
manhpham 0:c8673aa96267 466 #define ACTLR_L2RADIS_Pos 11U /*!< \brief ACTLR: L2RADIS Position */
manhpham 0:c8673aa96267 467 #define ACTLR_L2RADIS_Msk (1UL << ACTLR_L2RADIS_Pos) /*!< \brief ACTLR: L2RADIS Mask */
manhpham 0:c8673aa96267 468
manhpham 0:c8673aa96267 469 #define ACTLR_DODMBS_Pos 10U /*!< \brief ACTLR: DODMBS Position */
manhpham 0:c8673aa96267 470 #define ACTLR_DODMBS_Msk (1UL << ACTLR_DODMBS_Pos) /*!< \brief ACTLR: DODMBS Mask */
manhpham 0:c8673aa96267 471
manhpham 0:c8673aa96267 472 #define ACTLR_PARITY_Pos 9U /*!< \brief ACTLR: PARITY Position */
manhpham 0:c8673aa96267 473 #define ACTLR_PARITY_Msk (1UL << ACTLR_PARITY_Pos) /*!< \brief ACTLR: PARITY Mask */
manhpham 0:c8673aa96267 474
manhpham 0:c8673aa96267 475 #define ACTLR_AOW_Pos 8U /*!< \brief ACTLR: AOW Position */
manhpham 0:c8673aa96267 476 #define ACTLR_AOW_Msk (1UL << ACTLR_AOW_Pos) /*!< \brief ACTLR: AOW Mask */
manhpham 0:c8673aa96267 477
manhpham 0:c8673aa96267 478 #define ACTLR_EXCL_Pos 7U /*!< \brief ACTLR: EXCL Position */
manhpham 0:c8673aa96267 479 #define ACTLR_EXCL_Msk (1UL << ACTLR_EXCL_Pos) /*!< \brief ACTLR: EXCL Mask */
manhpham 0:c8673aa96267 480
manhpham 0:c8673aa96267 481 #define ACTLR_SMP_Pos 6U /*!< \brief ACTLR: SMP Position */
manhpham 0:c8673aa96267 482 #define ACTLR_SMP_Msk (1UL << ACTLR_SMP_Pos) /*!< \brief ACTLR: SMP Mask */
manhpham 0:c8673aa96267 483
manhpham 0:c8673aa96267 484 #define ACTLR_WFLZM_Pos 3U /*!< \brief ACTLR: WFLZM Position */
manhpham 0:c8673aa96267 485 #define ACTLR_WFLZM_Msk (1UL << ACTLR_WFLZM_Pos) /*!< \brief ACTLR: WFLZM Mask */
manhpham 0:c8673aa96267 486
manhpham 0:c8673aa96267 487 #define ACTLR_L1PE_Pos 2U /*!< \brief ACTLR: L1PE Position */
manhpham 0:c8673aa96267 488 #define ACTLR_L1PE_Msk (1UL << ACTLR_L1PE_Pos) /*!< \brief ACTLR: L1PE Mask */
manhpham 0:c8673aa96267 489
manhpham 0:c8673aa96267 490 #define ACTLR_FW_Pos 0U /*!< \brief ACTLR: FW Position */
manhpham 0:c8673aa96267 491 #define ACTLR_FW_Msk (1UL << ACTLR_FW_Pos) /*!< \brief ACTLR: FW Mask */
manhpham 0:c8673aa96267 492
manhpham 0:c8673aa96267 493 /* CP15 Register CPACR */
manhpham 0:c8673aa96267 494 typedef union
manhpham 0:c8673aa96267 495 {
manhpham 0:c8673aa96267 496 struct
manhpham 0:c8673aa96267 497 {
manhpham 0:c8673aa96267 498 uint32_t CP0:2; /*!< \brief bit: 0..1 Access rights for coprocessor 0 */
manhpham 0:c8673aa96267 499 uint32_t CP1:2; /*!< \brief bit: 2..3 Access rights for coprocessor 1 */
manhpham 0:c8673aa96267 500 uint32_t CP2:2; /*!< \brief bit: 4..5 Access rights for coprocessor 2 */
manhpham 0:c8673aa96267 501 uint32_t CP3:2; /*!< \brief bit: 6..7 Access rights for coprocessor 3 */
manhpham 0:c8673aa96267 502 uint32_t CP4:2; /*!< \brief bit: 8..9 Access rights for coprocessor 4 */
manhpham 0:c8673aa96267 503 uint32_t CP5:2; /*!< \brief bit:10..11 Access rights for coprocessor 5 */
manhpham 0:c8673aa96267 504 uint32_t CP6:2; /*!< \brief bit:12..13 Access rights for coprocessor 6 */
manhpham 0:c8673aa96267 505 uint32_t CP7:2; /*!< \brief bit:14..15 Access rights for coprocessor 7 */
manhpham 0:c8673aa96267 506 uint32_t CP8:2; /*!< \brief bit:16..17 Access rights for coprocessor 8 */
manhpham 0:c8673aa96267 507 uint32_t CP9:2; /*!< \brief bit:18..19 Access rights for coprocessor 9 */
manhpham 0:c8673aa96267 508 uint32_t CP10:2; /*!< \brief bit:20..21 Access rights for coprocessor 10 */
manhpham 0:c8673aa96267 509 uint32_t CP11:2; /*!< \brief bit:22..23 Access rights for coprocessor 11 */
manhpham 0:c8673aa96267 510 uint32_t CP12:2; /*!< \brief bit:24..25 Access rights for coprocessor 11 */
manhpham 0:c8673aa96267 511 uint32_t CP13:2; /*!< \brief bit:26..27 Access rights for coprocessor 11 */
manhpham 0:c8673aa96267 512 uint32_t TRCDIS:1; /*!< \brief bit: 28 Disable CP14 access to trace registers */
manhpham 0:c8673aa96267 513 RESERVED(0:1, uint32_t)
manhpham 0:c8673aa96267 514 uint32_t D32DIS:1; /*!< \brief bit: 30 Disable use of registers D16-D31 of the VFP register file */
manhpham 0:c8673aa96267 515 uint32_t ASEDIS:1; /*!< \brief bit: 31 Disable Advanced SIMD Functionality */
manhpham 0:c8673aa96267 516 } b; /*!< \brief Structure used for bit access */
manhpham 0:c8673aa96267 517 uint32_t w; /*!< \brief Type used for word access */
manhpham 0:c8673aa96267 518 } CPACR_Type;
manhpham 0:c8673aa96267 519
manhpham 0:c8673aa96267 520 #define CPACR_ASEDIS_Pos 31U /*!< \brief CPACR: ASEDIS Position */
manhpham 0:c8673aa96267 521 #define CPACR_ASEDIS_Msk (1UL << CPACR_ASEDIS_Pos) /*!< \brief CPACR: ASEDIS Mask */
manhpham 0:c8673aa96267 522
manhpham 0:c8673aa96267 523 #define CPACR_D32DIS_Pos 30U /*!< \brief CPACR: D32DIS Position */
manhpham 0:c8673aa96267 524 #define CPACR_D32DIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */
manhpham 0:c8673aa96267 525
manhpham 0:c8673aa96267 526 #define CPACR_TRCDIS_Pos 28U /*!< \brief CPACR: D32DIS Position */
manhpham 0:c8673aa96267 527 #define CPACR_TRCDIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */
manhpham 0:c8673aa96267 528
manhpham 0:c8673aa96267 529 #define CPACR_CP_Pos_(n) (n*2U) /*!< \brief CPACR: CPn Position */
manhpham 0:c8673aa96267 530 #define CPACR_CP_Msk_(n) (3UL << CPACR_CP_Pos_(n)) /*!< \brief CPACR: CPn Mask */
manhpham 0:c8673aa96267 531
manhpham 0:c8673aa96267 532 #define CPACR_CP_NA 0U /*!< \brief CPACR CPn field: Access denied. */
manhpham 0:c8673aa96267 533 #define CPACR_CP_PL1 1U /*!< \brief CPACR CPn field: Accessible from PL1 only. */
manhpham 0:c8673aa96267 534 #define CPACR_CP_FA 3U /*!< \brief CPACR CPn field: Full access. */
manhpham 0:c8673aa96267 535
manhpham 0:c8673aa96267 536 /* CP15 Register DFSR */
manhpham 0:c8673aa96267 537 typedef union
manhpham 0:c8673aa96267 538 {
manhpham 0:c8673aa96267 539 struct
manhpham 0:c8673aa96267 540 {
manhpham 0:c8673aa96267 541 uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */
manhpham 0:c8673aa96267 542 uint32_t Domain:4; /*!< \brief bit: 4.. 7 Fault on which domain */
manhpham 0:c8673aa96267 543 RESERVED(0:1, uint32_t)
manhpham 0:c8673aa96267 544 uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */
manhpham 0:c8673aa96267 545 uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */
manhpham 0:c8673aa96267 546 uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */
manhpham 0:c8673aa96267 547 uint32_t ExT:1; /*!< \brief bit: 12 External abort type */
manhpham 0:c8673aa96267 548 uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */
manhpham 0:c8673aa96267 549 RESERVED(1:18, uint32_t)
manhpham 0:c8673aa96267 550 } s; /*!< \brief Structure used for bit access in short format */
manhpham 0:c8673aa96267 551 struct
manhpham 0:c8673aa96267 552 {
manhpham 0:c8673aa96267 553 uint32_t STATUS:5; /*!< \brief bit: 0.. 5 Fault Status bits */
manhpham 0:c8673aa96267 554 RESERVED(0:3, uint32_t)
manhpham 0:c8673aa96267 555 uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */
manhpham 0:c8673aa96267 556 RESERVED(1:1, uint32_t)
manhpham 0:c8673aa96267 557 uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */
manhpham 0:c8673aa96267 558 uint32_t ExT:1; /*!< \brief bit: 12 External abort type */
manhpham 0:c8673aa96267 559 uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */
manhpham 0:c8673aa96267 560 RESERVED(2:18, uint32_t)
manhpham 0:c8673aa96267 561 } l; /*!< \brief Structure used for bit access in long format */
manhpham 0:c8673aa96267 562 uint32_t w; /*!< \brief Type used for word access */
manhpham 0:c8673aa96267 563 } DFSR_Type;
manhpham 0:c8673aa96267 564
manhpham 0:c8673aa96267 565 #define DFSR_CM_Pos 13U /*!< \brief DFSR: CM Position */
manhpham 0:c8673aa96267 566 #define DFSR_CM_Msk (1UL << DFSR_CM_Pos) /*!< \brief DFSR: CM Mask */
manhpham 0:c8673aa96267 567
manhpham 0:c8673aa96267 568 #define DFSR_Ext_Pos 12U /*!< \brief DFSR: Ext Position */
manhpham 0:c8673aa96267 569 #define DFSR_Ext_Msk (1UL << DFSR_Ext_Pos) /*!< \brief DFSR: Ext Mask */
manhpham 0:c8673aa96267 570
manhpham 0:c8673aa96267 571 #define DFSR_WnR_Pos 11U /*!< \brief DFSR: WnR Position */
manhpham 0:c8673aa96267 572 #define DFSR_WnR_Msk (1UL << DFSR_WnR_Pos) /*!< \brief DFSR: WnR Mask */
manhpham 0:c8673aa96267 573
manhpham 0:c8673aa96267 574 #define DFSR_FS1_Pos 10U /*!< \brief DFSR: FS1 Position */
manhpham 0:c8673aa96267 575 #define DFSR_FS1_Msk (1UL << DFSR_FS1_Pos) /*!< \brief DFSR: FS1 Mask */
manhpham 0:c8673aa96267 576
manhpham 0:c8673aa96267 577 #define DFSR_LPAE_Pos 9U /*!< \brief DFSR: LPAE Position */
manhpham 0:c8673aa96267 578 #define DFSR_LPAE_Msk (1UL << DFSR_LPAE_Pos) /*!< \brief DFSR: LPAE Mask */
manhpham 0:c8673aa96267 579
manhpham 0:c8673aa96267 580 #define DFSR_Domain_Pos 4U /*!< \brief DFSR: Domain Position */
manhpham 0:c8673aa96267 581 #define DFSR_Domain_Msk (0xFUL << DFSR_Domain_Pos) /*!< \brief DFSR: Domain Mask */
manhpham 0:c8673aa96267 582
manhpham 0:c8673aa96267 583 #define DFSR_FS0_Pos 0U /*!< \brief DFSR: FS0 Position */
manhpham 0:c8673aa96267 584 #define DFSR_FS0_Msk (0xFUL << DFSR_FS0_Pos) /*!< \brief DFSR: FS0 Mask */
manhpham 0:c8673aa96267 585
manhpham 0:c8673aa96267 586 #define DFSR_STATUS_Pos 0U /*!< \brief DFSR: STATUS Position */
manhpham 0:c8673aa96267 587 #define DFSR_STATUS_Msk (0x3FUL << DFSR_STATUS_Pos) /*!< \brief DFSR: STATUS Mask */
manhpham 0:c8673aa96267 588
manhpham 0:c8673aa96267 589 /* CP15 Register IFSR */
manhpham 0:c8673aa96267 590 typedef union
manhpham 0:c8673aa96267 591 {
manhpham 0:c8673aa96267 592 struct
manhpham 0:c8673aa96267 593 {
manhpham 0:c8673aa96267 594 uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */
manhpham 0:c8673aa96267 595 RESERVED(0:5, uint32_t)
manhpham 0:c8673aa96267 596 uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */
manhpham 0:c8673aa96267 597 uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */
manhpham 0:c8673aa96267 598 RESERVED(1:1, uint32_t)
manhpham 0:c8673aa96267 599 uint32_t ExT:1; /*!< \brief bit: 12 External abort type */
manhpham 0:c8673aa96267 600 RESERVED(2:19, uint32_t)
manhpham 0:c8673aa96267 601 } s; /*!< \brief Structure used for bit access in short format */
manhpham 0:c8673aa96267 602 struct
manhpham 0:c8673aa96267 603 {
manhpham 0:c8673aa96267 604 uint32_t STATUS:6; /*!< \brief bit: 0.. 5 Fault Status bits */
manhpham 0:c8673aa96267 605 RESERVED(0:3, uint32_t)
manhpham 0:c8673aa96267 606 uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */
manhpham 0:c8673aa96267 607 RESERVED(1:2, uint32_t)
manhpham 0:c8673aa96267 608 uint32_t ExT:1; /*!< \brief bit: 12 External abort type */
manhpham 0:c8673aa96267 609 RESERVED(2:19, uint32_t)
manhpham 0:c8673aa96267 610 } l; /*!< \brief Structure used for bit access in long format */
manhpham 0:c8673aa96267 611 uint32_t w; /*!< \brief Type used for word access */
manhpham 0:c8673aa96267 612 } IFSR_Type;
manhpham 0:c8673aa96267 613
manhpham 0:c8673aa96267 614 #define IFSR_ExT_Pos 12U /*!< \brief IFSR: ExT Position */
manhpham 0:c8673aa96267 615 #define IFSR_ExT_Msk (1UL << IFSR_ExT_Pos) /*!< \brief IFSR: ExT Mask */
manhpham 0:c8673aa96267 616
manhpham 0:c8673aa96267 617 #define IFSR_FS1_Pos 10U /*!< \brief IFSR: FS1 Position */
manhpham 0:c8673aa96267 618 #define IFSR_FS1_Msk (1UL << IFSR_FS1_Pos) /*!< \brief IFSR: FS1 Mask */
manhpham 0:c8673aa96267 619
manhpham 0:c8673aa96267 620 #define IFSR_LPAE_Pos 9U /*!< \brief IFSR: LPAE Position */
manhpham 0:c8673aa96267 621 #define IFSR_LPAE_Msk (0x1UL << IFSR_LPAE_Pos) /*!< \brief IFSR: LPAE Mask */
manhpham 0:c8673aa96267 622
manhpham 0:c8673aa96267 623 #define IFSR_FS0_Pos 0U /*!< \brief IFSR: FS0 Position */
manhpham 0:c8673aa96267 624 #define IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos) /*!< \brief IFSR: FS0 Mask */
manhpham 0:c8673aa96267 625
manhpham 0:c8673aa96267 626 #define IFSR_STATUS_Pos 0U /*!< \brief IFSR: STATUS Position */
manhpham 0:c8673aa96267 627 #define IFSR_STATUS_Msk (0x3FUL << IFSR_STATUS_Pos) /*!< \brief IFSR: STATUS Mask */
manhpham 0:c8673aa96267 628
manhpham 0:c8673aa96267 629 /* CP15 Register ISR */
manhpham 0:c8673aa96267 630 typedef union
manhpham 0:c8673aa96267 631 {
manhpham 0:c8673aa96267 632 struct
manhpham 0:c8673aa96267 633 {
manhpham 0:c8673aa96267 634 RESERVED(0:6, uint32_t)
manhpham 0:c8673aa96267 635 uint32_t F:1; /*!< \brief bit: 6 FIQ pending bit */
manhpham 0:c8673aa96267 636 uint32_t I:1; /*!< \brief bit: 7 IRQ pending bit */
manhpham 0:c8673aa96267 637 uint32_t A:1; /*!< \brief bit: 8 External abort pending bit */
manhpham 0:c8673aa96267 638 RESERVED(1:23, uint32_t)
manhpham 0:c8673aa96267 639 } b; /*!< \brief Structure used for bit access */
manhpham 0:c8673aa96267 640 uint32_t w; /*!< \brief Type used for word access */
manhpham 0:c8673aa96267 641 } ISR_Type;
manhpham 0:c8673aa96267 642
manhpham 0:c8673aa96267 643 #define ISR_A_Pos 13U /*!< \brief ISR: A Position */
manhpham 0:c8673aa96267 644 #define ISR_A_Msk (1UL << ISR_A_Pos) /*!< \brief ISR: A Mask */
manhpham 0:c8673aa96267 645
manhpham 0:c8673aa96267 646 #define ISR_I_Pos 12U /*!< \brief ISR: I Position */
manhpham 0:c8673aa96267 647 #define ISR_I_Msk (1UL << ISR_I_Pos) /*!< \brief ISR: I Mask */
manhpham 0:c8673aa96267 648
manhpham 0:c8673aa96267 649 #define ISR_F_Pos 11U /*!< \brief ISR: F Position */
manhpham 0:c8673aa96267 650 #define ISR_F_Msk (1UL << ISR_F_Pos) /*!< \brief ISR: F Mask */
manhpham 0:c8673aa96267 651
manhpham 0:c8673aa96267 652 /* DACR Register */
manhpham 0:c8673aa96267 653 #define DACR_D_Pos_(n) (2U*n) /*!< \brief DACR: Dn Position */
manhpham 0:c8673aa96267 654 #define DACR_D_Msk_(n) (3UL << DACR_D_Pos_(n)) /*!< \brief DACR: Dn Mask */
manhpham 0:c8673aa96267 655 #define DACR_Dn_NOACCESS 0U /*!< \brief DACR Dn field: No access */
manhpham 0:c8673aa96267 656 #define DACR_Dn_CLIENT 1U /*!< \brief DACR Dn field: Client */
manhpham 0:c8673aa96267 657 #define DACR_Dn_MANAGER 3U /*!< \brief DACR Dn field: Manager */
manhpham 0:c8673aa96267 658
manhpham 0:c8673aa96267 659 /**
manhpham 0:c8673aa96267 660 \brief Mask and shift a bit field value for use in a register bit range.
manhpham 0:c8673aa96267 661 \param [in] field Name of the register bit field.
manhpham 0:c8673aa96267 662 \param [in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
manhpham 0:c8673aa96267 663 \return Masked and shifted value.
manhpham 0:c8673aa96267 664 */
manhpham 0:c8673aa96267 665 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
manhpham 0:c8673aa96267 666
manhpham 0:c8673aa96267 667 /**
manhpham 0:c8673aa96267 668 \brief Mask and shift a register value to extract a bit filed value.
manhpham 0:c8673aa96267 669 \param [in] field Name of the register bit field.
manhpham 0:c8673aa96267 670 \param [in] value Value of register. This parameter is interpreted as an uint32_t type.
manhpham 0:c8673aa96267 671 \return Masked and shifted bit field value.
manhpham 0:c8673aa96267 672 */
manhpham 0:c8673aa96267 673 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
manhpham 0:c8673aa96267 674
manhpham 0:c8673aa96267 675
manhpham 0:c8673aa96267 676 /**
manhpham 0:c8673aa96267 677 \brief Union type to access the L2C_310 Cache Controller.
manhpham 0:c8673aa96267 678 */
manhpham 0:c8673aa96267 679 #if (__L2C_PRESENT == 1U) || defined(DOXYGEN)
manhpham 0:c8673aa96267 680 typedef struct
manhpham 0:c8673aa96267 681 {
manhpham 0:c8673aa96267 682 __IM uint32_t CACHE_ID; /*!< \brief Offset: 0x0000 (R/ ) Cache ID Register */
manhpham 0:c8673aa96267 683 __IM uint32_t CACHE_TYPE; /*!< \brief Offset: 0x0004 (R/ ) Cache Type Register */
manhpham 0:c8673aa96267 684 RESERVED(0[0x3e], uint32_t)
manhpham 0:c8673aa96267 685 __IOM uint32_t CONTROL; /*!< \brief Offset: 0x0100 (R/W) Control Register */
manhpham 0:c8673aa96267 686 __IOM uint32_t AUX_CNT; /*!< \brief Offset: 0x0104 (R/W) Auxiliary Control */
manhpham 0:c8673aa96267 687 RESERVED(1[0x3e], uint32_t)
manhpham 0:c8673aa96267 688 __IOM uint32_t EVENT_CONTROL; /*!< \brief Offset: 0x0200 (R/W) Event Counter Control */
manhpham 0:c8673aa96267 689 __IOM uint32_t EVENT_COUNTER1_CONF; /*!< \brief Offset: 0x0204 (R/W) Event Counter 1 Configuration */
manhpham 0:c8673aa96267 690 __IOM uint32_t EVENT_COUNTER0_CONF; /*!< \brief Offset: 0x0208 (R/W) Event Counter 1 Configuration */
manhpham 0:c8673aa96267 691 RESERVED(2[0x2], uint32_t)
manhpham 0:c8673aa96267 692 __IOM uint32_t INTERRUPT_MASK; /*!< \brief Offset: 0x0214 (R/W) Interrupt Mask */
manhpham 0:c8673aa96267 693 __IM uint32_t MASKED_INT_STATUS; /*!< \brief Offset: 0x0218 (R/ ) Masked Interrupt Status */
manhpham 0:c8673aa96267 694 __IM uint32_t RAW_INT_STATUS; /*!< \brief Offset: 0x021c (R/ ) Raw Interrupt Status */
manhpham 0:c8673aa96267 695 __OM uint32_t INTERRUPT_CLEAR; /*!< \brief Offset: 0x0220 ( /W) Interrupt Clear */
manhpham 0:c8673aa96267 696 RESERVED(3[0x143], uint32_t)
manhpham 0:c8673aa96267 697 __IOM uint32_t CACHE_SYNC; /*!< \brief Offset: 0x0730 (R/W) Cache Sync */
manhpham 0:c8673aa96267 698 RESERVED(4[0xf], uint32_t)
manhpham 0:c8673aa96267 699 __IOM uint32_t INV_LINE_PA; /*!< \brief Offset: 0x0770 (R/W) Invalidate Line By PA */
manhpham 0:c8673aa96267 700 RESERVED(6[2], uint32_t)
manhpham 0:c8673aa96267 701 __IOM uint32_t INV_WAY; /*!< \brief Offset: 0x077c (R/W) Invalidate by Way */
manhpham 0:c8673aa96267 702 RESERVED(5[0xc], uint32_t)
manhpham 0:c8673aa96267 703 __IOM uint32_t CLEAN_LINE_PA; /*!< \brief Offset: 0x07b0 (R/W) Clean Line by PA */
manhpham 0:c8673aa96267 704 RESERVED(7[1], uint32_t)
manhpham 0:c8673aa96267 705 __IOM uint32_t CLEAN_LINE_INDEX_WAY; /*!< \brief Offset: 0x07b8 (R/W) Clean Line by Index/Way */
manhpham 0:c8673aa96267 706 __IOM uint32_t CLEAN_WAY; /*!< \brief Offset: 0x07bc (R/W) Clean by Way */
manhpham 0:c8673aa96267 707 RESERVED(8[0xc], uint32_t)
manhpham 0:c8673aa96267 708 __IOM uint32_t CLEAN_INV_LINE_PA; /*!< \brief Offset: 0x07f0 (R/W) Clean and Invalidate Line by PA */
manhpham 0:c8673aa96267 709 RESERVED(9[1], uint32_t)
manhpham 0:c8673aa96267 710 __IOM uint32_t CLEAN_INV_LINE_INDEX_WAY; /*!< \brief Offset: 0x07f8 (R/W) Clean and Invalidate Line by Index/Way */
manhpham 0:c8673aa96267 711 __IOM uint32_t CLEAN_INV_WAY; /*!< \brief Offset: 0x07fc (R/W) Clean and Invalidate by Way */
manhpham 0:c8673aa96267 712 RESERVED(10[0x40], uint32_t)
manhpham 0:c8673aa96267 713 __IOM uint32_t DATA_LOCK_0_WAY; /*!< \brief Offset: 0x0900 (R/W) Data Lockdown 0 by Way */
manhpham 0:c8673aa96267 714 __IOM uint32_t INST_LOCK_0_WAY; /*!< \brief Offset: 0x0904 (R/W) Instruction Lockdown 0 by Way */
manhpham 0:c8673aa96267 715 __IOM uint32_t DATA_LOCK_1_WAY; /*!< \brief Offset: 0x0908 (R/W) Data Lockdown 1 by Way */
manhpham 0:c8673aa96267 716 __IOM uint32_t INST_LOCK_1_WAY; /*!< \brief Offset: 0x090c (R/W) Instruction Lockdown 1 by Way */
manhpham 0:c8673aa96267 717 __IOM uint32_t DATA_LOCK_2_WAY; /*!< \brief Offset: 0x0910 (R/W) Data Lockdown 2 by Way */
manhpham 0:c8673aa96267 718 __IOM uint32_t INST_LOCK_2_WAY; /*!< \brief Offset: 0x0914 (R/W) Instruction Lockdown 2 by Way */
manhpham 0:c8673aa96267 719 __IOM uint32_t DATA_LOCK_3_WAY; /*!< \brief Offset: 0x0918 (R/W) Data Lockdown 3 by Way */
manhpham 0:c8673aa96267 720 __IOM uint32_t INST_LOCK_3_WAY; /*!< \brief Offset: 0x091c (R/W) Instruction Lockdown 3 by Way */
manhpham 0:c8673aa96267 721 __IOM uint32_t DATA_LOCK_4_WAY; /*!< \brief Offset: 0x0920 (R/W) Data Lockdown 4 by Way */
manhpham 0:c8673aa96267 722 __IOM uint32_t INST_LOCK_4_WAY; /*!< \brief Offset: 0x0924 (R/W) Instruction Lockdown 4 by Way */
manhpham 0:c8673aa96267 723 __IOM uint32_t DATA_LOCK_5_WAY; /*!< \brief Offset: 0x0928 (R/W) Data Lockdown 5 by Way */
manhpham 0:c8673aa96267 724 __IOM uint32_t INST_LOCK_5_WAY; /*!< \brief Offset: 0x092c (R/W) Instruction Lockdown 5 by Way */
manhpham 0:c8673aa96267 725 __IOM uint32_t DATA_LOCK_6_WAY; /*!< \brief Offset: 0x0930 (R/W) Data Lockdown 5 by Way */
manhpham 0:c8673aa96267 726 __IOM uint32_t INST_LOCK_6_WAY; /*!< \brief Offset: 0x0934 (R/W) Instruction Lockdown 5 by Way */
manhpham 0:c8673aa96267 727 __IOM uint32_t DATA_LOCK_7_WAY; /*!< \brief Offset: 0x0938 (R/W) Data Lockdown 6 by Way */
manhpham 0:c8673aa96267 728 __IOM uint32_t INST_LOCK_7_WAY; /*!< \brief Offset: 0x093c (R/W) Instruction Lockdown 6 by Way */
manhpham 0:c8673aa96267 729 RESERVED(11[0x4], uint32_t)
manhpham 0:c8673aa96267 730 __IOM uint32_t LOCK_LINE_EN; /*!< \brief Offset: 0x0950 (R/W) Lockdown by Line Enable */
manhpham 0:c8673aa96267 731 __IOM uint32_t UNLOCK_ALL_BY_WAY; /*!< \brief Offset: 0x0954 (R/W) Unlock All Lines by Way */
manhpham 0:c8673aa96267 732 RESERVED(12[0xaa], uint32_t)
manhpham 0:c8673aa96267 733 __IOM uint32_t ADDRESS_FILTER_START; /*!< \brief Offset: 0x0c00 (R/W) Address Filtering Start */
manhpham 0:c8673aa96267 734 __IOM uint32_t ADDRESS_FILTER_END; /*!< \brief Offset: 0x0c04 (R/W) Address Filtering End */
manhpham 0:c8673aa96267 735 RESERVED(13[0xce], uint32_t)
manhpham 0:c8673aa96267 736 __IOM uint32_t DEBUG_CONTROL; /*!< \brief Offset: 0x0f40 (R/W) Debug Control Register */
manhpham 0:c8673aa96267 737 } L2C_310_TypeDef;
manhpham 0:c8673aa96267 738
manhpham 0:c8673aa96267 739 #define L2C_310 ((L2C_310_TypeDef *)L2C_310_BASE) /*!< \brief L2C_310 register set access pointer */
manhpham 0:c8673aa96267 740 #endif
manhpham 0:c8673aa96267 741
manhpham 0:c8673aa96267 742 #if (__GIC_PRESENT == 1U) || defined(DOXYGEN)
manhpham 0:c8673aa96267 743
manhpham 0:c8673aa96267 744 /** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD)
manhpham 0:c8673aa96267 745 */
manhpham 0:c8673aa96267 746 typedef struct
manhpham 0:c8673aa96267 747 {
manhpham 0:c8673aa96267 748 __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) Distributor Control Register */
manhpham 0:c8673aa96267 749 __IM uint32_t TYPER; /*!< \brief Offset: 0x004 (R/ ) Interrupt Controller Type Register */
manhpham 0:c8673aa96267 750 __IM uint32_t IIDR; /*!< \brief Offset: 0x008 (R/ ) Distributor Implementer Identification Register */
manhpham 0:c8673aa96267 751 RESERVED(0, uint32_t)
manhpham 0:c8673aa96267 752 __IOM uint32_t STATUSR; /*!< \brief Offset: 0x010 (R/W) Error Reporting Status Register, optional */
manhpham 0:c8673aa96267 753 RESERVED(1[11], uint32_t)
manhpham 0:c8673aa96267 754 __OM uint32_t SETSPI_NSR; /*!< \brief Offset: 0x040 ( /W) Set SPI Register */
manhpham 0:c8673aa96267 755 RESERVED(2, uint32_t)
manhpham 0:c8673aa96267 756 __OM uint32_t CLRSPI_NSR; /*!< \brief Offset: 0x048 ( /W) Clear SPI Register */
manhpham 0:c8673aa96267 757 RESERVED(3, uint32_t)
manhpham 0:c8673aa96267 758 __OM uint32_t SETSPI_SR; /*!< \brief Offset: 0x050 ( /W) Set SPI, Secure Register */
manhpham 0:c8673aa96267 759 RESERVED(4, uint32_t)
manhpham 0:c8673aa96267 760 __OM uint32_t CLRSPI_SR; /*!< \brief Offset: 0x058 ( /W) Clear SPI, Secure Register */
manhpham 0:c8673aa96267 761 RESERVED(5[9], uint32_t)
manhpham 0:c8673aa96267 762 __IOM uint32_t IGROUPR[32]; /*!< \brief Offset: 0x080 (R/W) Interrupt Group Registers */
manhpham 0:c8673aa96267 763 __IOM uint32_t ISENABLER[32]; /*!< \brief Offset: 0x100 (R/W) Interrupt Set-Enable Registers */
manhpham 0:c8673aa96267 764 __IOM uint32_t ICENABLER[32]; /*!< \brief Offset: 0x180 (R/W) Interrupt Clear-Enable Registers */
manhpham 0:c8673aa96267 765 __IOM uint32_t ISPENDR[32]; /*!< \brief Offset: 0x200 (R/W) Interrupt Set-Pending Registers */
manhpham 0:c8673aa96267 766 __IOM uint32_t ICPENDR[32]; /*!< \brief Offset: 0x280 (R/W) Interrupt Clear-Pending Registers */
manhpham 0:c8673aa96267 767 __IOM uint32_t ISACTIVER[32]; /*!< \brief Offset: 0x300 (R/W) Interrupt Set-Active Registers */
manhpham 0:c8673aa96267 768 __IOM uint32_t ICACTIVER[32]; /*!< \brief Offset: 0x380 (R/W) Interrupt Clear-Active Registers */
manhpham 0:c8673aa96267 769 __IOM uint32_t IPRIORITYR[255]; /*!< \brief Offset: 0x400 (R/W) Interrupt Priority Registers */
manhpham 0:c8673aa96267 770 RESERVED(6, uint32_t)
manhpham 0:c8673aa96267 771 __IOM uint32_t ITARGETSR[255]; /*!< \brief Offset: 0x800 (R/W) Interrupt Targets Registers */
manhpham 0:c8673aa96267 772 RESERVED(7, uint32_t)
manhpham 0:c8673aa96267 773 __IOM uint32_t ICFGR[64]; /*!< \brief Offset: 0xC00 (R/W) Interrupt Configuration Registers */
manhpham 0:c8673aa96267 774 __IOM uint32_t IGRPMODR[32]; /*!< \brief Offset: 0xD00 (R/W) Interrupt Group Modifier Registers */
manhpham 0:c8673aa96267 775 RESERVED(8[32], uint32_t)
manhpham 0:c8673aa96267 776 __IOM uint32_t NSACR[64]; /*!< \brief Offset: 0xE00 (R/W) Non-secure Access Control Registers */
manhpham 0:c8673aa96267 777 __OM uint32_t SGIR; /*!< \brief Offset: 0xF00 ( /W) Software Generated Interrupt Register */
manhpham 0:c8673aa96267 778 RESERVED(9[3], uint32_t)
manhpham 0:c8673aa96267 779 __IOM uint32_t CPENDSGIR[4]; /*!< \brief Offset: 0xF10 (R/W) SGI Clear-Pending Registers */
manhpham 0:c8673aa96267 780 __IOM uint32_t SPENDSGIR[4]; /*!< \brief Offset: 0xF20 (R/W) SGI Set-Pending Registers */
manhpham 0:c8673aa96267 781 RESERVED(10[5236], uint32_t)
manhpham 0:c8673aa96267 782 __IOM uint64_t IROUTER[988]; /*!< \brief Offset: 0x6100(R/W) Interrupt Routing Registers */
manhpham 0:c8673aa96267 783 } GICDistributor_Type;
manhpham 0:c8673aa96267 784
manhpham 0:c8673aa96267 785 #define GICDistributor ((GICDistributor_Type *) GIC_DISTRIBUTOR_BASE ) /*!< \brief GIC Distributor register set access pointer */
manhpham 0:c8673aa96267 786
manhpham 0:c8673aa96267 787 /** \brief Structure type to access the Generic Interrupt Controller Interface (GICC)
manhpham 0:c8673aa96267 788 */
manhpham 0:c8673aa96267 789 typedef struct
manhpham 0:c8673aa96267 790 {
manhpham 0:c8673aa96267 791 __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) CPU Interface Control Register */
manhpham 0:c8673aa96267 792 __IOM uint32_t PMR; /*!< \brief Offset: 0x004 (R/W) Interrupt Priority Mask Register */
manhpham 0:c8673aa96267 793 __IOM uint32_t BPR; /*!< \brief Offset: 0x008 (R/W) Binary Point Register */
manhpham 0:c8673aa96267 794 __IM uint32_t IAR; /*!< \brief Offset: 0x00C (R/ ) Interrupt Acknowledge Register */
manhpham 0:c8673aa96267 795 __OM uint32_t EOIR; /*!< \brief Offset: 0x010 ( /W) End Of Interrupt Register */
manhpham 0:c8673aa96267 796 __IM uint32_t RPR; /*!< \brief Offset: 0x014 (R/ ) Running Priority Register */
manhpham 0:c8673aa96267 797 __IM uint32_t HPPIR; /*!< \brief Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register */
manhpham 0:c8673aa96267 798 __IOM uint32_t ABPR; /*!< \brief Offset: 0x01C (R/W) Aliased Binary Point Register */
manhpham 0:c8673aa96267 799 __IM uint32_t AIAR; /*!< \brief Offset: 0x020 (R/ ) Aliased Interrupt Acknowledge Register */
manhpham 0:c8673aa96267 800 __OM uint32_t AEOIR; /*!< \brief Offset: 0x024 ( /W) Aliased End Of Interrupt Register */
manhpham 0:c8673aa96267 801 __IM uint32_t AHPPIR; /*!< \brief Offset: 0x028 (R/ ) Aliased Highest Priority Pending Interrupt Register */
manhpham 0:c8673aa96267 802 __IOM uint32_t STATUSR; /*!< \brief Offset: 0x02C (R/W) Error Reporting Status Register, optional */
manhpham 0:c8673aa96267 803 RESERVED(1[40], uint32_t)
manhpham 0:c8673aa96267 804 __IOM uint32_t APR[4]; /*!< \brief Offset: 0x0D0 (R/W) Active Priority Register */
manhpham 0:c8673aa96267 805 __IOM uint32_t NSAPR[4]; /*!< \brief Offset: 0x0E0 (R/W) Non-secure Active Priority Register */
manhpham 0:c8673aa96267 806 RESERVED(2[3], uint32_t)
manhpham 0:c8673aa96267 807 __IM uint32_t IIDR; /*!< \brief Offset: 0x0FC (R/ ) CPU Interface Identification Register */
manhpham 0:c8673aa96267 808 RESERVED(3[960], uint32_t)
manhpham 0:c8673aa96267 809 __OM uint32_t DIR; /*!< \brief Offset: 0x1000( /W) Deactivate Interrupt Register */
manhpham 0:c8673aa96267 810 } GICInterface_Type;
manhpham 0:c8673aa96267 811
manhpham 0:c8673aa96267 812 #define GICInterface ((GICInterface_Type *) GIC_INTERFACE_BASE ) /*!< \brief GIC Interface register set access pointer */
manhpham 0:c8673aa96267 813 #endif
manhpham 0:c8673aa96267 814
manhpham 0:c8673aa96267 815 #if (__TIM_PRESENT == 1U) || defined(DOXYGEN)
manhpham 0:c8673aa96267 816 #if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN)
manhpham 0:c8673aa96267 817 /** \brief Structure type to access the Private Timer
manhpham 0:c8673aa96267 818 */
manhpham 0:c8673aa96267 819 typedef struct
manhpham 0:c8673aa96267 820 {
manhpham 0:c8673aa96267 821 __IOM uint32_t LOAD; //!< \brief Offset: 0x000 (R/W) Private Timer Load Register
manhpham 0:c8673aa96267 822 __IOM uint32_t COUNTER; //!< \brief Offset: 0x004 (R/W) Private Timer Counter Register
manhpham 0:c8673aa96267 823 __IOM uint32_t CONTROL; //!< \brief Offset: 0x008 (R/W) Private Timer Control Register
manhpham 0:c8673aa96267 824 __IOM uint32_t ISR; //!< \brief Offset: 0x00C (R/W) Private Timer Interrupt Status Register
manhpham 0:c8673aa96267 825 RESERVED(0[4], uint32_t)
manhpham 0:c8673aa96267 826 __IOM uint32_t WLOAD; //!< \brief Offset: 0x020 (R/W) Watchdog Load Register
manhpham 0:c8673aa96267 827 __IOM uint32_t WCOUNTER; //!< \brief Offset: 0x024 (R/W) Watchdog Counter Register
manhpham 0:c8673aa96267 828 __IOM uint32_t WCONTROL; //!< \brief Offset: 0x028 (R/W) Watchdog Control Register
manhpham 0:c8673aa96267 829 __IOM uint32_t WISR; //!< \brief Offset: 0x02C (R/W) Watchdog Interrupt Status Register
manhpham 0:c8673aa96267 830 __IOM uint32_t WRESET; //!< \brief Offset: 0x030 (R/W) Watchdog Reset Status Register
manhpham 0:c8673aa96267 831 __OM uint32_t WDISABLE; //!< \brief Offset: 0x034 ( /W) Watchdog Disable Register
manhpham 0:c8673aa96267 832 } Timer_Type;
manhpham 0:c8673aa96267 833 #define PTIM ((Timer_Type *) TIMER_BASE ) /*!< \brief Timer register struct */
manhpham 0:c8673aa96267 834 #endif
manhpham 0:c8673aa96267 835 #endif
manhpham 0:c8673aa96267 836
manhpham 0:c8673aa96267 837 /*******************************************************************************
manhpham 0:c8673aa96267 838 * Hardware Abstraction Layer
manhpham 0:c8673aa96267 839 Core Function Interface contains:
manhpham 0:c8673aa96267 840 - L1 Cache Functions
manhpham 0:c8673aa96267 841 - L2C-310 Cache Controller Functions
manhpham 0:c8673aa96267 842 - PL1 Timer Functions
manhpham 0:c8673aa96267 843 - GIC Functions
manhpham 0:c8673aa96267 844 - MMU Functions
manhpham 0:c8673aa96267 845 ******************************************************************************/
manhpham 0:c8673aa96267 846
manhpham 0:c8673aa96267 847 /* ########################## L1 Cache functions ################################# */
manhpham 0:c8673aa96267 848
manhpham 0:c8673aa96267 849 /** \brief Enable Caches by setting I and C bits in SCTLR register.
manhpham 0:c8673aa96267 850 */
manhpham 0:c8673aa96267 851 __STATIC_FORCEINLINE void L1C_EnableCaches(void) {
manhpham 0:c8673aa96267 852 __set_SCTLR( __get_SCTLR() | SCTLR_I_Msk | SCTLR_C_Msk);
manhpham 0:c8673aa96267 853 __ISB();
manhpham 0:c8673aa96267 854 }
manhpham 0:c8673aa96267 855
manhpham 0:c8673aa96267 856 /** \brief Disable Caches by clearing I and C bits in SCTLR register.
manhpham 0:c8673aa96267 857 */
manhpham 0:c8673aa96267 858 __STATIC_FORCEINLINE void L1C_DisableCaches(void) {
manhpham 0:c8673aa96267 859 __set_SCTLR( __get_SCTLR() & (~SCTLR_I_Msk) & (~SCTLR_C_Msk));
manhpham 0:c8673aa96267 860 __ISB();
manhpham 0:c8673aa96267 861 }
manhpham 0:c8673aa96267 862
manhpham 0:c8673aa96267 863 /** \brief Enable Branch Prediction by setting Z bit in SCTLR register.
manhpham 0:c8673aa96267 864 */
manhpham 0:c8673aa96267 865 __STATIC_FORCEINLINE void L1C_EnableBTAC(void) {
manhpham 0:c8673aa96267 866 __set_SCTLR( __get_SCTLR() | SCTLR_Z_Msk);
manhpham 0:c8673aa96267 867 __ISB();
manhpham 0:c8673aa96267 868 }
manhpham 0:c8673aa96267 869
manhpham 0:c8673aa96267 870 /** \brief Disable Branch Prediction by clearing Z bit in SCTLR register.
manhpham 0:c8673aa96267 871 */
manhpham 0:c8673aa96267 872 __STATIC_FORCEINLINE void L1C_DisableBTAC(void) {
manhpham 0:c8673aa96267 873 __set_SCTLR( __get_SCTLR() & (~SCTLR_Z_Msk));
manhpham 0:c8673aa96267 874 __ISB();
manhpham 0:c8673aa96267 875 }
manhpham 0:c8673aa96267 876
manhpham 0:c8673aa96267 877 /** \brief Invalidate entire branch predictor array
manhpham 0:c8673aa96267 878 */
manhpham 0:c8673aa96267 879 __STATIC_FORCEINLINE void L1C_InvalidateBTAC(void) {
manhpham 0:c8673aa96267 880 __set_BPIALL(0);
manhpham 0:c8673aa96267 881 __DSB(); //ensure completion of the invalidation
manhpham 0:c8673aa96267 882 __ISB(); //ensure instruction fetch path sees new state
manhpham 0:c8673aa96267 883 }
manhpham 0:c8673aa96267 884
manhpham 0:c8673aa96267 885 /** \brief Invalidate the whole instruction cache
manhpham 0:c8673aa96267 886 */
manhpham 0:c8673aa96267 887 __STATIC_FORCEINLINE void L1C_InvalidateICacheAll(void) {
manhpham 0:c8673aa96267 888 __set_ICIALLU(0);
manhpham 0:c8673aa96267 889 __DSB(); //ensure completion of the invalidation
manhpham 0:c8673aa96267 890 __ISB(); //ensure instruction fetch path sees new I cache state
manhpham 0:c8673aa96267 891 }
manhpham 0:c8673aa96267 892
manhpham 0:c8673aa96267 893 /** \brief Clean data cache line by address.
manhpham 0:c8673aa96267 894 * \param [in] va Pointer to data to clear the cache for.
manhpham 0:c8673aa96267 895 */
manhpham 0:c8673aa96267 896 __STATIC_FORCEINLINE void L1C_CleanDCacheMVA(void *va) {
manhpham 0:c8673aa96267 897 __set_DCCMVAC((uint32_t)va);
manhpham 0:c8673aa96267 898 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
manhpham 0:c8673aa96267 899 }
manhpham 0:c8673aa96267 900
manhpham 0:c8673aa96267 901 /** \brief Invalidate data cache line by address.
manhpham 0:c8673aa96267 902 * \param [in] va Pointer to data to invalidate the cache for.
manhpham 0:c8673aa96267 903 */
manhpham 0:c8673aa96267 904 __STATIC_FORCEINLINE void L1C_InvalidateDCacheMVA(void *va) {
manhpham 0:c8673aa96267 905 __set_DCIMVAC((uint32_t)va);
manhpham 0:c8673aa96267 906 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
manhpham 0:c8673aa96267 907 }
manhpham 0:c8673aa96267 908
manhpham 0:c8673aa96267 909 /** \brief Clean and Invalidate data cache by address.
manhpham 0:c8673aa96267 910 * \param [in] va Pointer to data to invalidate the cache for.
manhpham 0:c8673aa96267 911 */
manhpham 0:c8673aa96267 912 __STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheMVA(void *va) {
manhpham 0:c8673aa96267 913 __set_DCCIMVAC((uint32_t)va);
manhpham 0:c8673aa96267 914 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
manhpham 0:c8673aa96267 915 }
manhpham 0:c8673aa96267 916
manhpham 0:c8673aa96267 917 /** \brief Calculate log2 rounded up
manhpham 0:c8673aa96267 918 * - log(0) => 0
manhpham 0:c8673aa96267 919 * - log(1) => 0
manhpham 0:c8673aa96267 920 * - log(2) => 1
manhpham 0:c8673aa96267 921 * - log(3) => 2
manhpham 0:c8673aa96267 922 * - log(4) => 2
manhpham 0:c8673aa96267 923 * - log(5) => 3
manhpham 0:c8673aa96267 924 * : :
manhpham 0:c8673aa96267 925 * - log(16) => 4
manhpham 0:c8673aa96267 926 * - log(32) => 5
manhpham 0:c8673aa96267 927 * : :
manhpham 0:c8673aa96267 928 * \param [in] n input value parameter
manhpham 0:c8673aa96267 929 * \return log2(n)
manhpham 0:c8673aa96267 930 */
manhpham 0:c8673aa96267 931 __STATIC_FORCEINLINE uint8_t __log2_up(uint32_t n)
manhpham 0:c8673aa96267 932 {
manhpham 0:c8673aa96267 933 if (n < 2U) {
manhpham 0:c8673aa96267 934 return 0U;
manhpham 0:c8673aa96267 935 }
manhpham 0:c8673aa96267 936 uint8_t log = 0U;
manhpham 0:c8673aa96267 937 uint32_t t = n;
manhpham 0:c8673aa96267 938 while(t > 1U)
manhpham 0:c8673aa96267 939 {
manhpham 0:c8673aa96267 940 log++;
manhpham 0:c8673aa96267 941 t >>= 1U;
manhpham 0:c8673aa96267 942 }
manhpham 0:c8673aa96267 943 if (n & 1U) { log++; }
manhpham 0:c8673aa96267 944 return log;
manhpham 0:c8673aa96267 945 }
manhpham 0:c8673aa96267 946
manhpham 0:c8673aa96267 947 /** \brief Apply cache maintenance to given cache level.
manhpham 0:c8673aa96267 948 * \param [in] level cache level to be maintained
manhpham 0:c8673aa96267 949 * \param [in] maint 0 - invalidate, 1 - clean, otherwise - invalidate and clean
manhpham 0:c8673aa96267 950 */
manhpham 0:c8673aa96267 951 __STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t maint)
manhpham 0:c8673aa96267 952 {
manhpham 0:c8673aa96267 953 register volatile uint32_t Dummy;
manhpham 0:c8673aa96267 954 register volatile uint32_t ccsidr;
manhpham 0:c8673aa96267 955 uint32_t num_sets;
manhpham 0:c8673aa96267 956 uint32_t num_ways;
manhpham 0:c8673aa96267 957 uint32_t shift_way;
manhpham 0:c8673aa96267 958 uint32_t log2_linesize;
manhpham 0:c8673aa96267 959 int32_t log2_num_ways;
manhpham 0:c8673aa96267 960
manhpham 0:c8673aa96267 961 Dummy = level << 1U;
manhpham 0:c8673aa96267 962 /* set csselr, select ccsidr register */
manhpham 0:c8673aa96267 963 __set_CCSIDR(Dummy);
manhpham 0:c8673aa96267 964 /* get current ccsidr register */
manhpham 0:c8673aa96267 965 ccsidr = __get_CCSIDR();
manhpham 0:c8673aa96267 966 num_sets = ((ccsidr & 0x0FFFE000U) >> 13U) + 1U;
manhpham 0:c8673aa96267 967 num_ways = ((ccsidr & 0x00001FF8U) >> 3U) + 1U;
manhpham 0:c8673aa96267 968 log2_linesize = (ccsidr & 0x00000007U) + 2U + 2U;
manhpham 0:c8673aa96267 969 log2_num_ways = __log2_up(num_ways);
manhpham 0:c8673aa96267 970 if ((log2_num_ways < 0) || (log2_num_ways > 32)) {
manhpham 0:c8673aa96267 971 return; // FATAL ERROR
manhpham 0:c8673aa96267 972 }
manhpham 0:c8673aa96267 973 shift_way = 32U - (uint32_t)log2_num_ways;
manhpham 0:c8673aa96267 974 for(int32_t way = num_ways-1; way >= 0; way--)
manhpham 0:c8673aa96267 975 {
manhpham 0:c8673aa96267 976 for(int32_t set = num_sets-1; set >= 0; set--)
manhpham 0:c8673aa96267 977 {
manhpham 0:c8673aa96267 978 Dummy = (level << 1U) | (((uint32_t)set) << log2_linesize) | (((uint32_t)way) << shift_way);
manhpham 0:c8673aa96267 979 switch (maint)
manhpham 0:c8673aa96267 980 {
manhpham 0:c8673aa96267 981 case 0U: __set_DCISW(Dummy); break;
manhpham 0:c8673aa96267 982 case 1U: __set_DCCSW(Dummy); break;
manhpham 0:c8673aa96267 983 default: __set_DCCISW(Dummy); break;
manhpham 0:c8673aa96267 984 }
manhpham 0:c8673aa96267 985 }
manhpham 0:c8673aa96267 986 }
manhpham 0:c8673aa96267 987 __DMB();
manhpham 0:c8673aa96267 988 }
manhpham 0:c8673aa96267 989
manhpham 0:c8673aa96267 990 /** \brief Clean and Invalidate the entire data or unified cache
manhpham 0:c8673aa96267 991 * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency
manhpham 0:c8673aa96267 992 * \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean
manhpham 0:c8673aa96267 993 */
manhpham 0:c8673aa96267 994 __STATIC_FORCEINLINE void L1C_CleanInvalidateCache(uint32_t op) {
manhpham 0:c8673aa96267 995 register volatile uint32_t clidr;
manhpham 0:c8673aa96267 996 uint32_t cache_type;
manhpham 0:c8673aa96267 997 clidr = __get_CLIDR();
manhpham 0:c8673aa96267 998 for(uint32_t i = 0U; i<7U; i++)
manhpham 0:c8673aa96267 999 {
manhpham 0:c8673aa96267 1000 cache_type = (clidr >> i*3U) & 0x7UL;
manhpham 0:c8673aa96267 1001 if ((cache_type >= 2U) && (cache_type <= 4U))
manhpham 0:c8673aa96267 1002 {
manhpham 0:c8673aa96267 1003 __L1C_MaintainDCacheSetWay(i, op);
manhpham 0:c8673aa96267 1004 }
manhpham 0:c8673aa96267 1005 }
manhpham 0:c8673aa96267 1006 }
manhpham 0:c8673aa96267 1007
manhpham 0:c8673aa96267 1008 /** \brief Clean and Invalidate the entire data or unified cache
manhpham 0:c8673aa96267 1009 * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency
manhpham 0:c8673aa96267 1010 * \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean
manhpham 0:c8673aa96267 1011 * \deprecated Use generic L1C_CleanInvalidateCache instead.
manhpham 0:c8673aa96267 1012 */
manhpham 0:c8673aa96267 1013 CMSIS_DEPRECATED
manhpham 0:c8673aa96267 1014 __STATIC_FORCEINLINE void __L1C_CleanInvalidateCache(uint32_t op) {
manhpham 0:c8673aa96267 1015 L1C_CleanInvalidateCache(op);
manhpham 0:c8673aa96267 1016 }
manhpham 0:c8673aa96267 1017
manhpham 0:c8673aa96267 1018 /** \brief Invalidate the whole data cache.
manhpham 0:c8673aa96267 1019 */
manhpham 0:c8673aa96267 1020 __STATIC_FORCEINLINE void L1C_InvalidateDCacheAll(void) {
manhpham 0:c8673aa96267 1021 L1C_CleanInvalidateCache(0);
manhpham 0:c8673aa96267 1022 }
manhpham 0:c8673aa96267 1023
manhpham 0:c8673aa96267 1024 /** \brief Clean the whole data cache.
manhpham 0:c8673aa96267 1025 */
manhpham 0:c8673aa96267 1026 __STATIC_FORCEINLINE void L1C_CleanDCacheAll(void) {
manhpham 0:c8673aa96267 1027 L1C_CleanInvalidateCache(1);
manhpham 0:c8673aa96267 1028 }
manhpham 0:c8673aa96267 1029
manhpham 0:c8673aa96267 1030 /** \brief Clean and invalidate the whole data cache.
manhpham 0:c8673aa96267 1031 */
manhpham 0:c8673aa96267 1032 __STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheAll(void) {
manhpham 0:c8673aa96267 1033 L1C_CleanInvalidateCache(2);
manhpham 0:c8673aa96267 1034 }
manhpham 0:c8673aa96267 1035
manhpham 0:c8673aa96267 1036 /* ########################## L2 Cache functions ################################# */
manhpham 0:c8673aa96267 1037 #if (__L2C_PRESENT == 1U) || defined(DOXYGEN)
manhpham 0:c8673aa96267 1038 /** \brief Cache Sync operation by writing CACHE_SYNC register.
manhpham 0:c8673aa96267 1039 */
manhpham 0:c8673aa96267 1040 __STATIC_INLINE void L2C_Sync(void)
manhpham 0:c8673aa96267 1041 {
manhpham 0:c8673aa96267 1042 L2C_310->CACHE_SYNC = 0x0;
manhpham 0:c8673aa96267 1043 }
manhpham 0:c8673aa96267 1044
manhpham 0:c8673aa96267 1045 /** \brief Read cache controller cache ID from CACHE_ID register.
manhpham 0:c8673aa96267 1046 * \return L2C_310_TypeDef::CACHE_ID
manhpham 0:c8673aa96267 1047 */
manhpham 0:c8673aa96267 1048 __STATIC_INLINE int L2C_GetID (void)
manhpham 0:c8673aa96267 1049 {
manhpham 0:c8673aa96267 1050 return L2C_310->CACHE_ID;
manhpham 0:c8673aa96267 1051 }
manhpham 0:c8673aa96267 1052
manhpham 0:c8673aa96267 1053 /** \brief Read cache controller cache type from CACHE_TYPE register.
manhpham 0:c8673aa96267 1054 * \return L2C_310_TypeDef::CACHE_TYPE
manhpham 0:c8673aa96267 1055 */
manhpham 0:c8673aa96267 1056 __STATIC_INLINE int L2C_GetType (void)
manhpham 0:c8673aa96267 1057 {
manhpham 0:c8673aa96267 1058 return L2C_310->CACHE_TYPE;
manhpham 0:c8673aa96267 1059 }
manhpham 0:c8673aa96267 1060
manhpham 0:c8673aa96267 1061 /** \brief Invalidate all cache by way
manhpham 0:c8673aa96267 1062 */
manhpham 0:c8673aa96267 1063 __STATIC_INLINE void L2C_InvAllByWay (void)
manhpham 0:c8673aa96267 1064 {
manhpham 0:c8673aa96267 1065 unsigned int assoc;
manhpham 0:c8673aa96267 1066
manhpham 0:c8673aa96267 1067 if (L2C_310->AUX_CNT & (1U << 16U)) {
manhpham 0:c8673aa96267 1068 assoc = 16U;
manhpham 0:c8673aa96267 1069 } else {
manhpham 0:c8673aa96267 1070 assoc = 8U;
manhpham 0:c8673aa96267 1071 }
manhpham 0:c8673aa96267 1072
manhpham 0:c8673aa96267 1073 L2C_310->INV_WAY = (1U << assoc) - 1U;
manhpham 0:c8673aa96267 1074 while(L2C_310->INV_WAY & ((1U << assoc) - 1U)); //poll invalidate
manhpham 0:c8673aa96267 1075
manhpham 0:c8673aa96267 1076 L2C_Sync();
manhpham 0:c8673aa96267 1077 }
manhpham 0:c8673aa96267 1078
manhpham 0:c8673aa96267 1079 /** \brief Clean and Invalidate all cache by way
manhpham 0:c8673aa96267 1080 */
manhpham 0:c8673aa96267 1081 __STATIC_INLINE void L2C_CleanInvAllByWay (void)
manhpham 0:c8673aa96267 1082 {
manhpham 0:c8673aa96267 1083 unsigned int assoc;
manhpham 0:c8673aa96267 1084
manhpham 0:c8673aa96267 1085 if (L2C_310->AUX_CNT & (1U << 16U)) {
manhpham 0:c8673aa96267 1086 assoc = 16U;
manhpham 0:c8673aa96267 1087 } else {
manhpham 0:c8673aa96267 1088 assoc = 8U;
manhpham 0:c8673aa96267 1089 }
manhpham 0:c8673aa96267 1090
manhpham 0:c8673aa96267 1091 L2C_310->CLEAN_INV_WAY = (1U << assoc) - 1U;
manhpham 0:c8673aa96267 1092 while(L2C_310->CLEAN_INV_WAY & ((1U << assoc) - 1U)); //poll invalidate
manhpham 0:c8673aa96267 1093
manhpham 0:c8673aa96267 1094 L2C_Sync();
manhpham 0:c8673aa96267 1095 }
manhpham 0:c8673aa96267 1096
manhpham 0:c8673aa96267 1097 /** \brief Enable Level 2 Cache
manhpham 0:c8673aa96267 1098 */
manhpham 0:c8673aa96267 1099 __STATIC_INLINE void L2C_Enable(void)
manhpham 0:c8673aa96267 1100 {
manhpham 0:c8673aa96267 1101 L2C_310->CONTROL = 0;
manhpham 0:c8673aa96267 1102 L2C_310->INTERRUPT_CLEAR = 0x000001FFuL;
manhpham 0:c8673aa96267 1103 L2C_310->DEBUG_CONTROL = 0;
manhpham 0:c8673aa96267 1104 L2C_310->DATA_LOCK_0_WAY = 0;
manhpham 0:c8673aa96267 1105 L2C_310->CACHE_SYNC = 0;
manhpham 0:c8673aa96267 1106 L2C_310->CONTROL = 0x01;
manhpham 0:c8673aa96267 1107 L2C_Sync();
manhpham 0:c8673aa96267 1108 }
manhpham 0:c8673aa96267 1109
manhpham 0:c8673aa96267 1110 /** \brief Disable Level 2 Cache
manhpham 0:c8673aa96267 1111 */
manhpham 0:c8673aa96267 1112 __STATIC_INLINE void L2C_Disable(void)
manhpham 0:c8673aa96267 1113 {
manhpham 0:c8673aa96267 1114 L2C_310->CONTROL = 0x00;
manhpham 0:c8673aa96267 1115 L2C_Sync();
manhpham 0:c8673aa96267 1116 }
manhpham 0:c8673aa96267 1117
manhpham 0:c8673aa96267 1118 /** \brief Invalidate cache by physical address
manhpham 0:c8673aa96267 1119 * \param [in] pa Pointer to data to invalidate cache for.
manhpham 0:c8673aa96267 1120 */
manhpham 0:c8673aa96267 1121 __STATIC_INLINE void L2C_InvPa (void *pa)
manhpham 0:c8673aa96267 1122 {
manhpham 0:c8673aa96267 1123 L2C_310->INV_LINE_PA = (unsigned int)pa;
manhpham 0:c8673aa96267 1124 L2C_Sync();
manhpham 0:c8673aa96267 1125 }
manhpham 0:c8673aa96267 1126
manhpham 0:c8673aa96267 1127 /** \brief Clean cache by physical address
manhpham 0:c8673aa96267 1128 * \param [in] pa Pointer to data to invalidate cache for.
manhpham 0:c8673aa96267 1129 */
manhpham 0:c8673aa96267 1130 __STATIC_INLINE void L2C_CleanPa (void *pa)
manhpham 0:c8673aa96267 1131 {
manhpham 0:c8673aa96267 1132 L2C_310->CLEAN_LINE_PA = (unsigned int)pa;
manhpham 0:c8673aa96267 1133 L2C_Sync();
manhpham 0:c8673aa96267 1134 }
manhpham 0:c8673aa96267 1135
manhpham 0:c8673aa96267 1136 /** \brief Clean and invalidate cache by physical address
manhpham 0:c8673aa96267 1137 * \param [in] pa Pointer to data to invalidate cache for.
manhpham 0:c8673aa96267 1138 */
manhpham 0:c8673aa96267 1139 __STATIC_INLINE void L2C_CleanInvPa (void *pa)
manhpham 0:c8673aa96267 1140 {
manhpham 0:c8673aa96267 1141 L2C_310->CLEAN_INV_LINE_PA = (unsigned int)pa;
manhpham 0:c8673aa96267 1142 L2C_Sync();
manhpham 0:c8673aa96267 1143 }
manhpham 0:c8673aa96267 1144 #endif
manhpham 0:c8673aa96267 1145
manhpham 0:c8673aa96267 1146 /* ########################## GIC functions ###################################### */
manhpham 0:c8673aa96267 1147 #if (__GIC_PRESENT == 1U) || defined(DOXYGEN)
manhpham 0:c8673aa96267 1148
manhpham 0:c8673aa96267 1149 /** \brief Enable the interrupt distributor using the GIC's CTLR register.
manhpham 0:c8673aa96267 1150 */
manhpham 0:c8673aa96267 1151 __STATIC_INLINE void GIC_EnableDistributor(void)
manhpham 0:c8673aa96267 1152 {
manhpham 0:c8673aa96267 1153 GICDistributor->CTLR |= 1U;
manhpham 0:c8673aa96267 1154 }
manhpham 0:c8673aa96267 1155
manhpham 0:c8673aa96267 1156 /** \brief Disable the interrupt distributor using the GIC's CTLR register.
manhpham 0:c8673aa96267 1157 */
manhpham 0:c8673aa96267 1158 __STATIC_INLINE void GIC_DisableDistributor(void)
manhpham 0:c8673aa96267 1159 {
manhpham 0:c8673aa96267 1160 GICDistributor->CTLR &=~1U;
manhpham 0:c8673aa96267 1161 }
manhpham 0:c8673aa96267 1162
manhpham 0:c8673aa96267 1163 /** \brief Read the GIC's TYPER register.
manhpham 0:c8673aa96267 1164 * \return GICDistributor_Type::TYPER
manhpham 0:c8673aa96267 1165 */
manhpham 0:c8673aa96267 1166 __STATIC_INLINE uint32_t GIC_DistributorInfo(void)
manhpham 0:c8673aa96267 1167 {
manhpham 0:c8673aa96267 1168 return (GICDistributor->TYPER);
manhpham 0:c8673aa96267 1169 }
manhpham 0:c8673aa96267 1170
manhpham 0:c8673aa96267 1171 /** \brief Reads the GIC's IIDR register.
manhpham 0:c8673aa96267 1172 * \return GICDistributor_Type::IIDR
manhpham 0:c8673aa96267 1173 */
manhpham 0:c8673aa96267 1174 __STATIC_INLINE uint32_t GIC_DistributorImplementer(void)
manhpham 0:c8673aa96267 1175 {
manhpham 0:c8673aa96267 1176 return (GICDistributor->IIDR);
manhpham 0:c8673aa96267 1177 }
manhpham 0:c8673aa96267 1178
manhpham 0:c8673aa96267 1179 /** \brief Sets the GIC's ITARGETSR register for the given interrupt.
manhpham 0:c8673aa96267 1180 * \param [in] IRQn Interrupt to be configured.
manhpham 0:c8673aa96267 1181 * \param [in] cpu_target CPU interfaces to assign this interrupt to.
manhpham 0:c8673aa96267 1182 */
manhpham 0:c8673aa96267 1183 __STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)
manhpham 0:c8673aa96267 1184 {
manhpham 0:c8673aa96267 1185 uint32_t mask = GICDistributor->ITARGETSR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U));
manhpham 0:c8673aa96267 1186 GICDistributor->ITARGETSR[IRQn / 4U] = mask | ((cpu_target & 0xFFUL) << ((IRQn % 4U) * 8U));
manhpham 0:c8673aa96267 1187 }
manhpham 0:c8673aa96267 1188
manhpham 0:c8673aa96267 1189 /** \brief Read the GIC's ITARGETSR register.
manhpham 0:c8673aa96267 1190 * \param [in] IRQn Interrupt to acquire the configuration for.
manhpham 0:c8673aa96267 1191 * \return GICDistributor_Type::ITARGETSR
manhpham 0:c8673aa96267 1192 */
manhpham 0:c8673aa96267 1193 __STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn)
manhpham 0:c8673aa96267 1194 {
manhpham 0:c8673aa96267 1195 return (GICDistributor->ITARGETSR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;
manhpham 0:c8673aa96267 1196 }
manhpham 0:c8673aa96267 1197
manhpham 0:c8673aa96267 1198 /** \brief Enable the CPU's interrupt interface.
manhpham 0:c8673aa96267 1199 */
manhpham 0:c8673aa96267 1200 __STATIC_INLINE void GIC_EnableInterface(void)
manhpham 0:c8673aa96267 1201 {
manhpham 0:c8673aa96267 1202 GICInterface->CTLR |= 1U; //enable interface
manhpham 0:c8673aa96267 1203 }
manhpham 0:c8673aa96267 1204
manhpham 0:c8673aa96267 1205 /** \brief Disable the CPU's interrupt interface.
manhpham 0:c8673aa96267 1206 */
manhpham 0:c8673aa96267 1207 __STATIC_INLINE void GIC_DisableInterface(void)
manhpham 0:c8673aa96267 1208 {
manhpham 0:c8673aa96267 1209 GICInterface->CTLR &=~1U; //disable distributor
manhpham 0:c8673aa96267 1210 }
manhpham 0:c8673aa96267 1211
manhpham 0:c8673aa96267 1212 /** \brief Read the CPU's IAR register.
manhpham 0:c8673aa96267 1213 * \return GICInterface_Type::IAR
manhpham 0:c8673aa96267 1214 */
manhpham 0:c8673aa96267 1215 __STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void)
manhpham 0:c8673aa96267 1216 {
manhpham 0:c8673aa96267 1217 return (IRQn_Type)(GICInterface->IAR);
manhpham 0:c8673aa96267 1218 }
manhpham 0:c8673aa96267 1219
manhpham 0:c8673aa96267 1220 /** \brief Writes the given interrupt number to the CPU's EOIR register.
manhpham 0:c8673aa96267 1221 * \param [in] IRQn The interrupt to be signaled as finished.
manhpham 0:c8673aa96267 1222 */
manhpham 0:c8673aa96267 1223 __STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn)
manhpham 0:c8673aa96267 1224 {
manhpham 0:c8673aa96267 1225 GICInterface->EOIR = IRQn;
manhpham 0:c8673aa96267 1226 }
manhpham 0:c8673aa96267 1227
manhpham 0:c8673aa96267 1228 /** \brief Enables the given interrupt using GIC's ISENABLER register.
manhpham 0:c8673aa96267 1229 * \param [in] IRQn The interrupt to be enabled.
manhpham 0:c8673aa96267 1230 */
manhpham 0:c8673aa96267 1231 __STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn)
manhpham 0:c8673aa96267 1232 {
manhpham 0:c8673aa96267 1233 GICDistributor->ISENABLER[IRQn / 32U] = 1U << (IRQn % 32U);
manhpham 0:c8673aa96267 1234 }
manhpham 0:c8673aa96267 1235
manhpham 0:c8673aa96267 1236 /** \brief Get interrupt enable status using GIC's ISENABLER register.
manhpham 0:c8673aa96267 1237 * \param [in] IRQn The interrupt to be queried.
manhpham 0:c8673aa96267 1238 * \return 0 - interrupt is not enabled, 1 - interrupt is enabled.
manhpham 0:c8673aa96267 1239 */
manhpham 0:c8673aa96267 1240 __STATIC_INLINE uint32_t GIC_GetEnableIRQ(IRQn_Type IRQn)
manhpham 0:c8673aa96267 1241 {
manhpham 0:c8673aa96267 1242 return (GICDistributor->ISENABLER[IRQn / 32U] >> (IRQn % 32U)) & 1UL;
manhpham 0:c8673aa96267 1243 }
manhpham 0:c8673aa96267 1244
manhpham 0:c8673aa96267 1245 /** \brief Disables the given interrupt using GIC's ICENABLER register.
manhpham 0:c8673aa96267 1246 * \param [in] IRQn The interrupt to be disabled.
manhpham 0:c8673aa96267 1247 */
manhpham 0:c8673aa96267 1248 __STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn)
manhpham 0:c8673aa96267 1249 {
manhpham 0:c8673aa96267 1250 GICDistributor->ICENABLER[IRQn / 32U] = 1U << (IRQn % 32U);
manhpham 0:c8673aa96267 1251 }
manhpham 0:c8673aa96267 1252
manhpham 0:c8673aa96267 1253 /** \brief Get interrupt pending status from GIC's ISPENDR register.
manhpham 0:c8673aa96267 1254 * \param [in] IRQn The interrupt to be queried.
manhpham 0:c8673aa96267 1255 * \return 0 - interrupt is not pending, 1 - interrupt is pendig.
manhpham 0:c8673aa96267 1256 */
manhpham 0:c8673aa96267 1257 __STATIC_INLINE uint32_t GIC_GetPendingIRQ(IRQn_Type IRQn)
manhpham 0:c8673aa96267 1258 {
manhpham 0:c8673aa96267 1259 uint32_t pend;
manhpham 0:c8673aa96267 1260
manhpham 0:c8673aa96267 1261 if (IRQn >= 16U) {
manhpham 0:c8673aa96267 1262 pend = (GICDistributor->ISPENDR[IRQn / 32U] >> (IRQn % 32U)) & 1UL;
manhpham 0:c8673aa96267 1263 } else {
manhpham 0:c8673aa96267 1264 // INTID 0-15 Software Generated Interrupt
manhpham 0:c8673aa96267 1265 pend = (GICDistributor->SPENDSGIR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;
manhpham 0:c8673aa96267 1266 // No CPU identification offered
manhpham 0:c8673aa96267 1267 if (pend != 0U) {
manhpham 0:c8673aa96267 1268 pend = 1U;
manhpham 0:c8673aa96267 1269 } else {
manhpham 0:c8673aa96267 1270 pend = 0U;
manhpham 0:c8673aa96267 1271 }
manhpham 0:c8673aa96267 1272 }
manhpham 0:c8673aa96267 1273
manhpham 0:c8673aa96267 1274 return (pend);
manhpham 0:c8673aa96267 1275 }
manhpham 0:c8673aa96267 1276
manhpham 0:c8673aa96267 1277 /** \brief Sets the given interrupt as pending using GIC's ISPENDR register.
manhpham 0:c8673aa96267 1278 * \param [in] IRQn The interrupt to be enabled.
manhpham 0:c8673aa96267 1279 */
manhpham 0:c8673aa96267 1280 __STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn)
manhpham 0:c8673aa96267 1281 {
manhpham 0:c8673aa96267 1282 if (IRQn >= 16U) {
manhpham 0:c8673aa96267 1283 GICDistributor->ISPENDR[IRQn / 32U] = 1U << (IRQn % 32U);
manhpham 0:c8673aa96267 1284 } else {
manhpham 0:c8673aa96267 1285 // INTID 0-15 Software Generated Interrupt
manhpham 0:c8673aa96267 1286 GICDistributor->SPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U);
manhpham 0:c8673aa96267 1287 // Forward the interrupt to the CPU interface that requested it
manhpham 0:c8673aa96267 1288 GICDistributor->SGIR = (IRQn | 0x02000000U);
manhpham 0:c8673aa96267 1289 }
manhpham 0:c8673aa96267 1290 }
manhpham 0:c8673aa96267 1291
manhpham 0:c8673aa96267 1292 /** \brief Clears the given interrupt from being pending using GIC's ICPENDR register.
manhpham 0:c8673aa96267 1293 * \param [in] IRQn The interrupt to be enabled.
manhpham 0:c8673aa96267 1294 */
manhpham 0:c8673aa96267 1295 __STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn)
manhpham 0:c8673aa96267 1296 {
manhpham 0:c8673aa96267 1297 if (IRQn >= 16U) {
manhpham 0:c8673aa96267 1298 GICDistributor->ICPENDR[IRQn / 32U] = 1U << (IRQn % 32U);
manhpham 0:c8673aa96267 1299 } else {
manhpham 0:c8673aa96267 1300 // INTID 0-15 Software Generated Interrupt
manhpham 0:c8673aa96267 1301 GICDistributor->CPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U);
manhpham 0:c8673aa96267 1302 }
manhpham 0:c8673aa96267 1303 }
manhpham 0:c8673aa96267 1304
manhpham 0:c8673aa96267 1305 /** \brief Sets the interrupt configuration using GIC's ICFGR register.
manhpham 0:c8673aa96267 1306 * \param [in] IRQn The interrupt to be configured.
manhpham 0:c8673aa96267 1307 * \param [in] int_config Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1)
manhpham 0:c8673aa96267 1308 * Bit 1: 0 - level sensitive, 1 - edge triggered
manhpham 0:c8673aa96267 1309 */
manhpham 0:c8673aa96267 1310 __STATIC_INLINE void GIC_SetConfiguration(IRQn_Type IRQn, uint32_t int_config)
manhpham 0:c8673aa96267 1311 {
manhpham 0:c8673aa96267 1312 uint32_t icfgr = GICDistributor->ICFGR[IRQn / 16U];
manhpham 0:c8673aa96267 1313 uint32_t shift = (IRQn % 16U) << 1U;
manhpham 0:c8673aa96267 1314
manhpham 0:c8673aa96267 1315 icfgr &= (~(3U << shift));
manhpham 0:c8673aa96267 1316 icfgr |= ( int_config << shift);
manhpham 0:c8673aa96267 1317
manhpham 0:c8673aa96267 1318 GICDistributor->ICFGR[IRQn / 16U] = icfgr;
manhpham 0:c8673aa96267 1319 }
manhpham 0:c8673aa96267 1320
manhpham 0:c8673aa96267 1321 /** \brief Get the interrupt configuration from the GIC's ICFGR register.
manhpham 0:c8673aa96267 1322 * \param [in] IRQn Interrupt to acquire the configuration for.
manhpham 0:c8673aa96267 1323 * \return Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1)
manhpham 0:c8673aa96267 1324 * Bit 1: 0 - level sensitive, 1 - edge triggered
manhpham 0:c8673aa96267 1325 */
manhpham 0:c8673aa96267 1326 __STATIC_INLINE uint32_t GIC_GetConfiguration(IRQn_Type IRQn)
manhpham 0:c8673aa96267 1327 {
manhpham 0:c8673aa96267 1328 return (GICDistributor->ICFGR[IRQn / 16U] >> ((IRQn % 16U) >> 1U));
manhpham 0:c8673aa96267 1329 }
manhpham 0:c8673aa96267 1330
manhpham 0:c8673aa96267 1331 /** \brief Set the priority for the given interrupt in the GIC's IPRIORITYR register.
manhpham 0:c8673aa96267 1332 * \param [in] IRQn The interrupt to be configured.
manhpham 0:c8673aa96267 1333 * \param [in] priority The priority for the interrupt, lower values denote higher priorities.
manhpham 0:c8673aa96267 1334 */
manhpham 0:c8673aa96267 1335 __STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
manhpham 0:c8673aa96267 1336 {
manhpham 0:c8673aa96267 1337 uint32_t mask = GICDistributor->IPRIORITYR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U));
manhpham 0:c8673aa96267 1338 GICDistributor->IPRIORITYR[IRQn / 4U] = mask | ((priority & 0xFFUL) << ((IRQn % 4U) * 8U));
manhpham 0:c8673aa96267 1339 }
manhpham 0:c8673aa96267 1340
manhpham 0:c8673aa96267 1341 /** \brief Read the current interrupt priority from GIC's IPRIORITYR register.
manhpham 0:c8673aa96267 1342 * \param [in] IRQn The interrupt to be queried.
manhpham 0:c8673aa96267 1343 */
manhpham 0:c8673aa96267 1344 __STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn)
manhpham 0:c8673aa96267 1345 {
manhpham 0:c8673aa96267 1346 return (GICDistributor->IPRIORITYR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;
manhpham 0:c8673aa96267 1347 }
manhpham 0:c8673aa96267 1348
manhpham 0:c8673aa96267 1349 /** \brief Set the interrupt priority mask using CPU's PMR register.
manhpham 0:c8673aa96267 1350 * \param [in] priority Priority mask to be set.
manhpham 0:c8673aa96267 1351 */
manhpham 0:c8673aa96267 1352 __STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority)
manhpham 0:c8673aa96267 1353 {
manhpham 0:c8673aa96267 1354 GICInterface->PMR = priority & 0xFFUL; //set priority mask
manhpham 0:c8673aa96267 1355 }
manhpham 0:c8673aa96267 1356
manhpham 0:c8673aa96267 1357 /** \brief Read the current interrupt priority mask from CPU's PMR register.
manhpham 0:c8673aa96267 1358 * \result GICInterface_Type::PMR
manhpham 0:c8673aa96267 1359 */
manhpham 0:c8673aa96267 1360 __STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void)
manhpham 0:c8673aa96267 1361 {
manhpham 0:c8673aa96267 1362 return GICInterface->PMR;
manhpham 0:c8673aa96267 1363 }
manhpham 0:c8673aa96267 1364
manhpham 0:c8673aa96267 1365 /** \brief Configures the group priority and subpriority split point using CPU's BPR register.
manhpham 0:c8673aa96267 1366 * \param [in] binary_point Amount of bits used as subpriority.
manhpham 0:c8673aa96267 1367 */
manhpham 0:c8673aa96267 1368 __STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point)
manhpham 0:c8673aa96267 1369 {
manhpham 0:c8673aa96267 1370 GICInterface->BPR = binary_point & 7U; //set binary point
manhpham 0:c8673aa96267 1371 }
manhpham 0:c8673aa96267 1372
manhpham 0:c8673aa96267 1373 /** \brief Read the current group priority and subpriority split point from CPU's BPR register.
manhpham 0:c8673aa96267 1374 * \return GICInterface_Type::BPR
manhpham 0:c8673aa96267 1375 */
manhpham 0:c8673aa96267 1376 __STATIC_INLINE uint32_t GIC_GetBinaryPoint(void)
manhpham 0:c8673aa96267 1377 {
manhpham 0:c8673aa96267 1378 return GICInterface->BPR;
manhpham 0:c8673aa96267 1379 }
manhpham 0:c8673aa96267 1380
manhpham 0:c8673aa96267 1381 /** \brief Get the status for a given interrupt.
manhpham 0:c8673aa96267 1382 * \param [in] IRQn The interrupt to get status for.
manhpham 0:c8673aa96267 1383 * \return 0 - not pending/active, 1 - pending, 2 - active, 3 - pending and active
manhpham 0:c8673aa96267 1384 */
manhpham 0:c8673aa96267 1385 __STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn)
manhpham 0:c8673aa96267 1386 {
manhpham 0:c8673aa96267 1387 uint32_t pending, active;
manhpham 0:c8673aa96267 1388
manhpham 0:c8673aa96267 1389 active = ((GICDistributor->ISACTIVER[IRQn / 32U]) >> (IRQn % 32U)) & 1UL;
manhpham 0:c8673aa96267 1390 pending = ((GICDistributor->ISPENDR[IRQn / 32U]) >> (IRQn % 32U)) & 1UL;
manhpham 0:c8673aa96267 1391
manhpham 0:c8673aa96267 1392 return ((active<<1U) | pending);
manhpham 0:c8673aa96267 1393 }
manhpham 0:c8673aa96267 1394
manhpham 0:c8673aa96267 1395 /** \brief Generate a software interrupt using GIC's SGIR register.
manhpham 0:c8673aa96267 1396 * \param [in] IRQn Software interrupt to be generated.
manhpham 0:c8673aa96267 1397 * \param [in] target_list List of CPUs the software interrupt should be forwarded to.
manhpham 0:c8673aa96267 1398 * \param [in] filter_list Filter to be applied to determine interrupt receivers.
manhpham 0:c8673aa96267 1399 */
manhpham 0:c8673aa96267 1400 __STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
manhpham 0:c8673aa96267 1401 {
manhpham 0:c8673aa96267 1402 GICDistributor->SGIR = ((filter_list & 3U) << 24U) | ((target_list & 0xFFUL) << 16U) | (IRQn & 0x0FUL);
manhpham 0:c8673aa96267 1403 }
manhpham 0:c8673aa96267 1404
manhpham 0:c8673aa96267 1405 /** \brief Get the interrupt number of the highest interrupt pending from CPU's HPPIR register.
manhpham 0:c8673aa96267 1406 * \return GICInterface_Type::HPPIR
manhpham 0:c8673aa96267 1407 */
manhpham 0:c8673aa96267 1408 __STATIC_INLINE uint32_t GIC_GetHighPendingIRQ(void)
manhpham 0:c8673aa96267 1409 {
manhpham 0:c8673aa96267 1410 return GICInterface->HPPIR;
manhpham 0:c8673aa96267 1411 }
manhpham 0:c8673aa96267 1412
manhpham 0:c8673aa96267 1413 /** \brief Provides information about the implementer and revision of the CPU interface.
manhpham 0:c8673aa96267 1414 * \return GICInterface_Type::IIDR
manhpham 0:c8673aa96267 1415 */
manhpham 0:c8673aa96267 1416 __STATIC_INLINE uint32_t GIC_GetInterfaceId(void)
manhpham 0:c8673aa96267 1417 {
manhpham 0:c8673aa96267 1418 return GICInterface->IIDR;
manhpham 0:c8673aa96267 1419 }
manhpham 0:c8673aa96267 1420
manhpham 0:c8673aa96267 1421 /** \brief Set the interrupt group from the GIC's IGROUPR register.
manhpham 0:c8673aa96267 1422 * \param [in] IRQn The interrupt to be queried.
manhpham 0:c8673aa96267 1423 * \param [in] group Interrupt group number: 0 - Group 0, 1 - Group 1
manhpham 0:c8673aa96267 1424 */
manhpham 0:c8673aa96267 1425 __STATIC_INLINE void GIC_SetGroup(IRQn_Type IRQn, uint32_t group)
manhpham 0:c8673aa96267 1426 {
manhpham 0:c8673aa96267 1427 uint32_t igroupr = GICDistributor->IGROUPR[IRQn / 32U];
manhpham 0:c8673aa96267 1428 uint32_t shift = (IRQn % 32U);
manhpham 0:c8673aa96267 1429
manhpham 0:c8673aa96267 1430 igroupr &= (~(1U << shift));
manhpham 0:c8673aa96267 1431 igroupr |= ( (group & 1U) << shift);
manhpham 0:c8673aa96267 1432
manhpham 0:c8673aa96267 1433 GICDistributor->IGROUPR[IRQn / 32U] = igroupr;
manhpham 0:c8673aa96267 1434 }
manhpham 0:c8673aa96267 1435 #define GIC_SetSecurity GIC_SetGroup
manhpham 0:c8673aa96267 1436
manhpham 0:c8673aa96267 1437 /** \brief Get the interrupt group from the GIC's IGROUPR register.
manhpham 0:c8673aa96267 1438 * \param [in] IRQn The interrupt to be queried.
manhpham 0:c8673aa96267 1439 * \return 0 - Group 0, 1 - Group 1
manhpham 0:c8673aa96267 1440 */
manhpham 0:c8673aa96267 1441 __STATIC_INLINE uint32_t GIC_GetGroup(IRQn_Type IRQn)
manhpham 0:c8673aa96267 1442 {
manhpham 0:c8673aa96267 1443 return (GICDistributor->IGROUPR[IRQn / 32U] >> (IRQn % 32U)) & 1UL;
manhpham 0:c8673aa96267 1444 }
manhpham 0:c8673aa96267 1445 #define GIC_GetSecurity GIC_GetGroup
manhpham 0:c8673aa96267 1446
manhpham 0:c8673aa96267 1447 /** \brief Initialize the interrupt distributor.
manhpham 0:c8673aa96267 1448 */
manhpham 0:c8673aa96267 1449 __STATIC_INLINE void GIC_DistInit(void)
manhpham 0:c8673aa96267 1450 {
manhpham 0:c8673aa96267 1451 uint32_t i;
manhpham 0:c8673aa96267 1452 uint32_t num_irq = 0U;
manhpham 0:c8673aa96267 1453 uint32_t priority_field;
manhpham 0:c8673aa96267 1454
manhpham 0:c8673aa96267 1455 //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0,
manhpham 0:c8673aa96267 1456 //configuring all of the interrupts as Secure.
manhpham 0:c8673aa96267 1457
manhpham 0:c8673aa96267 1458 //Disable interrupt forwarding
manhpham 0:c8673aa96267 1459 GIC_DisableDistributor();
manhpham 0:c8673aa96267 1460 //Get the maximum number of interrupts that the GIC supports
manhpham 0:c8673aa96267 1461 num_irq = 32U * ((GIC_DistributorInfo() & 0x1FU) + 1U);
manhpham 0:c8673aa96267 1462
manhpham 0:c8673aa96267 1463 /* Priority level is implementation defined.
manhpham 0:c8673aa96267 1464 To determine the number of priority bits implemented write 0xFF to an IPRIORITYR
manhpham 0:c8673aa96267 1465 priority field and read back the value stored.*/
manhpham 0:c8673aa96267 1466 GIC_SetPriority((IRQn_Type)0U, 0xFFU);
manhpham 0:c8673aa96267 1467 priority_field = GIC_GetPriority((IRQn_Type)0U);
manhpham 0:c8673aa96267 1468
manhpham 0:c8673aa96267 1469 for (i = 32U; i < num_irq; i++)
manhpham 0:c8673aa96267 1470 {
manhpham 0:c8673aa96267 1471 //Disable the SPI interrupt
manhpham 0:c8673aa96267 1472 GIC_DisableIRQ((IRQn_Type)i);
manhpham 0:c8673aa96267 1473 //Set level-sensitive (and N-N model)
manhpham 0:c8673aa96267 1474 GIC_SetConfiguration((IRQn_Type)i, 0U);
manhpham 0:c8673aa96267 1475 //Set priority
manhpham 0:c8673aa96267 1476 GIC_SetPriority((IRQn_Type)i, priority_field/2U);
manhpham 0:c8673aa96267 1477 //Set target list to CPU0
manhpham 0:c8673aa96267 1478 GIC_SetTarget((IRQn_Type)i, 1U);
manhpham 0:c8673aa96267 1479 }
manhpham 0:c8673aa96267 1480 //Enable distributor
manhpham 0:c8673aa96267 1481 GIC_EnableDistributor();
manhpham 0:c8673aa96267 1482 }
manhpham 0:c8673aa96267 1483
manhpham 0:c8673aa96267 1484 /** \brief Initialize the CPU's interrupt interface
manhpham 0:c8673aa96267 1485 */
manhpham 0:c8673aa96267 1486 __STATIC_INLINE void GIC_CPUInterfaceInit(void)
manhpham 0:c8673aa96267 1487 {
manhpham 0:c8673aa96267 1488 uint32_t i;
manhpham 0:c8673aa96267 1489 uint32_t priority_field;
manhpham 0:c8673aa96267 1490
manhpham 0:c8673aa96267 1491 //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0,
manhpham 0:c8673aa96267 1492 //configuring all of the interrupts as Secure.
manhpham 0:c8673aa96267 1493
manhpham 0:c8673aa96267 1494 //Disable interrupt forwarding
manhpham 0:c8673aa96267 1495 GIC_DisableInterface();
manhpham 0:c8673aa96267 1496
manhpham 0:c8673aa96267 1497 /* Priority level is implementation defined.
manhpham 0:c8673aa96267 1498 To determine the number of priority bits implemented write 0xFF to an IPRIORITYR
manhpham 0:c8673aa96267 1499 priority field and read back the value stored.*/
manhpham 0:c8673aa96267 1500 GIC_SetPriority((IRQn_Type)0U, 0xFFU);
manhpham 0:c8673aa96267 1501 priority_field = GIC_GetPriority((IRQn_Type)0U);
manhpham 0:c8673aa96267 1502
manhpham 0:c8673aa96267 1503 //SGI and PPI
manhpham 0:c8673aa96267 1504 for (i = 0U; i < 32U; i++)
manhpham 0:c8673aa96267 1505 {
manhpham 0:c8673aa96267 1506 if(i > 15U) {
manhpham 0:c8673aa96267 1507 //Set level-sensitive (and N-N model) for PPI
manhpham 0:c8673aa96267 1508 GIC_SetConfiguration((IRQn_Type)i, 0U);
manhpham 0:c8673aa96267 1509 }
manhpham 0:c8673aa96267 1510 //Disable SGI and PPI interrupts
manhpham 0:c8673aa96267 1511 GIC_DisableIRQ((IRQn_Type)i);
manhpham 0:c8673aa96267 1512 //Set priority
manhpham 0:c8673aa96267 1513 GIC_SetPriority((IRQn_Type)i, priority_field/2U);
manhpham 0:c8673aa96267 1514 }
manhpham 0:c8673aa96267 1515 //Enable interface
manhpham 0:c8673aa96267 1516 GIC_EnableInterface();
manhpham 0:c8673aa96267 1517 //Set binary point to 0
manhpham 0:c8673aa96267 1518 GIC_SetBinaryPoint(0U);
manhpham 0:c8673aa96267 1519 //Set priority mask
manhpham 0:c8673aa96267 1520 GIC_SetInterfacePriorityMask(0xFFU);
manhpham 0:c8673aa96267 1521 }
manhpham 0:c8673aa96267 1522
manhpham 0:c8673aa96267 1523 /** \brief Initialize and enable the GIC
manhpham 0:c8673aa96267 1524 */
manhpham 0:c8673aa96267 1525 __STATIC_INLINE void GIC_Enable(void)
manhpham 0:c8673aa96267 1526 {
manhpham 0:c8673aa96267 1527 GIC_DistInit();
manhpham 0:c8673aa96267 1528 GIC_CPUInterfaceInit(); //per CPU
manhpham 0:c8673aa96267 1529 }
manhpham 0:c8673aa96267 1530 #endif
manhpham 0:c8673aa96267 1531
manhpham 0:c8673aa96267 1532 /* ########################## Generic Timer functions ############################ */
manhpham 0:c8673aa96267 1533 #if (__TIM_PRESENT == 1U) || defined(DOXYGEN)
manhpham 0:c8673aa96267 1534
manhpham 0:c8673aa96267 1535 /* PL1 Physical Timer */
manhpham 0:c8673aa96267 1536 #if (__CORTEX_A == 7U) || defined(DOXYGEN)
manhpham 0:c8673aa96267 1537
manhpham 0:c8673aa96267 1538 /** \brief Physical Timer Control register */
manhpham 0:c8673aa96267 1539 typedef union
manhpham 0:c8673aa96267 1540 {
manhpham 0:c8673aa96267 1541 struct
manhpham 0:c8673aa96267 1542 {
manhpham 0:c8673aa96267 1543 uint32_t ENABLE:1; /*!< \brief bit: 0 Enables the timer. */
manhpham 0:c8673aa96267 1544 uint32_t IMASK:1; /*!< \brief bit: 1 Timer output signal mask bit. */
manhpham 0:c8673aa96267 1545 uint32_t ISTATUS:1; /*!< \brief bit: 2 The status of the timer. */
manhpham 0:c8673aa96267 1546 RESERVED(0:29, uint32_t)
manhpham 0:c8673aa96267 1547 } b; /*!< \brief Structure used for bit access */
manhpham 0:c8673aa96267 1548 uint32_t w; /*!< \brief Type used for word access */
manhpham 0:c8673aa96267 1549 } CNTP_CTL_Type;
manhpham 0:c8673aa96267 1550
manhpham 0:c8673aa96267 1551 /** \brief Configures the frequency the timer shall run at.
manhpham 0:c8673aa96267 1552 * \param [in] value The timer frequency in Hz.
manhpham 0:c8673aa96267 1553 */
manhpham 0:c8673aa96267 1554 __STATIC_INLINE void PL1_SetCounterFrequency(uint32_t value)
manhpham 0:c8673aa96267 1555 {
manhpham 0:c8673aa96267 1556 __set_CNTFRQ(value);
manhpham 0:c8673aa96267 1557 __ISB();
manhpham 0:c8673aa96267 1558 }
manhpham 0:c8673aa96267 1559
manhpham 0:c8673aa96267 1560 /** \brief Sets the reset value of the timer.
manhpham 0:c8673aa96267 1561 * \param [in] value The value the timer is loaded with.
manhpham 0:c8673aa96267 1562 */
manhpham 0:c8673aa96267 1563 __STATIC_INLINE void PL1_SetLoadValue(uint32_t value)
manhpham 0:c8673aa96267 1564 {
manhpham 0:c8673aa96267 1565 __set_CNTP_TVAL(value);
manhpham 0:c8673aa96267 1566 __ISB();
manhpham 0:c8673aa96267 1567 }
manhpham 0:c8673aa96267 1568
manhpham 0:c8673aa96267 1569 /** \brief Get the current counter value.
manhpham 0:c8673aa96267 1570 * \return Current counter value.
manhpham 0:c8673aa96267 1571 */
manhpham 0:c8673aa96267 1572 __STATIC_INLINE uint32_t PL1_GetCurrentValue(void)
manhpham 0:c8673aa96267 1573 {
manhpham 0:c8673aa96267 1574 return(__get_CNTP_TVAL());
manhpham 0:c8673aa96267 1575 }
manhpham 0:c8673aa96267 1576
manhpham 0:c8673aa96267 1577 /** \brief Get the current physical counter value.
manhpham 0:c8673aa96267 1578 * \return Current physical counter value.
manhpham 0:c8673aa96267 1579 */
manhpham 0:c8673aa96267 1580 __STATIC_INLINE uint64_t PL1_GetCurrentPhysicalValue(void)
manhpham 0:c8673aa96267 1581 {
manhpham 0:c8673aa96267 1582 return(__get_CNTPCT());
manhpham 0:c8673aa96267 1583 }
manhpham 0:c8673aa96267 1584
manhpham 0:c8673aa96267 1585 /** \brief Set the physical compare value.
manhpham 0:c8673aa96267 1586 * \param [in] value New physical timer compare value.
manhpham 0:c8673aa96267 1587 */
manhpham 0:c8673aa96267 1588 __STATIC_INLINE void PL1_SetPhysicalCompareValue(uint64_t value)
manhpham 0:c8673aa96267 1589 {
manhpham 0:c8673aa96267 1590 __set_CNTP_CVAL(value);
manhpham 0:c8673aa96267 1591 __ISB();
manhpham 0:c8673aa96267 1592 }
manhpham 0:c8673aa96267 1593
manhpham 0:c8673aa96267 1594 /** \brief Get the physical compare value.
manhpham 0:c8673aa96267 1595 * \return Physical compare value.
manhpham 0:c8673aa96267 1596 */
manhpham 0:c8673aa96267 1597 __STATIC_INLINE uint64_t PL1_GetPhysicalCompareValue(void)
manhpham 0:c8673aa96267 1598 {
manhpham 0:c8673aa96267 1599 return(__get_CNTP_CVAL());
manhpham 0:c8673aa96267 1600 }
manhpham 0:c8673aa96267 1601
manhpham 0:c8673aa96267 1602 /** \brief Configure the timer by setting the control value.
manhpham 0:c8673aa96267 1603 * \param [in] value New timer control value.
manhpham 0:c8673aa96267 1604 */
manhpham 0:c8673aa96267 1605 __STATIC_INLINE void PL1_SetControl(uint32_t value)
manhpham 0:c8673aa96267 1606 {
manhpham 0:c8673aa96267 1607 __set_CNTP_CTL(value);
manhpham 0:c8673aa96267 1608 __ISB();
manhpham 0:c8673aa96267 1609 }
manhpham 0:c8673aa96267 1610
manhpham 0:c8673aa96267 1611 /** \brief Get the control value.
manhpham 0:c8673aa96267 1612 * \return Control value.
manhpham 0:c8673aa96267 1613 */
manhpham 0:c8673aa96267 1614 __STATIC_INLINE uint32_t PL1_GetControl(void)
manhpham 0:c8673aa96267 1615 {
manhpham 0:c8673aa96267 1616 return(__get_CNTP_CTL());
manhpham 0:c8673aa96267 1617 }
manhpham 0:c8673aa96267 1618 #endif
manhpham 0:c8673aa96267 1619
manhpham 0:c8673aa96267 1620 /* Private Timer */
manhpham 0:c8673aa96267 1621 #if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN)
manhpham 0:c8673aa96267 1622 /** \brief Set the load value to timers LOAD register.
manhpham 0:c8673aa96267 1623 * \param [in] value The load value to be set.
manhpham 0:c8673aa96267 1624 */
manhpham 0:c8673aa96267 1625 __STATIC_INLINE void PTIM_SetLoadValue(uint32_t value)
manhpham 0:c8673aa96267 1626 {
manhpham 0:c8673aa96267 1627 PTIM->LOAD = value;
manhpham 0:c8673aa96267 1628 }
manhpham 0:c8673aa96267 1629
manhpham 0:c8673aa96267 1630 /** \brief Get the load value from timers LOAD register.
manhpham 0:c8673aa96267 1631 * \return Timer_Type::LOAD
manhpham 0:c8673aa96267 1632 */
manhpham 0:c8673aa96267 1633 __STATIC_INLINE uint32_t PTIM_GetLoadValue(void)
manhpham 0:c8673aa96267 1634 {
manhpham 0:c8673aa96267 1635 return(PTIM->LOAD);
manhpham 0:c8673aa96267 1636 }
manhpham 0:c8673aa96267 1637
manhpham 0:c8673aa96267 1638 /** \brief Set current counter value from its COUNTER register.
manhpham 0:c8673aa96267 1639 */
manhpham 0:c8673aa96267 1640 __STATIC_INLINE void PTIM_SetCurrentValue(uint32_t value)
manhpham 0:c8673aa96267 1641 {
manhpham 0:c8673aa96267 1642 PTIM->COUNTER = value;
manhpham 0:c8673aa96267 1643 }
manhpham 0:c8673aa96267 1644
manhpham 0:c8673aa96267 1645 /** \brief Get current counter value from timers COUNTER register.
manhpham 0:c8673aa96267 1646 * \result Timer_Type::COUNTER
manhpham 0:c8673aa96267 1647 */
manhpham 0:c8673aa96267 1648 __STATIC_INLINE uint32_t PTIM_GetCurrentValue(void)
manhpham 0:c8673aa96267 1649 {
manhpham 0:c8673aa96267 1650 return(PTIM->COUNTER);
manhpham 0:c8673aa96267 1651 }
manhpham 0:c8673aa96267 1652
manhpham 0:c8673aa96267 1653 /** \brief Configure the timer using its CONTROL register.
manhpham 0:c8673aa96267 1654 * \param [in] value The new configuration value to be set.
manhpham 0:c8673aa96267 1655 */
manhpham 0:c8673aa96267 1656 __STATIC_INLINE void PTIM_SetControl(uint32_t value)
manhpham 0:c8673aa96267 1657 {
manhpham 0:c8673aa96267 1658 PTIM->CONTROL = value;
manhpham 0:c8673aa96267 1659 }
manhpham 0:c8673aa96267 1660
manhpham 0:c8673aa96267 1661 /** ref Timer_Type::CONTROL Get the current timer configuration from its CONTROL register.
manhpham 0:c8673aa96267 1662 * \return Timer_Type::CONTROL
manhpham 0:c8673aa96267 1663 */
manhpham 0:c8673aa96267 1664 __STATIC_INLINE uint32_t PTIM_GetControl(void)
manhpham 0:c8673aa96267 1665 {
manhpham 0:c8673aa96267 1666 return(PTIM->CONTROL);
manhpham 0:c8673aa96267 1667 }
manhpham 0:c8673aa96267 1668
manhpham 0:c8673aa96267 1669 /** ref Timer_Type::CONTROL Get the event flag in timers ISR register.
manhpham 0:c8673aa96267 1670 * \return 0 - flag is not set, 1- flag is set
manhpham 0:c8673aa96267 1671 */
manhpham 0:c8673aa96267 1672 __STATIC_INLINE uint32_t PTIM_GetEventFlag(void)
manhpham 0:c8673aa96267 1673 {
manhpham 0:c8673aa96267 1674 return (PTIM->ISR & 1UL);
manhpham 0:c8673aa96267 1675 }
manhpham 0:c8673aa96267 1676
manhpham 0:c8673aa96267 1677 /** ref Timer_Type::CONTROL Clears the event flag in timers ISR register.
manhpham 0:c8673aa96267 1678 */
manhpham 0:c8673aa96267 1679 __STATIC_INLINE void PTIM_ClearEventFlag(void)
manhpham 0:c8673aa96267 1680 {
manhpham 0:c8673aa96267 1681 PTIM->ISR = 1;
manhpham 0:c8673aa96267 1682 }
manhpham 0:c8673aa96267 1683 #endif
manhpham 0:c8673aa96267 1684 #endif
manhpham 0:c8673aa96267 1685
manhpham 0:c8673aa96267 1686 /* ########################## MMU functions ###################################### */
manhpham 0:c8673aa96267 1687
manhpham 0:c8673aa96267 1688 #define SECTION_DESCRIPTOR (0x2)
manhpham 0:c8673aa96267 1689 #define SECTION_MASK (0xFFFFFFFC)
manhpham 0:c8673aa96267 1690
manhpham 0:c8673aa96267 1691 #define SECTION_TEXCB_MASK (0xFFFF8FF3)
manhpham 0:c8673aa96267 1692 #define SECTION_B_SHIFT (2)
manhpham 0:c8673aa96267 1693 #define SECTION_C_SHIFT (3)
manhpham 0:c8673aa96267 1694 #define SECTION_TEX0_SHIFT (12)
manhpham 0:c8673aa96267 1695 #define SECTION_TEX1_SHIFT (13)
manhpham 0:c8673aa96267 1696 #define SECTION_TEX2_SHIFT (14)
manhpham 0:c8673aa96267 1697
manhpham 0:c8673aa96267 1698 #define SECTION_XN_MASK (0xFFFFFFEF)
manhpham 0:c8673aa96267 1699 #define SECTION_XN_SHIFT (4)
manhpham 0:c8673aa96267 1700
manhpham 0:c8673aa96267 1701 #define SECTION_DOMAIN_MASK (0xFFFFFE1F)
manhpham 0:c8673aa96267 1702 #define SECTION_DOMAIN_SHIFT (5)
manhpham 0:c8673aa96267 1703
manhpham 0:c8673aa96267 1704 #define SECTION_P_MASK (0xFFFFFDFF)
manhpham 0:c8673aa96267 1705 #define SECTION_P_SHIFT (9)
manhpham 0:c8673aa96267 1706
manhpham 0:c8673aa96267 1707 #define SECTION_AP_MASK (0xFFFF73FF)
manhpham 0:c8673aa96267 1708 #define SECTION_AP_SHIFT (10)
manhpham 0:c8673aa96267 1709 #define SECTION_AP2_SHIFT (15)
manhpham 0:c8673aa96267 1710
manhpham 0:c8673aa96267 1711 #define SECTION_S_MASK (0xFFFEFFFF)
manhpham 0:c8673aa96267 1712 #define SECTION_S_SHIFT (16)
manhpham 0:c8673aa96267 1713
manhpham 0:c8673aa96267 1714 #define SECTION_NG_MASK (0xFFFDFFFF)
manhpham 0:c8673aa96267 1715 #define SECTION_NG_SHIFT (17)
manhpham 0:c8673aa96267 1716
manhpham 0:c8673aa96267 1717 #define SECTION_NS_MASK (0xFFF7FFFF)
manhpham 0:c8673aa96267 1718 #define SECTION_NS_SHIFT (19)
manhpham 0:c8673aa96267 1719
manhpham 0:c8673aa96267 1720 #define PAGE_L1_DESCRIPTOR (0x1)
manhpham 0:c8673aa96267 1721 #define PAGE_L1_MASK (0xFFFFFFFC)
manhpham 0:c8673aa96267 1722
manhpham 0:c8673aa96267 1723 #define PAGE_L2_4K_DESC (0x2)
manhpham 0:c8673aa96267 1724 #define PAGE_L2_4K_MASK (0xFFFFFFFD)
manhpham 0:c8673aa96267 1725
manhpham 0:c8673aa96267 1726 #define PAGE_L2_64K_DESC (0x1)
manhpham 0:c8673aa96267 1727 #define PAGE_L2_64K_MASK (0xFFFFFFFC)
manhpham 0:c8673aa96267 1728
manhpham 0:c8673aa96267 1729 #define PAGE_4K_TEXCB_MASK (0xFFFFFE33)
manhpham 0:c8673aa96267 1730 #define PAGE_4K_B_SHIFT (2)
manhpham 0:c8673aa96267 1731 #define PAGE_4K_C_SHIFT (3)
manhpham 0:c8673aa96267 1732 #define PAGE_4K_TEX0_SHIFT (6)
manhpham 0:c8673aa96267 1733 #define PAGE_4K_TEX1_SHIFT (7)
manhpham 0:c8673aa96267 1734 #define PAGE_4K_TEX2_SHIFT (8)
manhpham 0:c8673aa96267 1735
manhpham 0:c8673aa96267 1736 #define PAGE_64K_TEXCB_MASK (0xFFFF8FF3)
manhpham 0:c8673aa96267 1737 #define PAGE_64K_B_SHIFT (2)
manhpham 0:c8673aa96267 1738 #define PAGE_64K_C_SHIFT (3)
manhpham 0:c8673aa96267 1739 #define PAGE_64K_TEX0_SHIFT (12)
manhpham 0:c8673aa96267 1740 #define PAGE_64K_TEX1_SHIFT (13)
manhpham 0:c8673aa96267 1741 #define PAGE_64K_TEX2_SHIFT (14)
manhpham 0:c8673aa96267 1742
manhpham 0:c8673aa96267 1743 #define PAGE_TEXCB_MASK (0xFFFF8FF3)
manhpham 0:c8673aa96267 1744 #define PAGE_B_SHIFT (2)
manhpham 0:c8673aa96267 1745 #define PAGE_C_SHIFT (3)
manhpham 0:c8673aa96267 1746 #define PAGE_TEX_SHIFT (12)
manhpham 0:c8673aa96267 1747
manhpham 0:c8673aa96267 1748 #define PAGE_XN_4K_MASK (0xFFFFFFFE)
manhpham 0:c8673aa96267 1749 #define PAGE_XN_4K_SHIFT (0)
manhpham 0:c8673aa96267 1750 #define PAGE_XN_64K_MASK (0xFFFF7FFF)
manhpham 0:c8673aa96267 1751 #define PAGE_XN_64K_SHIFT (15)
manhpham 0:c8673aa96267 1752
manhpham 0:c8673aa96267 1753 #define PAGE_DOMAIN_MASK (0xFFFFFE1F)
manhpham 0:c8673aa96267 1754 #define PAGE_DOMAIN_SHIFT (5)
manhpham 0:c8673aa96267 1755
manhpham 0:c8673aa96267 1756 #define PAGE_P_MASK (0xFFFFFDFF)
manhpham 0:c8673aa96267 1757 #define PAGE_P_SHIFT (9)
manhpham 0:c8673aa96267 1758
manhpham 0:c8673aa96267 1759 #define PAGE_AP_MASK (0xFFFFFDCF)
manhpham 0:c8673aa96267 1760 #define PAGE_AP_SHIFT (4)
manhpham 0:c8673aa96267 1761 #define PAGE_AP2_SHIFT (9)
manhpham 0:c8673aa96267 1762
manhpham 0:c8673aa96267 1763 #define PAGE_S_MASK (0xFFFFFBFF)
manhpham 0:c8673aa96267 1764 #define PAGE_S_SHIFT (10)
manhpham 0:c8673aa96267 1765
manhpham 0:c8673aa96267 1766 #define PAGE_NG_MASK (0xFFFFF7FF)
manhpham 0:c8673aa96267 1767 #define PAGE_NG_SHIFT (11)
manhpham 0:c8673aa96267 1768
manhpham 0:c8673aa96267 1769 #define PAGE_NS_MASK (0xFFFFFFF7)
manhpham 0:c8673aa96267 1770 #define PAGE_NS_SHIFT (3)
manhpham 0:c8673aa96267 1771
manhpham 0:c8673aa96267 1772 #define OFFSET_1M (0x00100000)
manhpham 0:c8673aa96267 1773 #define OFFSET_64K (0x00010000)
manhpham 0:c8673aa96267 1774 #define OFFSET_4K (0x00001000)
manhpham 0:c8673aa96267 1775
manhpham 0:c8673aa96267 1776 #define DESCRIPTOR_FAULT (0x00000000)
manhpham 0:c8673aa96267 1777
manhpham 0:c8673aa96267 1778 /* Attributes enumerations */
manhpham 0:c8673aa96267 1779
manhpham 0:c8673aa96267 1780 /* Region size attributes */
manhpham 0:c8673aa96267 1781 typedef enum
manhpham 0:c8673aa96267 1782 {
manhpham 0:c8673aa96267 1783 SECTION,
manhpham 0:c8673aa96267 1784 PAGE_4k,
manhpham 0:c8673aa96267 1785 PAGE_64k,
manhpham 0:c8673aa96267 1786 } mmu_region_size_Type;
manhpham 0:c8673aa96267 1787
manhpham 0:c8673aa96267 1788 /* Region type attributes */
manhpham 0:c8673aa96267 1789 typedef enum
manhpham 0:c8673aa96267 1790 {
manhpham 0:c8673aa96267 1791 NORMAL,
manhpham 0:c8673aa96267 1792 DEVICE,
manhpham 0:c8673aa96267 1793 SHARED_DEVICE,
manhpham 0:c8673aa96267 1794 NON_SHARED_DEVICE,
manhpham 0:c8673aa96267 1795 STRONGLY_ORDERED
manhpham 0:c8673aa96267 1796 } mmu_memory_Type;
manhpham 0:c8673aa96267 1797
manhpham 0:c8673aa96267 1798 /* Region cacheability attributes */
manhpham 0:c8673aa96267 1799 typedef enum
manhpham 0:c8673aa96267 1800 {
manhpham 0:c8673aa96267 1801 NON_CACHEABLE,
manhpham 0:c8673aa96267 1802 WB_WA,
manhpham 0:c8673aa96267 1803 WT,
manhpham 0:c8673aa96267 1804 WB_NO_WA,
manhpham 0:c8673aa96267 1805 } mmu_cacheability_Type;
manhpham 0:c8673aa96267 1806
manhpham 0:c8673aa96267 1807 /* Region parity check attributes */
manhpham 0:c8673aa96267 1808 typedef enum
manhpham 0:c8673aa96267 1809 {
manhpham 0:c8673aa96267 1810 ECC_DISABLED,
manhpham 0:c8673aa96267 1811 ECC_ENABLED,
manhpham 0:c8673aa96267 1812 } mmu_ecc_check_Type;
manhpham 0:c8673aa96267 1813
manhpham 0:c8673aa96267 1814 /* Region execution attributes */
manhpham 0:c8673aa96267 1815 typedef enum
manhpham 0:c8673aa96267 1816 {
manhpham 0:c8673aa96267 1817 EXECUTE,
manhpham 0:c8673aa96267 1818 NON_EXECUTE,
manhpham 0:c8673aa96267 1819 } mmu_execute_Type;
manhpham 0:c8673aa96267 1820
manhpham 0:c8673aa96267 1821 /* Region global attributes */
manhpham 0:c8673aa96267 1822 typedef enum
manhpham 0:c8673aa96267 1823 {
manhpham 0:c8673aa96267 1824 GLOBAL,
manhpham 0:c8673aa96267 1825 NON_GLOBAL,
manhpham 0:c8673aa96267 1826 } mmu_global_Type;
manhpham 0:c8673aa96267 1827
manhpham 0:c8673aa96267 1828 /* Region shareability attributes */
manhpham 0:c8673aa96267 1829 typedef enum
manhpham 0:c8673aa96267 1830 {
manhpham 0:c8673aa96267 1831 NON_SHARED,
manhpham 0:c8673aa96267 1832 SHARED,
manhpham 0:c8673aa96267 1833 } mmu_shared_Type;
manhpham 0:c8673aa96267 1834
manhpham 0:c8673aa96267 1835 /* Region security attributes */
manhpham 0:c8673aa96267 1836 typedef enum
manhpham 0:c8673aa96267 1837 {
manhpham 0:c8673aa96267 1838 SECURE,
manhpham 0:c8673aa96267 1839 NON_SECURE,
manhpham 0:c8673aa96267 1840 } mmu_secure_Type;
manhpham 0:c8673aa96267 1841
manhpham 0:c8673aa96267 1842 /* Region access attributes */
manhpham 0:c8673aa96267 1843 typedef enum
manhpham 0:c8673aa96267 1844 {
manhpham 0:c8673aa96267 1845 NO_ACCESS,
manhpham 0:c8673aa96267 1846 RW,
manhpham 0:c8673aa96267 1847 READ,
manhpham 0:c8673aa96267 1848 } mmu_access_Type;
manhpham 0:c8673aa96267 1849
manhpham 0:c8673aa96267 1850 /* Memory Region definition */
manhpham 0:c8673aa96267 1851 typedef struct RegionStruct {
manhpham 0:c8673aa96267 1852 mmu_region_size_Type rg_t;
manhpham 0:c8673aa96267 1853 mmu_memory_Type mem_t;
manhpham 0:c8673aa96267 1854 uint8_t domain;
manhpham 0:c8673aa96267 1855 mmu_cacheability_Type inner_norm_t;
manhpham 0:c8673aa96267 1856 mmu_cacheability_Type outer_norm_t;
manhpham 0:c8673aa96267 1857 mmu_ecc_check_Type e_t;
manhpham 0:c8673aa96267 1858 mmu_execute_Type xn_t;
manhpham 0:c8673aa96267 1859 mmu_global_Type g_t;
manhpham 0:c8673aa96267 1860 mmu_secure_Type sec_t;
manhpham 0:c8673aa96267 1861 mmu_access_Type priv_t;
manhpham 0:c8673aa96267 1862 mmu_access_Type user_t;
manhpham 0:c8673aa96267 1863 mmu_shared_Type sh_t;
manhpham 0:c8673aa96267 1864
manhpham 0:c8673aa96267 1865 } mmu_region_attributes_Type;
manhpham 0:c8673aa96267 1866
manhpham 0:c8673aa96267 1867 //Following macros define the descriptors and attributes
manhpham 0:c8673aa96267 1868 //Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0
manhpham 0:c8673aa96267 1869 #define section_normal(descriptor_l1, region) region.rg_t = SECTION; \
manhpham 0:c8673aa96267 1870 region.domain = 0x0; \
manhpham 0:c8673aa96267 1871 region.e_t = ECC_DISABLED; \
manhpham 0:c8673aa96267 1872 region.g_t = GLOBAL; \
manhpham 0:c8673aa96267 1873 region.inner_norm_t = WB_WA; \
manhpham 0:c8673aa96267 1874 region.outer_norm_t = WB_WA; \
manhpham 0:c8673aa96267 1875 region.mem_t = NORMAL; \
manhpham 0:c8673aa96267 1876 region.sec_t = SECURE; \
manhpham 0:c8673aa96267 1877 region.xn_t = EXECUTE; \
manhpham 0:c8673aa96267 1878 region.priv_t = RW; \
manhpham 0:c8673aa96267 1879 region.user_t = RW; \
manhpham 0:c8673aa96267 1880 region.sh_t = NON_SHARED; \
manhpham 0:c8673aa96267 1881 MMU_GetSectionDescriptor(&descriptor_l1, region);
manhpham 0:c8673aa96267 1882
manhpham 0:c8673aa96267 1883 //Sect_Normal_NC. Outer & inner non-cacheable, non-shareable, executable, rw, domain 0
manhpham 0:c8673aa96267 1884 #define section_normal_nc(descriptor_l1, region) region.rg_t = SECTION; \
manhpham 0:c8673aa96267 1885 region.domain = 0x0; \
manhpham 0:c8673aa96267 1886 region.e_t = ECC_DISABLED; \
manhpham 0:c8673aa96267 1887 region.g_t = GLOBAL; \
manhpham 0:c8673aa96267 1888 region.inner_norm_t = NON_CACHEABLE; \
manhpham 0:c8673aa96267 1889 region.outer_norm_t = NON_CACHEABLE; \
manhpham 0:c8673aa96267 1890 region.mem_t = NORMAL; \
manhpham 0:c8673aa96267 1891 region.sec_t = SECURE; \
manhpham 0:c8673aa96267 1892 region.xn_t = EXECUTE; \
manhpham 0:c8673aa96267 1893 region.priv_t = RW; \
manhpham 0:c8673aa96267 1894 region.user_t = RW; \
manhpham 0:c8673aa96267 1895 region.sh_t = NON_SHARED; \
manhpham 0:c8673aa96267 1896 MMU_GetSectionDescriptor(&descriptor_l1, region);
manhpham 0:c8673aa96267 1897
manhpham 0:c8673aa96267 1898 //Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0
manhpham 0:c8673aa96267 1899 #define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \
manhpham 0:c8673aa96267 1900 region.domain = 0x0; \
manhpham 0:c8673aa96267 1901 region.e_t = ECC_DISABLED; \
manhpham 0:c8673aa96267 1902 region.g_t = GLOBAL; \
manhpham 0:c8673aa96267 1903 region.inner_norm_t = WB_WA; \
manhpham 0:c8673aa96267 1904 region.outer_norm_t = WB_WA; \
manhpham 0:c8673aa96267 1905 region.mem_t = NORMAL; \
manhpham 0:c8673aa96267 1906 region.sec_t = SECURE; \
manhpham 0:c8673aa96267 1907 region.xn_t = EXECUTE; \
manhpham 0:c8673aa96267 1908 region.priv_t = READ; \
manhpham 0:c8673aa96267 1909 region.user_t = READ; \
manhpham 0:c8673aa96267 1910 region.sh_t = NON_SHARED; \
manhpham 0:c8673aa96267 1911 MMU_GetSectionDescriptor(&descriptor_l1, region);
manhpham 0:c8673aa96267 1912
manhpham 0:c8673aa96267 1913 //Sect_Normal_RO. Sect_Normal_Cod, but not executable
manhpham 0:c8673aa96267 1914 #define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \
manhpham 0:c8673aa96267 1915 region.domain = 0x0; \
manhpham 0:c8673aa96267 1916 region.e_t = ECC_DISABLED; \
manhpham 0:c8673aa96267 1917 region.g_t = GLOBAL; \
manhpham 0:c8673aa96267 1918 region.inner_norm_t = WB_WA; \
manhpham 0:c8673aa96267 1919 region.outer_norm_t = WB_WA; \
manhpham 0:c8673aa96267 1920 region.mem_t = NORMAL; \
manhpham 0:c8673aa96267 1921 region.sec_t = SECURE; \
manhpham 0:c8673aa96267 1922 region.xn_t = NON_EXECUTE; \
manhpham 0:c8673aa96267 1923 region.priv_t = READ; \
manhpham 0:c8673aa96267 1924 region.user_t = READ; \
manhpham 0:c8673aa96267 1925 region.sh_t = NON_SHARED; \
manhpham 0:c8673aa96267 1926 MMU_GetSectionDescriptor(&descriptor_l1, region);
manhpham 0:c8673aa96267 1927
manhpham 0:c8673aa96267 1928 //Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable
manhpham 0:c8673aa96267 1929 #define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \
manhpham 0:c8673aa96267 1930 region.domain = 0x0; \
manhpham 0:c8673aa96267 1931 region.e_t = ECC_DISABLED; \
manhpham 0:c8673aa96267 1932 region.g_t = GLOBAL; \
manhpham 0:c8673aa96267 1933 region.inner_norm_t = WB_WA; \
manhpham 0:c8673aa96267 1934 region.outer_norm_t = WB_WA; \
manhpham 0:c8673aa96267 1935 region.mem_t = NORMAL; \
manhpham 0:c8673aa96267 1936 region.sec_t = SECURE; \
manhpham 0:c8673aa96267 1937 region.xn_t = NON_EXECUTE; \
manhpham 0:c8673aa96267 1938 region.priv_t = RW; \
manhpham 0:c8673aa96267 1939 region.user_t = RW; \
manhpham 0:c8673aa96267 1940 region.sh_t = NON_SHARED; \
manhpham 0:c8673aa96267 1941 MMU_GetSectionDescriptor(&descriptor_l1, region);
manhpham 0:c8673aa96267 1942 //Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
manhpham 0:c8673aa96267 1943 #define section_so(descriptor_l1, region) region.rg_t = SECTION; \
manhpham 0:c8673aa96267 1944 region.domain = 0x0; \
manhpham 0:c8673aa96267 1945 region.e_t = ECC_DISABLED; \
manhpham 0:c8673aa96267 1946 region.g_t = GLOBAL; \
manhpham 0:c8673aa96267 1947 region.inner_norm_t = NON_CACHEABLE; \
manhpham 0:c8673aa96267 1948 region.outer_norm_t = NON_CACHEABLE; \
manhpham 0:c8673aa96267 1949 region.mem_t = STRONGLY_ORDERED; \
manhpham 0:c8673aa96267 1950 region.sec_t = SECURE; \
manhpham 0:c8673aa96267 1951 region.xn_t = NON_EXECUTE; \
manhpham 0:c8673aa96267 1952 region.priv_t = RW; \
manhpham 0:c8673aa96267 1953 region.user_t = RW; \
manhpham 0:c8673aa96267 1954 region.sh_t = NON_SHARED; \
manhpham 0:c8673aa96267 1955 MMU_GetSectionDescriptor(&descriptor_l1, region);
manhpham 0:c8673aa96267 1956
manhpham 0:c8673aa96267 1957 //Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0
manhpham 0:c8673aa96267 1958 #define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \
manhpham 0:c8673aa96267 1959 region.domain = 0x0; \
manhpham 0:c8673aa96267 1960 region.e_t = ECC_DISABLED; \
manhpham 0:c8673aa96267 1961 region.g_t = GLOBAL; \
manhpham 0:c8673aa96267 1962 region.inner_norm_t = NON_CACHEABLE; \
manhpham 0:c8673aa96267 1963 region.outer_norm_t = NON_CACHEABLE; \
manhpham 0:c8673aa96267 1964 region.mem_t = STRONGLY_ORDERED; \
manhpham 0:c8673aa96267 1965 region.sec_t = SECURE; \
manhpham 0:c8673aa96267 1966 region.xn_t = NON_EXECUTE; \
manhpham 0:c8673aa96267 1967 region.priv_t = READ; \
manhpham 0:c8673aa96267 1968 region.user_t = READ; \
manhpham 0:c8673aa96267 1969 region.sh_t = NON_SHARED; \
manhpham 0:c8673aa96267 1970 MMU_GetSectionDescriptor(&descriptor_l1, region);
manhpham 0:c8673aa96267 1971
manhpham 0:c8673aa96267 1972 //Sect_Device_RW. Sect_Device_RO, but writeable
manhpham 0:c8673aa96267 1973 #define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \
manhpham 0:c8673aa96267 1974 region.domain = 0x0; \
manhpham 0:c8673aa96267 1975 region.e_t = ECC_DISABLED; \
manhpham 0:c8673aa96267 1976 region.g_t = GLOBAL; \
manhpham 0:c8673aa96267 1977 region.inner_norm_t = NON_CACHEABLE; \
manhpham 0:c8673aa96267 1978 region.outer_norm_t = NON_CACHEABLE; \
manhpham 0:c8673aa96267 1979 region.mem_t = STRONGLY_ORDERED; \
manhpham 0:c8673aa96267 1980 region.sec_t = SECURE; \
manhpham 0:c8673aa96267 1981 region.xn_t = NON_EXECUTE; \
manhpham 0:c8673aa96267 1982 region.priv_t = RW; \
manhpham 0:c8673aa96267 1983 region.user_t = RW; \
manhpham 0:c8673aa96267 1984 region.sh_t = NON_SHARED; \
manhpham 0:c8673aa96267 1985 MMU_GetSectionDescriptor(&descriptor_l1, region);
manhpham 0:c8673aa96267 1986 //Page_4k_Device_RW. Shared device, not executable, rw, domain 0
manhpham 0:c8673aa96267 1987 #define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \
manhpham 0:c8673aa96267 1988 region.domain = 0x0; \
manhpham 0:c8673aa96267 1989 region.e_t = ECC_DISABLED; \
manhpham 0:c8673aa96267 1990 region.g_t = GLOBAL; \
manhpham 0:c8673aa96267 1991 region.inner_norm_t = NON_CACHEABLE; \
manhpham 0:c8673aa96267 1992 region.outer_norm_t = NON_CACHEABLE; \
manhpham 0:c8673aa96267 1993 region.mem_t = SHARED_DEVICE; \
manhpham 0:c8673aa96267 1994 region.sec_t = SECURE; \
manhpham 0:c8673aa96267 1995 region.xn_t = NON_EXECUTE; \
manhpham 0:c8673aa96267 1996 region.priv_t = RW; \
manhpham 0:c8673aa96267 1997 region.user_t = RW; \
manhpham 0:c8673aa96267 1998 region.sh_t = NON_SHARED; \
manhpham 0:c8673aa96267 1999 MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
manhpham 0:c8673aa96267 2000
manhpham 0:c8673aa96267 2001 //Page_64k_Device_RW. Shared device, not executable, rw, domain 0
manhpham 0:c8673aa96267 2002 #define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \
manhpham 0:c8673aa96267 2003 region.domain = 0x0; \
manhpham 0:c8673aa96267 2004 region.e_t = ECC_DISABLED; \
manhpham 0:c8673aa96267 2005 region.g_t = GLOBAL; \
manhpham 0:c8673aa96267 2006 region.inner_norm_t = NON_CACHEABLE; \
manhpham 0:c8673aa96267 2007 region.outer_norm_t = NON_CACHEABLE; \
manhpham 0:c8673aa96267 2008 region.mem_t = SHARED_DEVICE; \
manhpham 0:c8673aa96267 2009 region.sec_t = SECURE; \
manhpham 0:c8673aa96267 2010 region.xn_t = NON_EXECUTE; \
manhpham 0:c8673aa96267 2011 region.priv_t = RW; \
manhpham 0:c8673aa96267 2012 region.user_t = RW; \
manhpham 0:c8673aa96267 2013 region.sh_t = NON_SHARED; \
manhpham 0:c8673aa96267 2014 MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
manhpham 0:c8673aa96267 2015
manhpham 0:c8673aa96267 2016 /** \brief Set section execution-never attribute
manhpham 0:c8673aa96267 2017
manhpham 0:c8673aa96267 2018 \param [out] descriptor_l1 L1 descriptor.
manhpham 0:c8673aa96267 2019 \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE.
manhpham 0:c8673aa96267 2020
manhpham 0:c8673aa96267 2021 \return 0
manhpham 0:c8673aa96267 2022 */
manhpham 0:c8673aa96267 2023 __STATIC_INLINE int MMU_XNSection(uint32_t *descriptor_l1, mmu_execute_Type xn)
manhpham 0:c8673aa96267 2024 {
manhpham 0:c8673aa96267 2025 *descriptor_l1 &= SECTION_XN_MASK;
manhpham 0:c8673aa96267 2026 *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
manhpham 0:c8673aa96267 2027 return 0;
manhpham 0:c8673aa96267 2028 }
manhpham 0:c8673aa96267 2029
manhpham 0:c8673aa96267 2030 /** \brief Set section domain
manhpham 0:c8673aa96267 2031
manhpham 0:c8673aa96267 2032 \param [out] descriptor_l1 L1 descriptor.
manhpham 0:c8673aa96267 2033 \param [in] domain Section domain
manhpham 0:c8673aa96267 2034
manhpham 0:c8673aa96267 2035 \return 0
manhpham 0:c8673aa96267 2036 */
manhpham 0:c8673aa96267 2037 __STATIC_INLINE int MMU_DomainSection(uint32_t *descriptor_l1, uint8_t domain)
manhpham 0:c8673aa96267 2038 {
manhpham 0:c8673aa96267 2039 *descriptor_l1 &= SECTION_DOMAIN_MASK;
manhpham 0:c8673aa96267 2040 *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
manhpham 0:c8673aa96267 2041 return 0;
manhpham 0:c8673aa96267 2042 }
manhpham 0:c8673aa96267 2043
manhpham 0:c8673aa96267 2044 /** \brief Set section parity check
manhpham 0:c8673aa96267 2045
manhpham 0:c8673aa96267 2046 \param [out] descriptor_l1 L1 descriptor.
manhpham 0:c8673aa96267 2047 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
manhpham 0:c8673aa96267 2048
manhpham 0:c8673aa96267 2049 \return 0
manhpham 0:c8673aa96267 2050 */
manhpham 0:c8673aa96267 2051 __STATIC_INLINE int MMU_PSection(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
manhpham 0:c8673aa96267 2052 {
manhpham 0:c8673aa96267 2053 *descriptor_l1 &= SECTION_P_MASK;
manhpham 0:c8673aa96267 2054 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
manhpham 0:c8673aa96267 2055 return 0;
manhpham 0:c8673aa96267 2056 }
manhpham 0:c8673aa96267 2057
manhpham 0:c8673aa96267 2058 /** \brief Set section access privileges
manhpham 0:c8673aa96267 2059
manhpham 0:c8673aa96267 2060 \param [out] descriptor_l1 L1 descriptor.
manhpham 0:c8673aa96267 2061 \param [in] user User Level Access: NO_ACCESS, RW, READ
manhpham 0:c8673aa96267 2062 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
manhpham 0:c8673aa96267 2063 \param [in] afe Access flag enable
manhpham 0:c8673aa96267 2064
manhpham 0:c8673aa96267 2065 \return 0
manhpham 0:c8673aa96267 2066 */
manhpham 0:c8673aa96267 2067 __STATIC_INLINE int MMU_APSection(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
manhpham 0:c8673aa96267 2068 {
manhpham 0:c8673aa96267 2069 uint32_t ap = 0;
manhpham 0:c8673aa96267 2070
manhpham 0:c8673aa96267 2071 if (afe == 0) { //full access
manhpham 0:c8673aa96267 2072 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
manhpham 0:c8673aa96267 2073 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
manhpham 0:c8673aa96267 2074 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
manhpham 0:c8673aa96267 2075 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
manhpham 0:c8673aa96267 2076 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
manhpham 0:c8673aa96267 2077 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
manhpham 0:c8673aa96267 2078 }
manhpham 0:c8673aa96267 2079
manhpham 0:c8673aa96267 2080 else { //Simplified access
manhpham 0:c8673aa96267 2081 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
manhpham 0:c8673aa96267 2082 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
manhpham 0:c8673aa96267 2083 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
manhpham 0:c8673aa96267 2084 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
manhpham 0:c8673aa96267 2085 }
manhpham 0:c8673aa96267 2086
manhpham 0:c8673aa96267 2087 *descriptor_l1 &= SECTION_AP_MASK;
manhpham 0:c8673aa96267 2088 *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
manhpham 0:c8673aa96267 2089 *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
manhpham 0:c8673aa96267 2090
manhpham 0:c8673aa96267 2091 return 0;
manhpham 0:c8673aa96267 2092 }
manhpham 0:c8673aa96267 2093
manhpham 0:c8673aa96267 2094 /** \brief Set section shareability
manhpham 0:c8673aa96267 2095
manhpham 0:c8673aa96267 2096 \param [out] descriptor_l1 L1 descriptor.
manhpham 0:c8673aa96267 2097 \param [in] s_bit Section shareability: NON_SHARED, SHARED
manhpham 0:c8673aa96267 2098
manhpham 0:c8673aa96267 2099 \return 0
manhpham 0:c8673aa96267 2100 */
manhpham 0:c8673aa96267 2101 __STATIC_INLINE int MMU_SharedSection(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
manhpham 0:c8673aa96267 2102 {
manhpham 0:c8673aa96267 2103 *descriptor_l1 &= SECTION_S_MASK;
manhpham 0:c8673aa96267 2104 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
manhpham 0:c8673aa96267 2105 return 0;
manhpham 0:c8673aa96267 2106 }
manhpham 0:c8673aa96267 2107
manhpham 0:c8673aa96267 2108 /** \brief Set section Global attribute
manhpham 0:c8673aa96267 2109
manhpham 0:c8673aa96267 2110 \param [out] descriptor_l1 L1 descriptor.
manhpham 0:c8673aa96267 2111 \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL
manhpham 0:c8673aa96267 2112
manhpham 0:c8673aa96267 2113 \return 0
manhpham 0:c8673aa96267 2114 */
manhpham 0:c8673aa96267 2115 __STATIC_INLINE int MMU_GlobalSection(uint32_t *descriptor_l1, mmu_global_Type g_bit)
manhpham 0:c8673aa96267 2116 {
manhpham 0:c8673aa96267 2117 *descriptor_l1 &= SECTION_NG_MASK;
manhpham 0:c8673aa96267 2118 *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
manhpham 0:c8673aa96267 2119 return 0;
manhpham 0:c8673aa96267 2120 }
manhpham 0:c8673aa96267 2121
manhpham 0:c8673aa96267 2122 /** \brief Set section Security attribute
manhpham 0:c8673aa96267 2123
manhpham 0:c8673aa96267 2124 \param [out] descriptor_l1 L1 descriptor.
manhpham 0:c8673aa96267 2125 \param [in] s_bit Section Security attribute: SECURE, NON_SECURE
manhpham 0:c8673aa96267 2126
manhpham 0:c8673aa96267 2127 \return 0
manhpham 0:c8673aa96267 2128 */
manhpham 0:c8673aa96267 2129 __STATIC_INLINE int MMU_SecureSection(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
manhpham 0:c8673aa96267 2130 {
manhpham 0:c8673aa96267 2131 *descriptor_l1 &= SECTION_NS_MASK;
manhpham 0:c8673aa96267 2132 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
manhpham 0:c8673aa96267 2133 return 0;
manhpham 0:c8673aa96267 2134 }
manhpham 0:c8673aa96267 2135
manhpham 0:c8673aa96267 2136 /* Page 4k or 64k */
manhpham 0:c8673aa96267 2137 /** \brief Set 4k/64k page execution-never attribute
manhpham 0:c8673aa96267 2138
manhpham 0:c8673aa96267 2139 \param [out] descriptor_l2 L2 descriptor.
manhpham 0:c8673aa96267 2140 \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE.
manhpham 0:c8673aa96267 2141 \param [in] page Page size: PAGE_4k, PAGE_64k,
manhpham 0:c8673aa96267 2142
manhpham 0:c8673aa96267 2143 \return 0
manhpham 0:c8673aa96267 2144 */
manhpham 0:c8673aa96267 2145 __STATIC_INLINE int MMU_XNPage(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
manhpham 0:c8673aa96267 2146 {
manhpham 0:c8673aa96267 2147 if (page == PAGE_4k)
manhpham 0:c8673aa96267 2148 {
manhpham 0:c8673aa96267 2149 *descriptor_l2 &= PAGE_XN_4K_MASK;
manhpham 0:c8673aa96267 2150 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
manhpham 0:c8673aa96267 2151 }
manhpham 0:c8673aa96267 2152 else
manhpham 0:c8673aa96267 2153 {
manhpham 0:c8673aa96267 2154 *descriptor_l2 &= PAGE_XN_64K_MASK;
manhpham 0:c8673aa96267 2155 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
manhpham 0:c8673aa96267 2156 }
manhpham 0:c8673aa96267 2157 return 0;
manhpham 0:c8673aa96267 2158 }
manhpham 0:c8673aa96267 2159
manhpham 0:c8673aa96267 2160 /** \brief Set 4k/64k page domain
manhpham 0:c8673aa96267 2161
manhpham 0:c8673aa96267 2162 \param [out] descriptor_l1 L1 descriptor.
manhpham 0:c8673aa96267 2163 \param [in] domain Page domain
manhpham 0:c8673aa96267 2164
manhpham 0:c8673aa96267 2165 \return 0
manhpham 0:c8673aa96267 2166 */
manhpham 0:c8673aa96267 2167 __STATIC_INLINE int MMU_DomainPage(uint32_t *descriptor_l1, uint8_t domain)
manhpham 0:c8673aa96267 2168 {
manhpham 0:c8673aa96267 2169 *descriptor_l1 &= PAGE_DOMAIN_MASK;
manhpham 0:c8673aa96267 2170 *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
manhpham 0:c8673aa96267 2171 return 0;
manhpham 0:c8673aa96267 2172 }
manhpham 0:c8673aa96267 2173
manhpham 0:c8673aa96267 2174 /** \brief Set 4k/64k page parity check
manhpham 0:c8673aa96267 2175
manhpham 0:c8673aa96267 2176 \param [out] descriptor_l1 L1 descriptor.
manhpham 0:c8673aa96267 2177 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
manhpham 0:c8673aa96267 2178
manhpham 0:c8673aa96267 2179 \return 0
manhpham 0:c8673aa96267 2180 */
manhpham 0:c8673aa96267 2181 __STATIC_INLINE int MMU_PPage(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
manhpham 0:c8673aa96267 2182 {
manhpham 0:c8673aa96267 2183 *descriptor_l1 &= SECTION_P_MASK;
manhpham 0:c8673aa96267 2184 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
manhpham 0:c8673aa96267 2185 return 0;
manhpham 0:c8673aa96267 2186 }
manhpham 0:c8673aa96267 2187
manhpham 0:c8673aa96267 2188 /** \brief Set 4k/64k page access privileges
manhpham 0:c8673aa96267 2189
manhpham 0:c8673aa96267 2190 \param [out] descriptor_l2 L2 descriptor.
manhpham 0:c8673aa96267 2191 \param [in] user User Level Access: NO_ACCESS, RW, READ
manhpham 0:c8673aa96267 2192 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
manhpham 0:c8673aa96267 2193 \param [in] afe Access flag enable
manhpham 0:c8673aa96267 2194
manhpham 0:c8673aa96267 2195 \return 0
manhpham 0:c8673aa96267 2196 */
manhpham 0:c8673aa96267 2197 __STATIC_INLINE int MMU_APPage(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
manhpham 0:c8673aa96267 2198 {
manhpham 0:c8673aa96267 2199 uint32_t ap = 0;
manhpham 0:c8673aa96267 2200
manhpham 0:c8673aa96267 2201 if (afe == 0) { //full access
manhpham 0:c8673aa96267 2202 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
manhpham 0:c8673aa96267 2203 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
manhpham 0:c8673aa96267 2204 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
manhpham 0:c8673aa96267 2205 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
manhpham 0:c8673aa96267 2206 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
manhpham 0:c8673aa96267 2207 else if ((priv == READ) && (user == READ)) { ap = 0x6; }
manhpham 0:c8673aa96267 2208 }
manhpham 0:c8673aa96267 2209
manhpham 0:c8673aa96267 2210 else { //Simplified access
manhpham 0:c8673aa96267 2211 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
manhpham 0:c8673aa96267 2212 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
manhpham 0:c8673aa96267 2213 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
manhpham 0:c8673aa96267 2214 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
manhpham 0:c8673aa96267 2215 }
manhpham 0:c8673aa96267 2216
manhpham 0:c8673aa96267 2217 *descriptor_l2 &= PAGE_AP_MASK;
manhpham 0:c8673aa96267 2218 *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
manhpham 0:c8673aa96267 2219 *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
manhpham 0:c8673aa96267 2220
manhpham 0:c8673aa96267 2221 return 0;
manhpham 0:c8673aa96267 2222 }
manhpham 0:c8673aa96267 2223
manhpham 0:c8673aa96267 2224 /** \brief Set 4k/64k page shareability
manhpham 0:c8673aa96267 2225
manhpham 0:c8673aa96267 2226 \param [out] descriptor_l2 L2 descriptor.
manhpham 0:c8673aa96267 2227 \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED
manhpham 0:c8673aa96267 2228
manhpham 0:c8673aa96267 2229 \return 0
manhpham 0:c8673aa96267 2230 */
manhpham 0:c8673aa96267 2231 __STATIC_INLINE int MMU_SharedPage(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
manhpham 0:c8673aa96267 2232 {
manhpham 0:c8673aa96267 2233 *descriptor_l2 &= PAGE_S_MASK;
manhpham 0:c8673aa96267 2234 *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
manhpham 0:c8673aa96267 2235 return 0;
manhpham 0:c8673aa96267 2236 }
manhpham 0:c8673aa96267 2237
manhpham 0:c8673aa96267 2238 /** \brief Set 4k/64k page Global attribute
manhpham 0:c8673aa96267 2239
manhpham 0:c8673aa96267 2240 \param [out] descriptor_l2 L2 descriptor.
manhpham 0:c8673aa96267 2241 \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL
manhpham 0:c8673aa96267 2242
manhpham 0:c8673aa96267 2243 \return 0
manhpham 0:c8673aa96267 2244 */
manhpham 0:c8673aa96267 2245 __STATIC_INLINE int MMU_GlobalPage(uint32_t *descriptor_l2, mmu_global_Type g_bit)
manhpham 0:c8673aa96267 2246 {
manhpham 0:c8673aa96267 2247 *descriptor_l2 &= PAGE_NG_MASK;
manhpham 0:c8673aa96267 2248 *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
manhpham 0:c8673aa96267 2249 return 0;
manhpham 0:c8673aa96267 2250 }
manhpham 0:c8673aa96267 2251
manhpham 0:c8673aa96267 2252 /** \brief Set 4k/64k page Security attribute
manhpham 0:c8673aa96267 2253
manhpham 0:c8673aa96267 2254 \param [out] descriptor_l1 L1 descriptor.
manhpham 0:c8673aa96267 2255 \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE
manhpham 0:c8673aa96267 2256
manhpham 0:c8673aa96267 2257 \return 0
manhpham 0:c8673aa96267 2258 */
manhpham 0:c8673aa96267 2259 __STATIC_INLINE int MMU_SecurePage(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
manhpham 0:c8673aa96267 2260 {
manhpham 0:c8673aa96267 2261 *descriptor_l1 &= PAGE_NS_MASK;
manhpham 0:c8673aa96267 2262 *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
manhpham 0:c8673aa96267 2263 return 0;
manhpham 0:c8673aa96267 2264 }
manhpham 0:c8673aa96267 2265
manhpham 0:c8673aa96267 2266 /** \brief Set Section memory attributes
manhpham 0:c8673aa96267 2267
manhpham 0:c8673aa96267 2268 \param [out] descriptor_l1 L1 descriptor.
manhpham 0:c8673aa96267 2269 \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
manhpham 0:c8673aa96267 2270 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
manhpham 0:c8673aa96267 2271 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
manhpham 0:c8673aa96267 2272
manhpham 0:c8673aa96267 2273 \return 0
manhpham 0:c8673aa96267 2274 */
manhpham 0:c8673aa96267 2275 __STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
manhpham 0:c8673aa96267 2276 {
manhpham 0:c8673aa96267 2277 *descriptor_l1 &= SECTION_TEXCB_MASK;
manhpham 0:c8673aa96267 2278
manhpham 0:c8673aa96267 2279 if (STRONGLY_ORDERED == mem)
manhpham 0:c8673aa96267 2280 {
manhpham 0:c8673aa96267 2281 return 0;
manhpham 0:c8673aa96267 2282 }
manhpham 0:c8673aa96267 2283 else if (SHARED_DEVICE == mem)
manhpham 0:c8673aa96267 2284 {
manhpham 0:c8673aa96267 2285 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
manhpham 0:c8673aa96267 2286 }
manhpham 0:c8673aa96267 2287 else if (NON_SHARED_DEVICE == mem)
manhpham 0:c8673aa96267 2288 {
manhpham 0:c8673aa96267 2289 *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
manhpham 0:c8673aa96267 2290 }
manhpham 0:c8673aa96267 2291 else if (NORMAL == mem)
manhpham 0:c8673aa96267 2292 {
manhpham 0:c8673aa96267 2293 *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
manhpham 0:c8673aa96267 2294 switch(inner)
manhpham 0:c8673aa96267 2295 {
manhpham 0:c8673aa96267 2296 case NON_CACHEABLE:
manhpham 0:c8673aa96267 2297 break;
manhpham 0:c8673aa96267 2298 case WB_WA:
manhpham 0:c8673aa96267 2299 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
manhpham 0:c8673aa96267 2300 break;
manhpham 0:c8673aa96267 2301 case WT:
manhpham 0:c8673aa96267 2302 *descriptor_l1 |= 1 << SECTION_C_SHIFT;
manhpham 0:c8673aa96267 2303 break;
manhpham 0:c8673aa96267 2304 case WB_NO_WA:
manhpham 0:c8673aa96267 2305 *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
manhpham 0:c8673aa96267 2306 break;
manhpham 0:c8673aa96267 2307 }
manhpham 0:c8673aa96267 2308 switch(outer)
manhpham 0:c8673aa96267 2309 {
manhpham 0:c8673aa96267 2310 case NON_CACHEABLE:
manhpham 0:c8673aa96267 2311 break;
manhpham 0:c8673aa96267 2312 case WB_WA:
manhpham 0:c8673aa96267 2313 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
manhpham 0:c8673aa96267 2314 break;
manhpham 0:c8673aa96267 2315 case WT:
manhpham 0:c8673aa96267 2316 *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
manhpham 0:c8673aa96267 2317 break;
manhpham 0:c8673aa96267 2318 case WB_NO_WA:
manhpham 0:c8673aa96267 2319 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
manhpham 0:c8673aa96267 2320 break;
manhpham 0:c8673aa96267 2321 }
manhpham 0:c8673aa96267 2322 }
manhpham 0:c8673aa96267 2323 return 0;
manhpham 0:c8673aa96267 2324 }
manhpham 0:c8673aa96267 2325
manhpham 0:c8673aa96267 2326 /** \brief Set 4k/64k page memory attributes
manhpham 0:c8673aa96267 2327
manhpham 0:c8673aa96267 2328 \param [out] descriptor_l2 L2 descriptor.
manhpham 0:c8673aa96267 2329 \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
manhpham 0:c8673aa96267 2330 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
manhpham 0:c8673aa96267 2331 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
manhpham 0:c8673aa96267 2332 \param [in] page Page size
manhpham 0:c8673aa96267 2333
manhpham 0:c8673aa96267 2334 \return 0
manhpham 0:c8673aa96267 2335 */
manhpham 0:c8673aa96267 2336 __STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
manhpham 0:c8673aa96267 2337 {
manhpham 0:c8673aa96267 2338 *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
manhpham 0:c8673aa96267 2339
manhpham 0:c8673aa96267 2340 if (page == PAGE_64k)
manhpham 0:c8673aa96267 2341 {
manhpham 0:c8673aa96267 2342 //same as section
manhpham 0:c8673aa96267 2343 MMU_MemorySection(descriptor_l2, mem, outer, inner);
manhpham 0:c8673aa96267 2344 }
manhpham 0:c8673aa96267 2345 else
manhpham 0:c8673aa96267 2346 {
manhpham 0:c8673aa96267 2347 if (STRONGLY_ORDERED == mem)
manhpham 0:c8673aa96267 2348 {
manhpham 0:c8673aa96267 2349 return 0;
manhpham 0:c8673aa96267 2350 }
manhpham 0:c8673aa96267 2351 else if (SHARED_DEVICE == mem)
manhpham 0:c8673aa96267 2352 {
manhpham 0:c8673aa96267 2353 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
manhpham 0:c8673aa96267 2354 }
manhpham 0:c8673aa96267 2355 else if (NON_SHARED_DEVICE == mem)
manhpham 0:c8673aa96267 2356 {
manhpham 0:c8673aa96267 2357 *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
manhpham 0:c8673aa96267 2358 }
manhpham 0:c8673aa96267 2359 else if (NORMAL == mem)
manhpham 0:c8673aa96267 2360 {
manhpham 0:c8673aa96267 2361 *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
manhpham 0:c8673aa96267 2362 switch(inner)
manhpham 0:c8673aa96267 2363 {
manhpham 0:c8673aa96267 2364 case NON_CACHEABLE:
manhpham 0:c8673aa96267 2365 break;
manhpham 0:c8673aa96267 2366 case WB_WA:
manhpham 0:c8673aa96267 2367 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
manhpham 0:c8673aa96267 2368 break;
manhpham 0:c8673aa96267 2369 case WT:
manhpham 0:c8673aa96267 2370 *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
manhpham 0:c8673aa96267 2371 break;
manhpham 0:c8673aa96267 2372 case WB_NO_WA:
manhpham 0:c8673aa96267 2373 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
manhpham 0:c8673aa96267 2374 break;
manhpham 0:c8673aa96267 2375 }
manhpham 0:c8673aa96267 2376 switch(outer)
manhpham 0:c8673aa96267 2377 {
manhpham 0:c8673aa96267 2378 case NON_CACHEABLE:
manhpham 0:c8673aa96267 2379 break;
manhpham 0:c8673aa96267 2380 case WB_WA:
manhpham 0:c8673aa96267 2381 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
manhpham 0:c8673aa96267 2382 break;
manhpham 0:c8673aa96267 2383 case WT:
manhpham 0:c8673aa96267 2384 *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
manhpham 0:c8673aa96267 2385 break;
manhpham 0:c8673aa96267 2386 case WB_NO_WA:
manhpham 0:c8673aa96267 2387 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
manhpham 0:c8673aa96267 2388 break;
manhpham 0:c8673aa96267 2389 }
manhpham 0:c8673aa96267 2390 }
manhpham 0:c8673aa96267 2391 }
manhpham 0:c8673aa96267 2392
manhpham 0:c8673aa96267 2393 return 0;
manhpham 0:c8673aa96267 2394 }
manhpham 0:c8673aa96267 2395
manhpham 0:c8673aa96267 2396 /** \brief Create a L1 section descriptor
manhpham 0:c8673aa96267 2397
manhpham 0:c8673aa96267 2398 \param [out] descriptor L1 descriptor
manhpham 0:c8673aa96267 2399 \param [in] reg Section attributes
manhpham 0:c8673aa96267 2400
manhpham 0:c8673aa96267 2401 \return 0
manhpham 0:c8673aa96267 2402 */
manhpham 0:c8673aa96267 2403 __STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
manhpham 0:c8673aa96267 2404 {
manhpham 0:c8673aa96267 2405 *descriptor = 0;
manhpham 0:c8673aa96267 2406
manhpham 0:c8673aa96267 2407 MMU_MemorySection(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
manhpham 0:c8673aa96267 2408 MMU_XNSection(descriptor,reg.xn_t);
manhpham 0:c8673aa96267 2409 MMU_DomainSection(descriptor, reg.domain);
manhpham 0:c8673aa96267 2410 MMU_PSection(descriptor, reg.e_t);
manhpham 0:c8673aa96267 2411 MMU_APSection(descriptor, reg.priv_t, reg.user_t, 1);
manhpham 0:c8673aa96267 2412 MMU_SharedSection(descriptor,reg.sh_t);
manhpham 0:c8673aa96267 2413 MMU_GlobalSection(descriptor,reg.g_t);
manhpham 0:c8673aa96267 2414 MMU_SecureSection(descriptor,reg.sec_t);
manhpham 0:c8673aa96267 2415 *descriptor &= SECTION_MASK;
manhpham 0:c8673aa96267 2416 *descriptor |= SECTION_DESCRIPTOR;
manhpham 0:c8673aa96267 2417
manhpham 0:c8673aa96267 2418 return 0;
manhpham 0:c8673aa96267 2419 }
manhpham 0:c8673aa96267 2420
manhpham 0:c8673aa96267 2421
manhpham 0:c8673aa96267 2422 /** \brief Create a L1 and L2 4k/64k page descriptor
manhpham 0:c8673aa96267 2423
manhpham 0:c8673aa96267 2424 \param [out] descriptor L1 descriptor
manhpham 0:c8673aa96267 2425 \param [out] descriptor2 L2 descriptor
manhpham 0:c8673aa96267 2426 \param [in] reg 4k/64k page attributes
manhpham 0:c8673aa96267 2427
manhpham 0:c8673aa96267 2428 \return 0
manhpham 0:c8673aa96267 2429 */
manhpham 0:c8673aa96267 2430 __STATIC_INLINE int MMU_GetPageDescriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
manhpham 0:c8673aa96267 2431 {
manhpham 0:c8673aa96267 2432 *descriptor = 0;
manhpham 0:c8673aa96267 2433 *descriptor2 = 0;
manhpham 0:c8673aa96267 2434
manhpham 0:c8673aa96267 2435 switch (reg.rg_t)
manhpham 0:c8673aa96267 2436 {
manhpham 0:c8673aa96267 2437 case PAGE_4k:
manhpham 0:c8673aa96267 2438 MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
manhpham 0:c8673aa96267 2439 MMU_XNPage(descriptor2, reg.xn_t, PAGE_4k);
manhpham 0:c8673aa96267 2440 MMU_DomainPage(descriptor, reg.domain);
manhpham 0:c8673aa96267 2441 MMU_PPage(descriptor, reg.e_t);
manhpham 0:c8673aa96267 2442 MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1);
manhpham 0:c8673aa96267 2443 MMU_SharedPage(descriptor2,reg.sh_t);
manhpham 0:c8673aa96267 2444 MMU_GlobalPage(descriptor2,reg.g_t);
manhpham 0:c8673aa96267 2445 MMU_SecurePage(descriptor,reg.sec_t);
manhpham 0:c8673aa96267 2446 *descriptor &= PAGE_L1_MASK;
manhpham 0:c8673aa96267 2447 *descriptor |= PAGE_L1_DESCRIPTOR;
manhpham 0:c8673aa96267 2448 *descriptor2 &= PAGE_L2_4K_MASK;
manhpham 0:c8673aa96267 2449 *descriptor2 |= PAGE_L2_4K_DESC;
manhpham 0:c8673aa96267 2450 break;
manhpham 0:c8673aa96267 2451
manhpham 0:c8673aa96267 2452 case PAGE_64k:
manhpham 0:c8673aa96267 2453 MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
manhpham 0:c8673aa96267 2454 MMU_XNPage(descriptor2, reg.xn_t, PAGE_64k);
manhpham 0:c8673aa96267 2455 MMU_DomainPage(descriptor, reg.domain);
manhpham 0:c8673aa96267 2456 MMU_PPage(descriptor, reg.e_t);
manhpham 0:c8673aa96267 2457 MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1);
manhpham 0:c8673aa96267 2458 MMU_SharedPage(descriptor2,reg.sh_t);
manhpham 0:c8673aa96267 2459 MMU_GlobalPage(descriptor2,reg.g_t);
manhpham 0:c8673aa96267 2460 MMU_SecurePage(descriptor,reg.sec_t);
manhpham 0:c8673aa96267 2461 *descriptor &= PAGE_L1_MASK;
manhpham 0:c8673aa96267 2462 *descriptor |= PAGE_L1_DESCRIPTOR;
manhpham 0:c8673aa96267 2463 *descriptor2 &= PAGE_L2_64K_MASK;
manhpham 0:c8673aa96267 2464 *descriptor2 |= PAGE_L2_64K_DESC;
manhpham 0:c8673aa96267 2465 break;
manhpham 0:c8673aa96267 2466
manhpham 0:c8673aa96267 2467 case SECTION:
manhpham 0:c8673aa96267 2468 //error
manhpham 0:c8673aa96267 2469 break;
manhpham 0:c8673aa96267 2470 }
manhpham 0:c8673aa96267 2471
manhpham 0:c8673aa96267 2472 return 0;
manhpham 0:c8673aa96267 2473 }
manhpham 0:c8673aa96267 2474
manhpham 0:c8673aa96267 2475 /** \brief Create a 1MB Section
manhpham 0:c8673aa96267 2476
manhpham 0:c8673aa96267 2477 \param [in] ttb Translation table base address
manhpham 0:c8673aa96267 2478 \param [in] base_address Section base address
manhpham 0:c8673aa96267 2479 \param [in] count Number of sections to create
manhpham 0:c8673aa96267 2480 \param [in] descriptor_l1 L1 descriptor (region attributes)
manhpham 0:c8673aa96267 2481
manhpham 0:c8673aa96267 2482 */
manhpham 0:c8673aa96267 2483 __STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
manhpham 0:c8673aa96267 2484 {
manhpham 0:c8673aa96267 2485 uint32_t offset;
manhpham 0:c8673aa96267 2486 uint32_t entry;
manhpham 0:c8673aa96267 2487 uint32_t i;
manhpham 0:c8673aa96267 2488
manhpham 0:c8673aa96267 2489 offset = base_address >> 20;
manhpham 0:c8673aa96267 2490 entry = (base_address & 0xFFF00000) | descriptor_l1;
manhpham 0:c8673aa96267 2491
manhpham 0:c8673aa96267 2492 //4 bytes aligned
manhpham 0:c8673aa96267 2493 ttb = ttb + offset;
manhpham 0:c8673aa96267 2494
manhpham 0:c8673aa96267 2495 for (i = 0; i < count; i++ )
manhpham 0:c8673aa96267 2496 {
manhpham 0:c8673aa96267 2497 //4 bytes aligned
manhpham 0:c8673aa96267 2498 *ttb++ = entry;
manhpham 0:c8673aa96267 2499 entry += OFFSET_1M;
manhpham 0:c8673aa96267 2500 }
manhpham 0:c8673aa96267 2501 }
manhpham 0:c8673aa96267 2502
manhpham 0:c8673aa96267 2503 /** \brief Create a 4k page entry
manhpham 0:c8673aa96267 2504
manhpham 0:c8673aa96267 2505 \param [in] ttb L1 table base address
manhpham 0:c8673aa96267 2506 \param [in] base_address 4k base address
manhpham 0:c8673aa96267 2507 \param [in] count Number of 4k pages to create
manhpham 0:c8673aa96267 2508 \param [in] descriptor_l1 L1 descriptor (region attributes)
manhpham 0:c8673aa96267 2509 \param [in] ttb_l2 L2 table base address
manhpham 0:c8673aa96267 2510 \param [in] descriptor_l2 L2 descriptor (region attributes)
manhpham 0:c8673aa96267 2511
manhpham 0:c8673aa96267 2512 */
manhpham 0:c8673aa96267 2513 __STATIC_INLINE void MMU_TTPage4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
manhpham 0:c8673aa96267 2514 {
manhpham 0:c8673aa96267 2515
manhpham 0:c8673aa96267 2516 uint32_t offset, offset2;
manhpham 0:c8673aa96267 2517 uint32_t entry, entry2;
manhpham 0:c8673aa96267 2518 uint32_t i;
manhpham 0:c8673aa96267 2519
manhpham 0:c8673aa96267 2520 offset = base_address >> 20;
manhpham 0:c8673aa96267 2521 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
manhpham 0:c8673aa96267 2522
manhpham 0:c8673aa96267 2523 //4 bytes aligned
manhpham 0:c8673aa96267 2524 ttb += offset;
manhpham 0:c8673aa96267 2525 //create l1_entry
manhpham 0:c8673aa96267 2526 *ttb = entry;
manhpham 0:c8673aa96267 2527
manhpham 0:c8673aa96267 2528 offset2 = (base_address & 0xff000) >> 12;
manhpham 0:c8673aa96267 2529 ttb_l2 += offset2;
manhpham 0:c8673aa96267 2530 entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
manhpham 0:c8673aa96267 2531 for (i = 0; i < count; i++ )
manhpham 0:c8673aa96267 2532 {
manhpham 0:c8673aa96267 2533 //4 bytes aligned
manhpham 0:c8673aa96267 2534 *ttb_l2++ = entry2;
manhpham 0:c8673aa96267 2535 entry2 += OFFSET_4K;
manhpham 0:c8673aa96267 2536 }
manhpham 0:c8673aa96267 2537 }
manhpham 0:c8673aa96267 2538
manhpham 0:c8673aa96267 2539 /** \brief Create a 64k page entry
manhpham 0:c8673aa96267 2540
manhpham 0:c8673aa96267 2541 \param [in] ttb L1 table base address
manhpham 0:c8673aa96267 2542 \param [in] base_address 64k base address
manhpham 0:c8673aa96267 2543 \param [in] count Number of 64k pages to create
manhpham 0:c8673aa96267 2544 \param [in] descriptor_l1 L1 descriptor (region attributes)
manhpham 0:c8673aa96267 2545 \param [in] ttb_l2 L2 table base address
manhpham 0:c8673aa96267 2546 \param [in] descriptor_l2 L2 descriptor (region attributes)
manhpham 0:c8673aa96267 2547
manhpham 0:c8673aa96267 2548 */
manhpham 0:c8673aa96267 2549 __STATIC_INLINE void MMU_TTPage64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
manhpham 0:c8673aa96267 2550 {
manhpham 0:c8673aa96267 2551 uint32_t offset, offset2;
manhpham 0:c8673aa96267 2552 uint32_t entry, entry2;
manhpham 0:c8673aa96267 2553 uint32_t i,j;
manhpham 0:c8673aa96267 2554
manhpham 0:c8673aa96267 2555
manhpham 0:c8673aa96267 2556 offset = base_address >> 20;
manhpham 0:c8673aa96267 2557 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
manhpham 0:c8673aa96267 2558
manhpham 0:c8673aa96267 2559 //4 bytes aligned
manhpham 0:c8673aa96267 2560 ttb += offset;
manhpham 0:c8673aa96267 2561 //create l1_entry
manhpham 0:c8673aa96267 2562 *ttb = entry;
manhpham 0:c8673aa96267 2563
manhpham 0:c8673aa96267 2564 offset2 = (base_address & 0xff000) >> 12;
manhpham 0:c8673aa96267 2565 ttb_l2 += offset2;
manhpham 0:c8673aa96267 2566 entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
manhpham 0:c8673aa96267 2567 for (i = 0; i < count; i++ )
manhpham 0:c8673aa96267 2568 {
manhpham 0:c8673aa96267 2569 //create 16 entries
manhpham 0:c8673aa96267 2570 for (j = 0; j < 16; j++)
manhpham 0:c8673aa96267 2571 {
manhpham 0:c8673aa96267 2572 //4 bytes aligned
manhpham 0:c8673aa96267 2573 *ttb_l2++ = entry2;
manhpham 0:c8673aa96267 2574 }
manhpham 0:c8673aa96267 2575 entry2 += OFFSET_64K;
manhpham 0:c8673aa96267 2576 }
manhpham 0:c8673aa96267 2577 }
manhpham 0:c8673aa96267 2578
manhpham 0:c8673aa96267 2579 /** \brief Enable MMU
manhpham 0:c8673aa96267 2580 */
manhpham 0:c8673aa96267 2581 __STATIC_INLINE void MMU_Enable(void)
manhpham 0:c8673aa96267 2582 {
manhpham 0:c8673aa96267 2583 // Set M bit 0 to enable the MMU
manhpham 0:c8673aa96267 2584 // Set AFE bit to enable simplified access permissions model
manhpham 0:c8673aa96267 2585 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
manhpham 0:c8673aa96267 2586 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
manhpham 0:c8673aa96267 2587 __ISB();
manhpham 0:c8673aa96267 2588 }
manhpham 0:c8673aa96267 2589
manhpham 0:c8673aa96267 2590 /** \brief Disable MMU
manhpham 0:c8673aa96267 2591 */
manhpham 0:c8673aa96267 2592 __STATIC_INLINE void MMU_Disable(void)
manhpham 0:c8673aa96267 2593 {
manhpham 0:c8673aa96267 2594 // Clear M bit 0 to disable the MMU
manhpham 0:c8673aa96267 2595 __set_SCTLR( __get_SCTLR() & ~1);
manhpham 0:c8673aa96267 2596 __ISB();
manhpham 0:c8673aa96267 2597 }
manhpham 0:c8673aa96267 2598
manhpham 0:c8673aa96267 2599 /** \brief Invalidate entire unified TLB
manhpham 0:c8673aa96267 2600 */
manhpham 0:c8673aa96267 2601
manhpham 0:c8673aa96267 2602 __STATIC_INLINE void MMU_InvalidateTLB(void)
manhpham 0:c8673aa96267 2603 {
manhpham 0:c8673aa96267 2604 __set_TLBIALL(0);
manhpham 0:c8673aa96267 2605 __DSB(); //ensure completion of the invalidation
manhpham 0:c8673aa96267 2606 __ISB(); //ensure instruction fetch path sees new state
manhpham 0:c8673aa96267 2607 }
manhpham 0:c8673aa96267 2608
manhpham 0:c8673aa96267 2609
manhpham 0:c8673aa96267 2610 #ifdef __cplusplus
manhpham 0:c8673aa96267 2611 }
manhpham 0:c8673aa96267 2612 #endif
manhpham 0:c8673aa96267 2613
manhpham 0:c8673aa96267 2614 #endif /* __CORE_CA_H_DEPENDANT */
manhpham 0:c8673aa96267 2615
manhpham 0:c8673aa96267 2616 #endif /* __CMSIS_GENERIC */