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VL53L1X.h@0:76ea242a637f, 2018-07-30 (annotated)
- Committer:
- jvfausto
- Date:
- Mon Jul 30 18:45:53 2018 +0000
- Revision:
- 0:76ea242a637f
- Child:
- 1:e54ded4af43a
Great Stuff, this will work better;
Who changed what in which revision?
| User | Revision | Line number | New contents of line | 
|---|---|---|---|
| jvfausto | 0:76ea242a637f | 1 | #ifndef VL53L1X_H | 
| jvfausto | 0:76ea242a637f | 2 | #define VL53L1X_H | 
| jvfausto | 0:76ea242a637f | 3 | |
| jvfausto | 0:76ea242a637f | 4 | #include "mbed.h" | 
| jvfausto | 0:76ea242a637f | 5 | |
| jvfausto | 0:76ea242a637f | 6 | class VL53L1X | 
| jvfausto | 0:76ea242a637f | 7 | { | 
| jvfausto | 0:76ea242a637f | 8 | public: | 
| jvfausto | 0:76ea242a637f | 9 | Timer t; | 
| jvfausto | 0:76ea242a637f | 10 | VL53L1X(PinName SDA, PinName SCL); | 
| jvfausto | 0:76ea242a637f | 11 | |
| jvfausto | 0:76ea242a637f | 12 | // register addresses from API vl53l1x_register_map.h | 
| jvfausto | 0:76ea242a637f | 13 | enum regAddr : uint16_t | 
| jvfausto | 0:76ea242a637f | 14 | { | 
| jvfausto | 0:76ea242a637f | 15 | SOFT_RESET = 0x0000, | 
| jvfausto | 0:76ea242a637f | 16 | I2C_SLAVE__DEVICE_ADDRESS = 0x0001, | 
| jvfausto | 0:76ea242a637f | 17 | ANA_CONFIG__VHV_REF_SEL_VDDPIX = 0x0002, | 
| jvfausto | 0:76ea242a637f | 18 | ANA_CONFIG__VHV_REF_SEL_VQUENCH = 0x0003, | 
| jvfausto | 0:76ea242a637f | 19 | ANA_CONFIG__REG_AVDD1V2_SEL = 0x0004, | 
| jvfausto | 0:76ea242a637f | 20 | ANA_CONFIG__FAST_OSC__TRIM = 0x0005, | 
| jvfausto | 0:76ea242a637f | 21 | OSC_MEASURED__FAST_OSC__FREQUENCY = 0x0006, | 
| jvfausto | 0:76ea242a637f | 22 | OSC_MEASURED__FAST_OSC__FREQUENCY_HI = 0x0006, | 
| jvfausto | 0:76ea242a637f | 23 | OSC_MEASURED__FAST_OSC__FREQUENCY_LO = 0x0007, | 
| jvfausto | 0:76ea242a637f | 24 | VHV_CONFIG__TIMEOUT_MACROP_LOOP_BOUND = 0x0008, | 
| jvfausto | 0:76ea242a637f | 25 | VHV_CONFIG__COUNT_THRESH = 0x0009, | 
| jvfausto | 0:76ea242a637f | 26 | VHV_CONFIG__OFFSET = 0x000A, | 
| jvfausto | 0:76ea242a637f | 27 | VHV_CONFIG__INIT = 0x000B, | 
| jvfausto | 0:76ea242a637f | 28 | GLOBAL_CONFIG__SPAD_ENABLES_REF_0 = 0x000D, | 
| jvfausto | 0:76ea242a637f | 29 | GLOBAL_CONFIG__SPAD_ENABLES_REF_1 = 0x000E, | 
| jvfausto | 0:76ea242a637f | 30 | GLOBAL_CONFIG__SPAD_ENABLES_REF_2 = 0x000F, | 
| jvfausto | 0:76ea242a637f | 31 | GLOBAL_CONFIG__SPAD_ENABLES_REF_3 = 0x0010, | 
| jvfausto | 0:76ea242a637f | 32 | GLOBAL_CONFIG__SPAD_ENABLES_REF_4 = 0x0011, | 
| jvfausto | 0:76ea242a637f | 33 | GLOBAL_CONFIG__SPAD_ENABLES_REF_5 = 0x0012, | 
| jvfausto | 0:76ea242a637f | 34 | GLOBAL_CONFIG__REF_EN_START_SELECT = 0x0013, | 
| jvfausto | 0:76ea242a637f | 35 | REF_SPAD_MAN__NUM_REQUESTED_REF_SPADS = 0x0014, | 
| jvfausto | 0:76ea242a637f | 36 | REF_SPAD_MAN__REF_LOCATION = 0x0015, | 
| jvfausto | 0:76ea242a637f | 37 | ALGO__CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS = 0x0016, | 
| jvfausto | 0:76ea242a637f | 38 | ALGO__CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS_HI = 0x0016, | 
| jvfausto | 0:76ea242a637f | 39 | ALGO__CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS_LO = 0x0017, | 
| jvfausto | 0:76ea242a637f | 40 | ALGO__CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS = 0x0018, | 
| jvfausto | 0:76ea242a637f | 41 | ALGO__CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS_HI = 0x0018, | 
| jvfausto | 0:76ea242a637f | 42 | ALGO__CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS_LO = 0x0019, | 
| jvfausto | 0:76ea242a637f | 43 | ALGO__CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS = 0x001A, | 
| jvfausto | 0:76ea242a637f | 44 | ALGO__CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS_HI = 0x001A, | 
| jvfausto | 0:76ea242a637f | 45 | ALGO__CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS_LO = 0x001B, | 
| jvfausto | 0:76ea242a637f | 46 | REF_SPAD_CHAR__TOTAL_RATE_TARGET_MCPS = 0x001C, | 
| jvfausto | 0:76ea242a637f | 47 | REF_SPAD_CHAR__TOTAL_RATE_TARGET_MCPS_HI = 0x001C, | 
| jvfausto | 0:76ea242a637f | 48 | REF_SPAD_CHAR__TOTAL_RATE_TARGET_MCPS_LO = 0x001D, | 
| jvfausto | 0:76ea242a637f | 49 | ALGO__PART_TO_PART_RANGE_OFFSET_MM = 0x001E, | 
| jvfausto | 0:76ea242a637f | 50 | ALGO__PART_TO_PART_RANGE_OFFSET_MM_HI = 0x001E, | 
| jvfausto | 0:76ea242a637f | 51 | ALGO__PART_TO_PART_RANGE_OFFSET_MM_LO = 0x001F, | 
| jvfausto | 0:76ea242a637f | 52 | MM_CONFIG__INNER_OFFSET_MM = 0x0020, | 
| jvfausto | 0:76ea242a637f | 53 | MM_CONFIG__INNER_OFFSET_MM_HI = 0x0020, | 
| jvfausto | 0:76ea242a637f | 54 | MM_CONFIG__INNER_OFFSET_MM_LO = 0x0021, | 
| jvfausto | 0:76ea242a637f | 55 | MM_CONFIG__OUTER_OFFSET_MM = 0x0022, | 
| jvfausto | 0:76ea242a637f | 56 | MM_CONFIG__OUTER_OFFSET_MM_HI = 0x0022, | 
| jvfausto | 0:76ea242a637f | 57 | MM_CONFIG__OUTER_OFFSET_MM_LO = 0x0023, | 
| jvfausto | 0:76ea242a637f | 58 | DSS_CONFIG__TARGET_TOTAL_RATE_MCPS = 0x0024, | 
| jvfausto | 0:76ea242a637f | 59 | DSS_CONFIG__TARGET_TOTAL_RATE_MCPS_HI = 0x0024, | 
| jvfausto | 0:76ea242a637f | 60 | DSS_CONFIG__TARGET_TOTAL_RATE_MCPS_LO = 0x0025, | 
| jvfausto | 0:76ea242a637f | 61 | DEBUG__CTRL = 0x0026, | 
| jvfausto | 0:76ea242a637f | 62 | TEST_MODE__CTRL = 0x0027, | 
| jvfausto | 0:76ea242a637f | 63 | CLK_GATING__CTRL = 0x0028, | 
| jvfausto | 0:76ea242a637f | 64 | NVM_BIST__CTRL = 0x0029, | 
| jvfausto | 0:76ea242a637f | 65 | NVM_BIST__NUM_NVM_WORDS = 0x002A, | 
| jvfausto | 0:76ea242a637f | 66 | NVM_BIST__START_ADDRESS = 0x002B, | 
| jvfausto | 0:76ea242a637f | 67 | HOST_IF__STATUS = 0x002C, | 
| jvfausto | 0:76ea242a637f | 68 | PAD_I2C_HV__CONFIG = 0x002D, | 
| jvfausto | 0:76ea242a637f | 69 | PAD_I2C_HV__EXTSUP_CONFIG = 0x002E, | 
| jvfausto | 0:76ea242a637f | 70 | GPIO_HV_PAD__CTRL = 0x002F, | 
| jvfausto | 0:76ea242a637f | 71 | GPIO_HV_MUX__CTRL = 0x0030, | 
| jvfausto | 0:76ea242a637f | 72 | GPIO__TIO_HV_STATUS = 0x0031, | 
| jvfausto | 0:76ea242a637f | 73 | GPIO__FIO_HV_STATUS = 0x0032, | 
| jvfausto | 0:76ea242a637f | 74 | ANA_CONFIG__SPAD_SEL_PSWIDTH = 0x0033, | 
| jvfausto | 0:76ea242a637f | 75 | ANA_CONFIG__VCSEL_PULSE_WIDTH_OFFSET = 0x0034, | 
| jvfausto | 0:76ea242a637f | 76 | ANA_CONFIG__FAST_OSC__CONFIG_CTRL = 0x0035, | 
| jvfausto | 0:76ea242a637f | 77 | SIGMA_ESTIMATOR__EFFECTIVE_PULSE_WIDTH_NS = 0x0036, | 
| jvfausto | 0:76ea242a637f | 78 | SIGMA_ESTIMATOR__EFFECTIVE_AMBIENT_WIDTH_NS = 0x0037, | 
| jvfausto | 0:76ea242a637f | 79 | SIGMA_ESTIMATOR__SIGMA_REF_MM = 0x0038, | 
| jvfausto | 0:76ea242a637f | 80 | ALGO__CROSSTALK_COMPENSATION_VALID_HEIGHT_MM = 0x0039, | 
| jvfausto | 0:76ea242a637f | 81 | SPARE_HOST_CONFIG__STATIC_CONFIG_SPARE_0 = 0x003A, | 
| jvfausto | 0:76ea242a637f | 82 | SPARE_HOST_CONFIG__STATIC_CONFIG_SPARE_1 = 0x003B, | 
| jvfausto | 0:76ea242a637f | 83 | ALGO__RANGE_IGNORE_THRESHOLD_MCPS = 0x003C, | 
| jvfausto | 0:76ea242a637f | 84 | ALGO__RANGE_IGNORE_THRESHOLD_MCPS_HI = 0x003C, | 
| jvfausto | 0:76ea242a637f | 85 | ALGO__RANGE_IGNORE_THRESHOLD_MCPS_LO = 0x003D, | 
| jvfausto | 0:76ea242a637f | 86 | ALGO__RANGE_IGNORE_VALID_HEIGHT_MM = 0x003E, | 
| jvfausto | 0:76ea242a637f | 87 | ALGO__RANGE_MIN_CLIP = 0x003F, | 
| jvfausto | 0:76ea242a637f | 88 | ALGO__CONSISTENCY_CHECK__TOLERANCE = 0x0040, | 
| jvfausto | 0:76ea242a637f | 89 | SPARE_HOST_CONFIG__STATIC_CONFIG_SPARE_2 = 0x0041, | 
| jvfausto | 0:76ea242a637f | 90 | SD_CONFIG__RESET_STAGES_MSB = 0x0042, | 
| jvfausto | 0:76ea242a637f | 91 | SD_CONFIG__RESET_STAGES_LSB = 0x0043, | 
| jvfausto | 0:76ea242a637f | 92 | GPH_CONFIG__STREAM_COUNT_UPDATE_VALUE = 0x0044, | 
| jvfausto | 0:76ea242a637f | 93 | GLOBAL_CONFIG__STREAM_DIVIDER = 0x0045, | 
| jvfausto | 0:76ea242a637f | 94 | SYSTEM__INTERRUPT_CONFIG_GPIO = 0x0046, | 
| jvfausto | 0:76ea242a637f | 95 | CAL_CONFIG__VCSEL_START = 0x0047, | 
| jvfausto | 0:76ea242a637f | 96 | CAL_CONFIG__REPEAT_RATE = 0x0048, | 
| jvfausto | 0:76ea242a637f | 97 | CAL_CONFIG__REPEAT_RATE_HI = 0x0048, | 
| jvfausto | 0:76ea242a637f | 98 | CAL_CONFIG__REPEAT_RATE_LO = 0x0049, | 
| jvfausto | 0:76ea242a637f | 99 | GLOBAL_CONFIG__VCSEL_WIDTH = 0x004A, | 
| jvfausto | 0:76ea242a637f | 100 | PHASECAL_CONFIG__TIMEOUT_MACROP = 0x004B, | 
| jvfausto | 0:76ea242a637f | 101 | PHASECAL_CONFIG__TARGET = 0x004C, | 
| jvfausto | 0:76ea242a637f | 102 | PHASECAL_CONFIG__OVERRIDE = 0x004D, | 
| jvfausto | 0:76ea242a637f | 103 | DSS_CONFIG__ROI_MODE_CONTROL = 0x004F, | 
| jvfausto | 0:76ea242a637f | 104 | SYSTEM__THRESH_RATE_HIGH = 0x0050, | 
| jvfausto | 0:76ea242a637f | 105 | SYSTEM__THRESH_RATE_HIGH_HI = 0x0050, | 
| jvfausto | 0:76ea242a637f | 106 | SYSTEM__THRESH_RATE_HIGH_LO = 0x0051, | 
| jvfausto | 0:76ea242a637f | 107 | SYSTEM__THRESH_RATE_LOW = 0x0052, | 
| jvfausto | 0:76ea242a637f | 108 | SYSTEM__THRESH_RATE_LOW_HI = 0x0052, | 
| jvfausto | 0:76ea242a637f | 109 | SYSTEM__THRESH_RATE_LOW_LO = 0x0053, | 
| jvfausto | 0:76ea242a637f | 110 | DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT = 0x0054, | 
| jvfausto | 0:76ea242a637f | 111 | DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT_HI = 0x0054, | 
| jvfausto | 0:76ea242a637f | 112 | DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT_LO = 0x0055, | 
| jvfausto | 0:76ea242a637f | 113 | DSS_CONFIG__MANUAL_BLOCK_SELECT = 0x0056, | 
| jvfausto | 0:76ea242a637f | 114 | DSS_CONFIG__APERTURE_ATTENUATION = 0x0057, | 
| jvfausto | 0:76ea242a637f | 115 | DSS_CONFIG__MAX_SPADS_LIMIT = 0x0058, | 
| jvfausto | 0:76ea242a637f | 116 | DSS_CONFIG__MIN_SPADS_LIMIT = 0x0059, | 
| jvfausto | 0:76ea242a637f | 117 | MM_CONFIG__TIMEOUT_MACROP_A = 0x005A, // added by Pololu for 16-bit accesses | 
| jvfausto | 0:76ea242a637f | 118 | MM_CONFIG__TIMEOUT_MACROP_A_HI = 0x005A, | 
| jvfausto | 0:76ea242a637f | 119 | MM_CONFIG__TIMEOUT_MACROP_A_LO = 0x005B, | 
| jvfausto | 0:76ea242a637f | 120 | MM_CONFIG__TIMEOUT_MACROP_B = 0x005C, // added by Pololu for 16-bit accesses | 
| jvfausto | 0:76ea242a637f | 121 | MM_CONFIG__TIMEOUT_MACROP_B_HI = 0x005C, | 
| jvfausto | 0:76ea242a637f | 122 | MM_CONFIG__TIMEOUT_MACROP_B_LO = 0x005D, | 
| jvfausto | 0:76ea242a637f | 123 | RANGE_CONFIG__TIMEOUT_MACROP_A = 0x005E, // added by Pololu for 16-bit accesses | 
| jvfausto | 0:76ea242a637f | 124 | RANGE_CONFIG__TIMEOUT_MACROP_A_HI = 0x005E, | 
| jvfausto | 0:76ea242a637f | 125 | RANGE_CONFIG__TIMEOUT_MACROP_A_LO = 0x005F, | 
| jvfausto | 0:76ea242a637f | 126 | RANGE_CONFIG__VCSEL_PERIOD_A = 0x0060, | 
| jvfausto | 0:76ea242a637f | 127 | RANGE_CONFIG__TIMEOUT_MACROP_B = 0x0061, // added by Pololu for 16-bit accesses | 
| jvfausto | 0:76ea242a637f | 128 | RANGE_CONFIG__TIMEOUT_MACROP_B_HI = 0x0061, | 
| jvfausto | 0:76ea242a637f | 129 | RANGE_CONFIG__TIMEOUT_MACROP_B_LO = 0x0062, | 
| jvfausto | 0:76ea242a637f | 130 | RANGE_CONFIG__VCSEL_PERIOD_B = 0x0063, | 
| jvfausto | 0:76ea242a637f | 131 | RANGE_CONFIG__SIGMA_THRESH = 0x0064, | 
| jvfausto | 0:76ea242a637f | 132 | RANGE_CONFIG__SIGMA_THRESH_HI = 0x0064, | 
| jvfausto | 0:76ea242a637f | 133 | RANGE_CONFIG__SIGMA_THRESH_LO = 0x0065, | 
| jvfausto | 0:76ea242a637f | 134 | RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS = 0x0066, | 
| jvfausto | 0:76ea242a637f | 135 | RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS_HI = 0x0066, | 
| jvfausto | 0:76ea242a637f | 136 | RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS_LO = 0x0067, | 
| jvfausto | 0:76ea242a637f | 137 | RANGE_CONFIG__VALID_PHASE_LOW = 0x0068, | 
| jvfausto | 0:76ea242a637f | 138 | RANGE_CONFIG__VALID_PHASE_HIGH = 0x0069, | 
| jvfausto | 0:76ea242a637f | 139 | SYSTEM__INTERMEASUREMENT_PERIOD = 0x006C, | 
| jvfausto | 0:76ea242a637f | 140 | SYSTEM__INTERMEASUREMENT_PERIOD_3 = 0x006C, | 
| jvfausto | 0:76ea242a637f | 141 | SYSTEM__INTERMEASUREMENT_PERIOD_2 = 0x006D, | 
| jvfausto | 0:76ea242a637f | 142 | SYSTEM__INTERMEASUREMENT_PERIOD_1 = 0x006E, | 
| jvfausto | 0:76ea242a637f | 143 | SYSTEM__INTERMEASUREMENT_PERIOD_0 = 0x006F, | 
| jvfausto | 0:76ea242a637f | 144 | SYSTEM__FRACTIONAL_ENABLE = 0x0070, | 
| jvfausto | 0:76ea242a637f | 145 | SYSTEM__GROUPED_PARAMETER_HOLD_0 = 0x0071, | 
| jvfausto | 0:76ea242a637f | 146 | SYSTEM__THRESH_HIGH = 0x0072, | 
| jvfausto | 0:76ea242a637f | 147 | SYSTEM__THRESH_HIGH_HI = 0x0072, | 
| jvfausto | 0:76ea242a637f | 148 | SYSTEM__THRESH_HIGH_LO = 0x0073, | 
| jvfausto | 0:76ea242a637f | 149 | SYSTEM__THRESH_LOW = 0x0074, | 
| jvfausto | 0:76ea242a637f | 150 | SYSTEM__THRESH_LOW_HI = 0x0074, | 
| jvfausto | 0:76ea242a637f | 151 | SYSTEM__THRESH_LOW_LO = 0x0075, | 
| jvfausto | 0:76ea242a637f | 152 | SYSTEM__ENABLE_XTALK_PER_QUADRANT = 0x0076, | 
| jvfausto | 0:76ea242a637f | 153 | SYSTEM__SEED_CONFIG = 0x0077, | 
| jvfausto | 0:76ea242a637f | 154 | SD_CONFIG__WOI_SD0 = 0x0078, | 
| jvfausto | 0:76ea242a637f | 155 | SD_CONFIG__WOI_SD1 = 0x0079, | 
| jvfausto | 0:76ea242a637f | 156 | SD_CONFIG__INITIAL_PHASE_SD0 = 0x007A, | 
| jvfausto | 0:76ea242a637f | 157 | SD_CONFIG__INITIAL_PHASE_SD1 = 0x007B, | 
| jvfausto | 0:76ea242a637f | 158 | SYSTEM__GROUPED_PARAMETER_HOLD_1 = 0x007C, | 
| jvfausto | 0:76ea242a637f | 159 | SD_CONFIG__FIRST_ORDER_SELECT = 0x007D, | 
| jvfausto | 0:76ea242a637f | 160 | SD_CONFIG__QUANTIFIER = 0x007E, | 
| jvfausto | 0:76ea242a637f | 161 | ROI_CONFIG__USER_ROI_CENTRE_SPAD = 0x007F, | 
| jvfausto | 0:76ea242a637f | 162 | ROI_CONFIG__USER_ROI_REQUESTED_GLOBAL_XY_SIZE = 0x0080, | 
| jvfausto | 0:76ea242a637f | 163 | SYSTEM__SEQUENCE_CONFIG = 0x0081, | 
| jvfausto | 0:76ea242a637f | 164 | SYSTEM__GROUPED_PARAMETER_HOLD = 0x0082, | 
| jvfausto | 0:76ea242a637f | 165 | POWER_MANAGEMENT__GO1_POWER_FORCE = 0x0083, | 
| jvfausto | 0:76ea242a637f | 166 | SYSTEM__STREAM_COUNT_CTRL = 0x0084, | 
| jvfausto | 0:76ea242a637f | 167 | FIRMWARE__ENABLE = 0x0085, | 
| jvfausto | 0:76ea242a637f | 168 | SYSTEM__INTERRUPT_CLEAR = 0x0086, | 
| jvfausto | 0:76ea242a637f | 169 | SYSTEM__MODE_START = 0x0087, | 
| jvfausto | 0:76ea242a637f | 170 | RESULT__INTERRUPT_STATUS = 0x0088, | 
| jvfausto | 0:76ea242a637f | 171 | RESULT__RANGE_STATUS = 0x0089, | 
| jvfausto | 0:76ea242a637f | 172 | RESULT__REPORT_STATUS = 0x008A, | 
| jvfausto | 0:76ea242a637f | 173 | RESULT__STREAM_COUNT = 0x008B, | 
| jvfausto | 0:76ea242a637f | 174 | RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0 = 0x008C, | 
| jvfausto | 0:76ea242a637f | 175 | RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_HI = 0x008C, | 
| jvfausto | 0:76ea242a637f | 176 | RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_LO = 0x008D, | 
| jvfausto | 0:76ea242a637f | 177 | RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0 = 0x008E, | 
| jvfausto | 0:76ea242a637f | 178 | RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_HI = 0x008E, | 
| jvfausto | 0:76ea242a637f | 179 | RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_LO = 0x008F, | 
| jvfausto | 0:76ea242a637f | 180 | RESULT__AMBIENT_COUNT_RATE_MCPS_SD0 = 0x0090, | 
| jvfausto | 0:76ea242a637f | 181 | RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_HI = 0x0090, | 
| jvfausto | 0:76ea242a637f | 182 | RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_LO = 0x0091, | 
| jvfausto | 0:76ea242a637f | 183 | RESULT__SIGMA_SD0 = 0x0092, | 
| jvfausto | 0:76ea242a637f | 184 | RESULT__SIGMA_SD0_HI = 0x0092, | 
| jvfausto | 0:76ea242a637f | 185 | RESULT__SIGMA_SD0_LO = 0x0093, | 
| jvfausto | 0:76ea242a637f | 186 | RESULT__PHASE_SD0 = 0x0094, | 
| jvfausto | 0:76ea242a637f | 187 | RESULT__PHASE_SD0_HI = 0x0094, | 
| jvfausto | 0:76ea242a637f | 188 | RESULT__PHASE_SD0_LO = 0x0095, | 
| jvfausto | 0:76ea242a637f | 189 | RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0 = 0x0096, | 
| jvfausto | 0:76ea242a637f | 190 | RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_HI = 0x0096, | 
| jvfausto | 0:76ea242a637f | 191 | RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_LO = 0x0097, | 
| jvfausto | 0:76ea242a637f | 192 | RESULT__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0 = 0x0098, | 
| jvfausto | 0:76ea242a637f | 193 | RESULT__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_HI = 0x0098, | 
| jvfausto | 0:76ea242a637f | 194 | RESULT__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_LO = 0x0099, | 
| jvfausto | 0:76ea242a637f | 195 | RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0 = 0x009A, | 
| jvfausto | 0:76ea242a637f | 196 | RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_HI = 0x009A, | 
| jvfausto | 0:76ea242a637f | 197 | RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_LO = 0x009B, | 
| jvfausto | 0:76ea242a637f | 198 | RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0 = 0x009C, | 
| jvfausto | 0:76ea242a637f | 199 | RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_HI = 0x009C, | 
| jvfausto | 0:76ea242a637f | 200 | RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_LO = 0x009D, | 
| jvfausto | 0:76ea242a637f | 201 | RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0 = 0x009E, | 
| jvfausto | 0:76ea242a637f | 202 | RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_HI = 0x009E, | 
| jvfausto | 0:76ea242a637f | 203 | RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_LO = 0x009F, | 
| jvfausto | 0:76ea242a637f | 204 | RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1 = 0x00A0, | 
| jvfausto | 0:76ea242a637f | 205 | RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_HI = 0x00A0, | 
| jvfausto | 0:76ea242a637f | 206 | RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_LO = 0x00A1, | 
| jvfausto | 0:76ea242a637f | 207 | RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1 = 0x00A2, | 
| jvfausto | 0:76ea242a637f | 208 | RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_HI = 0x00A2, | 
| jvfausto | 0:76ea242a637f | 209 | RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_LO = 0x00A3, | 
| jvfausto | 0:76ea242a637f | 210 | RESULT__AMBIENT_COUNT_RATE_MCPS_SD1 = 0x00A4, | 
| jvfausto | 0:76ea242a637f | 211 | RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_HI = 0x00A4, | 
| jvfausto | 0:76ea242a637f | 212 | RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_LO = 0x00A5, | 
| jvfausto | 0:76ea242a637f | 213 | RESULT__SIGMA_SD1 = 0x00A6, | 
| jvfausto | 0:76ea242a637f | 214 | RESULT__SIGMA_SD1_HI = 0x00A6, | 
| jvfausto | 0:76ea242a637f | 215 | RESULT__SIGMA_SD1_LO = 0x00A7, | 
| jvfausto | 0:76ea242a637f | 216 | RESULT__PHASE_SD1 = 0x00A8, | 
| jvfausto | 0:76ea242a637f | 217 | RESULT__PHASE_SD1_HI = 0x00A8, | 
| jvfausto | 0:76ea242a637f | 218 | RESULT__PHASE_SD1_LO = 0x00A9, | 
| jvfausto | 0:76ea242a637f | 219 | RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1 = 0x00AA, | 
| jvfausto | 0:76ea242a637f | 220 | RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_HI = 0x00AA, | 
| jvfausto | 0:76ea242a637f | 221 | RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_LO = 0x00AB, | 
| jvfausto | 0:76ea242a637f | 222 | RESULT__SPARE_0_SD1 = 0x00AC, | 
| jvfausto | 0:76ea242a637f | 223 | RESULT__SPARE_0_SD1_HI = 0x00AC, | 
| jvfausto | 0:76ea242a637f | 224 | RESULT__SPARE_0_SD1_LO = 0x00AD, | 
| jvfausto | 0:76ea242a637f | 225 | RESULT__SPARE_1_SD1 = 0x00AE, | 
| jvfausto | 0:76ea242a637f | 226 | RESULT__SPARE_1_SD1_HI = 0x00AE, | 
| jvfausto | 0:76ea242a637f | 227 | RESULT__SPARE_1_SD1_LO = 0x00AF, | 
| jvfausto | 0:76ea242a637f | 228 | RESULT__SPARE_2_SD1 = 0x00B0, | 
| jvfausto | 0:76ea242a637f | 229 | RESULT__SPARE_2_SD1_HI = 0x00B0, | 
| jvfausto | 0:76ea242a637f | 230 | RESULT__SPARE_2_SD1_LO = 0x00B1, | 
| jvfausto | 0:76ea242a637f | 231 | RESULT__SPARE_3_SD1 = 0x00B2, | 
| jvfausto | 0:76ea242a637f | 232 | RESULT__THRESH_INFO = 0x00B3, | 
| jvfausto | 0:76ea242a637f | 233 | RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0 = 0x00B4, | 
| jvfausto | 0:76ea242a637f | 234 | RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_3 = 0x00B4, | 
| jvfausto | 0:76ea242a637f | 235 | RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_2 = 0x00B5, | 
| jvfausto | 0:76ea242a637f | 236 | RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_1 = 0x00B6, | 
| jvfausto | 0:76ea242a637f | 237 | RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_0 = 0x00B7, | 
| jvfausto | 0:76ea242a637f | 238 | RESULT_CORE__RANGING_TOTAL_EVENTS_SD0 = 0x00B8, | 
| jvfausto | 0:76ea242a637f | 239 | RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_3 = 0x00B8, | 
| jvfausto | 0:76ea242a637f | 240 | RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_2 = 0x00B9, | 
| jvfausto | 0:76ea242a637f | 241 | RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_1 = 0x00BA, | 
| jvfausto | 0:76ea242a637f | 242 | RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_0 = 0x00BB, | 
| jvfausto | 0:76ea242a637f | 243 | RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0 = 0x00BC, | 
| jvfausto | 0:76ea242a637f | 244 | RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_3 = 0x00BC, | 
| jvfausto | 0:76ea242a637f | 245 | RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_2 = 0x00BD, | 
| jvfausto | 0:76ea242a637f | 246 | RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_1 = 0x00BE, | 
| jvfausto | 0:76ea242a637f | 247 | RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_0 = 0x00BF, | 
| jvfausto | 0:76ea242a637f | 248 | RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0 = 0x00C0, | 
| jvfausto | 0:76ea242a637f | 249 | RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_3 = 0x00C0, | 
| jvfausto | 0:76ea242a637f | 250 | RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_2 = 0x00C1, | 
| jvfausto | 0:76ea242a637f | 251 | RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_1 = 0x00C2, | 
| jvfausto | 0:76ea242a637f | 252 | RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_0 = 0x00C3, | 
| jvfausto | 0:76ea242a637f | 253 | RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1 = 0x00C4, | 
| jvfausto | 0:76ea242a637f | 254 | RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_3 = 0x00C4, | 
| jvfausto | 0:76ea242a637f | 255 | RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_2 = 0x00C5, | 
| jvfausto | 0:76ea242a637f | 256 | RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_1 = 0x00C6, | 
| jvfausto | 0:76ea242a637f | 257 | RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_0 = 0x00C7, | 
| jvfausto | 0:76ea242a637f | 258 | RESULT_CORE__RANGING_TOTAL_EVENTS_SD1 = 0x00C8, | 
| jvfausto | 0:76ea242a637f | 259 | RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_3 = 0x00C8, | 
| jvfausto | 0:76ea242a637f | 260 | RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_2 = 0x00C9, | 
| jvfausto | 0:76ea242a637f | 261 | RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_1 = 0x00CA, | 
| jvfausto | 0:76ea242a637f | 262 | RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_0 = 0x00CB, | 
| jvfausto | 0:76ea242a637f | 263 | RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1 = 0x00CC, | 
| jvfausto | 0:76ea242a637f | 264 | RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_3 = 0x00CC, | 
| jvfausto | 0:76ea242a637f | 265 | RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_2 = 0x00CD, | 
| jvfausto | 0:76ea242a637f | 266 | RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_1 = 0x00CE, | 
| jvfausto | 0:76ea242a637f | 267 | RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_0 = 0x00CF, | 
| jvfausto | 0:76ea242a637f | 268 | RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1 = 0x00D0, | 
| jvfausto | 0:76ea242a637f | 269 | RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_3 = 0x00D0, | 
| jvfausto | 0:76ea242a637f | 270 | RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_2 = 0x00D1, | 
| jvfausto | 0:76ea242a637f | 271 | RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_1 = 0x00D2, | 
| jvfausto | 0:76ea242a637f | 272 | RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_0 = 0x00D3, | 
| jvfausto | 0:76ea242a637f | 273 | RESULT_CORE__SPARE_0 = 0x00D4, | 
| jvfausto | 0:76ea242a637f | 274 | PHASECAL_RESULT__REFERENCE_PHASE = 0x00D6, | 
| jvfausto | 0:76ea242a637f | 275 | PHASECAL_RESULT__REFERENCE_PHASE_HI = 0x00D6, | 
| jvfausto | 0:76ea242a637f | 276 | PHASECAL_RESULT__REFERENCE_PHASE_LO = 0x00D7, | 
| jvfausto | 0:76ea242a637f | 277 | PHASECAL_RESULT__VCSEL_START = 0x00D8, | 
| jvfausto | 0:76ea242a637f | 278 | REF_SPAD_CHAR_RESULT__NUM_ACTUAL_REF_SPADS = 0x00D9, | 
| jvfausto | 0:76ea242a637f | 279 | REF_SPAD_CHAR_RESULT__REF_LOCATION = 0x00DA, | 
| jvfausto | 0:76ea242a637f | 280 | VHV_RESULT__COLDBOOT_STATUS = 0x00DB, | 
| jvfausto | 0:76ea242a637f | 281 | VHV_RESULT__SEARCH_RESULT = 0x00DC, | 
| jvfausto | 0:76ea242a637f | 282 | VHV_RESULT__LATEST_SETTING = 0x00DD, | 
| jvfausto | 0:76ea242a637f | 283 | RESULT__OSC_CALIBRATE_VAL = 0x00DE, | 
| jvfausto | 0:76ea242a637f | 284 | RESULT__OSC_CALIBRATE_VAL_HI = 0x00DE, | 
| jvfausto | 0:76ea242a637f | 285 | RESULT__OSC_CALIBRATE_VAL_LO = 0x00DF, | 
| jvfausto | 0:76ea242a637f | 286 | ANA_CONFIG__POWERDOWN_GO1 = 0x00E0, | 
| jvfausto | 0:76ea242a637f | 287 | ANA_CONFIG__REF_BG_CTRL = 0x00E1, | 
| jvfausto | 0:76ea242a637f | 288 | ANA_CONFIG__REGDVDD1V2_CTRL = 0x00E2, | 
| jvfausto | 0:76ea242a637f | 289 | ANA_CONFIG__OSC_SLOW_CTRL = 0x00E3, | 
| jvfausto | 0:76ea242a637f | 290 | TEST_MODE__STATUS = 0x00E4, | 
| jvfausto | 0:76ea242a637f | 291 | FIRMWARE__SYSTEM_STATUS = 0x00E5, | 
| jvfausto | 0:76ea242a637f | 292 | FIRMWARE__MODE_STATUS = 0x00E6, | 
| jvfausto | 0:76ea242a637f | 293 | FIRMWARE__SECONDARY_MODE_STATUS = 0x00E7, | 
| jvfausto | 0:76ea242a637f | 294 | FIRMWARE__CAL_REPEAT_RATE_COUNTER = 0x00E8, | 
| jvfausto | 0:76ea242a637f | 295 | FIRMWARE__CAL_REPEAT_RATE_COUNTER_HI = 0x00E8, | 
| jvfausto | 0:76ea242a637f | 296 | FIRMWARE__CAL_REPEAT_RATE_COUNTER_LO = 0x00E9, | 
| jvfausto | 0:76ea242a637f | 297 | FIRMWARE__HISTOGRAM_BIN = 0x00EA, | 
| jvfausto | 0:76ea242a637f | 298 | GPH__SYSTEM__THRESH_HIGH = 0x00EC, | 
| jvfausto | 0:76ea242a637f | 299 | GPH__SYSTEM__THRESH_HIGH_HI = 0x00EC, | 
| jvfausto | 0:76ea242a637f | 300 | GPH__SYSTEM__THRESH_HIGH_LO = 0x00ED, | 
| jvfausto | 0:76ea242a637f | 301 | GPH__SYSTEM__THRESH_LOW = 0x00EE, | 
| jvfausto | 0:76ea242a637f | 302 | GPH__SYSTEM__THRESH_LOW_HI = 0x00EE, | 
| jvfausto | 0:76ea242a637f | 303 | GPH__SYSTEM__THRESH_LOW_LO = 0x00EF, | 
| jvfausto | 0:76ea242a637f | 304 | GPH__SYSTEM__ENABLE_XTALK_PER_QUADRANT = 0x00F0, | 
| jvfausto | 0:76ea242a637f | 305 | GPH__SPARE_0 = 0x00F1, | 
| jvfausto | 0:76ea242a637f | 306 | GPH__SD_CONFIG__WOI_SD0 = 0x00F2, | 
| jvfausto | 0:76ea242a637f | 307 | GPH__SD_CONFIG__WOI_SD1 = 0x00F3, | 
| jvfausto | 0:76ea242a637f | 308 | GPH__SD_CONFIG__INITIAL_PHASE_SD0 = 0x00F4, | 
| jvfausto | 0:76ea242a637f | 309 | GPH__SD_CONFIG__INITIAL_PHASE_SD1 = 0x00F5, | 
| jvfausto | 0:76ea242a637f | 310 | GPH__SD_CONFIG__FIRST_ORDER_SELECT = 0x00F6, | 
| jvfausto | 0:76ea242a637f | 311 | GPH__SD_CONFIG__QUANTIFIER = 0x00F7, | 
| jvfausto | 0:76ea242a637f | 312 | GPH__ROI_CONFIG__USER_ROI_CENTRE_SPAD = 0x00F8, | 
| jvfausto | 0:76ea242a637f | 313 | GPH__ROI_CONFIG__USER_ROI_REQUESTED_GLOBAL_XY_SIZE = 0x00F9, | 
| jvfausto | 0:76ea242a637f | 314 | GPH__SYSTEM__SEQUENCE_CONFIG = 0x00FA, | 
| jvfausto | 0:76ea242a637f | 315 | GPH__GPH_ID = 0x00FB, | 
| jvfausto | 0:76ea242a637f | 316 | SYSTEM__INTERRUPT_SET = 0x00FC, | 
| jvfausto | 0:76ea242a637f | 317 | INTERRUPT_MANAGER__ENABLES = 0x00FD, | 
| jvfausto | 0:76ea242a637f | 318 | INTERRUPT_MANAGER__CLEAR = 0x00FE, | 
| jvfausto | 0:76ea242a637f | 319 | INTERRUPT_MANAGER__STATUS = 0x00FF, | 
| jvfausto | 0:76ea242a637f | 320 | MCU_TO_HOST_BANK__WR_ACCESS_EN = 0x0100, | 
| jvfausto | 0:76ea242a637f | 321 | POWER_MANAGEMENT__GO1_RESET_STATUS = 0x0101, | 
| jvfausto | 0:76ea242a637f | 322 | PAD_STARTUP_MODE__VALUE_RO = 0x0102, | 
| jvfausto | 0:76ea242a637f | 323 | PAD_STARTUP_MODE__VALUE_CTRL = 0x0103, | 
| jvfausto | 0:76ea242a637f | 324 | PLL_PERIOD_US = 0x0104, | 
| jvfausto | 0:76ea242a637f | 325 | PLL_PERIOD_US_3 = 0x0104, | 
| jvfausto | 0:76ea242a637f | 326 | PLL_PERIOD_US_2 = 0x0105, | 
| jvfausto | 0:76ea242a637f | 327 | PLL_PERIOD_US_1 = 0x0106, | 
| jvfausto | 0:76ea242a637f | 328 | PLL_PERIOD_US_0 = 0x0107, | 
| jvfausto | 0:76ea242a637f | 329 | INTERRUPT_SCHEDULER__DATA_OUT = 0x0108, | 
| jvfausto | 0:76ea242a637f | 330 | INTERRUPT_SCHEDULER__DATA_OUT_3 = 0x0108, | 
| jvfausto | 0:76ea242a637f | 331 | INTERRUPT_SCHEDULER__DATA_OUT_2 = 0x0109, | 
| jvfausto | 0:76ea242a637f | 332 | INTERRUPT_SCHEDULER__DATA_OUT_1 = 0x010A, | 
| jvfausto | 0:76ea242a637f | 333 | INTERRUPT_SCHEDULER__DATA_OUT_0 = 0x010B, | 
| jvfausto | 0:76ea242a637f | 334 | NVM_BIST__COMPLETE = 0x010C, | 
| jvfausto | 0:76ea242a637f | 335 | NVM_BIST__STATUS = 0x010D, | 
| jvfausto | 0:76ea242a637f | 336 | IDENTIFICATION__MODEL_ID = 0x010F, | 
| jvfausto | 0:76ea242a637f | 337 | IDENTIFICATION__MODULE_TYPE = 0x0110, | 
| jvfausto | 0:76ea242a637f | 338 | IDENTIFICATION__REVISION_ID = 0x0111, | 
| jvfausto | 0:76ea242a637f | 339 | IDENTIFICATION__MODULE_ID = 0x0112, | 
| jvfausto | 0:76ea242a637f | 340 | IDENTIFICATION__MODULE_ID_HI = 0x0112, | 
| jvfausto | 0:76ea242a637f | 341 | IDENTIFICATION__MODULE_ID_LO = 0x0113, | 
| jvfausto | 0:76ea242a637f | 342 | ANA_CONFIG__FAST_OSC__TRIM_MAX = 0x0114, | 
| jvfausto | 0:76ea242a637f | 343 | ANA_CONFIG__FAST_OSC__FREQ_SET = 0x0115, | 
| jvfausto | 0:76ea242a637f | 344 | ANA_CONFIG__VCSEL_TRIM = 0x0116, | 
| jvfausto | 0:76ea242a637f | 345 | ANA_CONFIG__VCSEL_SELION = 0x0117, | 
| jvfausto | 0:76ea242a637f | 346 | ANA_CONFIG__VCSEL_SELION_MAX = 0x0118, | 
| jvfausto | 0:76ea242a637f | 347 | PROTECTED_LASER_SAFETY__LOCK_BIT = 0x0119, | 
| jvfausto | 0:76ea242a637f | 348 | LASER_SAFETY__KEY = 0x011A, | 
| jvfausto | 0:76ea242a637f | 349 | LASER_SAFETY__KEY_RO = 0x011B, | 
| jvfausto | 0:76ea242a637f | 350 | LASER_SAFETY__CLIP = 0x011C, | 
| jvfausto | 0:76ea242a637f | 351 | LASER_SAFETY__MULT = 0x011D, | 
| jvfausto | 0:76ea242a637f | 352 | GLOBAL_CONFIG__SPAD_ENABLES_RTN_0 = 0x011E, | 
| jvfausto | 0:76ea242a637f | 353 | GLOBAL_CONFIG__SPAD_ENABLES_RTN_1 = 0x011F, | 
| jvfausto | 0:76ea242a637f | 354 | GLOBAL_CONFIG__SPAD_ENABLES_RTN_2 = 0x0120, | 
| jvfausto | 0:76ea242a637f | 355 | GLOBAL_CONFIG__SPAD_ENABLES_RTN_3 = 0x0121, | 
| jvfausto | 0:76ea242a637f | 356 | GLOBAL_CONFIG__SPAD_ENABLES_RTN_4 = 0x0122, | 
| jvfausto | 0:76ea242a637f | 357 | GLOBAL_CONFIG__SPAD_ENABLES_RTN_5 = 0x0123, | 
| jvfausto | 0:76ea242a637f | 358 | GLOBAL_CONFIG__SPAD_ENABLES_RTN_6 = 0x0124, | 
| jvfausto | 0:76ea242a637f | 359 | GLOBAL_CONFIG__SPAD_ENABLES_RTN_7 = 0x0125, | 
| jvfausto | 0:76ea242a637f | 360 | GLOBAL_CONFIG__SPAD_ENABLES_RTN_8 = 0x0126, | 
| jvfausto | 0:76ea242a637f | 361 | GLOBAL_CONFIG__SPAD_ENABLES_RTN_9 = 0x0127, | 
| jvfausto | 0:76ea242a637f | 362 | GLOBAL_CONFIG__SPAD_ENABLES_RTN_10 = 0x0128, | 
| jvfausto | 0:76ea242a637f | 363 | GLOBAL_CONFIG__SPAD_ENABLES_RTN_11 = 0x0129, | 
| jvfausto | 0:76ea242a637f | 364 | GLOBAL_CONFIG__SPAD_ENABLES_RTN_12 = 0x012A, | 
| jvfausto | 0:76ea242a637f | 365 | GLOBAL_CONFIG__SPAD_ENABLES_RTN_13 = 0x012B, | 
| jvfausto | 0:76ea242a637f | 366 | GLOBAL_CONFIG__SPAD_ENABLES_RTN_14 = 0x012C, | 
| jvfausto | 0:76ea242a637f | 367 | GLOBAL_CONFIG__SPAD_ENABLES_RTN_15 = 0x012D, | 
| jvfausto | 0:76ea242a637f | 368 | GLOBAL_CONFIG__SPAD_ENABLES_RTN_16 = 0x012E, | 
| jvfausto | 0:76ea242a637f | 369 | GLOBAL_CONFIG__SPAD_ENABLES_RTN_17 = 0x012F, | 
| jvfausto | 0:76ea242a637f | 370 | GLOBAL_CONFIG__SPAD_ENABLES_RTN_18 = 0x0130, | 
| jvfausto | 0:76ea242a637f | 371 | GLOBAL_CONFIG__SPAD_ENABLES_RTN_19 = 0x0131, | 
| jvfausto | 0:76ea242a637f | 372 | GLOBAL_CONFIG__SPAD_ENABLES_RTN_20 = 0x0132, | 
| jvfausto | 0:76ea242a637f | 373 | GLOBAL_CONFIG__SPAD_ENABLES_RTN_21 = 0x0133, | 
| jvfausto | 0:76ea242a637f | 374 | GLOBAL_CONFIG__SPAD_ENABLES_RTN_22 = 0x0134, | 
| jvfausto | 0:76ea242a637f | 375 | GLOBAL_CONFIG__SPAD_ENABLES_RTN_23 = 0x0135, | 
| jvfausto | 0:76ea242a637f | 376 | GLOBAL_CONFIG__SPAD_ENABLES_RTN_24 = 0x0136, | 
| jvfausto | 0:76ea242a637f | 377 | GLOBAL_CONFIG__SPAD_ENABLES_RTN_25 = 0x0137, | 
| jvfausto | 0:76ea242a637f | 378 | GLOBAL_CONFIG__SPAD_ENABLES_RTN_26 = 0x0138, | 
| jvfausto | 0:76ea242a637f | 379 | GLOBAL_CONFIG__SPAD_ENABLES_RTN_27 = 0x0139, | 
| jvfausto | 0:76ea242a637f | 380 | GLOBAL_CONFIG__SPAD_ENABLES_RTN_28 = 0x013A, | 
| jvfausto | 0:76ea242a637f | 381 | GLOBAL_CONFIG__SPAD_ENABLES_RTN_29 = 0x013B, | 
| jvfausto | 0:76ea242a637f | 382 | GLOBAL_CONFIG__SPAD_ENABLES_RTN_30 = 0x013C, | 
| jvfausto | 0:76ea242a637f | 383 | GLOBAL_CONFIG__SPAD_ENABLES_RTN_31 = 0x013D, | 
| jvfausto | 0:76ea242a637f | 384 | ROI_CONFIG__MODE_ROI_CENTRE_SPAD = 0x013E, | 
| jvfausto | 0:76ea242a637f | 385 | ROI_CONFIG__MODE_ROI_XY_SIZE = 0x013F, | 
| jvfausto | 0:76ea242a637f | 386 | GO2_HOST_BANK_ACCESS__OVERRIDE = 0x0300, | 
| jvfausto | 0:76ea242a637f | 387 | MCU_UTIL_MULTIPLIER__MULTIPLICAND = 0x0400, | 
| jvfausto | 0:76ea242a637f | 388 | MCU_UTIL_MULTIPLIER__MULTIPLICAND_3 = 0x0400, | 
| jvfausto | 0:76ea242a637f | 389 | MCU_UTIL_MULTIPLIER__MULTIPLICAND_2 = 0x0401, | 
| jvfausto | 0:76ea242a637f | 390 | MCU_UTIL_MULTIPLIER__MULTIPLICAND_1 = 0x0402, | 
| jvfausto | 0:76ea242a637f | 391 | MCU_UTIL_MULTIPLIER__MULTIPLICAND_0 = 0x0403, | 
| jvfausto | 0:76ea242a637f | 392 | MCU_UTIL_MULTIPLIER__MULTIPLIER = 0x0404, | 
| jvfausto | 0:76ea242a637f | 393 | MCU_UTIL_MULTIPLIER__MULTIPLIER_3 = 0x0404, | 
| jvfausto | 0:76ea242a637f | 394 | MCU_UTIL_MULTIPLIER__MULTIPLIER_2 = 0x0405, | 
| jvfausto | 0:76ea242a637f | 395 | MCU_UTIL_MULTIPLIER__MULTIPLIER_1 = 0x0406, | 
| jvfausto | 0:76ea242a637f | 396 | MCU_UTIL_MULTIPLIER__MULTIPLIER_0 = 0x0407, | 
| jvfausto | 0:76ea242a637f | 397 | MCU_UTIL_MULTIPLIER__PRODUCT_HI = 0x0408, | 
| jvfausto | 0:76ea242a637f | 398 | MCU_UTIL_MULTIPLIER__PRODUCT_HI_3 = 0x0408, | 
| jvfausto | 0:76ea242a637f | 399 | MCU_UTIL_MULTIPLIER__PRODUCT_HI_2 = 0x0409, | 
| jvfausto | 0:76ea242a637f | 400 | MCU_UTIL_MULTIPLIER__PRODUCT_HI_1 = 0x040A, | 
| jvfausto | 0:76ea242a637f | 401 | MCU_UTIL_MULTIPLIER__PRODUCT_HI_0 = 0x040B, | 
| jvfausto | 0:76ea242a637f | 402 | MCU_UTIL_MULTIPLIER__PRODUCT_LO = 0x040C, | 
| jvfausto | 0:76ea242a637f | 403 | MCU_UTIL_MULTIPLIER__PRODUCT_LO_3 = 0x040C, | 
| jvfausto | 0:76ea242a637f | 404 | MCU_UTIL_MULTIPLIER__PRODUCT_LO_2 = 0x040D, | 
| jvfausto | 0:76ea242a637f | 405 | MCU_UTIL_MULTIPLIER__PRODUCT_LO_1 = 0x040E, | 
| jvfausto | 0:76ea242a637f | 406 | MCU_UTIL_MULTIPLIER__PRODUCT_LO_0 = 0x040F, | 
| jvfausto | 0:76ea242a637f | 407 | MCU_UTIL_MULTIPLIER__START = 0x0410, | 
| jvfausto | 0:76ea242a637f | 408 | MCU_UTIL_MULTIPLIER__STATUS = 0x0411, | 
| jvfausto | 0:76ea242a637f | 409 | MCU_UTIL_DIVIDER__START = 0x0412, | 
| jvfausto | 0:76ea242a637f | 410 | MCU_UTIL_DIVIDER__STATUS = 0x0413, | 
| jvfausto | 0:76ea242a637f | 411 | MCU_UTIL_DIVIDER__DIVIDEND = 0x0414, | 
| jvfausto | 0:76ea242a637f | 412 | MCU_UTIL_DIVIDER__DIVIDEND_3 = 0x0414, | 
| jvfausto | 0:76ea242a637f | 413 | MCU_UTIL_DIVIDER__DIVIDEND_2 = 0x0415, | 
| jvfausto | 0:76ea242a637f | 414 | MCU_UTIL_DIVIDER__DIVIDEND_1 = 0x0416, | 
| jvfausto | 0:76ea242a637f | 415 | MCU_UTIL_DIVIDER__DIVIDEND_0 = 0x0417, | 
| jvfausto | 0:76ea242a637f | 416 | MCU_UTIL_DIVIDER__DIVISOR = 0x0418, | 
| jvfausto | 0:76ea242a637f | 417 | MCU_UTIL_DIVIDER__DIVISOR_3 = 0x0418, | 
| jvfausto | 0:76ea242a637f | 418 | MCU_UTIL_DIVIDER__DIVISOR_2 = 0x0419, | 
| jvfausto | 0:76ea242a637f | 419 | MCU_UTIL_DIVIDER__DIVISOR_1 = 0x041A, | 
| jvfausto | 0:76ea242a637f | 420 | MCU_UTIL_DIVIDER__DIVISOR_0 = 0x041B, | 
| jvfausto | 0:76ea242a637f | 421 | MCU_UTIL_DIVIDER__QUOTIENT = 0x041C, | 
| jvfausto | 0:76ea242a637f | 422 | MCU_UTIL_DIVIDER__QUOTIENT_3 = 0x041C, | 
| jvfausto | 0:76ea242a637f | 423 | MCU_UTIL_DIVIDER__QUOTIENT_2 = 0x041D, | 
| jvfausto | 0:76ea242a637f | 424 | MCU_UTIL_DIVIDER__QUOTIENT_1 = 0x041E, | 
| jvfausto | 0:76ea242a637f | 425 | MCU_UTIL_DIVIDER__QUOTIENT_0 = 0x041F, | 
| jvfausto | 0:76ea242a637f | 426 | TIMER0__VALUE_IN = 0x0420, | 
| jvfausto | 0:76ea242a637f | 427 | TIMER0__VALUE_IN_3 = 0x0420, | 
| jvfausto | 0:76ea242a637f | 428 | TIMER0__VALUE_IN_2 = 0x0421, | 
| jvfausto | 0:76ea242a637f | 429 | TIMER0__VALUE_IN_1 = 0x0422, | 
| jvfausto | 0:76ea242a637f | 430 | TIMER0__VALUE_IN_0 = 0x0423, | 
| jvfausto | 0:76ea242a637f | 431 | TIMER1__VALUE_IN = 0x0424, | 
| jvfausto | 0:76ea242a637f | 432 | TIMER1__VALUE_IN_3 = 0x0424, | 
| jvfausto | 0:76ea242a637f | 433 | TIMER1__VALUE_IN_2 = 0x0425, | 
| jvfausto | 0:76ea242a637f | 434 | TIMER1__VALUE_IN_1 = 0x0426, | 
| jvfausto | 0:76ea242a637f | 435 | TIMER1__VALUE_IN_0 = 0x0427, | 
| jvfausto | 0:76ea242a637f | 436 | TIMER0__CTRL = 0x0428, | 
| jvfausto | 0:76ea242a637f | 437 | TIMER1__CTRL = 0x0429, | 
| jvfausto | 0:76ea242a637f | 438 | MCU_GENERAL_PURPOSE__GP_0 = 0x042C, | 
| jvfausto | 0:76ea242a637f | 439 | MCU_GENERAL_PURPOSE__GP_1 = 0x042D, | 
| jvfausto | 0:76ea242a637f | 440 | MCU_GENERAL_PURPOSE__GP_2 = 0x042E, | 
| jvfausto | 0:76ea242a637f | 441 | MCU_GENERAL_PURPOSE__GP_3 = 0x042F, | 
| jvfausto | 0:76ea242a637f | 442 | MCU_RANGE_CALC__CONFIG = 0x0430, | 
| jvfausto | 0:76ea242a637f | 443 | MCU_RANGE_CALC__OFFSET_CORRECTED_RANGE = 0x0432, | 
| jvfausto | 0:76ea242a637f | 444 | MCU_RANGE_CALC__OFFSET_CORRECTED_RANGE_HI = 0x0432, | 
| jvfausto | 0:76ea242a637f | 445 | MCU_RANGE_CALC__OFFSET_CORRECTED_RANGE_LO = 0x0433, | 
| jvfausto | 0:76ea242a637f | 446 | MCU_RANGE_CALC__SPARE_4 = 0x0434, | 
| jvfausto | 0:76ea242a637f | 447 | MCU_RANGE_CALC__SPARE_4_3 = 0x0434, | 
| jvfausto | 0:76ea242a637f | 448 | MCU_RANGE_CALC__SPARE_4_2 = 0x0435, | 
| jvfausto | 0:76ea242a637f | 449 | MCU_RANGE_CALC__SPARE_4_1 = 0x0436, | 
| jvfausto | 0:76ea242a637f | 450 | MCU_RANGE_CALC__SPARE_4_0 = 0x0437, | 
| jvfausto | 0:76ea242a637f | 451 | MCU_RANGE_CALC__AMBIENT_DURATION_PRE_CALC = 0x0438, | 
| jvfausto | 0:76ea242a637f | 452 | MCU_RANGE_CALC__AMBIENT_DURATION_PRE_CALC_HI = 0x0438, | 
| jvfausto | 0:76ea242a637f | 453 | MCU_RANGE_CALC__AMBIENT_DURATION_PRE_CALC_LO = 0x0439, | 
| jvfausto | 0:76ea242a637f | 454 | MCU_RANGE_CALC__ALGO_VCSEL_PERIOD = 0x043C, | 
| jvfausto | 0:76ea242a637f | 455 | MCU_RANGE_CALC__SPARE_5 = 0x043D, | 
| jvfausto | 0:76ea242a637f | 456 | MCU_RANGE_CALC__ALGO_TOTAL_PERIODS = 0x043E, | 
| jvfausto | 0:76ea242a637f | 457 | MCU_RANGE_CALC__ALGO_TOTAL_PERIODS_HI = 0x043E, | 
| jvfausto | 0:76ea242a637f | 458 | MCU_RANGE_CALC__ALGO_TOTAL_PERIODS_LO = 0x043F, | 
| jvfausto | 0:76ea242a637f | 459 | MCU_RANGE_CALC__ALGO_ACCUM_PHASE = 0x0440, | 
| jvfausto | 0:76ea242a637f | 460 | MCU_RANGE_CALC__ALGO_ACCUM_PHASE_3 = 0x0440, | 
| jvfausto | 0:76ea242a637f | 461 | MCU_RANGE_CALC__ALGO_ACCUM_PHASE_2 = 0x0441, | 
| jvfausto | 0:76ea242a637f | 462 | MCU_RANGE_CALC__ALGO_ACCUM_PHASE_1 = 0x0442, | 
| jvfausto | 0:76ea242a637f | 463 | MCU_RANGE_CALC__ALGO_ACCUM_PHASE_0 = 0x0443, | 
| jvfausto | 0:76ea242a637f | 464 | MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS = 0x0444, | 
| jvfausto | 0:76ea242a637f | 465 | MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS_3 = 0x0444, | 
| jvfausto | 0:76ea242a637f | 466 | MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS_2 = 0x0445, | 
| jvfausto | 0:76ea242a637f | 467 | MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS_1 = 0x0446, | 
| jvfausto | 0:76ea242a637f | 468 | MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS_0 = 0x0447, | 
| jvfausto | 0:76ea242a637f | 469 | MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS = 0x0448, | 
| jvfausto | 0:76ea242a637f | 470 | MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS_3 = 0x0448, | 
| jvfausto | 0:76ea242a637f | 471 | MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS_2 = 0x0449, | 
| jvfausto | 0:76ea242a637f | 472 | MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS_1 = 0x044A, | 
| jvfausto | 0:76ea242a637f | 473 | MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS_0 = 0x044B, | 
| jvfausto | 0:76ea242a637f | 474 | MCU_RANGE_CALC__SPARE_6 = 0x044C, | 
| jvfausto | 0:76ea242a637f | 475 | MCU_RANGE_CALC__SPARE_6_HI = 0x044C, | 
| jvfausto | 0:76ea242a637f | 476 | MCU_RANGE_CALC__SPARE_6_LO = 0x044D, | 
| jvfausto | 0:76ea242a637f | 477 | MCU_RANGE_CALC__ALGO_ADJUST_VCSEL_PERIOD = 0x044E, | 
| jvfausto | 0:76ea242a637f | 478 | MCU_RANGE_CALC__ALGO_ADJUST_VCSEL_PERIOD_HI = 0x044E, | 
| jvfausto | 0:76ea242a637f | 479 | MCU_RANGE_CALC__ALGO_ADJUST_VCSEL_PERIOD_LO = 0x044F, | 
| jvfausto | 0:76ea242a637f | 480 | MCU_RANGE_CALC__NUM_SPADS = 0x0450, | 
| jvfausto | 0:76ea242a637f | 481 | MCU_RANGE_CALC__NUM_SPADS_HI = 0x0450, | 
| jvfausto | 0:76ea242a637f | 482 | MCU_RANGE_CALC__NUM_SPADS_LO = 0x0451, | 
| jvfausto | 0:76ea242a637f | 483 | MCU_RANGE_CALC__PHASE_OUTPUT = 0x0452, | 
| jvfausto | 0:76ea242a637f | 484 | MCU_RANGE_CALC__PHASE_OUTPUT_HI = 0x0452, | 
| jvfausto | 0:76ea242a637f | 485 | MCU_RANGE_CALC__PHASE_OUTPUT_LO = 0x0453, | 
| jvfausto | 0:76ea242a637f | 486 | MCU_RANGE_CALC__RATE_PER_SPAD_MCPS = 0x0454, | 
| jvfausto | 0:76ea242a637f | 487 | MCU_RANGE_CALC__RATE_PER_SPAD_MCPS_3 = 0x0454, | 
| jvfausto | 0:76ea242a637f | 488 | MCU_RANGE_CALC__RATE_PER_SPAD_MCPS_2 = 0x0455, | 
| jvfausto | 0:76ea242a637f | 489 | MCU_RANGE_CALC__RATE_PER_SPAD_MCPS_1 = 0x0456, | 
| jvfausto | 0:76ea242a637f | 490 | MCU_RANGE_CALC__RATE_PER_SPAD_MCPS_0 = 0x0457, | 
| jvfausto | 0:76ea242a637f | 491 | MCU_RANGE_CALC__SPARE_7 = 0x0458, | 
| jvfausto | 0:76ea242a637f | 492 | MCU_RANGE_CALC__SPARE_8 = 0x0459, | 
| jvfausto | 0:76ea242a637f | 493 | MCU_RANGE_CALC__PEAK_SIGNAL_RATE_MCPS = 0x045A, | 
| jvfausto | 0:76ea242a637f | 494 | MCU_RANGE_CALC__PEAK_SIGNAL_RATE_MCPS_HI = 0x045A, | 
| jvfausto | 0:76ea242a637f | 495 | MCU_RANGE_CALC__PEAK_SIGNAL_RATE_MCPS_LO = 0x045B, | 
| jvfausto | 0:76ea242a637f | 496 | MCU_RANGE_CALC__AVG_SIGNAL_RATE_MCPS = 0x045C, | 
| jvfausto | 0:76ea242a637f | 497 | MCU_RANGE_CALC__AVG_SIGNAL_RATE_MCPS_HI = 0x045C, | 
| jvfausto | 0:76ea242a637f | 498 | MCU_RANGE_CALC__AVG_SIGNAL_RATE_MCPS_LO = 0x045D, | 
| jvfausto | 0:76ea242a637f | 499 | MCU_RANGE_CALC__AMBIENT_RATE_MCPS = 0x045E, | 
| jvfausto | 0:76ea242a637f | 500 | MCU_RANGE_CALC__AMBIENT_RATE_MCPS_HI = 0x045E, | 
| jvfausto | 0:76ea242a637f | 501 | MCU_RANGE_CALC__AMBIENT_RATE_MCPS_LO = 0x045F, | 
| jvfausto | 0:76ea242a637f | 502 | MCU_RANGE_CALC__XTALK = 0x0460, | 
| jvfausto | 0:76ea242a637f | 503 | MCU_RANGE_CALC__XTALK_HI = 0x0460, | 
| jvfausto | 0:76ea242a637f | 504 | MCU_RANGE_CALC__XTALK_LO = 0x0461, | 
| jvfausto | 0:76ea242a637f | 505 | MCU_RANGE_CALC__CALC_STATUS = 0x0462, | 
| jvfausto | 0:76ea242a637f | 506 | MCU_RANGE_CALC__DEBUG = 0x0463, | 
| jvfausto | 0:76ea242a637f | 507 | MCU_RANGE_CALC__PEAK_SIGNAL_RATE_XTALK_CORR_MCPS = 0x0464, | 
| jvfausto | 0:76ea242a637f | 508 | MCU_RANGE_CALC__PEAK_SIGNAL_RATE_XTALK_CORR_MCPS_HI = 0x0464, | 
| jvfausto | 0:76ea242a637f | 509 | MCU_RANGE_CALC__PEAK_SIGNAL_RATE_XTALK_CORR_MCPS_LO = 0x0465, | 
| jvfausto | 0:76ea242a637f | 510 | MCU_RANGE_CALC__SPARE_0 = 0x0468, | 
| jvfausto | 0:76ea242a637f | 511 | MCU_RANGE_CALC__SPARE_1 = 0x0469, | 
| jvfausto | 0:76ea242a637f | 512 | MCU_RANGE_CALC__SPARE_2 = 0x046A, | 
| jvfausto | 0:76ea242a637f | 513 | MCU_RANGE_CALC__SPARE_3 = 0x046B, | 
| jvfausto | 0:76ea242a637f | 514 | PATCH__CTRL = 0x0470, | 
| jvfausto | 0:76ea242a637f | 515 | PATCH__JMP_ENABLES = 0x0472, | 
| jvfausto | 0:76ea242a637f | 516 | PATCH__JMP_ENABLES_HI = 0x0472, | 
| jvfausto | 0:76ea242a637f | 517 | PATCH__JMP_ENABLES_LO = 0x0473, | 
| jvfausto | 0:76ea242a637f | 518 | PATCH__DATA_ENABLES = 0x0474, | 
| jvfausto | 0:76ea242a637f | 519 | PATCH__DATA_ENABLES_HI = 0x0474, | 
| jvfausto | 0:76ea242a637f | 520 | PATCH__DATA_ENABLES_LO = 0x0475, | 
| jvfausto | 0:76ea242a637f | 521 | PATCH__OFFSET_0 = 0x0476, | 
| jvfausto | 0:76ea242a637f | 522 | PATCH__OFFSET_0_HI = 0x0476, | 
| jvfausto | 0:76ea242a637f | 523 | PATCH__OFFSET_0_LO = 0x0477, | 
| jvfausto | 0:76ea242a637f | 524 | PATCH__OFFSET_1 = 0x0478, | 
| jvfausto | 0:76ea242a637f | 525 | PATCH__OFFSET_1_HI = 0x0478, | 
| jvfausto | 0:76ea242a637f | 526 | PATCH__OFFSET_1_LO = 0x0479, | 
| jvfausto | 0:76ea242a637f | 527 | PATCH__OFFSET_2 = 0x047A, | 
| jvfausto | 0:76ea242a637f | 528 | PATCH__OFFSET_2_HI = 0x047A, | 
| jvfausto | 0:76ea242a637f | 529 | PATCH__OFFSET_2_LO = 0x047B, | 
| jvfausto | 0:76ea242a637f | 530 | PATCH__OFFSET_3 = 0x047C, | 
| jvfausto | 0:76ea242a637f | 531 | PATCH__OFFSET_3_HI = 0x047C, | 
| jvfausto | 0:76ea242a637f | 532 | PATCH__OFFSET_3_LO = 0x047D, | 
| jvfausto | 0:76ea242a637f | 533 | PATCH__OFFSET_4 = 0x047E, | 
| jvfausto | 0:76ea242a637f | 534 | PATCH__OFFSET_4_HI = 0x047E, | 
| jvfausto | 0:76ea242a637f | 535 | PATCH__OFFSET_4_LO = 0x047F, | 
| jvfausto | 0:76ea242a637f | 536 | PATCH__OFFSET_5 = 0x0480, | 
| jvfausto | 0:76ea242a637f | 537 | PATCH__OFFSET_5_HI = 0x0480, | 
| jvfausto | 0:76ea242a637f | 538 | PATCH__OFFSET_5_LO = 0x0481, | 
| jvfausto | 0:76ea242a637f | 539 | PATCH__OFFSET_6 = 0x0482, | 
| jvfausto | 0:76ea242a637f | 540 | PATCH__OFFSET_6_HI = 0x0482, | 
| jvfausto | 0:76ea242a637f | 541 | PATCH__OFFSET_6_LO = 0x0483, | 
| jvfausto | 0:76ea242a637f | 542 | PATCH__OFFSET_7 = 0x0484, | 
| jvfausto | 0:76ea242a637f | 543 | PATCH__OFFSET_7_HI = 0x0484, | 
| jvfausto | 0:76ea242a637f | 544 | PATCH__OFFSET_7_LO = 0x0485, | 
| jvfausto | 0:76ea242a637f | 545 | PATCH__OFFSET_8 = 0x0486, | 
| jvfausto | 0:76ea242a637f | 546 | PATCH__OFFSET_8_HI = 0x0486, | 
| jvfausto | 0:76ea242a637f | 547 | PATCH__OFFSET_8_LO = 0x0487, | 
| jvfausto | 0:76ea242a637f | 548 | PATCH__OFFSET_9 = 0x0488, | 
| jvfausto | 0:76ea242a637f | 549 | PATCH__OFFSET_9_HI = 0x0488, | 
| jvfausto | 0:76ea242a637f | 550 | PATCH__OFFSET_9_LO = 0x0489, | 
| jvfausto | 0:76ea242a637f | 551 | PATCH__OFFSET_10 = 0x048A, | 
| jvfausto | 0:76ea242a637f | 552 | PATCH__OFFSET_10_HI = 0x048A, | 
| jvfausto | 0:76ea242a637f | 553 | PATCH__OFFSET_10_LO = 0x048B, | 
| jvfausto | 0:76ea242a637f | 554 | PATCH__OFFSET_11 = 0x048C, | 
| jvfausto | 0:76ea242a637f | 555 | PATCH__OFFSET_11_HI = 0x048C, | 
| jvfausto | 0:76ea242a637f | 556 | PATCH__OFFSET_11_LO = 0x048D, | 
| jvfausto | 0:76ea242a637f | 557 | PATCH__OFFSET_12 = 0x048E, | 
| jvfausto | 0:76ea242a637f | 558 | PATCH__OFFSET_12_HI = 0x048E, | 
| jvfausto | 0:76ea242a637f | 559 | PATCH__OFFSET_12_LO = 0x048F, | 
| jvfausto | 0:76ea242a637f | 560 | PATCH__OFFSET_13 = 0x0490, | 
| jvfausto | 0:76ea242a637f | 561 | PATCH__OFFSET_13_HI = 0x0490, | 
| jvfausto | 0:76ea242a637f | 562 | PATCH__OFFSET_13_LO = 0x0491, | 
| jvfausto | 0:76ea242a637f | 563 | PATCH__OFFSET_14 = 0x0492, | 
| jvfausto | 0:76ea242a637f | 564 | PATCH__OFFSET_14_HI = 0x0492, | 
| jvfausto | 0:76ea242a637f | 565 | PATCH__OFFSET_14_LO = 0x0493, | 
| jvfausto | 0:76ea242a637f | 566 | PATCH__OFFSET_15 = 0x0494, | 
| jvfausto | 0:76ea242a637f | 567 | PATCH__OFFSET_15_HI = 0x0494, | 
| jvfausto | 0:76ea242a637f | 568 | PATCH__OFFSET_15_LO = 0x0495, | 
| jvfausto | 0:76ea242a637f | 569 | PATCH__ADDRESS_0 = 0x0496, | 
| jvfausto | 0:76ea242a637f | 570 | PATCH__ADDRESS_0_HI = 0x0496, | 
| jvfausto | 0:76ea242a637f | 571 | PATCH__ADDRESS_0_LO = 0x0497, | 
| jvfausto | 0:76ea242a637f | 572 | PATCH__ADDRESS_1 = 0x0498, | 
| jvfausto | 0:76ea242a637f | 573 | PATCH__ADDRESS_1_HI = 0x0498, | 
| jvfausto | 0:76ea242a637f | 574 | PATCH__ADDRESS_1_LO = 0x0499, | 
| jvfausto | 0:76ea242a637f | 575 | PATCH__ADDRESS_2 = 0x049A, | 
| jvfausto | 0:76ea242a637f | 576 | PATCH__ADDRESS_2_HI = 0x049A, | 
| jvfausto | 0:76ea242a637f | 577 | PATCH__ADDRESS_2_LO = 0x049B, | 
| jvfausto | 0:76ea242a637f | 578 | PATCH__ADDRESS_3 = 0x049C, | 
| jvfausto | 0:76ea242a637f | 579 | PATCH__ADDRESS_3_HI = 0x049C, | 
| jvfausto | 0:76ea242a637f | 580 | PATCH__ADDRESS_3_LO = 0x049D, | 
| jvfausto | 0:76ea242a637f | 581 | PATCH__ADDRESS_4 = 0x049E, | 
| jvfausto | 0:76ea242a637f | 582 | PATCH__ADDRESS_4_HI = 0x049E, | 
| jvfausto | 0:76ea242a637f | 583 | PATCH__ADDRESS_4_LO = 0x049F, | 
| jvfausto | 0:76ea242a637f | 584 | PATCH__ADDRESS_5 = 0x04A0, | 
| jvfausto | 0:76ea242a637f | 585 | PATCH__ADDRESS_5_HI = 0x04A0, | 
| jvfausto | 0:76ea242a637f | 586 | PATCH__ADDRESS_5_LO = 0x04A1, | 
| jvfausto | 0:76ea242a637f | 587 | PATCH__ADDRESS_6 = 0x04A2, | 
| jvfausto | 0:76ea242a637f | 588 | PATCH__ADDRESS_6_HI = 0x04A2, | 
| jvfausto | 0:76ea242a637f | 589 | PATCH__ADDRESS_6_LO = 0x04A3, | 
| jvfausto | 0:76ea242a637f | 590 | PATCH__ADDRESS_7 = 0x04A4, | 
| jvfausto | 0:76ea242a637f | 591 | PATCH__ADDRESS_7_HI = 0x04A4, | 
| jvfausto | 0:76ea242a637f | 592 | PATCH__ADDRESS_7_LO = 0x04A5, | 
| jvfausto | 0:76ea242a637f | 593 | PATCH__ADDRESS_8 = 0x04A6, | 
| jvfausto | 0:76ea242a637f | 594 | PATCH__ADDRESS_8_HI = 0x04A6, | 
| jvfausto | 0:76ea242a637f | 595 | PATCH__ADDRESS_8_LO = 0x04A7, | 
| jvfausto | 0:76ea242a637f | 596 | PATCH__ADDRESS_9 = 0x04A8, | 
| jvfausto | 0:76ea242a637f | 597 | PATCH__ADDRESS_9_HI = 0x04A8, | 
| jvfausto | 0:76ea242a637f | 598 | PATCH__ADDRESS_9_LO = 0x04A9, | 
| jvfausto | 0:76ea242a637f | 599 | PATCH__ADDRESS_10 = 0x04AA, | 
| jvfausto | 0:76ea242a637f | 600 | PATCH__ADDRESS_10_HI = 0x04AA, | 
| jvfausto | 0:76ea242a637f | 601 | PATCH__ADDRESS_10_LO = 0x04AB, | 
| jvfausto | 0:76ea242a637f | 602 | PATCH__ADDRESS_11 = 0x04AC, | 
| jvfausto | 0:76ea242a637f | 603 | PATCH__ADDRESS_11_HI = 0x04AC, | 
| jvfausto | 0:76ea242a637f | 604 | PATCH__ADDRESS_11_LO = 0x04AD, | 
| jvfausto | 0:76ea242a637f | 605 | PATCH__ADDRESS_12 = 0x04AE, | 
| jvfausto | 0:76ea242a637f | 606 | PATCH__ADDRESS_12_HI = 0x04AE, | 
| jvfausto | 0:76ea242a637f | 607 | PATCH__ADDRESS_12_LO = 0x04AF, | 
| jvfausto | 0:76ea242a637f | 608 | PATCH__ADDRESS_13 = 0x04B0, | 
| jvfausto | 0:76ea242a637f | 609 | PATCH__ADDRESS_13_HI = 0x04B0, | 
| jvfausto | 0:76ea242a637f | 610 | PATCH__ADDRESS_13_LO = 0x04B1, | 
| jvfausto | 0:76ea242a637f | 611 | PATCH__ADDRESS_14 = 0x04B2, | 
| jvfausto | 0:76ea242a637f | 612 | PATCH__ADDRESS_14_HI = 0x04B2, | 
| jvfausto | 0:76ea242a637f | 613 | PATCH__ADDRESS_14_LO = 0x04B3, | 
| jvfausto | 0:76ea242a637f | 614 | PATCH__ADDRESS_15 = 0x04B4, | 
| jvfausto | 0:76ea242a637f | 615 | PATCH__ADDRESS_15_HI = 0x04B4, | 
| jvfausto | 0:76ea242a637f | 616 | PATCH__ADDRESS_15_LO = 0x04B5, | 
| jvfausto | 0:76ea242a637f | 617 | SPI_ASYNC_MUX__CTRL = 0x04C0, | 
| jvfausto | 0:76ea242a637f | 618 | CLK__CONFIG = 0x04C4, | 
| jvfausto | 0:76ea242a637f | 619 | GPIO_LV_MUX__CTRL = 0x04CC, | 
| jvfausto | 0:76ea242a637f | 620 | GPIO_LV_PAD__CTRL = 0x04CD, | 
| jvfausto | 0:76ea242a637f | 621 | PAD_I2C_LV__CONFIG = 0x04D0, | 
| jvfausto | 0:76ea242a637f | 622 | PAD_STARTUP_MODE__VALUE_RO_GO1 = 0x04D4, | 
| jvfausto | 0:76ea242a637f | 623 | HOST_IF__STATUS_GO1 = 0x04D5, | 
| jvfausto | 0:76ea242a637f | 624 | MCU_CLK_GATING__CTRL = 0x04D8, | 
| jvfausto | 0:76ea242a637f | 625 | TEST__BIST_ROM_CTRL = 0x04E0, | 
| jvfausto | 0:76ea242a637f | 626 | TEST__BIST_ROM_RESULT = 0x04E1, | 
| jvfausto | 0:76ea242a637f | 627 | TEST__BIST_ROM_MCU_SIG = 0x04E2, | 
| jvfausto | 0:76ea242a637f | 628 | TEST__BIST_ROM_MCU_SIG_HI = 0x04E2, | 
| jvfausto | 0:76ea242a637f | 629 | TEST__BIST_ROM_MCU_SIG_LO = 0x04E3, | 
| jvfausto | 0:76ea242a637f | 630 | TEST__BIST_RAM_CTRL = 0x04E4, | 
| jvfausto | 0:76ea242a637f | 631 | TEST__BIST_RAM_RESULT = 0x04E5, | 
| jvfausto | 0:76ea242a637f | 632 | TEST__TMC = 0x04E8, | 
| jvfausto | 0:76ea242a637f | 633 | TEST__PLL_BIST_MIN_THRESHOLD = 0x04F0, | 
| jvfausto | 0:76ea242a637f | 634 | TEST__PLL_BIST_MIN_THRESHOLD_HI = 0x04F0, | 
| jvfausto | 0:76ea242a637f | 635 | TEST__PLL_BIST_MIN_THRESHOLD_LO = 0x04F1, | 
| jvfausto | 0:76ea242a637f | 636 | TEST__PLL_BIST_MAX_THRESHOLD = 0x04F2, | 
| jvfausto | 0:76ea242a637f | 637 | TEST__PLL_BIST_MAX_THRESHOLD_HI = 0x04F2, | 
| jvfausto | 0:76ea242a637f | 638 | TEST__PLL_BIST_MAX_THRESHOLD_LO = 0x04F3, | 
| jvfausto | 0:76ea242a637f | 639 | TEST__PLL_BIST_COUNT_OUT = 0x04F4, | 
| jvfausto | 0:76ea242a637f | 640 | TEST__PLL_BIST_COUNT_OUT_HI = 0x04F4, | 
| jvfausto | 0:76ea242a637f | 641 | TEST__PLL_BIST_COUNT_OUT_LO = 0x04F5, | 
| jvfausto | 0:76ea242a637f | 642 | TEST__PLL_BIST_GONOGO = 0x04F6, | 
| jvfausto | 0:76ea242a637f | 643 | TEST__PLL_BIST_CTRL = 0x04F7, | 
| jvfausto | 0:76ea242a637f | 644 | RANGING_CORE__DEVICE_ID = 0x0680, | 
| jvfausto | 0:76ea242a637f | 645 | RANGING_CORE__REVISION_ID = 0x0681, | 
| jvfausto | 0:76ea242a637f | 646 | RANGING_CORE__CLK_CTRL1 = 0x0683, | 
| jvfausto | 0:76ea242a637f | 647 | RANGING_CORE__CLK_CTRL2 = 0x0684, | 
| jvfausto | 0:76ea242a637f | 648 | RANGING_CORE__WOI_1 = 0x0685, | 
| jvfausto | 0:76ea242a637f | 649 | RANGING_CORE__WOI_REF_1 = 0x0686, | 
| jvfausto | 0:76ea242a637f | 650 | RANGING_CORE__START_RANGING = 0x0687, | 
| jvfausto | 0:76ea242a637f | 651 | RANGING_CORE__LOW_LIMIT_1 = 0x0690, | 
| jvfausto | 0:76ea242a637f | 652 | RANGING_CORE__HIGH_LIMIT_1 = 0x0691, | 
| jvfausto | 0:76ea242a637f | 653 | RANGING_CORE__LOW_LIMIT_REF_1 = 0x0692, | 
| jvfausto | 0:76ea242a637f | 654 | RANGING_CORE__HIGH_LIMIT_REF_1 = 0x0693, | 
| jvfausto | 0:76ea242a637f | 655 | RANGING_CORE__QUANTIFIER_1_MSB = 0x0694, | 
| jvfausto | 0:76ea242a637f | 656 | RANGING_CORE__QUANTIFIER_1_LSB = 0x0695, | 
| jvfausto | 0:76ea242a637f | 657 | RANGING_CORE__QUANTIFIER_REF_1_MSB = 0x0696, | 
| jvfausto | 0:76ea242a637f | 658 | RANGING_CORE__QUANTIFIER_REF_1_LSB = 0x0697, | 
| jvfausto | 0:76ea242a637f | 659 | RANGING_CORE__AMBIENT_OFFSET_1_MSB = 0x0698, | 
| jvfausto | 0:76ea242a637f | 660 | RANGING_CORE__AMBIENT_OFFSET_1_LSB = 0x0699, | 
| jvfausto | 0:76ea242a637f | 661 | RANGING_CORE__AMBIENT_OFFSET_REF_1_MSB = 0x069A, | 
| jvfausto | 0:76ea242a637f | 662 | RANGING_CORE__AMBIENT_OFFSET_REF_1_LSB = 0x069B, | 
| jvfausto | 0:76ea242a637f | 663 | RANGING_CORE__FILTER_STRENGTH_1 = 0x069C, | 
| jvfausto | 0:76ea242a637f | 664 | RANGING_CORE__FILTER_STRENGTH_REF_1 = 0x069D, | 
| jvfausto | 0:76ea242a637f | 665 | RANGING_CORE__SIGNAL_EVENT_LIMIT_1_MSB = 0x069E, | 
| jvfausto | 0:76ea242a637f | 666 | RANGING_CORE__SIGNAL_EVENT_LIMIT_1_LSB = 0x069F, | 
| jvfausto | 0:76ea242a637f | 667 | RANGING_CORE__SIGNAL_EVENT_LIMIT_REF_1_MSB = 0x06A0, | 
| jvfausto | 0:76ea242a637f | 668 | RANGING_CORE__SIGNAL_EVENT_LIMIT_REF_1_LSB = 0x06A1, | 
| jvfausto | 0:76ea242a637f | 669 | RANGING_CORE__TIMEOUT_OVERALL_PERIODS_MSB = 0x06A4, | 
| jvfausto | 0:76ea242a637f | 670 | RANGING_CORE__TIMEOUT_OVERALL_PERIODS_LSB = 0x06A5, | 
| jvfausto | 0:76ea242a637f | 671 | RANGING_CORE__INVERT_HW = 0x06A6, | 
| jvfausto | 0:76ea242a637f | 672 | RANGING_CORE__FORCE_HW = 0x06A7, | 
| jvfausto | 0:76ea242a637f | 673 | RANGING_CORE__STATIC_HW_VALUE = 0x06A8, | 
| jvfausto | 0:76ea242a637f | 674 | RANGING_CORE__FORCE_CONTINUOUS_AMBIENT = 0x06A9, | 
| jvfausto | 0:76ea242a637f | 675 | RANGING_CORE__TEST_PHASE_SELECT_TO_FILTER = 0x06AA, | 
| jvfausto | 0:76ea242a637f | 676 | RANGING_CORE__TEST_PHASE_SELECT_TO_TIMING_GEN = 0x06AB, | 
| jvfausto | 0:76ea242a637f | 677 | RANGING_CORE__INITIAL_PHASE_VALUE_1 = 0x06AC, | 
| jvfausto | 0:76ea242a637f | 678 | RANGING_CORE__INITIAL_PHASE_VALUE_REF_1 = 0x06AD, | 
| jvfausto | 0:76ea242a637f | 679 | RANGING_CORE__FORCE_UP_IN = 0x06AE, | 
| jvfausto | 0:76ea242a637f | 680 | RANGING_CORE__FORCE_DN_IN = 0x06AF, | 
| jvfausto | 0:76ea242a637f | 681 | RANGING_CORE__STATIC_UP_VALUE_1 = 0x06B0, | 
| jvfausto | 0:76ea242a637f | 682 | RANGING_CORE__STATIC_UP_VALUE_REF_1 = 0x06B1, | 
| jvfausto | 0:76ea242a637f | 683 | RANGING_CORE__STATIC_DN_VALUE_1 = 0x06B2, | 
| jvfausto | 0:76ea242a637f | 684 | RANGING_CORE__STATIC_DN_VALUE_REF_1 = 0x06B3, | 
| jvfausto | 0:76ea242a637f | 685 | RANGING_CORE__MONITOR_UP_DN = 0x06B4, | 
| jvfausto | 0:76ea242a637f | 686 | RANGING_CORE__INVERT_UP_DN = 0x06B5, | 
| jvfausto | 0:76ea242a637f | 687 | RANGING_CORE__CPUMP_1 = 0x06B6, | 
| jvfausto | 0:76ea242a637f | 688 | RANGING_CORE__CPUMP_2 = 0x06B7, | 
| jvfausto | 0:76ea242a637f | 689 | RANGING_CORE__CPUMP_3 = 0x06B8, | 
| jvfausto | 0:76ea242a637f | 690 | RANGING_CORE__OSC_1 = 0x06B9, | 
| jvfausto | 0:76ea242a637f | 691 | RANGING_CORE__PLL_1 = 0x06BB, | 
| jvfausto | 0:76ea242a637f | 692 | RANGING_CORE__PLL_2 = 0x06BC, | 
| jvfausto | 0:76ea242a637f | 693 | RANGING_CORE__REFERENCE_1 = 0x06BD, | 
| jvfausto | 0:76ea242a637f | 694 | RANGING_CORE__REFERENCE_3 = 0x06BF, | 
| jvfausto | 0:76ea242a637f | 695 | RANGING_CORE__REFERENCE_4 = 0x06C0, | 
| jvfausto | 0:76ea242a637f | 696 | RANGING_CORE__REFERENCE_5 = 0x06C1, | 
| jvfausto | 0:76ea242a637f | 697 | RANGING_CORE__REGAVDD1V2 = 0x06C3, | 
| jvfausto | 0:76ea242a637f | 698 | RANGING_CORE__CALIB_1 = 0x06C4, | 
| jvfausto | 0:76ea242a637f | 699 | RANGING_CORE__CALIB_2 = 0x06C5, | 
| jvfausto | 0:76ea242a637f | 700 | RANGING_CORE__CALIB_3 = 0x06C6, | 
| jvfausto | 0:76ea242a637f | 701 | RANGING_CORE__TST_MUX_SEL1 = 0x06C9, | 
| jvfausto | 0:76ea242a637f | 702 | RANGING_CORE__TST_MUX_SEL2 = 0x06CA, | 
| jvfausto | 0:76ea242a637f | 703 | RANGING_CORE__TST_MUX = 0x06CB, | 
| jvfausto | 0:76ea242a637f | 704 | RANGING_CORE__GPIO_OUT_TESTMUX = 0x06CC, | 
| jvfausto | 0:76ea242a637f | 705 | RANGING_CORE__CUSTOM_FE = 0x06CD, | 
| jvfausto | 0:76ea242a637f | 706 | RANGING_CORE__CUSTOM_FE_2 = 0x06CE, | 
| jvfausto | 0:76ea242a637f | 707 | RANGING_CORE__SPAD_READOUT = 0x06CF, | 
| jvfausto | 0:76ea242a637f | 708 | RANGING_CORE__SPAD_READOUT_1 = 0x06D0, | 
| jvfausto | 0:76ea242a637f | 709 | RANGING_CORE__SPAD_READOUT_2 = 0x06D1, | 
| jvfausto | 0:76ea242a637f | 710 | RANGING_CORE__SPAD_PS = 0x06D2, | 
| jvfausto | 0:76ea242a637f | 711 | RANGING_CORE__LASER_SAFETY_2 = 0x06D4, | 
| jvfausto | 0:76ea242a637f | 712 | RANGING_CORE__NVM_CTRL__MODE = 0x0780, | 
| jvfausto | 0:76ea242a637f | 713 | RANGING_CORE__NVM_CTRL__PDN = 0x0781, | 
| jvfausto | 0:76ea242a637f | 714 | RANGING_CORE__NVM_CTRL__PROGN = 0x0782, | 
| jvfausto | 0:76ea242a637f | 715 | RANGING_CORE__NVM_CTRL__READN = 0x0783, | 
| jvfausto | 0:76ea242a637f | 716 | RANGING_CORE__NVM_CTRL__PULSE_WIDTH_MSB = 0x0784, | 
| jvfausto | 0:76ea242a637f | 717 | RANGING_CORE__NVM_CTRL__PULSE_WIDTH_LSB = 0x0785, | 
| jvfausto | 0:76ea242a637f | 718 | RANGING_CORE__NVM_CTRL__HV_RISE_MSB = 0x0786, | 
| jvfausto | 0:76ea242a637f | 719 | RANGING_CORE__NVM_CTRL__HV_RISE_LSB = 0x0787, | 
| jvfausto | 0:76ea242a637f | 720 | RANGING_CORE__NVM_CTRL__HV_FALL_MSB = 0x0788, | 
| jvfausto | 0:76ea242a637f | 721 | RANGING_CORE__NVM_CTRL__HV_FALL_LSB = 0x0789, | 
| jvfausto | 0:76ea242a637f | 722 | RANGING_CORE__NVM_CTRL__TST = 0x078A, | 
| jvfausto | 0:76ea242a637f | 723 | RANGING_CORE__NVM_CTRL__TESTREAD = 0x078B, | 
| jvfausto | 0:76ea242a637f | 724 | RANGING_CORE__NVM_CTRL__DATAIN_MMM = 0x078C, | 
| jvfausto | 0:76ea242a637f | 725 | RANGING_CORE__NVM_CTRL__DATAIN_LMM = 0x078D, | 
| jvfausto | 0:76ea242a637f | 726 | RANGING_CORE__NVM_CTRL__DATAIN_LLM = 0x078E, | 
| jvfausto | 0:76ea242a637f | 727 | RANGING_CORE__NVM_CTRL__DATAIN_LLL = 0x078F, | 
| jvfausto | 0:76ea242a637f | 728 | RANGING_CORE__NVM_CTRL__DATAOUT_MMM = 0x0790, | 
| jvfausto | 0:76ea242a637f | 729 | RANGING_CORE__NVM_CTRL__DATAOUT_LMM = 0x0791, | 
| jvfausto | 0:76ea242a637f | 730 | RANGING_CORE__NVM_CTRL__DATAOUT_LLM = 0x0792, | 
| jvfausto | 0:76ea242a637f | 731 | RANGING_CORE__NVM_CTRL__DATAOUT_LLL = 0x0793, | 
| jvfausto | 0:76ea242a637f | 732 | RANGING_CORE__NVM_CTRL__ADDR = 0x0794, | 
| jvfausto | 0:76ea242a637f | 733 | RANGING_CORE__NVM_CTRL__DATAOUT_ECC = 0x0795, | 
| jvfausto | 0:76ea242a637f | 734 | RANGING_CORE__RET_SPAD_EN_0 = 0x0796, | 
| jvfausto | 0:76ea242a637f | 735 | RANGING_CORE__RET_SPAD_EN_1 = 0x0797, | 
| jvfausto | 0:76ea242a637f | 736 | RANGING_CORE__RET_SPAD_EN_2 = 0x0798, | 
| jvfausto | 0:76ea242a637f | 737 | RANGING_CORE__RET_SPAD_EN_3 = 0x0799, | 
| jvfausto | 0:76ea242a637f | 738 | RANGING_CORE__RET_SPAD_EN_4 = 0x079A, | 
| jvfausto | 0:76ea242a637f | 739 | RANGING_CORE__RET_SPAD_EN_5 = 0x079B, | 
| jvfausto | 0:76ea242a637f | 740 | RANGING_CORE__RET_SPAD_EN_6 = 0x079C, | 
| jvfausto | 0:76ea242a637f | 741 | RANGING_CORE__RET_SPAD_EN_7 = 0x079D, | 
| jvfausto | 0:76ea242a637f | 742 | RANGING_CORE__RET_SPAD_EN_8 = 0x079E, | 
| jvfausto | 0:76ea242a637f | 743 | RANGING_CORE__RET_SPAD_EN_9 = 0x079F, | 
| jvfausto | 0:76ea242a637f | 744 | RANGING_CORE__RET_SPAD_EN_10 = 0x07A0, | 
| jvfausto | 0:76ea242a637f | 745 | RANGING_CORE__RET_SPAD_EN_11 = 0x07A1, | 
| jvfausto | 0:76ea242a637f | 746 | RANGING_CORE__RET_SPAD_EN_12 = 0x07A2, | 
| jvfausto | 0:76ea242a637f | 747 | RANGING_CORE__RET_SPAD_EN_13 = 0x07A3, | 
| jvfausto | 0:76ea242a637f | 748 | RANGING_CORE__RET_SPAD_EN_14 = 0x07A4, | 
| jvfausto | 0:76ea242a637f | 749 | RANGING_CORE__RET_SPAD_EN_15 = 0x07A5, | 
| jvfausto | 0:76ea242a637f | 750 | RANGING_CORE__RET_SPAD_EN_16 = 0x07A6, | 
| jvfausto | 0:76ea242a637f | 751 | RANGING_CORE__RET_SPAD_EN_17 = 0x07A7, | 
| jvfausto | 0:76ea242a637f | 752 | RANGING_CORE__SPAD_SHIFT_EN = 0x07BA, | 
| jvfausto | 0:76ea242a637f | 753 | RANGING_CORE__SPAD_DISABLE_CTRL = 0x07BB, | 
| jvfausto | 0:76ea242a637f | 754 | RANGING_CORE__SPAD_EN_SHIFT_OUT_DEBUG = 0x07BC, | 
| jvfausto | 0:76ea242a637f | 755 | RANGING_CORE__SPI_MODE = 0x07BD, | 
| jvfausto | 0:76ea242a637f | 756 | RANGING_CORE__GPIO_DIR = 0x07BE, | 
| jvfausto | 0:76ea242a637f | 757 | RANGING_CORE__VCSEL_PERIOD = 0x0880, | 
| jvfausto | 0:76ea242a637f | 758 | RANGING_CORE__VCSEL_START = 0x0881, | 
| jvfausto | 0:76ea242a637f | 759 | RANGING_CORE__VCSEL_STOP = 0x0882, | 
| jvfausto | 0:76ea242a637f | 760 | RANGING_CORE__VCSEL_1 = 0x0885, | 
| jvfausto | 0:76ea242a637f | 761 | RANGING_CORE__VCSEL_STATUS = 0x088D, | 
| jvfausto | 0:76ea242a637f | 762 | RANGING_CORE__STATUS = 0x0980, | 
| jvfausto | 0:76ea242a637f | 763 | RANGING_CORE__LASER_CONTINUITY_STATE = 0x0981, | 
| jvfausto | 0:76ea242a637f | 764 | RANGING_CORE__RANGE_1_MMM = 0x0982, | 
| jvfausto | 0:76ea242a637f | 765 | RANGING_CORE__RANGE_1_LMM = 0x0983, | 
| jvfausto | 0:76ea242a637f | 766 | RANGING_CORE__RANGE_1_LLM = 0x0984, | 
| jvfausto | 0:76ea242a637f | 767 | RANGING_CORE__RANGE_1_LLL = 0x0985, | 
| jvfausto | 0:76ea242a637f | 768 | RANGING_CORE__RANGE_REF_1_MMM = 0x0986, | 
| jvfausto | 0:76ea242a637f | 769 | RANGING_CORE__RANGE_REF_1_LMM = 0x0987, | 
| jvfausto | 0:76ea242a637f | 770 | RANGING_CORE__RANGE_REF_1_LLM = 0x0988, | 
| jvfausto | 0:76ea242a637f | 771 | RANGING_CORE__RANGE_REF_1_LLL = 0x0989, | 
| jvfausto | 0:76ea242a637f | 772 | RANGING_CORE__AMBIENT_WINDOW_EVENTS_1_MMM = 0x098A, | 
| jvfausto | 0:76ea242a637f | 773 | RANGING_CORE__AMBIENT_WINDOW_EVENTS_1_LMM = 0x098B, | 
| jvfausto | 0:76ea242a637f | 774 | RANGING_CORE__AMBIENT_WINDOW_EVENTS_1_LLM = 0x098C, | 
| jvfausto | 0:76ea242a637f | 775 | RANGING_CORE__AMBIENT_WINDOW_EVENTS_1_LLL = 0x098D, | 
| jvfausto | 0:76ea242a637f | 776 | RANGING_CORE__RANGING_TOTAL_EVENTS_1_MMM = 0x098E, | 
| jvfausto | 0:76ea242a637f | 777 | RANGING_CORE__RANGING_TOTAL_EVENTS_1_LMM = 0x098F, | 
| jvfausto | 0:76ea242a637f | 778 | RANGING_CORE__RANGING_TOTAL_EVENTS_1_LLM = 0x0990, | 
| jvfausto | 0:76ea242a637f | 779 | RANGING_CORE__RANGING_TOTAL_EVENTS_1_LLL = 0x0991, | 
| jvfausto | 0:76ea242a637f | 780 | RANGING_CORE__SIGNAL_TOTAL_EVENTS_1_MMM = 0x0992, | 
| jvfausto | 0:76ea242a637f | 781 | RANGING_CORE__SIGNAL_TOTAL_EVENTS_1_LMM = 0x0993, | 
| jvfausto | 0:76ea242a637f | 782 | RANGING_CORE__SIGNAL_TOTAL_EVENTS_1_LLM = 0x0994, | 
| jvfausto | 0:76ea242a637f | 783 | RANGING_CORE__SIGNAL_TOTAL_EVENTS_1_LLL = 0x0995, | 
| jvfausto | 0:76ea242a637f | 784 | RANGING_CORE__TOTAL_PERIODS_ELAPSED_1_MM = 0x0996, | 
| jvfausto | 0:76ea242a637f | 785 | RANGING_CORE__TOTAL_PERIODS_ELAPSED_1_LM = 0x0997, | 
| jvfausto | 0:76ea242a637f | 786 | RANGING_CORE__TOTAL_PERIODS_ELAPSED_1_LL = 0x0998, | 
| jvfausto | 0:76ea242a637f | 787 | RANGING_CORE__AMBIENT_MISMATCH_MM = 0x0999, | 
| jvfausto | 0:76ea242a637f | 788 | RANGING_CORE__AMBIENT_MISMATCH_LM = 0x099A, | 
| jvfausto | 0:76ea242a637f | 789 | RANGING_CORE__AMBIENT_MISMATCH_LL = 0x099B, | 
| jvfausto | 0:76ea242a637f | 790 | RANGING_CORE__AMBIENT_WINDOW_EVENTS_REF_1_MMM = 0x099C, | 
| jvfausto | 0:76ea242a637f | 791 | RANGING_CORE__AMBIENT_WINDOW_EVENTS_REF_1_LMM = 0x099D, | 
| jvfausto | 0:76ea242a637f | 792 | RANGING_CORE__AMBIENT_WINDOW_EVENTS_REF_1_LLM = 0x099E, | 
| jvfausto | 0:76ea242a637f | 793 | RANGING_CORE__AMBIENT_WINDOW_EVENTS_REF_1_LLL = 0x099F, | 
| jvfausto | 0:76ea242a637f | 794 | RANGING_CORE__RANGING_TOTAL_EVENTS_REF_1_MMM = 0x09A0, | 
| jvfausto | 0:76ea242a637f | 795 | RANGING_CORE__RANGING_TOTAL_EVENTS_REF_1_LMM = 0x09A1, | 
| jvfausto | 0:76ea242a637f | 796 | RANGING_CORE__RANGING_TOTAL_EVENTS_REF_1_LLM = 0x09A2, | 
| jvfausto | 0:76ea242a637f | 797 | RANGING_CORE__RANGING_TOTAL_EVENTS_REF_1_LLL = 0x09A3, | 
| jvfausto | 0:76ea242a637f | 798 | RANGING_CORE__SIGNAL_TOTAL_EVENTS_REF_1_MMM = 0x09A4, | 
| jvfausto | 0:76ea242a637f | 799 | RANGING_CORE__SIGNAL_TOTAL_EVENTS_REF_1_LMM = 0x09A5, | 
| jvfausto | 0:76ea242a637f | 800 | RANGING_CORE__SIGNAL_TOTAL_EVENTS_REF_1_LLM = 0x09A6, | 
| jvfausto | 0:76ea242a637f | 801 | RANGING_CORE__SIGNAL_TOTAL_EVENTS_REF_1_LLL = 0x09A7, | 
| jvfausto | 0:76ea242a637f | 802 | RANGING_CORE__TOTAL_PERIODS_ELAPSED_REF_1_MM = 0x09A8, | 
| jvfausto | 0:76ea242a637f | 803 | RANGING_CORE__TOTAL_PERIODS_ELAPSED_REF_1_LM = 0x09A9, | 
| jvfausto | 0:76ea242a637f | 804 | RANGING_CORE__TOTAL_PERIODS_ELAPSED_REF_1_LL = 0x09AA, | 
| jvfausto | 0:76ea242a637f | 805 | RANGING_CORE__AMBIENT_MISMATCH_REF_MM = 0x09AB, | 
| jvfausto | 0:76ea242a637f | 806 | RANGING_CORE__AMBIENT_MISMATCH_REF_LM = 0x09AC, | 
| jvfausto | 0:76ea242a637f | 807 | RANGING_CORE__AMBIENT_MISMATCH_REF_LL = 0x09AD, | 
| jvfausto | 0:76ea242a637f | 808 | RANGING_CORE__GPIO_CONFIG__A0 = 0x0A00, | 
| jvfausto | 0:76ea242a637f | 809 | RANGING_CORE__RESET_CONTROL__A0 = 0x0A01, | 
| jvfausto | 0:76ea242a637f | 810 | RANGING_CORE__INTR_MANAGER__A0 = 0x0A02, | 
| jvfausto | 0:76ea242a637f | 811 | RANGING_CORE__POWER_FSM_TIME_OSC__A0 = 0x0A06, | 
| jvfausto | 0:76ea242a637f | 812 | RANGING_CORE__VCSEL_ATEST__A0 = 0x0A07, | 
| jvfausto | 0:76ea242a637f | 813 | RANGING_CORE__VCSEL_PERIOD_CLIPPED__A0 = 0x0A08, | 
| jvfausto | 0:76ea242a637f | 814 | RANGING_CORE__VCSEL_STOP_CLIPPED__A0 = 0x0A09, | 
| jvfausto | 0:76ea242a637f | 815 | RANGING_CORE__CALIB_2__A0 = 0x0A0A, | 
| jvfausto | 0:76ea242a637f | 816 | RANGING_CORE__STOP_CONDITION__A0 = 0x0A0B, | 
| jvfausto | 0:76ea242a637f | 817 | RANGING_CORE__STATUS_RESET__A0 = 0x0A0C, | 
| jvfausto | 0:76ea242a637f | 818 | RANGING_CORE__READOUT_CFG__A0 = 0x0A0D, | 
| jvfausto | 0:76ea242a637f | 819 | RANGING_CORE__WINDOW_SETTING__A0 = 0x0A0E, | 
| jvfausto | 0:76ea242a637f | 820 | RANGING_CORE__VCSEL_DELAY__A0 = 0x0A1A, | 
| jvfausto | 0:76ea242a637f | 821 | RANGING_CORE__REFERENCE_2__A0 = 0x0A1B, | 
| jvfausto | 0:76ea242a637f | 822 | RANGING_CORE__REGAVDD1V2__A0 = 0x0A1D, | 
| jvfausto | 0:76ea242a637f | 823 | RANGING_CORE__TST_MUX__A0 = 0x0A1F, | 
| jvfausto | 0:76ea242a637f | 824 | RANGING_CORE__CUSTOM_FE_2__A0 = 0x0A20, | 
| jvfausto | 0:76ea242a637f | 825 | RANGING_CORE__SPAD_READOUT__A0 = 0x0A21, | 
| jvfausto | 0:76ea242a637f | 826 | RANGING_CORE__CPUMP_1__A0 = 0x0A22, | 
| jvfausto | 0:76ea242a637f | 827 | RANGING_CORE__SPARE_REGISTER__A0 = 0x0A23, | 
| jvfausto | 0:76ea242a637f | 828 | RANGING_CORE__VCSEL_CONT_STAGE5_BYPASS__A0 = 0x0A24, | 
| jvfausto | 0:76ea242a637f | 829 | RANGING_CORE__RET_SPAD_EN_18 = 0x0A25, | 
| jvfausto | 0:76ea242a637f | 830 | RANGING_CORE__RET_SPAD_EN_19 = 0x0A26, | 
| jvfausto | 0:76ea242a637f | 831 | RANGING_CORE__RET_SPAD_EN_20 = 0x0A27, | 
| jvfausto | 0:76ea242a637f | 832 | RANGING_CORE__RET_SPAD_EN_21 = 0x0A28, | 
| jvfausto | 0:76ea242a637f | 833 | RANGING_CORE__RET_SPAD_EN_22 = 0x0A29, | 
| jvfausto | 0:76ea242a637f | 834 | RANGING_CORE__RET_SPAD_EN_23 = 0x0A2A, | 
| jvfausto | 0:76ea242a637f | 835 | RANGING_CORE__RET_SPAD_EN_24 = 0x0A2B, | 
| jvfausto | 0:76ea242a637f | 836 | RANGING_CORE__RET_SPAD_EN_25 = 0x0A2C, | 
| jvfausto | 0:76ea242a637f | 837 | RANGING_CORE__RET_SPAD_EN_26 = 0x0A2D, | 
| jvfausto | 0:76ea242a637f | 838 | RANGING_CORE__RET_SPAD_EN_27 = 0x0A2E, | 
| jvfausto | 0:76ea242a637f | 839 | RANGING_CORE__RET_SPAD_EN_28 = 0x0A2F, | 
| jvfausto | 0:76ea242a637f | 840 | RANGING_CORE__RET_SPAD_EN_29 = 0x0A30, | 
| jvfausto | 0:76ea242a637f | 841 | RANGING_CORE__RET_SPAD_EN_30 = 0x0A31, | 
| jvfausto | 0:76ea242a637f | 842 | RANGING_CORE__RET_SPAD_EN_31 = 0x0A32, | 
| jvfausto | 0:76ea242a637f | 843 | RANGING_CORE__REF_SPAD_EN_0__EWOK = 0x0A33, | 
| jvfausto | 0:76ea242a637f | 844 | RANGING_CORE__REF_SPAD_EN_1__EWOK = 0x0A34, | 
| jvfausto | 0:76ea242a637f | 845 | RANGING_CORE__REF_SPAD_EN_2__EWOK = 0x0A35, | 
| jvfausto | 0:76ea242a637f | 846 | RANGING_CORE__REF_SPAD_EN_3__EWOK = 0x0A36, | 
| jvfausto | 0:76ea242a637f | 847 | RANGING_CORE__REF_SPAD_EN_4__EWOK = 0x0A37, | 
| jvfausto | 0:76ea242a637f | 848 | RANGING_CORE__REF_SPAD_EN_5__EWOK = 0x0A38, | 
| jvfausto | 0:76ea242a637f | 849 | RANGING_CORE__REF_EN_START_SELECT = 0x0A39, | 
| jvfausto | 0:76ea242a637f | 850 | RANGING_CORE__REGDVDD1V2_ATEST__EWOK = 0x0A41, | 
| jvfausto | 0:76ea242a637f | 851 | SOFT_RESET_GO1 = 0x0B00, | 
| jvfausto | 0:76ea242a637f | 852 | PRIVATE__PATCH_BASE_ADDR_RSLV = 0x0E00, | 
| jvfausto | 0:76ea242a637f | 853 | PREV_SHADOW_RESULT__INTERRUPT_STATUS = 0x0ED0, | 
| jvfausto | 0:76ea242a637f | 854 | PREV_SHADOW_RESULT__RANGE_STATUS = 0x0ED1, | 
| jvfausto | 0:76ea242a637f | 855 | PREV_SHADOW_RESULT__REPORT_STATUS = 0x0ED2, | 
| jvfausto | 0:76ea242a637f | 856 | PREV_SHADOW_RESULT__STREAM_COUNT = 0x0ED3, | 
| jvfausto | 0:76ea242a637f | 857 | PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0 = 0x0ED4, | 
| jvfausto | 0:76ea242a637f | 858 | PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_HI = 0x0ED4, | 
| jvfausto | 0:76ea242a637f | 859 | PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_LO = 0x0ED5, | 
| jvfausto | 0:76ea242a637f | 860 | PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0 = 0x0ED6, | 
| jvfausto | 0:76ea242a637f | 861 | PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_HI = 0x0ED6, | 
| jvfausto | 0:76ea242a637f | 862 | PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_LO = 0x0ED7, | 
| jvfausto | 0:76ea242a637f | 863 | PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0 = 0x0ED8, | 
| jvfausto | 0:76ea242a637f | 864 | PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_HI = 0x0ED8, | 
| jvfausto | 0:76ea242a637f | 865 | PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_LO = 0x0ED9, | 
| jvfausto | 0:76ea242a637f | 866 | PREV_SHADOW_RESULT__SIGMA_SD0 = 0x0EDA, | 
| jvfausto | 0:76ea242a637f | 867 | PREV_SHADOW_RESULT__SIGMA_SD0_HI = 0x0EDA, | 
| jvfausto | 0:76ea242a637f | 868 | PREV_SHADOW_RESULT__SIGMA_SD0_LO = 0x0EDB, | 
| jvfausto | 0:76ea242a637f | 869 | PREV_SHADOW_RESULT__PHASE_SD0 = 0x0EDC, | 
| jvfausto | 0:76ea242a637f | 870 | PREV_SHADOW_RESULT__PHASE_SD0_HI = 0x0EDC, | 
| jvfausto | 0:76ea242a637f | 871 | PREV_SHADOW_RESULT__PHASE_SD0_LO = 0x0EDD, | 
| jvfausto | 0:76ea242a637f | 872 | PREV_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0 = 0x0EDE, | 
| jvfausto | 0:76ea242a637f | 873 | PREV_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_HI = 0x0EDE, | 
| jvfausto | 0:76ea242a637f | 874 | PREV_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_LO = 0x0EDF, | 
| jvfausto | 0:76ea242a637f | 875 | PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0 = 0x0EE0, | 
| jvfausto | 0:76ea242a637f | 876 | PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_HI = 0x0EE0, | 
| jvfausto | 0:76ea242a637f | 877 | PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_LO = 0x0EE1, | 
| jvfausto | 0:76ea242a637f | 878 | PREV_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0 = 0x0EE2, | 
| jvfausto | 0:76ea242a637f | 879 | PREV_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_HI = 0x0EE2, | 
| jvfausto | 0:76ea242a637f | 880 | PREV_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_LO = 0x0EE3, | 
| jvfausto | 0:76ea242a637f | 881 | PREV_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0 = 0x0EE4, | 
| jvfausto | 0:76ea242a637f | 882 | PREV_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_HI = 0x0EE4, | 
| jvfausto | 0:76ea242a637f | 883 | PREV_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_LO = 0x0EE5, | 
| jvfausto | 0:76ea242a637f | 884 | PREV_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0 = 0x0EE6, | 
| jvfausto | 0:76ea242a637f | 885 | PREV_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_HI = 0x0EE6, | 
| jvfausto | 0:76ea242a637f | 886 | PREV_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_LO = 0x0EE7, | 
| jvfausto | 0:76ea242a637f | 887 | PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1 = 0x0EE8, | 
| jvfausto | 0:76ea242a637f | 888 | PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_HI = 0x0EE8, | 
| jvfausto | 0:76ea242a637f | 889 | PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_LO = 0x0EE9, | 
| jvfausto | 0:76ea242a637f | 890 | PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1 = 0x0EEA, | 
| jvfausto | 0:76ea242a637f | 891 | PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_HI = 0x0EEA, | 
| jvfausto | 0:76ea242a637f | 892 | PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_LO = 0x0EEB, | 
| jvfausto | 0:76ea242a637f | 893 | PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1 = 0x0EEC, | 
| jvfausto | 0:76ea242a637f | 894 | PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_HI = 0x0EEC, | 
| jvfausto | 0:76ea242a637f | 895 | PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_LO = 0x0EED, | 
| jvfausto | 0:76ea242a637f | 896 | PREV_SHADOW_RESULT__SIGMA_SD1 = 0x0EEE, | 
| jvfausto | 0:76ea242a637f | 897 | PREV_SHADOW_RESULT__SIGMA_SD1_HI = 0x0EEE, | 
| jvfausto | 0:76ea242a637f | 898 | PREV_SHADOW_RESULT__SIGMA_SD1_LO = 0x0EEF, | 
| jvfausto | 0:76ea242a637f | 899 | PREV_SHADOW_RESULT__PHASE_SD1 = 0x0EF0, | 
| jvfausto | 0:76ea242a637f | 900 | PREV_SHADOW_RESULT__PHASE_SD1_HI = 0x0EF0, | 
| jvfausto | 0:76ea242a637f | 901 | PREV_SHADOW_RESULT__PHASE_SD1_LO = 0x0EF1, | 
| jvfausto | 0:76ea242a637f | 902 | PREV_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1 = 0x0EF2, | 
| jvfausto | 0:76ea242a637f | 903 | PREV_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_HI = 0x0EF2, | 
| jvfausto | 0:76ea242a637f | 904 | PREV_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_LO = 0x0EF3, | 
| jvfausto | 0:76ea242a637f | 905 | PREV_SHADOW_RESULT__SPARE_0_SD1 = 0x0EF4, | 
| jvfausto | 0:76ea242a637f | 906 | PREV_SHADOW_RESULT__SPARE_0_SD1_HI = 0x0EF4, | 
| jvfausto | 0:76ea242a637f | 907 | PREV_SHADOW_RESULT__SPARE_0_SD1_LO = 0x0EF5, | 
| jvfausto | 0:76ea242a637f | 908 | PREV_SHADOW_RESULT__SPARE_1_SD1 = 0x0EF6, | 
| jvfausto | 0:76ea242a637f | 909 | PREV_SHADOW_RESULT__SPARE_1_SD1_HI = 0x0EF6, | 
| jvfausto | 0:76ea242a637f | 910 | PREV_SHADOW_RESULT__SPARE_1_SD1_LO = 0x0EF7, | 
| jvfausto | 0:76ea242a637f | 911 | PREV_SHADOW_RESULT__SPARE_2_SD1 = 0x0EF8, | 
| jvfausto | 0:76ea242a637f | 912 | PREV_SHADOW_RESULT__SPARE_2_SD1_HI = 0x0EF8, | 
| jvfausto | 0:76ea242a637f | 913 | PREV_SHADOW_RESULT__SPARE_2_SD1_LO = 0x0EF9, | 
| jvfausto | 0:76ea242a637f | 914 | PREV_SHADOW_RESULT__SPARE_3_SD1 = 0x0EFA, | 
| jvfausto | 0:76ea242a637f | 915 | PREV_SHADOW_RESULT__SPARE_3_SD1_HI = 0x0EFA, | 
| jvfausto | 0:76ea242a637f | 916 | PREV_SHADOW_RESULT__SPARE_3_SD1_LO = 0x0EFB, | 
| jvfausto | 0:76ea242a637f | 917 | PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0 = 0x0EFC, | 
| jvfausto | 0:76ea242a637f | 918 | PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_3 = 0x0EFC, | 
| jvfausto | 0:76ea242a637f | 919 | PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_2 = 0x0EFD, | 
| jvfausto | 0:76ea242a637f | 920 | PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_1 = 0x0EFE, | 
| jvfausto | 0:76ea242a637f | 921 | PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_0 = 0x0EFF, | 
| jvfausto | 0:76ea242a637f | 922 | PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0 = 0x0F00, | 
| jvfausto | 0:76ea242a637f | 923 | PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_3 = 0x0F00, | 
| jvfausto | 0:76ea242a637f | 924 | PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_2 = 0x0F01, | 
| jvfausto | 0:76ea242a637f | 925 | PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_1 = 0x0F02, | 
| jvfausto | 0:76ea242a637f | 926 | PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_0 = 0x0F03, | 
| jvfausto | 0:76ea242a637f | 927 | PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0 = 0x0F04, | 
| jvfausto | 0:76ea242a637f | 928 | PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_3 = 0x0F04, | 
| jvfausto | 0:76ea242a637f | 929 | PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_2 = 0x0F05, | 
| jvfausto | 0:76ea242a637f | 930 | PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_1 = 0x0F06, | 
| jvfausto | 0:76ea242a637f | 931 | PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_0 = 0x0F07, | 
| jvfausto | 0:76ea242a637f | 932 | PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0 = 0x0F08, | 
| jvfausto | 0:76ea242a637f | 933 | PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_3 = 0x0F08, | 
| jvfausto | 0:76ea242a637f | 934 | PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_2 = 0x0F09, | 
| jvfausto | 0:76ea242a637f | 935 | PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_1 = 0x0F0A, | 
| jvfausto | 0:76ea242a637f | 936 | PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_0 = 0x0F0B, | 
| jvfausto | 0:76ea242a637f | 937 | PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1 = 0x0F0C, | 
| jvfausto | 0:76ea242a637f | 938 | PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_3 = 0x0F0C, | 
| jvfausto | 0:76ea242a637f | 939 | PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_2 = 0x0F0D, | 
| jvfausto | 0:76ea242a637f | 940 | PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_1 = 0x0F0E, | 
| jvfausto | 0:76ea242a637f | 941 | PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_0 = 0x0F0F, | 
| jvfausto | 0:76ea242a637f | 942 | PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1 = 0x0F10, | 
| jvfausto | 0:76ea242a637f | 943 | PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_3 = 0x0F10, | 
| jvfausto | 0:76ea242a637f | 944 | PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_2 = 0x0F11, | 
| jvfausto | 0:76ea242a637f | 945 | PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_1 = 0x0F12, | 
| jvfausto | 0:76ea242a637f | 946 | PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_0 = 0x0F13, | 
| jvfausto | 0:76ea242a637f | 947 | PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1 = 0x0F14, | 
| jvfausto | 0:76ea242a637f | 948 | PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_3 = 0x0F14, | 
| jvfausto | 0:76ea242a637f | 949 | PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_2 = 0x0F15, | 
| jvfausto | 0:76ea242a637f | 950 | PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_1 = 0x0F16, | 
| jvfausto | 0:76ea242a637f | 951 | PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_0 = 0x0F17, | 
| jvfausto | 0:76ea242a637f | 952 | PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1 = 0x0F18, | 
| jvfausto | 0:76ea242a637f | 953 | PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_3 = 0x0F18, | 
| jvfausto | 0:76ea242a637f | 954 | PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_2 = 0x0F19, | 
| jvfausto | 0:76ea242a637f | 955 | PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_1 = 0x0F1A, | 
| jvfausto | 0:76ea242a637f | 956 | PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_0 = 0x0F1B, | 
| jvfausto | 0:76ea242a637f | 957 | PREV_SHADOW_RESULT_CORE__SPARE_0 = 0x0F1C, | 
| jvfausto | 0:76ea242a637f | 958 | RESULT__DEBUG_STATUS = 0x0F20, | 
| jvfausto | 0:76ea242a637f | 959 | RESULT__DEBUG_STAGE = 0x0F21, | 
| jvfausto | 0:76ea242a637f | 960 | GPH__SYSTEM__THRESH_RATE_HIGH = 0x0F24, | 
| jvfausto | 0:76ea242a637f | 961 | GPH__SYSTEM__THRESH_RATE_HIGH_HI = 0x0F24, | 
| jvfausto | 0:76ea242a637f | 962 | GPH__SYSTEM__THRESH_RATE_HIGH_LO = 0x0F25, | 
| jvfausto | 0:76ea242a637f | 963 | GPH__SYSTEM__THRESH_RATE_LOW = 0x0F26, | 
| jvfausto | 0:76ea242a637f | 964 | GPH__SYSTEM__THRESH_RATE_LOW_HI = 0x0F26, | 
| jvfausto | 0:76ea242a637f | 965 | GPH__SYSTEM__THRESH_RATE_LOW_LO = 0x0F27, | 
| jvfausto | 0:76ea242a637f | 966 | GPH__SYSTEM__INTERRUPT_CONFIG_GPIO = 0x0F28, | 
| jvfausto | 0:76ea242a637f | 967 | GPH__DSS_CONFIG__ROI_MODE_CONTROL = 0x0F2F, | 
| jvfausto | 0:76ea242a637f | 968 | GPH__DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT = 0x0F30, | 
| jvfausto | 0:76ea242a637f | 969 | GPH__DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT_HI = 0x0F30, | 
| jvfausto | 0:76ea242a637f | 970 | GPH__DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT_LO = 0x0F31, | 
| jvfausto | 0:76ea242a637f | 971 | GPH__DSS_CONFIG__MANUAL_BLOCK_SELECT = 0x0F32, | 
| jvfausto | 0:76ea242a637f | 972 | GPH__DSS_CONFIG__MAX_SPADS_LIMIT = 0x0F33, | 
| jvfausto | 0:76ea242a637f | 973 | GPH__DSS_CONFIG__MIN_SPADS_LIMIT = 0x0F34, | 
| jvfausto | 0:76ea242a637f | 974 | GPH__MM_CONFIG__TIMEOUT_MACROP_A_HI = 0x0F36, | 
| jvfausto | 0:76ea242a637f | 975 | GPH__MM_CONFIG__TIMEOUT_MACROP_A_LO = 0x0F37, | 
| jvfausto | 0:76ea242a637f | 976 | GPH__MM_CONFIG__TIMEOUT_MACROP_B_HI = 0x0F38, | 
| jvfausto | 0:76ea242a637f | 977 | GPH__MM_CONFIG__TIMEOUT_MACROP_B_LO = 0x0F39, | 
| jvfausto | 0:76ea242a637f | 978 | GPH__RANGE_CONFIG__TIMEOUT_MACROP_A_HI = 0x0F3A, | 
| jvfausto | 0:76ea242a637f | 979 | GPH__RANGE_CONFIG__TIMEOUT_MACROP_A_LO = 0x0F3B, | 
| jvfausto | 0:76ea242a637f | 980 | GPH__RANGE_CONFIG__VCSEL_PERIOD_A = 0x0F3C, | 
| jvfausto | 0:76ea242a637f | 981 | GPH__RANGE_CONFIG__VCSEL_PERIOD_B = 0x0F3D, | 
| jvfausto | 0:76ea242a637f | 982 | GPH__RANGE_CONFIG__TIMEOUT_MACROP_B_HI = 0x0F3E, | 
| jvfausto | 0:76ea242a637f | 983 | GPH__RANGE_CONFIG__TIMEOUT_MACROP_B_LO = 0x0F3F, | 
| jvfausto | 0:76ea242a637f | 984 | GPH__RANGE_CONFIG__SIGMA_THRESH = 0x0F40, | 
| jvfausto | 0:76ea242a637f | 985 | GPH__RANGE_CONFIG__SIGMA_THRESH_HI = 0x0F40, | 
| jvfausto | 0:76ea242a637f | 986 | GPH__RANGE_CONFIG__SIGMA_THRESH_LO = 0x0F41, | 
| jvfausto | 0:76ea242a637f | 987 | GPH__RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS = 0x0F42, | 
| jvfausto | 0:76ea242a637f | 988 | GPH__RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS_HI = 0x0F42, | 
| jvfausto | 0:76ea242a637f | 989 | GPH__RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS_LO = 0x0F43, | 
| jvfausto | 0:76ea242a637f | 990 | GPH__RANGE_CONFIG__VALID_PHASE_LOW = 0x0F44, | 
| jvfausto | 0:76ea242a637f | 991 | GPH__RANGE_CONFIG__VALID_PHASE_HIGH = 0x0F45, | 
| jvfausto | 0:76ea242a637f | 992 | FIRMWARE__INTERNAL_STREAM_COUNT_DIV = 0x0F46, | 
| jvfausto | 0:76ea242a637f | 993 | FIRMWARE__INTERNAL_STREAM_COUNTER_VAL = 0x0F47, | 
| jvfausto | 0:76ea242a637f | 994 | DSS_CALC__ROI_CTRL = 0x0F54, | 
| jvfausto | 0:76ea242a637f | 995 | DSS_CALC__SPARE_1 = 0x0F55, | 
| jvfausto | 0:76ea242a637f | 996 | DSS_CALC__SPARE_2 = 0x0F56, | 
| jvfausto | 0:76ea242a637f | 997 | DSS_CALC__SPARE_3 = 0x0F57, | 
| jvfausto | 0:76ea242a637f | 998 | DSS_CALC__SPARE_4 = 0x0F58, | 
| jvfausto | 0:76ea242a637f | 999 | DSS_CALC__SPARE_5 = 0x0F59, | 
| jvfausto | 0:76ea242a637f | 1000 | DSS_CALC__SPARE_6 = 0x0F5A, | 
| jvfausto | 0:76ea242a637f | 1001 | DSS_CALC__SPARE_7 = 0x0F5B, | 
| jvfausto | 0:76ea242a637f | 1002 | DSS_CALC__USER_ROI_SPAD_EN_0 = 0x0F5C, | 
| jvfausto | 0:76ea242a637f | 1003 | DSS_CALC__USER_ROI_SPAD_EN_1 = 0x0F5D, | 
| jvfausto | 0:76ea242a637f | 1004 | DSS_CALC__USER_ROI_SPAD_EN_2 = 0x0F5E, | 
| jvfausto | 0:76ea242a637f | 1005 | DSS_CALC__USER_ROI_SPAD_EN_3 = 0x0F5F, | 
| jvfausto | 0:76ea242a637f | 1006 | DSS_CALC__USER_ROI_SPAD_EN_4 = 0x0F60, | 
| jvfausto | 0:76ea242a637f | 1007 | DSS_CALC__USER_ROI_SPAD_EN_5 = 0x0F61, | 
| jvfausto | 0:76ea242a637f | 1008 | DSS_CALC__USER_ROI_SPAD_EN_6 = 0x0F62, | 
| jvfausto | 0:76ea242a637f | 1009 | DSS_CALC__USER_ROI_SPAD_EN_7 = 0x0F63, | 
| jvfausto | 0:76ea242a637f | 1010 | DSS_CALC__USER_ROI_SPAD_EN_8 = 0x0F64, | 
| jvfausto | 0:76ea242a637f | 1011 | DSS_CALC__USER_ROI_SPAD_EN_9 = 0x0F65, | 
| jvfausto | 0:76ea242a637f | 1012 | DSS_CALC__USER_ROI_SPAD_EN_10 = 0x0F66, | 
| jvfausto | 0:76ea242a637f | 1013 | DSS_CALC__USER_ROI_SPAD_EN_11 = 0x0F67, | 
| jvfausto | 0:76ea242a637f | 1014 | DSS_CALC__USER_ROI_SPAD_EN_12 = 0x0F68, | 
| jvfausto | 0:76ea242a637f | 1015 | DSS_CALC__USER_ROI_SPAD_EN_13 = 0x0F69, | 
| jvfausto | 0:76ea242a637f | 1016 | DSS_CALC__USER_ROI_SPAD_EN_14 = 0x0F6A, | 
| jvfausto | 0:76ea242a637f | 1017 | DSS_CALC__USER_ROI_SPAD_EN_15 = 0x0F6B, | 
| jvfausto | 0:76ea242a637f | 1018 | DSS_CALC__USER_ROI_SPAD_EN_16 = 0x0F6C, | 
| jvfausto | 0:76ea242a637f | 1019 | DSS_CALC__USER_ROI_SPAD_EN_17 = 0x0F6D, | 
| jvfausto | 0:76ea242a637f | 1020 | DSS_CALC__USER_ROI_SPAD_EN_18 = 0x0F6E, | 
| jvfausto | 0:76ea242a637f | 1021 | DSS_CALC__USER_ROI_SPAD_EN_19 = 0x0F6F, | 
| jvfausto | 0:76ea242a637f | 1022 | DSS_CALC__USER_ROI_SPAD_EN_20 = 0x0F70, | 
| jvfausto | 0:76ea242a637f | 1023 | DSS_CALC__USER_ROI_SPAD_EN_21 = 0x0F71, | 
| jvfausto | 0:76ea242a637f | 1024 | DSS_CALC__USER_ROI_SPAD_EN_22 = 0x0F72, | 
| jvfausto | 0:76ea242a637f | 1025 | DSS_CALC__USER_ROI_SPAD_EN_23 = 0x0F73, | 
| jvfausto | 0:76ea242a637f | 1026 | DSS_CALC__USER_ROI_SPAD_EN_24 = 0x0F74, | 
| jvfausto | 0:76ea242a637f | 1027 | DSS_CALC__USER_ROI_SPAD_EN_25 = 0x0F75, | 
| jvfausto | 0:76ea242a637f | 1028 | DSS_CALC__USER_ROI_SPAD_EN_26 = 0x0F76, | 
| jvfausto | 0:76ea242a637f | 1029 | DSS_CALC__USER_ROI_SPAD_EN_27 = 0x0F77, | 
| jvfausto | 0:76ea242a637f | 1030 | DSS_CALC__USER_ROI_SPAD_EN_28 = 0x0F78, | 
| jvfausto | 0:76ea242a637f | 1031 | DSS_CALC__USER_ROI_SPAD_EN_29 = 0x0F79, | 
| jvfausto | 0:76ea242a637f | 1032 | DSS_CALC__USER_ROI_SPAD_EN_30 = 0x0F7A, | 
| jvfausto | 0:76ea242a637f | 1033 | DSS_CALC__USER_ROI_SPAD_EN_31 = 0x0F7B, | 
| jvfausto | 0:76ea242a637f | 1034 | DSS_CALC__USER_ROI_0 = 0x0F7C, | 
| jvfausto | 0:76ea242a637f | 1035 | DSS_CALC__USER_ROI_1 = 0x0F7D, | 
| jvfausto | 0:76ea242a637f | 1036 | DSS_CALC__MODE_ROI_0 = 0x0F7E, | 
| jvfausto | 0:76ea242a637f | 1037 | DSS_CALC__MODE_ROI_1 = 0x0F7F, | 
| jvfausto | 0:76ea242a637f | 1038 | SIGMA_ESTIMATOR_CALC__SPARE_0 = 0x0F80, | 
| jvfausto | 0:76ea242a637f | 1039 | VHV_RESULT__PEAK_SIGNAL_RATE_MCPS = 0x0F82, | 
| jvfausto | 0:76ea242a637f | 1040 | VHV_RESULT__PEAK_SIGNAL_RATE_MCPS_HI = 0x0F82, | 
| jvfausto | 0:76ea242a637f | 1041 | VHV_RESULT__PEAK_SIGNAL_RATE_MCPS_LO = 0x0F83, | 
| jvfausto | 0:76ea242a637f | 1042 | VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF = 0x0F84, | 
| jvfausto | 0:76ea242a637f | 1043 | VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF_3 = 0x0F84, | 
| jvfausto | 0:76ea242a637f | 1044 | VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF_2 = 0x0F85, | 
| jvfausto | 0:76ea242a637f | 1045 | VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF_1 = 0x0F86, | 
| jvfausto | 0:76ea242a637f | 1046 | VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF_0 = 0x0F87, | 
| jvfausto | 0:76ea242a637f | 1047 | PHASECAL_RESULT__PHASE_OUTPUT_REF = 0x0F88, | 
| jvfausto | 0:76ea242a637f | 1048 | PHASECAL_RESULT__PHASE_OUTPUT_REF_HI = 0x0F88, | 
| jvfausto | 0:76ea242a637f | 1049 | PHASECAL_RESULT__PHASE_OUTPUT_REF_LO = 0x0F89, | 
| jvfausto | 0:76ea242a637f | 1050 | DSS_RESULT__TOTAL_RATE_PER_SPAD = 0x0F8A, | 
| jvfausto | 0:76ea242a637f | 1051 | DSS_RESULT__TOTAL_RATE_PER_SPAD_HI = 0x0F8A, | 
| jvfausto | 0:76ea242a637f | 1052 | DSS_RESULT__TOTAL_RATE_PER_SPAD_LO = 0x0F8B, | 
| jvfausto | 0:76ea242a637f | 1053 | DSS_RESULT__ENABLED_BLOCKS = 0x0F8C, | 
| jvfausto | 0:76ea242a637f | 1054 | DSS_RESULT__NUM_REQUESTED_SPADS = 0x0F8E, | 
| jvfausto | 0:76ea242a637f | 1055 | DSS_RESULT__NUM_REQUESTED_SPADS_HI = 0x0F8E, | 
| jvfausto | 0:76ea242a637f | 1056 | DSS_RESULT__NUM_REQUESTED_SPADS_LO = 0x0F8F, | 
| jvfausto | 0:76ea242a637f | 1057 | MM_RESULT__INNER_INTERSECTION_RATE = 0x0F92, | 
| jvfausto | 0:76ea242a637f | 1058 | MM_RESULT__INNER_INTERSECTION_RATE_HI = 0x0F92, | 
| jvfausto | 0:76ea242a637f | 1059 | MM_RESULT__INNER_INTERSECTION_RATE_LO = 0x0F93, | 
| jvfausto | 0:76ea242a637f | 1060 | MM_RESULT__OUTER_COMPLEMENT_RATE = 0x0F94, | 
| jvfausto | 0:76ea242a637f | 1061 | MM_RESULT__OUTER_COMPLEMENT_RATE_HI = 0x0F94, | 
| jvfausto | 0:76ea242a637f | 1062 | MM_RESULT__OUTER_COMPLEMENT_RATE_LO = 0x0F95, | 
| jvfausto | 0:76ea242a637f | 1063 | MM_RESULT__TOTAL_OFFSET = 0x0F96, | 
| jvfausto | 0:76ea242a637f | 1064 | MM_RESULT__TOTAL_OFFSET_HI = 0x0F96, | 
| jvfausto | 0:76ea242a637f | 1065 | MM_RESULT__TOTAL_OFFSET_LO = 0x0F97, | 
| jvfausto | 0:76ea242a637f | 1066 | XTALK_CALC__XTALK_FOR_ENABLED_SPADS = 0x0F98, | 
| jvfausto | 0:76ea242a637f | 1067 | XTALK_CALC__XTALK_FOR_ENABLED_SPADS_3 = 0x0F98, | 
| jvfausto | 0:76ea242a637f | 1068 | XTALK_CALC__XTALK_FOR_ENABLED_SPADS_2 = 0x0F99, | 
| jvfausto | 0:76ea242a637f | 1069 | XTALK_CALC__XTALK_FOR_ENABLED_SPADS_1 = 0x0F9A, | 
| jvfausto | 0:76ea242a637f | 1070 | XTALK_CALC__XTALK_FOR_ENABLED_SPADS_0 = 0x0F9B, | 
| jvfausto | 0:76ea242a637f | 1071 | XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS = 0x0F9C, | 
| jvfausto | 0:76ea242a637f | 1072 | XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS_3 = 0x0F9C, | 
| jvfausto | 0:76ea242a637f | 1073 | XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS_2 = 0x0F9D, | 
| jvfausto | 0:76ea242a637f | 1074 | XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS_1 = 0x0F9E, | 
| jvfausto | 0:76ea242a637f | 1075 | XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS_0 = 0x0F9F, | 
| jvfausto | 0:76ea242a637f | 1076 | XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS = 0x0FA0, | 
| jvfausto | 0:76ea242a637f | 1077 | XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS_3 = 0x0FA0, | 
| jvfausto | 0:76ea242a637f | 1078 | XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS_2 = 0x0FA1, | 
| jvfausto | 0:76ea242a637f | 1079 | XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS_1 = 0x0FA2, | 
| jvfausto | 0:76ea242a637f | 1080 | XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS_0 = 0x0FA3, | 
| jvfausto | 0:76ea242a637f | 1081 | XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS = 0x0FA4, | 
| jvfausto | 0:76ea242a637f | 1082 | XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS_3 = 0x0FA4, | 
| jvfausto | 0:76ea242a637f | 1083 | XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS_2 = 0x0FA5, | 
| jvfausto | 0:76ea242a637f | 1084 | XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS_1 = 0x0FA6, | 
| jvfausto | 0:76ea242a637f | 1085 | XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS_0 = 0x0FA7, | 
| jvfausto | 0:76ea242a637f | 1086 | RANGE_RESULT__ACCUM_PHASE = 0x0FA8, | 
| jvfausto | 0:76ea242a637f | 1087 | RANGE_RESULT__ACCUM_PHASE_3 = 0x0FA8, | 
| jvfausto | 0:76ea242a637f | 1088 | RANGE_RESULT__ACCUM_PHASE_2 = 0x0FA9, | 
| jvfausto | 0:76ea242a637f | 1089 | RANGE_RESULT__ACCUM_PHASE_1 = 0x0FAA, | 
| jvfausto | 0:76ea242a637f | 1090 | RANGE_RESULT__ACCUM_PHASE_0 = 0x0FAB, | 
| jvfausto | 0:76ea242a637f | 1091 | RANGE_RESULT__OFFSET_CORRECTED_RANGE = 0x0FAC, | 
| jvfausto | 0:76ea242a637f | 1092 | RANGE_RESULT__OFFSET_CORRECTED_RANGE_HI = 0x0FAC, | 
| jvfausto | 0:76ea242a637f | 1093 | RANGE_RESULT__OFFSET_CORRECTED_RANGE_LO = 0x0FAD, | 
| jvfausto | 0:76ea242a637f | 1094 | SHADOW_PHASECAL_RESULT__VCSEL_START = 0x0FAE, | 
| jvfausto | 0:76ea242a637f | 1095 | SHADOW_RESULT__INTERRUPT_STATUS = 0x0FB0, | 
| jvfausto | 0:76ea242a637f | 1096 | SHADOW_RESULT__RANGE_STATUS = 0x0FB1, | 
| jvfausto | 0:76ea242a637f | 1097 | SHADOW_RESULT__REPORT_STATUS = 0x0FB2, | 
| jvfausto | 0:76ea242a637f | 1098 | SHADOW_RESULT__STREAM_COUNT = 0x0FB3, | 
| jvfausto | 0:76ea242a637f | 1099 | SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0 = 0x0FB4, | 
| jvfausto | 0:76ea242a637f | 1100 | SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_HI = 0x0FB4, | 
| jvfausto | 0:76ea242a637f | 1101 | SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_LO = 0x0FB5, | 
| jvfausto | 0:76ea242a637f | 1102 | SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0 = 0x0FB6, | 
| jvfausto | 0:76ea242a637f | 1103 | SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_HI = 0x0FB6, | 
| jvfausto | 0:76ea242a637f | 1104 | SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_LO = 0x0FB7, | 
| jvfausto | 0:76ea242a637f | 1105 | SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0 = 0x0FB8, | 
| jvfausto | 0:76ea242a637f | 1106 | SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_HI = 0x0FB8, | 
| jvfausto | 0:76ea242a637f | 1107 | SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_LO = 0x0FB9, | 
| jvfausto | 0:76ea242a637f | 1108 | SHADOW_RESULT__SIGMA_SD0 = 0x0FBA, | 
| jvfausto | 0:76ea242a637f | 1109 | SHADOW_RESULT__SIGMA_SD0_HI = 0x0FBA, | 
| jvfausto | 0:76ea242a637f | 1110 | SHADOW_RESULT__SIGMA_SD0_LO = 0x0FBB, | 
| jvfausto | 0:76ea242a637f | 1111 | SHADOW_RESULT__PHASE_SD0 = 0x0FBC, | 
| jvfausto | 0:76ea242a637f | 1112 | SHADOW_RESULT__PHASE_SD0_HI = 0x0FBC, | 
| jvfausto | 0:76ea242a637f | 1113 | SHADOW_RESULT__PHASE_SD0_LO = 0x0FBD, | 
| jvfausto | 0:76ea242a637f | 1114 | SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0 = 0x0FBE, | 
| jvfausto | 0:76ea242a637f | 1115 | SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_HI = 0x0FBE, | 
| jvfausto | 0:76ea242a637f | 1116 | SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_LO = 0x0FBF, | 
| jvfausto | 0:76ea242a637f | 1117 | SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0 = 0x0FC0, | 
| jvfausto | 0:76ea242a637f | 1118 | SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_HI = 0x0FC0, | 
| jvfausto | 0:76ea242a637f | 1119 | SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_LO = 0x0FC1, | 
| jvfausto | 0:76ea242a637f | 1120 | SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0 = 0x0FC2, | 
| jvfausto | 0:76ea242a637f | 1121 | SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_HI = 0x0FC2, | 
| jvfausto | 0:76ea242a637f | 1122 | SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_LO = 0x0FC3, | 
| jvfausto | 0:76ea242a637f | 1123 | SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0 = 0x0FC4, | 
| jvfausto | 0:76ea242a637f | 1124 | SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_HI = 0x0FC4, | 
| jvfausto | 0:76ea242a637f | 1125 | SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_LO = 0x0FC5, | 
| jvfausto | 0:76ea242a637f | 1126 | SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0 = 0x0FC6, | 
| jvfausto | 0:76ea242a637f | 1127 | SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_HI = 0x0FC6, | 
| jvfausto | 0:76ea242a637f | 1128 | SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_LO = 0x0FC7, | 
| jvfausto | 0:76ea242a637f | 1129 | SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1 = 0x0FC8, | 
| jvfausto | 0:76ea242a637f | 1130 | SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_HI = 0x0FC8, | 
| jvfausto | 0:76ea242a637f | 1131 | SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_LO = 0x0FC9, | 
| jvfausto | 0:76ea242a637f | 1132 | SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1 = 0x0FCA, | 
| jvfausto | 0:76ea242a637f | 1133 | SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_HI = 0x0FCA, | 
| jvfausto | 0:76ea242a637f | 1134 | SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_LO = 0x0FCB, | 
| jvfausto | 0:76ea242a637f | 1135 | SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1 = 0x0FCC, | 
| jvfausto | 0:76ea242a637f | 1136 | SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_HI = 0x0FCC, | 
| jvfausto | 0:76ea242a637f | 1137 | SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_LO = 0x0FCD, | 
| jvfausto | 0:76ea242a637f | 1138 | SHADOW_RESULT__SIGMA_SD1 = 0x0FCE, | 
| jvfausto | 0:76ea242a637f | 1139 | SHADOW_RESULT__SIGMA_SD1_HI = 0x0FCE, | 
| jvfausto | 0:76ea242a637f | 1140 | SHADOW_RESULT__SIGMA_SD1_LO = 0x0FCF, | 
| jvfausto | 0:76ea242a637f | 1141 | SHADOW_RESULT__PHASE_SD1 = 0x0FD0, | 
| jvfausto | 0:76ea242a637f | 1142 | SHADOW_RESULT__PHASE_SD1_HI = 0x0FD0, | 
| jvfausto | 0:76ea242a637f | 1143 | SHADOW_RESULT__PHASE_SD1_LO = 0x0FD1, | 
| jvfausto | 0:76ea242a637f | 1144 | SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1 = 0x0FD2, | 
| jvfausto | 0:76ea242a637f | 1145 | SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_HI = 0x0FD2, | 
| jvfausto | 0:76ea242a637f | 1146 | SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_LO = 0x0FD3, | 
| jvfausto | 0:76ea242a637f | 1147 | SHADOW_RESULT__SPARE_0_SD1 = 0x0FD4, | 
| jvfausto | 0:76ea242a637f | 1148 | SHADOW_RESULT__SPARE_0_SD1_HI = 0x0FD4, | 
| jvfausto | 0:76ea242a637f | 1149 | SHADOW_RESULT__SPARE_0_SD1_LO = 0x0FD5, | 
| jvfausto | 0:76ea242a637f | 1150 | SHADOW_RESULT__SPARE_1_SD1 = 0x0FD6, | 
| jvfausto | 0:76ea242a637f | 1151 | SHADOW_RESULT__SPARE_1_SD1_HI = 0x0FD6, | 
| jvfausto | 0:76ea242a637f | 1152 | SHADOW_RESULT__SPARE_1_SD1_LO = 0x0FD7, | 
| jvfausto | 0:76ea242a637f | 1153 | SHADOW_RESULT__SPARE_2_SD1 = 0x0FD8, | 
| jvfausto | 0:76ea242a637f | 1154 | SHADOW_RESULT__SPARE_2_SD1_HI = 0x0FD8, | 
| jvfausto | 0:76ea242a637f | 1155 | SHADOW_RESULT__SPARE_2_SD1_LO = 0x0FD9, | 
| jvfausto | 0:76ea242a637f | 1156 | SHADOW_RESULT__SPARE_3_SD1 = 0x0FDA, | 
| jvfausto | 0:76ea242a637f | 1157 | SHADOW_RESULT__THRESH_INFO = 0x0FDB, | 
| jvfausto | 0:76ea242a637f | 1158 | SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0 = 0x0FDC, | 
| jvfausto | 0:76ea242a637f | 1159 | SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_3 = 0x0FDC, | 
| jvfausto | 0:76ea242a637f | 1160 | SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_2 = 0x0FDD, | 
| jvfausto | 0:76ea242a637f | 1161 | SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_1 = 0x0FDE, | 
| jvfausto | 0:76ea242a637f | 1162 | SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_0 = 0x0FDF, | 
| jvfausto | 0:76ea242a637f | 1163 | SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0 = 0x0FE0, | 
| jvfausto | 0:76ea242a637f | 1164 | SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_3 = 0x0FE0, | 
| jvfausto | 0:76ea242a637f | 1165 | SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_2 = 0x0FE1, | 
| jvfausto | 0:76ea242a637f | 1166 | SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_1 = 0x0FE2, | 
| jvfausto | 0:76ea242a637f | 1167 | SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_0 = 0x0FE3, | 
| jvfausto | 0:76ea242a637f | 1168 | SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0 = 0x0FE4, | 
| jvfausto | 0:76ea242a637f | 1169 | SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_3 = 0x0FE4, | 
| jvfausto | 0:76ea242a637f | 1170 | SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_2 = 0x0FE5, | 
| jvfausto | 0:76ea242a637f | 1171 | SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_1 = 0x0FE6, | 
| jvfausto | 0:76ea242a637f | 1172 | SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_0 = 0x0FE7, | 
| jvfausto | 0:76ea242a637f | 1173 | SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0 = 0x0FE8, | 
| jvfausto | 0:76ea242a637f | 1174 | SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_3 = 0x0FE8, | 
| jvfausto | 0:76ea242a637f | 1175 | SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_2 = 0x0FE9, | 
| jvfausto | 0:76ea242a637f | 1176 | SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_1 = 0x0FEA, | 
| jvfausto | 0:76ea242a637f | 1177 | SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_0 = 0x0FEB, | 
| jvfausto | 0:76ea242a637f | 1178 | SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1 = 0x0FEC, | 
| jvfausto | 0:76ea242a637f | 1179 | SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_3 = 0x0FEC, | 
| jvfausto | 0:76ea242a637f | 1180 | SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_2 = 0x0FED, | 
| jvfausto | 0:76ea242a637f | 1181 | SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_1 = 0x0FEE, | 
| jvfausto | 0:76ea242a637f | 1182 | SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_0 = 0x0FEF, | 
| jvfausto | 0:76ea242a637f | 1183 | SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1 = 0x0FF0, | 
| jvfausto | 0:76ea242a637f | 1184 | SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_3 = 0x0FF0, | 
| jvfausto | 0:76ea242a637f | 1185 | SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_2 = 0x0FF1, | 
| jvfausto | 0:76ea242a637f | 1186 | SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_1 = 0x0FF2, | 
| jvfausto | 0:76ea242a637f | 1187 | SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_0 = 0x0FF3, | 
| jvfausto | 0:76ea242a637f | 1188 | SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1 = 0x0FF4, | 
| jvfausto | 0:76ea242a637f | 1189 | SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_3 = 0x0FF4, | 
| jvfausto | 0:76ea242a637f | 1190 | SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_2 = 0x0FF5, | 
| jvfausto | 0:76ea242a637f | 1191 | SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_1 = 0x0FF6, | 
| jvfausto | 0:76ea242a637f | 1192 | SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_0 = 0x0FF7, | 
| jvfausto | 0:76ea242a637f | 1193 | SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1 = 0x0FF8, | 
| jvfausto | 0:76ea242a637f | 1194 | SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_3 = 0x0FF8, | 
| jvfausto | 0:76ea242a637f | 1195 | SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_2 = 0x0FF9, | 
| jvfausto | 0:76ea242a637f | 1196 | SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_1 = 0x0FFA, | 
| jvfausto | 0:76ea242a637f | 1197 | SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_0 = 0x0FFB, | 
| jvfausto | 0:76ea242a637f | 1198 | SHADOW_RESULT_CORE__SPARE_0 = 0x0FFC, | 
| jvfausto | 0:76ea242a637f | 1199 | SHADOW_PHASECAL_RESULT__REFERENCE_PHASE_HI = 0x0FFE, | 
| jvfausto | 0:76ea242a637f | 1200 | SHADOW_PHASECAL_RESULT__REFERENCE_PHASE_LO = 0x0FFF, | 
| jvfausto | 0:76ea242a637f | 1201 | }; | 
| jvfausto | 0:76ea242a637f | 1202 | |
| jvfausto | 0:76ea242a637f | 1203 | enum DistanceMode { Short, Medium, Long, Unknown }; | 
| jvfausto | 0:76ea242a637f | 1204 | |
| jvfausto | 0:76ea242a637f | 1205 | enum RangeStatus : uint8_t | 
| jvfausto | 0:76ea242a637f | 1206 | { | 
| jvfausto | 0:76ea242a637f | 1207 | RangeValid = 0, | 
| jvfausto | 0:76ea242a637f | 1208 | |
| jvfausto | 0:76ea242a637f | 1209 | // "sigma estimator check is above the internal defined threshold" | 
| jvfausto | 0:76ea242a637f | 1210 | // (sigma = standard deviation of measurement) | 
| jvfausto | 0:76ea242a637f | 1211 | SigmaFail = 1, | 
| jvfausto | 0:76ea242a637f | 1212 | |
| jvfausto | 0:76ea242a637f | 1213 | // "signal value is below the internal defined threshold" | 
| jvfausto | 0:76ea242a637f | 1214 | SignalFail = 2, | 
| jvfausto | 0:76ea242a637f | 1215 | |
| jvfausto | 0:76ea242a637f | 1216 | // "Target is below minimum detection threshold." | 
| jvfausto | 0:76ea242a637f | 1217 | RangeValidMinRangeClipped = 3, | 
| jvfausto | 0:76ea242a637f | 1218 | |
| jvfausto | 0:76ea242a637f | 1219 | // "phase is out of bounds" | 
| jvfausto | 0:76ea242a637f | 1220 | // (nothing detected in range; try a longer distance mode if applicable) | 
| jvfausto | 0:76ea242a637f | 1221 | OutOfBoundsFail = 4, | 
| jvfausto | 0:76ea242a637f | 1222 | |
| jvfausto | 0:76ea242a637f | 1223 | // "HW or VCSEL failure" | 
| jvfausto | 0:76ea242a637f | 1224 | HardwareFail = 5, | 
| jvfausto | 0:76ea242a637f | 1225 | |
| jvfausto | 0:76ea242a637f | 1226 | // "The Range is valid but the wraparound check has not been done." | 
| jvfausto | 0:76ea242a637f | 1227 | RangeValidNoWrapCheckFail = 6, | 
| jvfausto | 0:76ea242a637f | 1228 | |
| jvfausto | 0:76ea242a637f | 1229 | // "Wrapped target, not matching phases" | 
| jvfausto | 0:76ea242a637f | 1230 | // "no matching phase in other VCSEL period timing." | 
| jvfausto | 0:76ea242a637f | 1231 | WrapTargetFail = 7, | 
| jvfausto | 0:76ea242a637f | 1232 | |
| jvfausto | 0:76ea242a637f | 1233 | // "Internal algo underflow or overflow in lite ranging." | 
| jvfausto | 0:76ea242a637f | 1234 | // ProcessingFail = 8: not used in API | 
| jvfausto | 0:76ea242a637f | 1235 | |
| jvfausto | 0:76ea242a637f | 1236 | // "Specific to lite ranging." | 
| jvfausto | 0:76ea242a637f | 1237 | // should never occur with this lib (which uses low power auto ranging, | 
| jvfausto | 0:76ea242a637f | 1238 | // as the API does) | 
| jvfausto | 0:76ea242a637f | 1239 | XtalkSignalFail = 9, | 
| jvfausto | 0:76ea242a637f | 1240 | |
| jvfausto | 0:76ea242a637f | 1241 | // "1st interrupt when starting ranging in back to back mode. Ignore | 
| jvfausto | 0:76ea242a637f | 1242 | // data." | 
| jvfausto | 0:76ea242a637f | 1243 | // should never occur with this lib | 
| jvfausto | 0:76ea242a637f | 1244 | SynchronizationInt = 10, // (the API spells this "syncronisation") | 
| jvfausto | 0:76ea242a637f | 1245 | |
| jvfausto | 0:76ea242a637f | 1246 | // "All Range ok but object is result of multiple pulses merging together. | 
| jvfausto | 0:76ea242a637f | 1247 | // Used by RQL for merged pulse detection" | 
| jvfausto | 0:76ea242a637f | 1248 | // RangeValid MergedPulse = 11: not used in API | 
| jvfausto | 0:76ea242a637f | 1249 | |
| jvfausto | 0:76ea242a637f | 1250 | // "Used by RQL as different to phase fail." | 
| jvfausto | 0:76ea242a637f | 1251 | // TargetPresentLackOfSignal = 12: | 
| jvfausto | 0:76ea242a637f | 1252 | |
| jvfausto | 0:76ea242a637f | 1253 | // "Target is below minimum detection threshold." | 
| jvfausto | 0:76ea242a637f | 1254 | MinRangeFail = 13, | 
| jvfausto | 0:76ea242a637f | 1255 | |
| jvfausto | 0:76ea242a637f | 1256 | // "The reported range is invalid" | 
| jvfausto | 0:76ea242a637f | 1257 | // RangeInvalid = 14: can't actually be returned by API (range can never become negative, even after correction) | 
| jvfausto | 0:76ea242a637f | 1258 | |
| jvfausto | 0:76ea242a637f | 1259 | // "No Update." | 
| jvfausto | 0:76ea242a637f | 1260 | None = 255, | 
| jvfausto | 0:76ea242a637f | 1261 | }; | 
| jvfausto | 0:76ea242a637f | 1262 | |
| jvfausto | 0:76ea242a637f | 1263 | struct RangingData | 
| jvfausto | 0:76ea242a637f | 1264 | { | 
| jvfausto | 0:76ea242a637f | 1265 | uint16_t range_mm; | 
| jvfausto | 0:76ea242a637f | 1266 | RangeStatus range_status; | 
| jvfausto | 0:76ea242a637f | 1267 | float peak_signal_count_rate_MCPS; | 
| jvfausto | 0:76ea242a637f | 1268 | float ambient_count_rate_MCPS; | 
| jvfausto | 0:76ea242a637f | 1269 | }; | 
| jvfausto | 0:76ea242a637f | 1270 | |
| jvfausto | 0:76ea242a637f | 1271 | RangingData ranging_data; | 
| jvfausto | 0:76ea242a637f | 1272 | |
| jvfausto | 0:76ea242a637f | 1273 | uint8_t last_status; // status of last I2C transmission | 
| jvfausto | 0:76ea242a637f | 1274 | |
| jvfausto | 0:76ea242a637f | 1275 | VL53L1X(); | 
| jvfausto | 0:76ea242a637f | 1276 | |
| jvfausto | 0:76ea242a637f | 1277 | void setAddress(uint8_t new_addr); | 
| jvfausto | 0:76ea242a637f | 1278 | uint8_t getAddress() { return address; } | 
| jvfausto | 0:76ea242a637f | 1279 | |
| jvfausto | 0:76ea242a637f | 1280 | bool init(bool io_2v8 = true); | 
| jvfausto | 0:76ea242a637f | 1281 | |
| jvfausto | 0:76ea242a637f | 1282 | void writeReg(uint16_t registerAddr, uint8_t data); | 
| jvfausto | 0:76ea242a637f | 1283 | void writeReg16Bit(uint16_t registerAddr, uint16_t data); | 
| jvfausto | 0:76ea242a637f | 1284 | void writeReg32Bit(uint16_t registerAddr, uint32_t data); | 
| jvfausto | 0:76ea242a637f | 1285 | uint8_t readReg(uint16_t registerAddr); | 
| jvfausto | 0:76ea242a637f | 1286 | uint16_t readReg16Bit(uint16_t registerAddr); | 
| jvfausto | 0:76ea242a637f | 1287 | uint32_t readReg32Bit(uint16_t registerAddr); | 
| jvfausto | 0:76ea242a637f | 1288 | |
| jvfausto | 0:76ea242a637f | 1289 | bool setDistanceMode(DistanceMode mode); | 
| jvfausto | 0:76ea242a637f | 1290 | DistanceMode getDistanceMode() { return distance_mode; } | 
| jvfausto | 0:76ea242a637f | 1291 | |
| jvfausto | 0:76ea242a637f | 1292 | bool setMeasurementTimingBudget(uint32_t budget_us); | 
| jvfausto | 0:76ea242a637f | 1293 | uint32_t getMeasurementTimingBudget(); | 
| jvfausto | 0:76ea242a637f | 1294 | |
| jvfausto | 0:76ea242a637f | 1295 | void startContinuous(uint32_t period_ms); | 
| jvfausto | 0:76ea242a637f | 1296 | void stopContinuous(); | 
| jvfausto | 0:76ea242a637f | 1297 | uint16_t read(bool blocking = true); | 
| jvfausto | 0:76ea242a637f | 1298 | uint16_t readRangeContinuousMillimeters(bool blocking = true) { return read(blocking); } // alias of read() | 
| jvfausto | 0:76ea242a637f | 1299 | |
| jvfausto | 0:76ea242a637f | 1300 | // check if sensor has new reading available | 
| jvfausto | 0:76ea242a637f | 1301 | // assumes interrupt is active low (GPIO_HV_MUX__CTRL bit 4 is 1) | 
| jvfausto | 0:76ea242a637f | 1302 | bool dataReady() { | 
| jvfausto | 0:76ea242a637f | 1303 | int isThereData = readReg(GPIO__TIO_HV_STATUS); | 
| jvfausto | 0:76ea242a637f | 1304 | printf("%x\r\n", isThereData); | 
| jvfausto | 0:76ea242a637f | 1305 | return (isThereData & 0x01) == 0; | 
| jvfausto | 0:76ea242a637f | 1306 | } | 
| jvfausto | 0:76ea242a637f | 1307 | |
| jvfausto | 0:76ea242a637f | 1308 | static const char * rangeStatusToString(RangeStatus status); | 
| jvfausto | 0:76ea242a637f | 1309 | |
| jvfausto | 0:76ea242a637f | 1310 | void setTimeout(uint16_t timeout) { io_timeout = timeout; } | 
| jvfausto | 0:76ea242a637f | 1311 | uint16_t getTimeout() { return io_timeout; } | 
| jvfausto | 0:76ea242a637f | 1312 | bool timeoutOccurred(); | 
| jvfausto | 0:76ea242a637f | 1313 | |
| jvfausto | 0:76ea242a637f | 1314 | private: | 
| jvfausto | 0:76ea242a637f | 1315 | I2C _i2c; | 
| jvfausto | 0:76ea242a637f | 1316 | |
| jvfausto | 0:76ea242a637f | 1317 | |
| jvfausto | 0:76ea242a637f | 1318 | // The Arduino two-wire interface uses a 7-bit number for the address, | 
| jvfausto | 0:76ea242a637f | 1319 | // and sets the last bit correctly based on reads and writes | 
| jvfausto | 0:76ea242a637f | 1320 | static const uint8_t AddressDefault = 0b0101001; | 
| jvfausto | 0:76ea242a637f | 1321 | |
| jvfausto | 0:76ea242a637f | 1322 | // value used in measurement timing budget calculations | 
| jvfausto | 0:76ea242a637f | 1323 | // assumes PresetMode is LOWPOWER_AUTONOMOUS | 
| jvfausto | 0:76ea242a637f | 1324 | // | 
| jvfausto | 0:76ea242a637f | 1325 | // vhv = LOWPOWER_AUTO_VHV_LOOP_DURATION_US + LOWPOWERAUTO_VHV_LOOP_BOUND | 
| jvfausto | 0:76ea242a637f | 1326 | // (tuning parm default) * LOWPOWER_AUTO_VHV_LOOP_DURATION_US | 
| jvfausto | 0:76ea242a637f | 1327 | // = 245 + 3 * 245 = 980 | 
| jvfausto | 0:76ea242a637f | 1328 | // TimingGuard = LOWPOWER_AUTO_OVERHEAD_BEFORE_A_RANGING + | 
| jvfausto | 0:76ea242a637f | 1329 | // LOWPOWER_AUTO_OVERHEAD_BETWEEN_A_B_RANGING + vhv | 
| jvfausto | 0:76ea242a637f | 1330 | // = 1448 + 2100 + 980 = 4528 | 
| jvfausto | 0:76ea242a637f | 1331 | static const uint32_t TimingGuard = 4528; | 
| jvfausto | 0:76ea242a637f | 1332 | |
| jvfausto | 0:76ea242a637f | 1333 | // value in DSS_CONFIG__TARGET_TOTAL_RATE_MCPS register, used in DSS | 
| jvfausto | 0:76ea242a637f | 1334 | // calculations | 
| jvfausto | 0:76ea242a637f | 1335 | static const uint16_t TargetRate = 0x0A00; | 
| jvfausto | 0:76ea242a637f | 1336 | |
| jvfausto | 0:76ea242a637f | 1337 | // for storing values read from RESULT__RANGE_STATUS (0x0089) | 
| jvfausto | 0:76ea242a637f | 1338 | // through RESULT__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_LOW | 
| jvfausto | 0:76ea242a637f | 1339 | // (0x0099) | 
| jvfausto | 0:76ea242a637f | 1340 | struct ResultBuffer | 
| jvfausto | 0:76ea242a637f | 1341 | { | 
| jvfausto | 0:76ea242a637f | 1342 | uint8_t range_status; | 
| jvfausto | 0:76ea242a637f | 1343 | // uint8_t report_status: not used | 
| jvfausto | 0:76ea242a637f | 1344 | uint8_t stream_count; | 
| jvfausto | 0:76ea242a637f | 1345 | uint16_t dss_actual_effective_spads_sd0; | 
| jvfausto | 0:76ea242a637f | 1346 | // uint16_t peak_signal_count_rate_mcps_sd0: not used | 
| jvfausto | 0:76ea242a637f | 1347 | uint16_t ambient_count_rate_mcps_sd0; | 
| jvfausto | 0:76ea242a637f | 1348 | // uint16_t sigma_sd0: not used | 
| jvfausto | 0:76ea242a637f | 1349 | // uint16_t phase_sd0: not used | 
| jvfausto | 0:76ea242a637f | 1350 | uint16_t final_crosstalk_corrected_range_mm_sd0; | 
| jvfausto | 0:76ea242a637f | 1351 | uint16_t peak_signal_count_rate_crosstalk_corrected_mcps_sd0; | 
| jvfausto | 0:76ea242a637f | 1352 | }; | 
| jvfausto | 0:76ea242a637f | 1353 | |
| jvfausto | 0:76ea242a637f | 1354 | // making this static would save RAM for multiple instances as long as there | 
| jvfausto | 0:76ea242a637f | 1355 | // aren't multiple sensors being read at the same time (e.g. on separate | 
| jvfausto | 0:76ea242a637f | 1356 | // I2C buses) | 
| jvfausto | 0:76ea242a637f | 1357 | ResultBuffer results; | 
| jvfausto | 0:76ea242a637f | 1358 | |
| jvfausto | 0:76ea242a637f | 1359 | uint8_t address; | 
| jvfausto | 0:76ea242a637f | 1360 | |
| jvfausto | 0:76ea242a637f | 1361 | uint16_t io_timeout; | 
| jvfausto | 0:76ea242a637f | 1362 | bool did_timeout; | 
| jvfausto | 0:76ea242a637f | 1363 | uint16_t timeout_start_ms; | 
| jvfausto | 0:76ea242a637f | 1364 | |
| jvfausto | 0:76ea242a637f | 1365 | uint16_t fast_osc_frequency; | 
| jvfausto | 0:76ea242a637f | 1366 | uint16_t osc_calibrate_val; | 
| jvfausto | 0:76ea242a637f | 1367 | |
| jvfausto | 0:76ea242a637f | 1368 | bool calibrated; | 
| jvfausto | 0:76ea242a637f | 1369 | uint8_t saved_vhv_init; | 
| jvfausto | 0:76ea242a637f | 1370 | uint8_t saved_vhv_timeout; | 
| jvfausto | 0:76ea242a637f | 1371 | |
| jvfausto | 0:76ea242a637f | 1372 | DistanceMode distance_mode; | 
| jvfausto | 0:76ea242a637f | 1373 | |
| jvfausto | 0:76ea242a637f | 1374 | // Record the current time to check an upcoming timeout against | 
| jvfausto | 0:76ea242a637f | 1375 | void startTimeout() { timeout_start_ms = t.read()/10000; } | 
| jvfausto | 0:76ea242a637f | 1376 | |
| jvfausto | 0:76ea242a637f | 1377 | // Check if timeout is enabled (set to nonzero value) and has expired | 
| jvfausto | 0:76ea242a637f | 1378 | bool checkTimeoutExpired() {return (io_timeout > 0) && ((uint16_t)(t.read()/10000 - timeout_start_ms) > io_timeout); } | 
| jvfausto | 0:76ea242a637f | 1379 | |
| jvfausto | 0:76ea242a637f | 1380 | void setupManualCalibration(); | 
| jvfausto | 0:76ea242a637f | 1381 | void readResults(); | 
| jvfausto | 0:76ea242a637f | 1382 | void updateDSS(); | 
| jvfausto | 0:76ea242a637f | 1383 | void getRangingData(); | 
| jvfausto | 0:76ea242a637f | 1384 | |
| jvfausto | 0:76ea242a637f | 1385 | static uint32_t decodeTimeout(uint16_t reg_val); | 
| jvfausto | 0:76ea242a637f | 1386 | static uint16_t encodeTimeout(uint32_t timeout_mclks); | 
| jvfausto | 0:76ea242a637f | 1387 | static uint32_t timeoutMclksToMicroseconds(uint32_t timeout_mclks, uint32_t macro_period_us); | 
| jvfausto | 0:76ea242a637f | 1388 | static uint32_t timeoutMicrosecondsToMclks(uint32_t timeout_us, uint32_t macro_period_us); | 
| jvfausto | 0:76ea242a637f | 1389 | uint32_t calcMacroPeriod(uint8_t vcsel_period); | 
| jvfausto | 0:76ea242a637f | 1390 | |
| jvfausto | 0:76ea242a637f | 1391 | // Convert count rate from fixed point 9.7 format to float | 
| jvfausto | 0:76ea242a637f | 1392 | float countRateFixedToFloat(uint16_t count_rate_fixed) { return (float)count_rate_fixed / (1 << 7); } | 
| jvfausto | 0:76ea242a637f | 1393 | }; | 
| jvfausto | 0:76ea242a637f | 1394 | #endif |