João Victor / stm32f4-discovery-CAN-Activation

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targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F412ZG/device/TOOLCHAIN_GCC_ARM/startup_stm32f412zx.s@153:fa9ff456f731, 2016-12-20 (annotated)

Committer:
<>
Date:
Tue Dec 20 17:27:56 2016 +0000
Revision:
153:fa9ff456f731
This updates the lib to the mbed lib v132

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 153:fa9ff456f731 1 /**
<> 153:fa9ff456f731 2 ******************************************************************************
<> 153:fa9ff456f731 3 * @file startup_stm32f412zx.s
<> 153:fa9ff456f731 4 * @author MCD Application Team
<> 153:fa9ff456f731 5 * @version V2.5.1
<> 153:fa9ff456f731 6 * @date 28-June-2016
<> 153:fa9ff456f731 7 * @brief STM32F412Zx Devices vector table for GCC based toolchains.
<> 153:fa9ff456f731 8 * This module performs:
<> 153:fa9ff456f731 9 * - Set the initial SP
<> 153:fa9ff456f731 10 * - Set the initial PC == Reset_Handler,
<> 153:fa9ff456f731 11 * - Set the vector table entries with the exceptions ISR address
<> 153:fa9ff456f731 12 * - Branches to main in the C library (which eventually
<> 153:fa9ff456f731 13 * calls main()).
<> 153:fa9ff456f731 14 * After Reset the Cortex-M4 processor is in Thread mode,
<> 153:fa9ff456f731 15 * priority is Privileged, and the Stack is set to Main.
<> 153:fa9ff456f731 16 ******************************************************************************
<> 153:fa9ff456f731 17 * @attention
<> 153:fa9ff456f731 18 *
<> 153:fa9ff456f731 19 * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
<> 153:fa9ff456f731 20 *
<> 153:fa9ff456f731 21 * Redistribution and use in source and binary forms, with or without modification,
<> 153:fa9ff456f731 22 * are permitted provided that the following conditions are met:
<> 153:fa9ff456f731 23 * 1. Redistributions of source code must retain the above copyright notice,
<> 153:fa9ff456f731 24 * this list of conditions and the following disclaimer.
<> 153:fa9ff456f731 25 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 153:fa9ff456f731 26 * this list of conditions and the following disclaimer in the documentation
<> 153:fa9ff456f731 27 * and/or other materials provided with the distribution.
<> 153:fa9ff456f731 28 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 153:fa9ff456f731 29 * may be used to endorse or promote products derived from this software
<> 153:fa9ff456f731 30 * without specific prior written permission.
<> 153:fa9ff456f731 31 *
<> 153:fa9ff456f731 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 153:fa9ff456f731 33 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 153:fa9ff456f731 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 153:fa9ff456f731 35 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 153:fa9ff456f731 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 153:fa9ff456f731 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 153:fa9ff456f731 38 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 153:fa9ff456f731 39 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 153:fa9ff456f731 40 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 153:fa9ff456f731 41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 153:fa9ff456f731 42 *
<> 153:fa9ff456f731 43 ******************************************************************************
<> 153:fa9ff456f731 44 */
<> 153:fa9ff456f731 45
<> 153:fa9ff456f731 46 .syntax unified
<> 153:fa9ff456f731 47 .cpu cortex-m4
<> 153:fa9ff456f731 48 .fpu softvfp
<> 153:fa9ff456f731 49 .thumb
<> 153:fa9ff456f731 50
<> 153:fa9ff456f731 51 .global g_pfnVectors
<> 153:fa9ff456f731 52 .global Default_Handler
<> 153:fa9ff456f731 53
<> 153:fa9ff456f731 54 /* start address for the initialization values of the .data section.
<> 153:fa9ff456f731 55 defined in linker script */
<> 153:fa9ff456f731 56 .word _sidata
<> 153:fa9ff456f731 57 /* start address for the .data section. defined in linker script */
<> 153:fa9ff456f731 58 .word _sdata
<> 153:fa9ff456f731 59 /* end address for the .data section. defined in linker script */
<> 153:fa9ff456f731 60 .word _edata
<> 153:fa9ff456f731 61 /* start address for the .bss section. defined in linker script */
<> 153:fa9ff456f731 62 .word _sbss
<> 153:fa9ff456f731 63 /* end address for the .bss section. defined in linker script */
<> 153:fa9ff456f731 64 .word _ebss
<> 153:fa9ff456f731 65 /* stack used for SystemInit_ExtMemCtl; always internal RAM used */
<> 153:fa9ff456f731 66
<> 153:fa9ff456f731 67 /**
<> 153:fa9ff456f731 68 * @brief This is the code that gets called when the processor first
<> 153:fa9ff456f731 69 * starts execution following a reset event. Only the absolutely
<> 153:fa9ff456f731 70 * necessary set is performed, after which the application
<> 153:fa9ff456f731 71 * supplied main() routine is called.
<> 153:fa9ff456f731 72 * @param None
<> 153:fa9ff456f731 73 * @retval : None
<> 153:fa9ff456f731 74 */
<> 153:fa9ff456f731 75
<> 153:fa9ff456f731 76 .section .text.Reset_Handler
<> 153:fa9ff456f731 77 .weak Reset_Handler
<> 153:fa9ff456f731 78 .type Reset_Handler, %function
<> 153:fa9ff456f731 79 Reset_Handler:
<> 153:fa9ff456f731 80 ldr sp, =_estack /* set stack pointer */
<> 153:fa9ff456f731 81
<> 153:fa9ff456f731 82 /* Copy the data segment initializers from flash to SRAM */
<> 153:fa9ff456f731 83 movs r1, #0
<> 153:fa9ff456f731 84 b LoopCopyDataInit
<> 153:fa9ff456f731 85
<> 153:fa9ff456f731 86 CopyDataInit:
<> 153:fa9ff456f731 87 ldr r3, =_sidata
<> 153:fa9ff456f731 88 ldr r3, [r3, r1]
<> 153:fa9ff456f731 89 str r3, [r0, r1]
<> 153:fa9ff456f731 90 adds r1, r1, #4
<> 153:fa9ff456f731 91
<> 153:fa9ff456f731 92 LoopCopyDataInit:
<> 153:fa9ff456f731 93 ldr r0, =_sdata
<> 153:fa9ff456f731 94 ldr r3, =_edata
<> 153:fa9ff456f731 95 adds r2, r0, r1
<> 153:fa9ff456f731 96 cmp r2, r3
<> 153:fa9ff456f731 97 bcc CopyDataInit
<> 153:fa9ff456f731 98 ldr r2, =_sbss
<> 153:fa9ff456f731 99 b LoopFillZerobss
<> 153:fa9ff456f731 100 /* Zero fill the bss segment. */
<> 153:fa9ff456f731 101 FillZerobss:
<> 153:fa9ff456f731 102 movs r3, #0
<> 153:fa9ff456f731 103 str r3, [r2], #4
<> 153:fa9ff456f731 104
<> 153:fa9ff456f731 105 LoopFillZerobss:
<> 153:fa9ff456f731 106 ldr r3, = _ebss
<> 153:fa9ff456f731 107 cmp r2, r3
<> 153:fa9ff456f731 108 bcc FillZerobss
<> 153:fa9ff456f731 109
<> 153:fa9ff456f731 110 /* Call the clock system intitialization function.*/
<> 153:fa9ff456f731 111 bl SystemInit
<> 153:fa9ff456f731 112 /* Call static constructors */
<> 153:fa9ff456f731 113 //bl __libc_init_array
<> 153:fa9ff456f731 114 /* Call the application's entry point.*/
<> 153:fa9ff456f731 115 //bl main
<> 153:fa9ff456f731 116 // Calling the crt0 'cold-start' entry point. There __libc_init_array is called
<> 153:fa9ff456f731 117 // and when existing hardware_init_hook() and software_init_hook() before
<> 153:fa9ff456f731 118 // starting main(). software_init_hook() is available and has to be called due
<> 153:fa9ff456f731 119 // to initializsation when using rtos.
<> 153:fa9ff456f731 120 bl _start
<> 153:fa9ff456f731 121 bx lr
<> 153:fa9ff456f731 122 .size Reset_Handler, .-Reset_Handler
<> 153:fa9ff456f731 123
<> 153:fa9ff456f731 124 /**
<> 153:fa9ff456f731 125 * @brief This is the code that gets called when the processor receives an
<> 153:fa9ff456f731 126 * unexpected interrupt. This simply enters an infinite loop, preserving
<> 153:fa9ff456f731 127 * the system state for examination by a debugger.
<> 153:fa9ff456f731 128 * @param None
<> 153:fa9ff456f731 129 * @retval None
<> 153:fa9ff456f731 130 */
<> 153:fa9ff456f731 131 .section .text.Default_Handler,"ax",%progbits
<> 153:fa9ff456f731 132 Default_Handler:
<> 153:fa9ff456f731 133 Infinite_Loop:
<> 153:fa9ff456f731 134 b Infinite_Loop
<> 153:fa9ff456f731 135 .size Default_Handler, .-Default_Handler
<> 153:fa9ff456f731 136 /******************************************************************************
<> 153:fa9ff456f731 137 *
<> 153:fa9ff456f731 138 * The minimal vector table for a Cortex M3. Note that the proper constructs
<> 153:fa9ff456f731 139 * must be placed on this to ensure that it ends up at physical address
<> 153:fa9ff456f731 140 * 0x0000.0000.
<> 153:fa9ff456f731 141 *
<> 153:fa9ff456f731 142 *******************************************************************************/
<> 153:fa9ff456f731 143 .section .isr_vector,"a",%progbits
<> 153:fa9ff456f731 144 .type g_pfnVectors, %object
<> 153:fa9ff456f731 145 .size g_pfnVectors, .-g_pfnVectors
<> 153:fa9ff456f731 146
<> 153:fa9ff456f731 147 g_pfnVectors:
<> 153:fa9ff456f731 148 .word _estack
<> 153:fa9ff456f731 149 .word Reset_Handler
<> 153:fa9ff456f731 150 .word NMI_Handler
<> 153:fa9ff456f731 151 .word HardFault_Handler
<> 153:fa9ff456f731 152 .word MemManage_Handler
<> 153:fa9ff456f731 153 .word BusFault_Handler
<> 153:fa9ff456f731 154 .word UsageFault_Handler
<> 153:fa9ff456f731 155 .word 0
<> 153:fa9ff456f731 156 .word 0
<> 153:fa9ff456f731 157 .word 0
<> 153:fa9ff456f731 158 .word 0
<> 153:fa9ff456f731 159 .word SVC_Handler
<> 153:fa9ff456f731 160 .word DebugMon_Handler
<> 153:fa9ff456f731 161 .word 0
<> 153:fa9ff456f731 162 .word PendSV_Handler
<> 153:fa9ff456f731 163 .word SysTick_Handler
<> 153:fa9ff456f731 164
<> 153:fa9ff456f731 165 /* External Interrupts */
<> 153:fa9ff456f731 166 .word WWDG_IRQHandler /* Window WatchDog */
<> 153:fa9ff456f731 167 .word PVD_IRQHandler /* PVD through EXTI Line detection */
<> 153:fa9ff456f731 168 .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
<> 153:fa9ff456f731 169 .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
<> 153:fa9ff456f731 170 .word FLASH_IRQHandler /* FLASH */
<> 153:fa9ff456f731 171 .word RCC_IRQHandler /* RCC */
<> 153:fa9ff456f731 172 .word EXTI0_IRQHandler /* EXTI Line0 */
<> 153:fa9ff456f731 173 .word EXTI1_IRQHandler /* EXTI Line1 */
<> 153:fa9ff456f731 174 .word EXTI2_IRQHandler /* EXTI Line2 */
<> 153:fa9ff456f731 175 .word EXTI3_IRQHandler /* EXTI Line3 */
<> 153:fa9ff456f731 176 .word EXTI4_IRQHandler /* EXTI Line4 */
<> 153:fa9ff456f731 177 .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
<> 153:fa9ff456f731 178 .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
<> 153:fa9ff456f731 179 .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
<> 153:fa9ff456f731 180 .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
<> 153:fa9ff456f731 181 .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
<> 153:fa9ff456f731 182 .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
<> 153:fa9ff456f731 183 .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
<> 153:fa9ff456f731 184 .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
<> 153:fa9ff456f731 185 .word CAN1_TX_IRQHandler /* CAN1 TX */
<> 153:fa9ff456f731 186 .word CAN1_RX0_IRQHandler /* CAN1 RX0 */
<> 153:fa9ff456f731 187 .word CAN1_RX1_IRQHandler /* CAN1 RX1 */
<> 153:fa9ff456f731 188 .word CAN1_SCE_IRQHandler /* CAN1 SCE */
<> 153:fa9ff456f731 189 .word EXTI9_5_IRQHandler /* External Line[9:5]s */
<> 153:fa9ff456f731 190 .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
<> 153:fa9ff456f731 191 .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
<> 153:fa9ff456f731 192 .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
<> 153:fa9ff456f731 193 .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
<> 153:fa9ff456f731 194 .word TIM2_IRQHandler /* TIM2 */
<> 153:fa9ff456f731 195 .word TIM3_IRQHandler /* TIM3 */
<> 153:fa9ff456f731 196 .word TIM4_IRQHandler /* TIM4 */
<> 153:fa9ff456f731 197 .word I2C1_EV_IRQHandler /* I2C1 Event */
<> 153:fa9ff456f731 198 .word I2C1_ER_IRQHandler /* I2C1 Error */
<> 153:fa9ff456f731 199 .word I2C2_EV_IRQHandler /* I2C2 Event */
<> 153:fa9ff456f731 200 .word I2C2_ER_IRQHandler /* I2C2 Error */
<> 153:fa9ff456f731 201 .word SPI1_IRQHandler /* SPI1 */
<> 153:fa9ff456f731 202 .word SPI2_IRQHandler /* SPI2 */
<> 153:fa9ff456f731 203 .word USART1_IRQHandler /* USART1 */
<> 153:fa9ff456f731 204 .word USART2_IRQHandler /* USART2 */
<> 153:fa9ff456f731 205 .word USART3_IRQHandler /* USART3 */
<> 153:fa9ff456f731 206 .word EXTI15_10_IRQHandler /* External Line[15:10]s */
<> 153:fa9ff456f731 207 .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
<> 153:fa9ff456f731 208 .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
<> 153:fa9ff456f731 209 .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
<> 153:fa9ff456f731 210 .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
<> 153:fa9ff456f731 211 .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
<> 153:fa9ff456f731 212 .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
<> 153:fa9ff456f731 213 .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
<> 153:fa9ff456f731 214 .word 0 /* Reserved */
<> 153:fa9ff456f731 215 .word SDIO_IRQHandler /* SDIO */
<> 153:fa9ff456f731 216 .word TIM5_IRQHandler /* TIM5 */
<> 153:fa9ff456f731 217 .word SPI3_IRQHandler /* SPI3 */
<> 153:fa9ff456f731 218 .word 0 /* Reserved */
<> 153:fa9ff456f731 219 .word 0 /* Reserved */
<> 153:fa9ff456f731 220 .word TIM6_IRQHandler /* TIM6 */
<> 153:fa9ff456f731 221 .word TIM7_IRQHandler /* TIM7 */
<> 153:fa9ff456f731 222 .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
<> 153:fa9ff456f731 223 .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
<> 153:fa9ff456f731 224 .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
<> 153:fa9ff456f731 225 .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
<> 153:fa9ff456f731 226 .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
<> 153:fa9ff456f731 227 .word DFSDM1_FLT0_IRQHandler /* DFSDM1 Filter0 */
<> 153:fa9ff456f731 228 .word DFSDM1_FLT1_IRQHandler /* DFSDM1 Filter1 */
<> 153:fa9ff456f731 229 .word CAN2_TX_IRQHandler /* CAN2 TX */
<> 153:fa9ff456f731 230 .word CAN2_RX0_IRQHandler /* CAN2 RX0 */
<> 153:fa9ff456f731 231 .word CAN2_RX1_IRQHandler /* CAN2 RX1 */
<> 153:fa9ff456f731 232 .word CAN2_SCE_IRQHandler /* CAN2 SCE */
<> 153:fa9ff456f731 233 .word OTG_FS_IRQHandler /* USB OTG FS */
<> 153:fa9ff456f731 234 .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
<> 153:fa9ff456f731 235 .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
<> 153:fa9ff456f731 236 .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
<> 153:fa9ff456f731 237 .word USART6_IRQHandler /* USART6 */
<> 153:fa9ff456f731 238 .word I2C3_EV_IRQHandler /* I2C3 event */
<> 153:fa9ff456f731 239 .word I2C3_ER_IRQHandler /* I2C3 error */
<> 153:fa9ff456f731 240 .word 0 /* Reserved */
<> 153:fa9ff456f731 241 .word 0 /* Reserved */
<> 153:fa9ff456f731 242 .word 0 /* Reserved */
<> 153:fa9ff456f731 243 .word 0 /* Reserved */
<> 153:fa9ff456f731 244 .word 0 /* Reserved */
<> 153:fa9ff456f731 245 .word 0 /* Reserved */
<> 153:fa9ff456f731 246 .word RNG_IRQHandler /* RNG */
<> 153:fa9ff456f731 247 .word FPU_IRQHandler /* FPU */
<> 153:fa9ff456f731 248 .word 0 /* Reserved */
<> 153:fa9ff456f731 249 .word 0 /* Reserved */
<> 153:fa9ff456f731 250 .word SPI4_IRQHandler /* SPI4 */
<> 153:fa9ff456f731 251 .word SPI5_IRQHandler /* SPI5 */
<> 153:fa9ff456f731 252 .word 0 /* Reserved */
<> 153:fa9ff456f731 253 .word 0 /* Reserved */
<> 153:fa9ff456f731 254 .word 0 /* Reserved */
<> 153:fa9ff456f731 255 .word 0 /* Reserved */
<> 153:fa9ff456f731 256 .word 0 /* Reserved */
<> 153:fa9ff456f731 257 .word 0 /* Reserved */
<> 153:fa9ff456f731 258 .word QUADSPI_IRQHandler /* QuadSPI */
<> 153:fa9ff456f731 259 .word 0 /* Reserved */
<> 153:fa9ff456f731 260 .word 0 /* Reserved */
<> 153:fa9ff456f731 261 .word FMPI2C1_EV_IRQHandler /* FMPI2C1 Event */
<> 153:fa9ff456f731 262 .word FMPI2C1_ER_IRQHandler /* FMPI2C1 Error */
<> 153:fa9ff456f731 263
<> 153:fa9ff456f731 264 /*******************************************************************************
<> 153:fa9ff456f731 265 *
<> 153:fa9ff456f731 266 * Provide weak aliases for each Exception handler to the Default_Handler.
<> 153:fa9ff456f731 267 * As they are weak aliases, any function with the same name will override
<> 153:fa9ff456f731 268 * this definition.
<> 153:fa9ff456f731 269 *
<> 153:fa9ff456f731 270 *******************************************************************************/
<> 153:fa9ff456f731 271 .weak NMI_Handler
<> 153:fa9ff456f731 272 .thumb_set NMI_Handler,Default_Handler
<> 153:fa9ff456f731 273
<> 153:fa9ff456f731 274 .weak HardFault_Handler
<> 153:fa9ff456f731 275 .thumb_set HardFault_Handler,Default_Handler
<> 153:fa9ff456f731 276
<> 153:fa9ff456f731 277 .weak MemManage_Handler
<> 153:fa9ff456f731 278 .thumb_set MemManage_Handler,Default_Handler
<> 153:fa9ff456f731 279
<> 153:fa9ff456f731 280 .weak BusFault_Handler
<> 153:fa9ff456f731 281 .thumb_set BusFault_Handler,Default_Handler
<> 153:fa9ff456f731 282
<> 153:fa9ff456f731 283 .weak UsageFault_Handler
<> 153:fa9ff456f731 284 .thumb_set UsageFault_Handler,Default_Handler
<> 153:fa9ff456f731 285
<> 153:fa9ff456f731 286 .weak SVC_Handler
<> 153:fa9ff456f731 287 .thumb_set SVC_Handler,Default_Handler
<> 153:fa9ff456f731 288
<> 153:fa9ff456f731 289 .weak DebugMon_Handler
<> 153:fa9ff456f731 290 .thumb_set DebugMon_Handler,Default_Handler
<> 153:fa9ff456f731 291
<> 153:fa9ff456f731 292 .weak PendSV_Handler
<> 153:fa9ff456f731 293 .thumb_set PendSV_Handler,Default_Handler
<> 153:fa9ff456f731 294
<> 153:fa9ff456f731 295 .weak SysTick_Handler
<> 153:fa9ff456f731 296 .thumb_set SysTick_Handler,Default_Handler
<> 153:fa9ff456f731 297
<> 153:fa9ff456f731 298 .weak WWDG_IRQHandler
<> 153:fa9ff456f731 299 .thumb_set WWDG_IRQHandler,Default_Handler
<> 153:fa9ff456f731 300
<> 153:fa9ff456f731 301 .weak PVD_IRQHandler
<> 153:fa9ff456f731 302 .thumb_set PVD_IRQHandler,Default_Handler
<> 153:fa9ff456f731 303
<> 153:fa9ff456f731 304 .weak TAMP_STAMP_IRQHandler
<> 153:fa9ff456f731 305 .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
<> 153:fa9ff456f731 306
<> 153:fa9ff456f731 307 .weak RTC_WKUP_IRQHandler
<> 153:fa9ff456f731 308 .thumb_set RTC_WKUP_IRQHandler,Default_Handler
<> 153:fa9ff456f731 309
<> 153:fa9ff456f731 310 .weak FLASH_IRQHandler
<> 153:fa9ff456f731 311 .thumb_set FLASH_IRQHandler,Default_Handler
<> 153:fa9ff456f731 312
<> 153:fa9ff456f731 313 .weak RCC_IRQHandler
<> 153:fa9ff456f731 314 .thumb_set RCC_IRQHandler,Default_Handler
<> 153:fa9ff456f731 315
<> 153:fa9ff456f731 316 .weak EXTI0_IRQHandler
<> 153:fa9ff456f731 317 .thumb_set EXTI0_IRQHandler,Default_Handler
<> 153:fa9ff456f731 318
<> 153:fa9ff456f731 319 .weak EXTI1_IRQHandler
<> 153:fa9ff456f731 320 .thumb_set EXTI1_IRQHandler,Default_Handler
<> 153:fa9ff456f731 321
<> 153:fa9ff456f731 322 .weak EXTI2_IRQHandler
<> 153:fa9ff456f731 323 .thumb_set EXTI2_IRQHandler,Default_Handler
<> 153:fa9ff456f731 324
<> 153:fa9ff456f731 325 .weak EXTI3_IRQHandler
<> 153:fa9ff456f731 326 .thumb_set EXTI3_IRQHandler,Default_Handler
<> 153:fa9ff456f731 327
<> 153:fa9ff456f731 328 .weak EXTI4_IRQHandler
<> 153:fa9ff456f731 329 .thumb_set EXTI4_IRQHandler,Default_Handler
<> 153:fa9ff456f731 330
<> 153:fa9ff456f731 331 .weak DMA1_Stream0_IRQHandler
<> 153:fa9ff456f731 332 .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
<> 153:fa9ff456f731 333
<> 153:fa9ff456f731 334 .weak DMA1_Stream1_IRQHandler
<> 153:fa9ff456f731 335 .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
<> 153:fa9ff456f731 336
<> 153:fa9ff456f731 337 .weak DMA1_Stream2_IRQHandler
<> 153:fa9ff456f731 338 .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
<> 153:fa9ff456f731 339
<> 153:fa9ff456f731 340 .weak DMA1_Stream3_IRQHandler
<> 153:fa9ff456f731 341 .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
<> 153:fa9ff456f731 342
<> 153:fa9ff456f731 343 .weak DMA1_Stream4_IRQHandler
<> 153:fa9ff456f731 344 .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
<> 153:fa9ff456f731 345
<> 153:fa9ff456f731 346 .weak DMA1_Stream5_IRQHandler
<> 153:fa9ff456f731 347 .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
<> 153:fa9ff456f731 348
<> 153:fa9ff456f731 349 .weak DMA1_Stream6_IRQHandler
<> 153:fa9ff456f731 350 .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
<> 153:fa9ff456f731 351
<> 153:fa9ff456f731 352 .weak ADC_IRQHandler
<> 153:fa9ff456f731 353 .thumb_set ADC_IRQHandler,Default_Handler
<> 153:fa9ff456f731 354
<> 153:fa9ff456f731 355 .weak CAN1_TX_IRQHandler
<> 153:fa9ff456f731 356 .thumb_set CAN1_TX_IRQHandler,Default_Handler
<> 153:fa9ff456f731 357
<> 153:fa9ff456f731 358 .weak CAN1_RX0_IRQHandler
<> 153:fa9ff456f731 359 .thumb_set CAN1_RX0_IRQHandler,Default_Handler
<> 153:fa9ff456f731 360
<> 153:fa9ff456f731 361 .weak CAN1_RX1_IRQHandler
<> 153:fa9ff456f731 362 .thumb_set CAN1_RX1_IRQHandler,Default_Handler
<> 153:fa9ff456f731 363
<> 153:fa9ff456f731 364 .weak CAN1_SCE_IRQHandler
<> 153:fa9ff456f731 365 .thumb_set CAN1_SCE_IRQHandler,Default_Handler
<> 153:fa9ff456f731 366
<> 153:fa9ff456f731 367 .weak EXTI9_5_IRQHandler
<> 153:fa9ff456f731 368 .thumb_set EXTI9_5_IRQHandler,Default_Handler
<> 153:fa9ff456f731 369
<> 153:fa9ff456f731 370 .weak TIM1_BRK_TIM9_IRQHandler
<> 153:fa9ff456f731 371 .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
<> 153:fa9ff456f731 372
<> 153:fa9ff456f731 373 .weak TIM1_UP_TIM10_IRQHandler
<> 153:fa9ff456f731 374 .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
<> 153:fa9ff456f731 375
<> 153:fa9ff456f731 376 .weak TIM1_TRG_COM_TIM11_IRQHandler
<> 153:fa9ff456f731 377 .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
<> 153:fa9ff456f731 378
<> 153:fa9ff456f731 379 .weak TIM1_CC_IRQHandler
<> 153:fa9ff456f731 380 .thumb_set TIM1_CC_IRQHandler,Default_Handler
<> 153:fa9ff456f731 381
<> 153:fa9ff456f731 382 .weak TIM2_IRQHandler
<> 153:fa9ff456f731 383 .thumb_set TIM2_IRQHandler,Default_Handler
<> 153:fa9ff456f731 384
<> 153:fa9ff456f731 385 .weak TIM3_IRQHandler
<> 153:fa9ff456f731 386 .thumb_set TIM3_IRQHandler,Default_Handler
<> 153:fa9ff456f731 387
<> 153:fa9ff456f731 388 .weak TIM4_IRQHandler
<> 153:fa9ff456f731 389 .thumb_set TIM4_IRQHandler,Default_Handler
<> 153:fa9ff456f731 390
<> 153:fa9ff456f731 391 .weak I2C1_EV_IRQHandler
<> 153:fa9ff456f731 392 .thumb_set I2C1_EV_IRQHandler,Default_Handler
<> 153:fa9ff456f731 393
<> 153:fa9ff456f731 394 .weak I2C1_ER_IRQHandler
<> 153:fa9ff456f731 395 .thumb_set I2C1_ER_IRQHandler,Default_Handler
<> 153:fa9ff456f731 396
<> 153:fa9ff456f731 397 .weak I2C2_EV_IRQHandler
<> 153:fa9ff456f731 398 .thumb_set I2C2_EV_IRQHandler,Default_Handler
<> 153:fa9ff456f731 399
<> 153:fa9ff456f731 400 .weak I2C2_ER_IRQHandler
<> 153:fa9ff456f731 401 .thumb_set I2C2_ER_IRQHandler,Default_Handler
<> 153:fa9ff456f731 402
<> 153:fa9ff456f731 403 .weak SPI1_IRQHandler
<> 153:fa9ff456f731 404 .thumb_set SPI1_IRQHandler,Default_Handler
<> 153:fa9ff456f731 405
<> 153:fa9ff456f731 406 .weak SPI2_IRQHandler
<> 153:fa9ff456f731 407 .thumb_set SPI2_IRQHandler,Default_Handler
<> 153:fa9ff456f731 408
<> 153:fa9ff456f731 409 .weak USART1_IRQHandler
<> 153:fa9ff456f731 410 .thumb_set USART1_IRQHandler,Default_Handler
<> 153:fa9ff456f731 411
<> 153:fa9ff456f731 412 .weak USART2_IRQHandler
<> 153:fa9ff456f731 413 .thumb_set USART2_IRQHandler,Default_Handler
<> 153:fa9ff456f731 414
<> 153:fa9ff456f731 415 .weak USART3_IRQHandler
<> 153:fa9ff456f731 416 .thumb_set USART3_IRQHandler,Default_Handler
<> 153:fa9ff456f731 417
<> 153:fa9ff456f731 418 .weak EXTI15_10_IRQHandler
<> 153:fa9ff456f731 419 .thumb_set EXTI15_10_IRQHandler,Default_Handler
<> 153:fa9ff456f731 420
<> 153:fa9ff456f731 421 .weak RTC_Alarm_IRQHandler
<> 153:fa9ff456f731 422 .thumb_set RTC_Alarm_IRQHandler,Default_Handler
<> 153:fa9ff456f731 423
<> 153:fa9ff456f731 424 .weak OTG_FS_WKUP_IRQHandler
<> 153:fa9ff456f731 425 .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
<> 153:fa9ff456f731 426
<> 153:fa9ff456f731 427 .weak TIM8_BRK_TIM12_IRQHandler
<> 153:fa9ff456f731 428 .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
<> 153:fa9ff456f731 429
<> 153:fa9ff456f731 430 .weak TIM8_UP_TIM13_IRQHandler
<> 153:fa9ff456f731 431 .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
<> 153:fa9ff456f731 432
<> 153:fa9ff456f731 433 .weak TIM8_TRG_COM_TIM14_IRQHandler
<> 153:fa9ff456f731 434 .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
<> 153:fa9ff456f731 435
<> 153:fa9ff456f731 436 .weak TIM8_CC_IRQHandler
<> 153:fa9ff456f731 437 .thumb_set TIM8_CC_IRQHandler,Default_Handler
<> 153:fa9ff456f731 438
<> 153:fa9ff456f731 439 .weak DMA1_Stream7_IRQHandler
<> 153:fa9ff456f731 440 .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
<> 153:fa9ff456f731 441
<> 153:fa9ff456f731 442 .weak SDIO_IRQHandler
<> 153:fa9ff456f731 443 .thumb_set SDIO_IRQHandler,Default_Handler
<> 153:fa9ff456f731 444
<> 153:fa9ff456f731 445 .weak TIM5_IRQHandler
<> 153:fa9ff456f731 446 .thumb_set TIM5_IRQHandler,Default_Handler
<> 153:fa9ff456f731 447
<> 153:fa9ff456f731 448 .weak SPI3_IRQHandler
<> 153:fa9ff456f731 449 .thumb_set SPI3_IRQHandler,Default_Handler
<> 153:fa9ff456f731 450
<> 153:fa9ff456f731 451 .weak TIM6_IRQHandler
<> 153:fa9ff456f731 452 .thumb_set TIM6_IRQHandler,Default_Handler
<> 153:fa9ff456f731 453
<> 153:fa9ff456f731 454 .weak TIM7_IRQHandler
<> 153:fa9ff456f731 455 .thumb_set TIM7_IRQHandler,Default_Handler
<> 153:fa9ff456f731 456
<> 153:fa9ff456f731 457 .weak DMA2_Stream0_IRQHandler
<> 153:fa9ff456f731 458 .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
<> 153:fa9ff456f731 459
<> 153:fa9ff456f731 460 .weak DMA2_Stream1_IRQHandler
<> 153:fa9ff456f731 461 .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
<> 153:fa9ff456f731 462
<> 153:fa9ff456f731 463 .weak DMA2_Stream2_IRQHandler
<> 153:fa9ff456f731 464 .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
<> 153:fa9ff456f731 465
<> 153:fa9ff456f731 466 .weak DMA2_Stream3_IRQHandler
<> 153:fa9ff456f731 467 .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
<> 153:fa9ff456f731 468
<> 153:fa9ff456f731 469 .weak DMA2_Stream4_IRQHandler
<> 153:fa9ff456f731 470 .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
<> 153:fa9ff456f731 471
<> 153:fa9ff456f731 472 .weak DFSDM1_FLT0_IRQHandler
<> 153:fa9ff456f731 473 .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
<> 153:fa9ff456f731 474
<> 153:fa9ff456f731 475 .weak DFSDM1_FLT1_IRQHandler
<> 153:fa9ff456f731 476 .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
<> 153:fa9ff456f731 477
<> 153:fa9ff456f731 478 .weak CAN2_TX_IRQHandler
<> 153:fa9ff456f731 479 .thumb_set CAN2_TX_IRQHandler,Default_Handler
<> 153:fa9ff456f731 480
<> 153:fa9ff456f731 481 .weak CAN2_RX0_IRQHandler
<> 153:fa9ff456f731 482 .thumb_set CAN2_RX0_IRQHandler,Default_Handler
<> 153:fa9ff456f731 483
<> 153:fa9ff456f731 484 .weak CAN2_RX1_IRQHandler
<> 153:fa9ff456f731 485 .thumb_set CAN2_RX1_IRQHandler,Default_Handler
<> 153:fa9ff456f731 486
<> 153:fa9ff456f731 487 .weak CAN2_SCE_IRQHandler
<> 153:fa9ff456f731 488 .thumb_set CAN2_SCE_IRQHandler,Default_Handler
<> 153:fa9ff456f731 489
<> 153:fa9ff456f731 490 .weak OTG_FS_IRQHandler
<> 153:fa9ff456f731 491 .thumb_set OTG_FS_IRQHandler,Default_Handler
<> 153:fa9ff456f731 492
<> 153:fa9ff456f731 493 .weak DMA2_Stream5_IRQHandler
<> 153:fa9ff456f731 494 .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
<> 153:fa9ff456f731 495
<> 153:fa9ff456f731 496 .weak DMA2_Stream6_IRQHandler
<> 153:fa9ff456f731 497 .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
<> 153:fa9ff456f731 498
<> 153:fa9ff456f731 499 .weak DMA2_Stream7_IRQHandler
<> 153:fa9ff456f731 500 .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
<> 153:fa9ff456f731 501
<> 153:fa9ff456f731 502 .weak USART6_IRQHandler
<> 153:fa9ff456f731 503 .thumb_set USART6_IRQHandler,Default_Handler
<> 153:fa9ff456f731 504
<> 153:fa9ff456f731 505 .weak I2C3_EV_IRQHandler
<> 153:fa9ff456f731 506 .thumb_set I2C3_EV_IRQHandler,Default_Handler
<> 153:fa9ff456f731 507
<> 153:fa9ff456f731 508 .weak I2C3_ER_IRQHandler
<> 153:fa9ff456f731 509 .thumb_set I2C3_ER_IRQHandler,Default_Handler
<> 153:fa9ff456f731 510
<> 153:fa9ff456f731 511 .weak RNG_IRQHandler
<> 153:fa9ff456f731 512 .thumb_set RNG_IRQHandler,Default_Handler
<> 153:fa9ff456f731 513
<> 153:fa9ff456f731 514 .weak FPU_IRQHandler
<> 153:fa9ff456f731 515 .thumb_set FPU_IRQHandler,Default_Handler
<> 153:fa9ff456f731 516
<> 153:fa9ff456f731 517 .weak SPI4_IRQHandler
<> 153:fa9ff456f731 518 .thumb_set SPI4_IRQHandler,Default_Handler
<> 153:fa9ff456f731 519
<> 153:fa9ff456f731 520 .weak SPI5_IRQHandler
<> 153:fa9ff456f731 521 .thumb_set SPI5_IRQHandler,Default_Handler
<> 153:fa9ff456f731 522
<> 153:fa9ff456f731 523 .weak QUADSPI_IRQHandler
<> 153:fa9ff456f731 524 .thumb_set QUADSPI_IRQHandler,Default_Handler
<> 153:fa9ff456f731 525
<> 153:fa9ff456f731 526 .weak FMPI2C1_EV_IRQHandler
<> 153:fa9ff456f731 527 .thumb_set FMPI2C1_EV_IRQHandler,Default_Handler
<> 153:fa9ff456f731 528
<> 153:fa9ff456f731 529 .weak FMPI2C1_ER_IRQHandler
<> 153:fa9ff456f731 530 .thumb_set FMPI2C1_ER_IRQHandler,Default_Handler
<> 153:fa9ff456f731 531 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/