João Victor / stm32f4-discovery-CAN-Activation

Fork of mbed-dev by mbed official

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
124:6a4a5b7d7324
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_rcc.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.0.4
<> 144:ef7eb2e8f9f7 6 * @date 29-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief RCC HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Reset and Clock Control (RCC) peripheral:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 @verbatim
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15 ##### RCC specific features #####
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17 [..]
<> 144:ef7eb2e8f9f7 18 After reset the device is running from Internal High Speed oscillator
<> 144:ef7eb2e8f9f7 19 (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled,
<> 144:ef7eb2e8f9f7 20 and all peripherals are off except internal SRAM, Flash and JTAG.
<> 144:ef7eb2e8f9f7 21 (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;
<> 144:ef7eb2e8f9f7 22 all peripherals mapped on these buses are running at HSI speed.
<> 144:ef7eb2e8f9f7 23 (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
<> 144:ef7eb2e8f9f7 24 (+) All GPIOs are in input floating state, except the JTAG pins which
<> 144:ef7eb2e8f9f7 25 are assigned to be used for debug purpose.
<> 144:ef7eb2e8f9f7 26 [..] Once the device started from reset, the user application has to:
<> 144:ef7eb2e8f9f7 27 (+) Configure the clock source to be used to drive the System clock
<> 144:ef7eb2e8f9f7 28 (if the application needs higher frequency/performance)
<> 144:ef7eb2e8f9f7 29 (+) Configure the System clock frequency and Flash settings
<> 144:ef7eb2e8f9f7 30 (+) Configure the AHB and APB buses prescalers
<> 144:ef7eb2e8f9f7 31 (+) Enable the clock for the peripheral(s) to be used
<> 144:ef7eb2e8f9f7 32 (+) Configure the clock source(s) for peripherals whose clocks are not
<> 144:ef7eb2e8f9f7 33 derived from the System clock (I2S, RTC, ADC, USB OTG FS)
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 ##### RCC Limitations #####
<> 144:ef7eb2e8f9f7 36 ==============================================================================
<> 144:ef7eb2e8f9f7 37 [..]
<> 144:ef7eb2e8f9f7 38 A delay between an RCC peripheral clock enable and the effective peripheral
<> 144:ef7eb2e8f9f7 39 enabling should be taken into account in order to manage the peripheral read/write
<> 144:ef7eb2e8f9f7 40 from/to registers.
<> 144:ef7eb2e8f9f7 41 (+) This delay depends on the peripheral mapping.
<> 144:ef7eb2e8f9f7 42 (++) AHB & APB peripherals, 1 dummy read is necessary
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 [..]
<> 144:ef7eb2e8f9f7 45 Workarounds:
<> 144:ef7eb2e8f9f7 46 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
<> 144:ef7eb2e8f9f7 47 inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 @endverbatim
<> 144:ef7eb2e8f9f7 50 ******************************************************************************
<> 144:ef7eb2e8f9f7 51 * @attention
<> 144:ef7eb2e8f9f7 52 *
<> 144:ef7eb2e8f9f7 53 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 54 *
<> 144:ef7eb2e8f9f7 55 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 56 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 57 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 58 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 59 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 60 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 61 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 62 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 63 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 64 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 65 *
<> 144:ef7eb2e8f9f7 66 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 67 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 68 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 69 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 70 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 71 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 72 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 73 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 74 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 75 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 76 *
<> 144:ef7eb2e8f9f7 77 ******************************************************************************
<> 144:ef7eb2e8f9f7 78 */
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 81 #include "stm32f1xx_hal.h"
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 84 * @{
<> 144:ef7eb2e8f9f7 85 */
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /** @defgroup RCC RCC
<> 144:ef7eb2e8f9f7 88 * @brief RCC HAL module driver
<> 144:ef7eb2e8f9f7 89 * @{
<> 144:ef7eb2e8f9f7 90 */
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 #ifdef HAL_RCC_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 95 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 96 /** @defgroup RCC_Private_Constants RCC Private Constants
<> 144:ef7eb2e8f9f7 97 * @{
<> 144:ef7eb2e8f9f7 98 */
<> 144:ef7eb2e8f9f7 99 /* Bits position in in the CFGR register */
<> 144:ef7eb2e8f9f7 100 #define RCC_CFGR_HPRE_BITNUMBER POSITION_VAL(RCC_CFGR_HPRE)
<> 144:ef7eb2e8f9f7 101 #define RCC_CFGR_PPRE1_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE1)
<> 144:ef7eb2e8f9f7 102 #define RCC_CFGR_PPRE2_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE2)
<> 144:ef7eb2e8f9f7 103 /**
<> 144:ef7eb2e8f9f7 104 * @}
<> 144:ef7eb2e8f9f7 105 */
<> 144:ef7eb2e8f9f7 106 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 107 /** @defgroup RCC_Private_Macros RCC Private Macros
<> 144:ef7eb2e8f9f7 108 * @{
<> 144:ef7eb2e8f9f7 109 */
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 #define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
<> 144:ef7eb2e8f9f7 112 #define MCO1_GPIO_PORT GPIOA
<> 144:ef7eb2e8f9f7 113 #define MCO1_PIN GPIO_PIN_8
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 /**
<> 144:ef7eb2e8f9f7 116 * @}
<> 144:ef7eb2e8f9f7 117 */
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 120 /** @defgroup RCC_Private_Variables RCC Private Variables
<> 144:ef7eb2e8f9f7 121 * @{
<> 144:ef7eb2e8f9f7 122 */
<> 144:ef7eb2e8f9f7 123 /**
<> 144:ef7eb2e8f9f7 124 * @}
<> 144:ef7eb2e8f9f7 125 */
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 128 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /** @defgroup RCC_Exported_Functions RCC Exported Functions
<> 144:ef7eb2e8f9f7 131 * @{
<> 144:ef7eb2e8f9f7 132 */
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 135 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 136 *
<> 144:ef7eb2e8f9f7 137 @verbatim
<> 144:ef7eb2e8f9f7 138 ===============================================================================
<> 144:ef7eb2e8f9f7 139 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 140 ===============================================================================
<> 144:ef7eb2e8f9f7 141 [..]
<> 144:ef7eb2e8f9f7 142 This section provides functions allowing to configure the internal/external oscillators
<> 144:ef7eb2e8f9f7 143 (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
<> 144:ef7eb2e8f9f7 144 and APB2).
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 [..] Internal/external clock and PLL configuration
<> 144:ef7eb2e8f9f7 147 (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through
<> 144:ef7eb2e8f9f7 148 the PLL as System clock source.
<> 144:ef7eb2e8f9f7 149 (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC
<> 144:ef7eb2e8f9f7 150 clock source.
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 (#) HSE (high-speed external), 4 to 24 MHz (STM32F100xx) or 4 to 16 MHz (STM32F101x/STM32F102x/STM32F103x) or 3 to 25 MHz (STM32F105x/STM32F107x) crystal oscillator used directly or
<> 144:ef7eb2e8f9f7 153 through the PLL as System clock source. Can be used also as RTC clock source.
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 (#) PLL (clocked by HSI or HSE), featuring different output clocks:
<> 144:ef7eb2e8f9f7 158 (++) The first output is used to generate the high speed system clock (up to 72 MHz for STM32F10xxx or up to 24 MHz for STM32F100xx)
<> 144:ef7eb2e8f9f7 159 (++) The second output is used to generate the clock for the USB OTG FS (48 MHz)
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
<> 144:ef7eb2e8f9f7 162 and if a HSE clock failure occurs(HSE used directly or through PLL as System
<> 144:ef7eb2e8f9f7 163 clock source), the System clocks automatically switched to HSI and an interrupt
<> 144:ef7eb2e8f9f7 164 is generated if enabled. The interrupt is linked to the Cortex-M3 NMI
<> 144:ef7eb2e8f9f7 165 (Non-Maskable Interrupt) exception vector.
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI,
<> 144:ef7eb2e8f9f7 168 HSE or PLL clock (divided by 2) on PA8 pin + PLL2CLK, PLL3CLK/2, PLL3CLK and XTI for STM32F105x/STM32F107x
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 [..] System, AHB and APB buses clocks configuration
<> 144:ef7eb2e8f9f7 171 (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
<> 144:ef7eb2e8f9f7 172 HSE and PLL.
<> 144:ef7eb2e8f9f7 173 The AHB clock (HCLK) is derived from System clock through configurable
<> 144:ef7eb2e8f9f7 174 prescaler and used to clock the CPU, memory and peripherals mapped
<> 144:ef7eb2e8f9f7 175 on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
<> 144:ef7eb2e8f9f7 176 from AHB clock through configurable prescalers and used to clock
<> 144:ef7eb2e8f9f7 177 the peripherals mapped on these buses. You can use
<> 144:ef7eb2e8f9f7 178 "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
<> 144:ef7eb2e8f9f7 181 (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock
<> 144:ef7eb2e8f9f7 182 divided by 128.
<> 144:ef7eb2e8f9f7 183 (+@) USB OTG FS and RTC: USB OTG FS require a frequency equal to 48 MHz
<> 144:ef7eb2e8f9f7 184 to work correctly. This clock is derived of the main PLL through PLL Multiplier.
<> 144:ef7eb2e8f9f7 185 (+@) I2S interface on STM32F105x/STM32F107x can be derived from PLL3CLK
<> 144:ef7eb2e8f9f7 186 (+@) IWDG clock which is always the LSI clock.
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 (#) For STM32F10xxx, the maximum frequency of the SYSCLK and HCLK/PCLK2 is 72 MHz, PCLK1 36 MHz.
<> 144:ef7eb2e8f9f7 189 For STM32F100xx, the maximum frequency of the SYSCLK and HCLK/PCLK1/PCLK2 is 24 MHz.
<> 144:ef7eb2e8f9f7 190 Depending on the SYSCLK frequency, the flash latency should be adapted accordingly.
<> 144:ef7eb2e8f9f7 191 @endverbatim
<> 144:ef7eb2e8f9f7 192 * @{
<> 144:ef7eb2e8f9f7 193 */
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 /*
<> 144:ef7eb2e8f9f7 196 Additional consideration on the SYSCLK based on Latency settings:
<> 144:ef7eb2e8f9f7 197 +-----------------------------------------------+
<> 144:ef7eb2e8f9f7 198 | Latency | SYSCLK clock frequency (MHz) |
<> 144:ef7eb2e8f9f7 199 |---------------|-------------------------------|
<> 144:ef7eb2e8f9f7 200 |0WS(1CPU cycle)| 0 < SYSCLK <= 24 |
<> 144:ef7eb2e8f9f7 201 |---------------|-------------------------------|
<> 144:ef7eb2e8f9f7 202 |1WS(2CPU cycle)| 24 < SYSCLK <= 48 |
<> 144:ef7eb2e8f9f7 203 |---------------|-------------------------------|
<> 144:ef7eb2e8f9f7 204 |2WS(3CPU cycle)| 48 < SYSCLK <= 72 |
<> 144:ef7eb2e8f9f7 205 +-----------------------------------------------+
<> 144:ef7eb2e8f9f7 206 */
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 /**
<> 144:ef7eb2e8f9f7 209 * @brief Resets the RCC clock configuration to the default reset state.
<> 144:ef7eb2e8f9f7 210 * @note The default reset state of the clock configuration is given below:
<> 144:ef7eb2e8f9f7 211 * - HSI ON and used as system clock source
<> 144:ef7eb2e8f9f7 212 * - HSE and PLL OFF
<> 144:ef7eb2e8f9f7 213 * - AHB, APB1 and APB2 prescaler set to 1.
<> 144:ef7eb2e8f9f7 214 * - CSS and MCO1 OFF
<> 144:ef7eb2e8f9f7 215 * - All interrupts disabled
<> 144:ef7eb2e8f9f7 216 * @note This function does not modify the configuration of the
<> 144:ef7eb2e8f9f7 217 * - Peripheral clocks
<> 144:ef7eb2e8f9f7 218 * - LSI, LSE and RTC clocks
<> 144:ef7eb2e8f9f7 219 * @retval None
<> 144:ef7eb2e8f9f7 220 */
<> 144:ef7eb2e8f9f7 221 void HAL_RCC_DeInit(void)
<> 144:ef7eb2e8f9f7 222 {
<> 144:ef7eb2e8f9f7 223 /* Switch SYSCLK to HSI */
<> 144:ef7eb2e8f9f7 224 CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW);
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 /* Reset HSEON, CSSON, & PLLON bits */
<> 144:ef7eb2e8f9f7 227 CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 /* Reset HSEBYP bit */
<> 144:ef7eb2e8f9f7 230 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 /* Reset CFGR register */
<> 144:ef7eb2e8f9f7 233 CLEAR_REG(RCC->CFGR);
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 /* Set HSITRIM bits to the reset value */
<> 144:ef7eb2e8f9f7 236 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, ((uint32_t)0x10 << POSITION_VAL(RCC_CR_HSITRIM)));
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 #if (defined(STM32F105xC) || defined(STM32F107xC) || defined (STM32F100xB) || defined (STM32F100xE))
<> 144:ef7eb2e8f9f7 239 /* Reset CFGR2 register */
<> 144:ef7eb2e8f9f7 240 CLEAR_REG(RCC->CFGR2);
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
<> 144:ef7eb2e8f9f7 243 /* Disable all interrupts */
<> 144:ef7eb2e8f9f7 244 CLEAR_REG(RCC->CIR);
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /* Update the SystemCoreClock global variable */
<> 144:ef7eb2e8f9f7 247 SystemCoreClock = HSI_VALUE;
<> 144:ef7eb2e8f9f7 248 }
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 /**
<> 144:ef7eb2e8f9f7 251 * @brief Initializes the RCC Oscillators according to the specified parameters in the
<> 144:ef7eb2e8f9f7 252 * RCC_OscInitTypeDef.
<> 144:ef7eb2e8f9f7 253 * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
<> 144:ef7eb2e8f9f7 254 * contains the configuration information for the RCC Oscillators.
<> 144:ef7eb2e8f9f7 255 * @note The PLL is not disabled when used as system clock.
<> 144:ef7eb2e8f9f7 256 * @note The PLL is not disabled when USB OTG FS clock is enabled (specific to devices with USB FS)
<> 144:ef7eb2e8f9f7 257 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
<> 144:ef7eb2e8f9f7 258 * supported by this macro. User should request a transition to LSE Off
<> 144:ef7eb2e8f9f7 259 * first and then LSE On or LSE Bypass.
<> 144:ef7eb2e8f9f7 260 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
<> 144:ef7eb2e8f9f7 261 * supported by this macro. User should request a transition to HSE Off
<> 144:ef7eb2e8f9f7 262 * first and then HSE On or HSE Bypass.
<> 144:ef7eb2e8f9f7 263 * @retval HAL status
<> 144:ef7eb2e8f9f7 264 */
<> 144:ef7eb2e8f9f7 265 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
<> 144:ef7eb2e8f9f7 266 {
<> 144:ef7eb2e8f9f7 267 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 /* Check the parameters */
<> 144:ef7eb2e8f9f7 270 assert_param(RCC_OscInitStruct != NULL);
<> 144:ef7eb2e8f9f7 271 assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 /*------------------------------- HSE Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 274 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
<> 144:ef7eb2e8f9f7 275 {
<> 144:ef7eb2e8f9f7 276 /* Check the parameters */
<> 144:ef7eb2e8f9f7 277 assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
<> 144:ef7eb2e8f9f7 280 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
<> 144:ef7eb2e8f9f7 281 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
<> 144:ef7eb2e8f9f7 282 {
<> 144:ef7eb2e8f9f7 283 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
<> 144:ef7eb2e8f9f7 284 {
<> 144:ef7eb2e8f9f7 285 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 286 }
<> 144:ef7eb2e8f9f7 287 }
<> 144:ef7eb2e8f9f7 288 else
<> 144:ef7eb2e8f9f7 289 {
<> 144:ef7eb2e8f9f7 290 /* Set the new HSE configuration ---------------------------------------*/
<> 144:ef7eb2e8f9f7 291 __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294 /* Check the HSE State */
<> 144:ef7eb2e8f9f7 295 if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
<> 144:ef7eb2e8f9f7 296 {
<> 144:ef7eb2e8f9f7 297 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 298 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /* Wait till HSE is ready */
<> 144:ef7eb2e8f9f7 301 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
<> 144:ef7eb2e8f9f7 302 {
<> 144:ef7eb2e8f9f7 303 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 304 {
<> 144:ef7eb2e8f9f7 305 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 306 }
<> 144:ef7eb2e8f9f7 307 }
<> 144:ef7eb2e8f9f7 308 }
<> 144:ef7eb2e8f9f7 309 else
<> 144:ef7eb2e8f9f7 310 {
<> 144:ef7eb2e8f9f7 311 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 312 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 /* Wait till HSE is disabled */
<> 144:ef7eb2e8f9f7 315 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
<> 144:ef7eb2e8f9f7 316 {
<> 144:ef7eb2e8f9f7 317 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 318 {
<> 144:ef7eb2e8f9f7 319 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 320 }
<> 144:ef7eb2e8f9f7 321 }
<> 144:ef7eb2e8f9f7 322 }
<> 144:ef7eb2e8f9f7 323 }
<> 144:ef7eb2e8f9f7 324 }
<> 144:ef7eb2e8f9f7 325 /*----------------------------- HSI Configuration --------------------------*/
<> 144:ef7eb2e8f9f7 326 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
<> 144:ef7eb2e8f9f7 327 {
<> 144:ef7eb2e8f9f7 328 /* Check the parameters */
<> 144:ef7eb2e8f9f7 329 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
<> 144:ef7eb2e8f9f7 330 assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
<> 144:ef7eb2e8f9f7 333 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
<> 144:ef7eb2e8f9f7 334 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
<> 144:ef7eb2e8f9f7 335 {
<> 144:ef7eb2e8f9f7 336 /* When HSI is used as system clock it will not disabled */
<> 144:ef7eb2e8f9f7 337 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
<> 144:ef7eb2e8f9f7 338 {
<> 144:ef7eb2e8f9f7 339 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 340 }
<> 144:ef7eb2e8f9f7 341 /* Otherwise, just the calibration is allowed */
<> 144:ef7eb2e8f9f7 342 else
<> 144:ef7eb2e8f9f7 343 {
<> 144:ef7eb2e8f9f7 344 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
<> 144:ef7eb2e8f9f7 345 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
<> 144:ef7eb2e8f9f7 346 }
<> 144:ef7eb2e8f9f7 347 }
<> 144:ef7eb2e8f9f7 348 else
<> 144:ef7eb2e8f9f7 349 {
<> 144:ef7eb2e8f9f7 350 /* Check the HSI State */
<> 144:ef7eb2e8f9f7 351 if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
<> 144:ef7eb2e8f9f7 352 {
<> 144:ef7eb2e8f9f7 353 /* Enable the Internal High Speed oscillator (HSI). */
<> 144:ef7eb2e8f9f7 354 __HAL_RCC_HSI_ENABLE();
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 357 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 /* Wait till HSI is ready */
<> 144:ef7eb2e8f9f7 360 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
<> 144:ef7eb2e8f9f7 361 {
<> 144:ef7eb2e8f9f7 362 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 363 {
<> 144:ef7eb2e8f9f7 364 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 365 }
<> 144:ef7eb2e8f9f7 366 }
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
<> 144:ef7eb2e8f9f7 369 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
<> 144:ef7eb2e8f9f7 370 }
<> 144:ef7eb2e8f9f7 371 else
<> 144:ef7eb2e8f9f7 372 {
<> 144:ef7eb2e8f9f7 373 /* Disable the Internal High Speed oscillator (HSI). */
<> 144:ef7eb2e8f9f7 374 __HAL_RCC_HSI_DISABLE();
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 377 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 378
<> 144:ef7eb2e8f9f7 379 /* Wait till HSI is disabled */
<> 144:ef7eb2e8f9f7 380 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
<> 144:ef7eb2e8f9f7 381 {
<> 144:ef7eb2e8f9f7 382 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 383 {
<> 144:ef7eb2e8f9f7 384 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 385 }
<> 144:ef7eb2e8f9f7 386 }
<> 144:ef7eb2e8f9f7 387 }
<> 144:ef7eb2e8f9f7 388 }
<> 144:ef7eb2e8f9f7 389 }
<> 144:ef7eb2e8f9f7 390 /*------------------------------ LSI Configuration -------------------------*/
<> 144:ef7eb2e8f9f7 391 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
<> 144:ef7eb2e8f9f7 392 {
<> 144:ef7eb2e8f9f7 393 /* Check the parameters */
<> 144:ef7eb2e8f9f7 394 assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 /* Check the LSI State */
<> 144:ef7eb2e8f9f7 397 if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
<> 144:ef7eb2e8f9f7 398 {
<> 144:ef7eb2e8f9f7 399 /* Enable the Internal Low Speed oscillator (LSI). */
<> 144:ef7eb2e8f9f7 400 __HAL_RCC_LSI_ENABLE();
<> 144:ef7eb2e8f9f7 401
<> 144:ef7eb2e8f9f7 402 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 403 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 404
<> 144:ef7eb2e8f9f7 405 /* Wait till LSI is ready */
<> 144:ef7eb2e8f9f7 406 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
<> 144:ef7eb2e8f9f7 407 {
<> 144:ef7eb2e8f9f7 408 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 409 {
<> 144:ef7eb2e8f9f7 410 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 411 }
<> 144:ef7eb2e8f9f7 412 }
<> 144:ef7eb2e8f9f7 413 /* To have a fully stabilized clock in the specified range, a software delay of 1ms
<> 144:ef7eb2e8f9f7 414 should be added.*/
<> 144:ef7eb2e8f9f7 415 HAL_Delay(1);
<> 144:ef7eb2e8f9f7 416 }
<> 144:ef7eb2e8f9f7 417 else
<> 144:ef7eb2e8f9f7 418 {
<> 144:ef7eb2e8f9f7 419 /* Disable the Internal Low Speed oscillator (LSI). */
<> 144:ef7eb2e8f9f7 420 __HAL_RCC_LSI_DISABLE();
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 423 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 /* Wait till LSI is disabled */
<> 144:ef7eb2e8f9f7 426 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
<> 144:ef7eb2e8f9f7 427 {
<> 144:ef7eb2e8f9f7 428 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 429 {
<> 144:ef7eb2e8f9f7 430 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 431 }
<> 144:ef7eb2e8f9f7 432 }
<> 144:ef7eb2e8f9f7 433 }
<> 144:ef7eb2e8f9f7 434 }
<> 144:ef7eb2e8f9f7 435 /*------------------------------ LSE Configuration -------------------------*/
<> 144:ef7eb2e8f9f7 436 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
<> 144:ef7eb2e8f9f7 437 {
<> 144:ef7eb2e8f9f7 438 /* Check the parameters */
<> 144:ef7eb2e8f9f7 439 assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 /* Enable Power Clock*/
<> 144:ef7eb2e8f9f7 442 __HAL_RCC_PWR_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 /* Enable write access to Backup domain */
<> 144:ef7eb2e8f9f7 445 SET_BIT(PWR->CR, PWR_CR_DBP);
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 /* Wait for Backup domain Write protection disable */
<> 144:ef7eb2e8f9f7 448 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450 while((PWR->CR & PWR_CR_DBP) == RESET)
<> 144:ef7eb2e8f9f7 451 {
<> 144:ef7eb2e8f9f7 452 if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 453 {
<> 144:ef7eb2e8f9f7 454 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 455 }
<> 144:ef7eb2e8f9f7 456 }
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 /* Set the new LSE configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 459 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
<> 144:ef7eb2e8f9f7 460 /* Check the LSE State */
<> 144:ef7eb2e8f9f7 461 if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
<> 144:ef7eb2e8f9f7 462 {
<> 144:ef7eb2e8f9f7 463 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 464 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /* Wait till LSE is ready */
<> 144:ef7eb2e8f9f7 467 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
<> 144:ef7eb2e8f9f7 468 {
<> 144:ef7eb2e8f9f7 469 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 470 {
<> 144:ef7eb2e8f9f7 471 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 472 }
<> 144:ef7eb2e8f9f7 473 }
<> 144:ef7eb2e8f9f7 474 }
<> 144:ef7eb2e8f9f7 475 else
<> 144:ef7eb2e8f9f7 476 {
<> 144:ef7eb2e8f9f7 477 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 478 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 479
<> 144:ef7eb2e8f9f7 480 /* Wait till LSE is disabled */
<> 144:ef7eb2e8f9f7 481 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
<> 144:ef7eb2e8f9f7 482 {
<> 144:ef7eb2e8f9f7 483 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 484 {
<> 144:ef7eb2e8f9f7 485 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 486 }
<> 144:ef7eb2e8f9f7 487 }
<> 144:ef7eb2e8f9f7 488 }
<> 144:ef7eb2e8f9f7 489 }
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 #if defined(RCC_CR_PLL2ON)
<> 144:ef7eb2e8f9f7 492 /*-------------------------------- PLL2 Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 493 /* Check the parameters */
<> 144:ef7eb2e8f9f7 494 assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State));
<> 144:ef7eb2e8f9f7 495 if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE)
<> 144:ef7eb2e8f9f7 496 {
<> 144:ef7eb2e8f9f7 497 /* This bit can not be cleared if the PLL2 clock is used indirectly as system
<> 144:ef7eb2e8f9f7 498 clock (i.e. it is used as PLL clock entry that is used as system clock). */
<> 144:ef7eb2e8f9f7 499 if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
<> 144:ef7eb2e8f9f7 500 (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
<> 144:ef7eb2e8f9f7 501 ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
<> 144:ef7eb2e8f9f7 502 {
<> 144:ef7eb2e8f9f7 503 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 504 }
<> 144:ef7eb2e8f9f7 505 else
<> 144:ef7eb2e8f9f7 506 {
<> 144:ef7eb2e8f9f7 507 if((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON)
<> 144:ef7eb2e8f9f7 508 {
<> 144:ef7eb2e8f9f7 509 /* Check the parameters */
<> 144:ef7eb2e8f9f7 510 assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL));
<> 144:ef7eb2e8f9f7 511 assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value));
<> 144:ef7eb2e8f9f7 512
<> 144:ef7eb2e8f9f7 513 /* Prediv2 can be written only when the PLLI2S is disabled. */
<> 144:ef7eb2e8f9f7 514 /* Return an error only if new value is different from the programmed value */
<> 144:ef7eb2e8f9f7 515 if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL3ON) && \
<> 144:ef7eb2e8f9f7 516 (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value))
<> 144:ef7eb2e8f9f7 517 {
<> 144:ef7eb2e8f9f7 518 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 519 }
<> 144:ef7eb2e8f9f7 520
<> 144:ef7eb2e8f9f7 521 /* Disable the main PLL2. */
<> 144:ef7eb2e8f9f7 522 __HAL_RCC_PLL2_DISABLE();
<> 144:ef7eb2e8f9f7 523
<> 144:ef7eb2e8f9f7 524 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 525 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527 /* Wait till PLL2 is disabled */
<> 144:ef7eb2e8f9f7 528 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
<> 144:ef7eb2e8f9f7 529 {
<> 144:ef7eb2e8f9f7 530 if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 531 {
<> 144:ef7eb2e8f9f7 532 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 533 }
<> 144:ef7eb2e8f9f7 534 }
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 /* Configure the HSE prediv2 factor --------------------------------*/
<> 144:ef7eb2e8f9f7 537 __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value);
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539 /* Configure the main PLL2 multiplication factors. */
<> 144:ef7eb2e8f9f7 540 __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL);
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 /* Enable the main PLL2. */
<> 144:ef7eb2e8f9f7 543 __HAL_RCC_PLL2_ENABLE();
<> 144:ef7eb2e8f9f7 544
<> 144:ef7eb2e8f9f7 545 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 546 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 547
<> 144:ef7eb2e8f9f7 548 /* Wait till PLL2 is ready */
<> 144:ef7eb2e8f9f7 549 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET)
<> 144:ef7eb2e8f9f7 550 {
<> 144:ef7eb2e8f9f7 551 if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 552 {
<> 144:ef7eb2e8f9f7 553 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 554 }
<> 144:ef7eb2e8f9f7 555 }
<> 144:ef7eb2e8f9f7 556 }
<> 144:ef7eb2e8f9f7 557 else
<> 144:ef7eb2e8f9f7 558 {
<> 144:ef7eb2e8f9f7 559 /* Set PREDIV1 source to HSE */
<> 144:ef7eb2e8f9f7 560 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC);
<> 144:ef7eb2e8f9f7 561
<> 144:ef7eb2e8f9f7 562 /* Disable the main PLL2. */
<> 144:ef7eb2e8f9f7 563 __HAL_RCC_PLL2_DISABLE();
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 566 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 /* Wait till PLL2 is disabled */
<> 144:ef7eb2e8f9f7 569 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
<> 144:ef7eb2e8f9f7 570 {
<> 144:ef7eb2e8f9f7 571 if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 572 {
<> 144:ef7eb2e8f9f7 573 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 574 }
<> 144:ef7eb2e8f9f7 575 }
<> 144:ef7eb2e8f9f7 576 }
<> 144:ef7eb2e8f9f7 577 }
<> 144:ef7eb2e8f9f7 578 }
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 #endif /* RCC_CR_PLL2ON */
<> 144:ef7eb2e8f9f7 581 /*-------------------------------- PLL Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 582 /* Check the parameters */
<> 144:ef7eb2e8f9f7 583 assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
<> 144:ef7eb2e8f9f7 584 if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
<> 144:ef7eb2e8f9f7 585 {
<> 144:ef7eb2e8f9f7 586 /* Check if the PLL is used as system clock or not */
<> 144:ef7eb2e8f9f7 587 if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
<> 144:ef7eb2e8f9f7 588 {
<> 144:ef7eb2e8f9f7 589 if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
<> 144:ef7eb2e8f9f7 590 {
<> 144:ef7eb2e8f9f7 591 /* Check the parameters */
<> 144:ef7eb2e8f9f7 592 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
<> 144:ef7eb2e8f9f7 593 assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 /* Disable the main PLL. */
<> 144:ef7eb2e8f9f7 596 __HAL_RCC_PLL_DISABLE();
<> 144:ef7eb2e8f9f7 597
<> 144:ef7eb2e8f9f7 598 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 599 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 600
<> 144:ef7eb2e8f9f7 601 /* Wait till PLL is disabled */
<> 144:ef7eb2e8f9f7 602 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
<> 144:ef7eb2e8f9f7 603 {
<> 144:ef7eb2e8f9f7 604 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 605 {
<> 144:ef7eb2e8f9f7 606 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 607 }
<> 144:ef7eb2e8f9f7 608 }
<> 144:ef7eb2e8f9f7 609
<> 144:ef7eb2e8f9f7 610 /* Configure the HSE prediv factor --------------------------------*/
<> 144:ef7eb2e8f9f7 611 /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
<> 144:ef7eb2e8f9f7 612 if(RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
<> 144:ef7eb2e8f9f7 613 {
<> 144:ef7eb2e8f9f7 614 /* Check the parameter */
<> 144:ef7eb2e8f9f7 615 assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue));
<> 144:ef7eb2e8f9f7 616 #if defined(RCC_CFGR2_PREDIV1SRC)
<> 144:ef7eb2e8f9f7 617 assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source));
<> 144:ef7eb2e8f9f7 618
<> 144:ef7eb2e8f9f7 619 /* Set PREDIV1 source */
<> 144:ef7eb2e8f9f7 620 SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
<> 144:ef7eb2e8f9f7 621 #endif /* RCC_CFGR2_PREDIV1SRC */
<> 144:ef7eb2e8f9f7 622
<> 144:ef7eb2e8f9f7 623 /* Set PREDIV1 Value */
<> 144:ef7eb2e8f9f7 624 __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
<> 144:ef7eb2e8f9f7 625 }
<> 144:ef7eb2e8f9f7 626
<> 144:ef7eb2e8f9f7 627 /* Configure the main PLL clock source and multiplication factors. */
<> 144:ef7eb2e8f9f7 628 __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
<> 144:ef7eb2e8f9f7 629 RCC_OscInitStruct->PLL.PLLMUL);
<> 144:ef7eb2e8f9f7 630 /* Enable the main PLL. */
<> 144:ef7eb2e8f9f7 631 __HAL_RCC_PLL_ENABLE();
<> 144:ef7eb2e8f9f7 632
<> 144:ef7eb2e8f9f7 633 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 634 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 635
<> 144:ef7eb2e8f9f7 636 /* Wait till PLL is ready */
<> 144:ef7eb2e8f9f7 637 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
<> 144:ef7eb2e8f9f7 638 {
<> 144:ef7eb2e8f9f7 639 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 640 {
<> 144:ef7eb2e8f9f7 641 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 642 }
<> 144:ef7eb2e8f9f7 643 }
<> 144:ef7eb2e8f9f7 644 }
<> 144:ef7eb2e8f9f7 645 else
<> 144:ef7eb2e8f9f7 646 {
<> 144:ef7eb2e8f9f7 647 /* Disable the main PLL. */
<> 144:ef7eb2e8f9f7 648 __HAL_RCC_PLL_DISABLE();
<> 144:ef7eb2e8f9f7 649
<> 144:ef7eb2e8f9f7 650 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 651 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 652
<> 144:ef7eb2e8f9f7 653 /* Wait till PLL is disabled */
<> 144:ef7eb2e8f9f7 654 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
<> 144:ef7eb2e8f9f7 655 {
<> 144:ef7eb2e8f9f7 656 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 657 {
<> 144:ef7eb2e8f9f7 658 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 659 }
<> 144:ef7eb2e8f9f7 660 }
<> 144:ef7eb2e8f9f7 661 }
<> 144:ef7eb2e8f9f7 662 }
<> 144:ef7eb2e8f9f7 663 else
<> 144:ef7eb2e8f9f7 664 {
<> 144:ef7eb2e8f9f7 665 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 666 }
<> 144:ef7eb2e8f9f7 667 }
<> 144:ef7eb2e8f9f7 668
<> 144:ef7eb2e8f9f7 669 return HAL_OK;
<> 144:ef7eb2e8f9f7 670 }
<> 144:ef7eb2e8f9f7 671
<> 144:ef7eb2e8f9f7 672 /**
<> 144:ef7eb2e8f9f7 673 * @brief Initializes the CPU, AHB and APB buses clocks according to the specified
<> 144:ef7eb2e8f9f7 674 * parameters in the RCC_ClkInitStruct.
<> 144:ef7eb2e8f9f7 675 * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
<> 144:ef7eb2e8f9f7 676 * contains the configuration information for the RCC peripheral.
<> 144:ef7eb2e8f9f7 677 * @param FLatency FLASH Latency
<> 144:ef7eb2e8f9f7 678 * The value of this parameter depend on device used within the same series
<> 144:ef7eb2e8f9f7 679 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
<> 144:ef7eb2e8f9f7 680 * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function
<> 144:ef7eb2e8f9f7 681 *
<> 144:ef7eb2e8f9f7 682 * @note The HSI is used (enabled by hardware) as system clock source after
<> 144:ef7eb2e8f9f7 683 * start-up from Reset, wake-up from STOP and STANDBY mode, or in case
<> 144:ef7eb2e8f9f7 684 * of failure of the HSE used directly or indirectly as system clock
<> 144:ef7eb2e8f9f7 685 * (if the Clock Security System CSS is enabled).
<> 144:ef7eb2e8f9f7 686 *
<> 144:ef7eb2e8f9f7 687 * @note A switch from one clock source to another occurs only if the target
<> 144:ef7eb2e8f9f7 688 * clock source is ready (clock stable after start-up delay or PLL locked).
<> 144:ef7eb2e8f9f7 689 * If a clock source which is not yet ready is selected, the switch will
<> 144:ef7eb2e8f9f7 690 * occur when the clock source will be ready.
<> 144:ef7eb2e8f9f7 691 * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
<> 144:ef7eb2e8f9f7 692 * currently used as system clock source.
<> 144:ef7eb2e8f9f7 693 * @retval HAL status
<> 144:ef7eb2e8f9f7 694 */
<> 144:ef7eb2e8f9f7 695 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
<> 144:ef7eb2e8f9f7 696 {
<> 144:ef7eb2e8f9f7 697 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 698
<> 144:ef7eb2e8f9f7 699 /* Check the parameters */
<> 144:ef7eb2e8f9f7 700 assert_param(RCC_ClkInitStruct != NULL);
<> 144:ef7eb2e8f9f7 701 assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
<> 144:ef7eb2e8f9f7 702 assert_param(IS_FLASH_LATENCY(FLatency));
<> 144:ef7eb2e8f9f7 703
<> 144:ef7eb2e8f9f7 704 /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
<> 144:ef7eb2e8f9f7 705 must be correctly programmed according to the frequency of the CPU clock
<> 144:ef7eb2e8f9f7 706 (HCLK) of the device. */
<> 144:ef7eb2e8f9f7 707
<> 144:ef7eb2e8f9f7 708 #if defined(FLASH_ACR_LATENCY)
<> 144:ef7eb2e8f9f7 709 /* Increasing the number of wait states because of higher CPU frequency */
<> 144:ef7eb2e8f9f7 710 if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
<> 144:ef7eb2e8f9f7 711 {
<> 144:ef7eb2e8f9f7 712 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
<> 144:ef7eb2e8f9f7 713 __HAL_FLASH_SET_LATENCY(FLatency);
<> 144:ef7eb2e8f9f7 714
<> 144:ef7eb2e8f9f7 715 /* Check that the new number of wait states is taken into account to access the Flash
<> 144:ef7eb2e8f9f7 716 memory by reading the FLASH_ACR register */
<> 144:ef7eb2e8f9f7 717 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
<> 144:ef7eb2e8f9f7 718 {
<> 144:ef7eb2e8f9f7 719 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 720 }
<> 144:ef7eb2e8f9f7 721 }
<> 144:ef7eb2e8f9f7 722
<> 144:ef7eb2e8f9f7 723 #endif /* FLASH_ACR_LATENCY */
<> 144:ef7eb2e8f9f7 724 /*-------------------------- HCLK Configuration --------------------------*/
<> 144:ef7eb2e8f9f7 725 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
<> 144:ef7eb2e8f9f7 726 {
<> 144:ef7eb2e8f9f7 727 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
<> 144:ef7eb2e8f9f7 728 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
<> 144:ef7eb2e8f9f7 729 }
<> 144:ef7eb2e8f9f7 730
<> 144:ef7eb2e8f9f7 731 /*------------------------- SYSCLK Configuration ---------------------------*/
<> 144:ef7eb2e8f9f7 732 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
<> 144:ef7eb2e8f9f7 733 {
<> 144:ef7eb2e8f9f7 734 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
<> 144:ef7eb2e8f9f7 735
<> 144:ef7eb2e8f9f7 736 /* HSE is selected as System Clock Source */
<> 144:ef7eb2e8f9f7 737 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
<> 144:ef7eb2e8f9f7 738 {
<> 144:ef7eb2e8f9f7 739 /* Check the HSE ready flag */
<> 144:ef7eb2e8f9f7 740 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
<> 144:ef7eb2e8f9f7 741 {
<> 144:ef7eb2e8f9f7 742 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 743 }
<> 144:ef7eb2e8f9f7 744 }
<> 144:ef7eb2e8f9f7 745 /* PLL is selected as System Clock Source */
<> 144:ef7eb2e8f9f7 746 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
<> 144:ef7eb2e8f9f7 747 {
<> 144:ef7eb2e8f9f7 748 /* Check the PLL ready flag */
<> 144:ef7eb2e8f9f7 749 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
<> 144:ef7eb2e8f9f7 750 {
<> 144:ef7eb2e8f9f7 751 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 752 }
<> 144:ef7eb2e8f9f7 753 }
<> 144:ef7eb2e8f9f7 754 /* HSI is selected as System Clock Source */
<> 144:ef7eb2e8f9f7 755 else
<> 144:ef7eb2e8f9f7 756 {
<> 144:ef7eb2e8f9f7 757 /* Check the HSI ready flag */
<> 144:ef7eb2e8f9f7 758 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
<> 144:ef7eb2e8f9f7 759 {
<> 144:ef7eb2e8f9f7 760 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 761 }
<> 144:ef7eb2e8f9f7 762 }
<> 144:ef7eb2e8f9f7 763 __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
<> 144:ef7eb2e8f9f7 764
<> 144:ef7eb2e8f9f7 765 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 766 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 767
<> 144:ef7eb2e8f9f7 768 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
<> 144:ef7eb2e8f9f7 769 {
<> 144:ef7eb2e8f9f7 770 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
<> 144:ef7eb2e8f9f7 771 {
<> 144:ef7eb2e8f9f7 772 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 773 {
<> 144:ef7eb2e8f9f7 774 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 775 }
<> 144:ef7eb2e8f9f7 776 }
<> 144:ef7eb2e8f9f7 777 }
<> 144:ef7eb2e8f9f7 778 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
<> 144:ef7eb2e8f9f7 779 {
<> 144:ef7eb2e8f9f7 780 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
<> 144:ef7eb2e8f9f7 781 {
<> 144:ef7eb2e8f9f7 782 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 783 {
<> 144:ef7eb2e8f9f7 784 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 785 }
<> 144:ef7eb2e8f9f7 786 }
<> 144:ef7eb2e8f9f7 787 }
<> 144:ef7eb2e8f9f7 788 else
<> 144:ef7eb2e8f9f7 789 {
<> 144:ef7eb2e8f9f7 790 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
<> 144:ef7eb2e8f9f7 791 {
<> 144:ef7eb2e8f9f7 792 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 793 {
<> 144:ef7eb2e8f9f7 794 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 795 }
<> 144:ef7eb2e8f9f7 796 }
<> 144:ef7eb2e8f9f7 797 }
<> 144:ef7eb2e8f9f7 798 }
<> 144:ef7eb2e8f9f7 799 #if defined(FLASH_ACR_LATENCY)
<> 144:ef7eb2e8f9f7 800 /* Decreasing the number of wait states because of lower CPU frequency */
<> 144:ef7eb2e8f9f7 801 if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
<> 144:ef7eb2e8f9f7 802 {
<> 144:ef7eb2e8f9f7 803 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
<> 144:ef7eb2e8f9f7 804 __HAL_FLASH_SET_LATENCY(FLatency);
<> 144:ef7eb2e8f9f7 805
<> 144:ef7eb2e8f9f7 806 /* Check that the new number of wait states is taken into account to access the Flash
<> 144:ef7eb2e8f9f7 807 memory by reading the FLASH_ACR register */
<> 144:ef7eb2e8f9f7 808 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
<> 144:ef7eb2e8f9f7 809 {
<> 144:ef7eb2e8f9f7 810 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 811 }
<> 144:ef7eb2e8f9f7 812 }
<> 144:ef7eb2e8f9f7 813 #endif /* FLASH_ACR_LATENCY */
<> 144:ef7eb2e8f9f7 814
<> 144:ef7eb2e8f9f7 815 /*-------------------------- PCLK1 Configuration ---------------------------*/
<> 144:ef7eb2e8f9f7 816 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
<> 144:ef7eb2e8f9f7 817 {
<> 144:ef7eb2e8f9f7 818 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
<> 144:ef7eb2e8f9f7 819 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
<> 144:ef7eb2e8f9f7 820 }
<> 144:ef7eb2e8f9f7 821
<> 144:ef7eb2e8f9f7 822 /*-------------------------- PCLK2 Configuration ---------------------------*/
<> 144:ef7eb2e8f9f7 823 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
<> 144:ef7eb2e8f9f7 824 {
<> 144:ef7eb2e8f9f7 825 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
<> 144:ef7eb2e8f9f7 826 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
<> 144:ef7eb2e8f9f7 827 }
<> 144:ef7eb2e8f9f7 828
<> 144:ef7eb2e8f9f7 829 /* Update the SystemCoreClock global variable */
<> 144:ef7eb2e8f9f7 830 SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
<> 144:ef7eb2e8f9f7 831
<> 144:ef7eb2e8f9f7 832 /* Configure the source of time base considering new system clocks settings*/
<> 144:ef7eb2e8f9f7 833 HAL_InitTick (TICK_INT_PRIORITY);
<> 144:ef7eb2e8f9f7 834
<> 144:ef7eb2e8f9f7 835 return HAL_OK;
<> 144:ef7eb2e8f9f7 836 }
<> 144:ef7eb2e8f9f7 837
<> 144:ef7eb2e8f9f7 838 /**
<> 144:ef7eb2e8f9f7 839 * @}
<> 144:ef7eb2e8f9f7 840 */
<> 144:ef7eb2e8f9f7 841
<> 144:ef7eb2e8f9f7 842 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
<> 144:ef7eb2e8f9f7 843 * @brief RCC clocks control functions
<> 144:ef7eb2e8f9f7 844 *
<> 144:ef7eb2e8f9f7 845 @verbatim
<> 144:ef7eb2e8f9f7 846 ===============================================================================
<> 144:ef7eb2e8f9f7 847 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 848 ===============================================================================
<> 144:ef7eb2e8f9f7 849 [..]
<> 144:ef7eb2e8f9f7 850 This subsection provides a set of functions allowing to control the RCC Clocks
<> 144:ef7eb2e8f9f7 851 frequencies.
<> 144:ef7eb2e8f9f7 852
<> 144:ef7eb2e8f9f7 853 @endverbatim
<> 144:ef7eb2e8f9f7 854 * @{
<> 144:ef7eb2e8f9f7 855 */
<> 144:ef7eb2e8f9f7 856
<> 144:ef7eb2e8f9f7 857 /**
<> 144:ef7eb2e8f9f7 858 * @brief Selects the clock source to output on MCO pin.
<> 144:ef7eb2e8f9f7 859 * @note MCO pin should be configured in alternate function mode.
<> 144:ef7eb2e8f9f7 860 * @param RCC_MCOx specifies the output direction for the clock source.
<> 144:ef7eb2e8f9f7 861 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 862 * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
<> 144:ef7eb2e8f9f7 863 * @param RCC_MCOSource specifies the clock source to output.
<> 144:ef7eb2e8f9f7 864 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 865 * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
<> 144:ef7eb2e8f9f7 866 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock
<> 144:ef7eb2e8f9f7 867 * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
<> 144:ef7eb2e8f9f7 868 * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
<> 144:ef7eb2e8f9f7 869 @if STM32F105xC
<> 144:ef7eb2e8f9f7 870 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source
<> 144:ef7eb2e8f9f7 871 * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source
<> 144:ef7eb2e8f9f7 872 * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source
<> 144:ef7eb2e8f9f7 873 * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source
<> 144:ef7eb2e8f9f7 874 * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source
<> 144:ef7eb2e8f9f7 875 @endif
<> 144:ef7eb2e8f9f7 876 @if STM32F107xC
<> 144:ef7eb2e8f9f7 877 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source
<> 144:ef7eb2e8f9f7 878 * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source
<> 144:ef7eb2e8f9f7 879 * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source
<> 144:ef7eb2e8f9f7 880 * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source
<> 144:ef7eb2e8f9f7 881 * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source
<> 144:ef7eb2e8f9f7 882 @endif
<> 144:ef7eb2e8f9f7 883 * @param RCC_MCODiv specifies the MCO DIV.
<> 144:ef7eb2e8f9f7 884 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 885 * @arg @ref RCC_MCODIV_1 no division applied to MCO clock
<> 144:ef7eb2e8f9f7 886 * @retval None
<> 144:ef7eb2e8f9f7 887 */
<> 144:ef7eb2e8f9f7 888 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
<> 144:ef7eb2e8f9f7 889 {
<> 144:ef7eb2e8f9f7 890 GPIO_InitTypeDef gpio = {0};
<> 144:ef7eb2e8f9f7 891
<> 144:ef7eb2e8f9f7 892 /* Check the parameters */
<> 144:ef7eb2e8f9f7 893 assert_param(IS_RCC_MCO(RCC_MCOx));
<> 144:ef7eb2e8f9f7 894 assert_param(IS_RCC_MCODIV(RCC_MCODiv));
<> 144:ef7eb2e8f9f7 895 assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
<> 144:ef7eb2e8f9f7 896
<> 144:ef7eb2e8f9f7 897 /* Configure the MCO1 pin in alternate function mode */
<> 144:ef7eb2e8f9f7 898 gpio.Mode = GPIO_MODE_AF_PP;
<> 144:ef7eb2e8f9f7 899 gpio.Speed = GPIO_SPEED_FREQ_HIGH;
<> 144:ef7eb2e8f9f7 900 gpio.Pull = GPIO_NOPULL;
<> 144:ef7eb2e8f9f7 901 gpio.Pin = MCO1_PIN;
<> 144:ef7eb2e8f9f7 902
<> 144:ef7eb2e8f9f7 903 /* MCO1 Clock Enable */
<> 144:ef7eb2e8f9f7 904 MCO1_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 905
<> 144:ef7eb2e8f9f7 906 HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio);
<> 144:ef7eb2e8f9f7 907
<> 144:ef7eb2e8f9f7 908 /* Configure the MCO clock source */
<> 144:ef7eb2e8f9f7 909 __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv);
<> 144:ef7eb2e8f9f7 910 }
<> 144:ef7eb2e8f9f7 911
<> 144:ef7eb2e8f9f7 912 /**
<> 144:ef7eb2e8f9f7 913 * @brief Enables the Clock Security System.
<> 144:ef7eb2e8f9f7 914 * @note If a failure is detected on the HSE oscillator clock, this oscillator
<> 144:ef7eb2e8f9f7 915 * is automatically disabled and an interrupt is generated to inform the
<> 144:ef7eb2e8f9f7 916 * software about the failure (Clock Security System Interrupt, CSSI),
<> 144:ef7eb2e8f9f7 917 * allowing the MCU to perform rescue operations. The CSSI is linked to
<> 144:ef7eb2e8f9f7 918 * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.
<> 144:ef7eb2e8f9f7 919 * @retval None
<> 144:ef7eb2e8f9f7 920 */
<> 144:ef7eb2e8f9f7 921 void HAL_RCC_EnableCSS(void)
<> 144:ef7eb2e8f9f7 922 {
<> 144:ef7eb2e8f9f7 923 *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
<> 144:ef7eb2e8f9f7 924 }
<> 144:ef7eb2e8f9f7 925
<> 144:ef7eb2e8f9f7 926 /**
<> 144:ef7eb2e8f9f7 927 * @brief Disables the Clock Security System.
<> 144:ef7eb2e8f9f7 928 * @retval None
<> 144:ef7eb2e8f9f7 929 */
<> 144:ef7eb2e8f9f7 930 void HAL_RCC_DisableCSS(void)
<> 144:ef7eb2e8f9f7 931 {
<> 144:ef7eb2e8f9f7 932 *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
<> 144:ef7eb2e8f9f7 933 }
<> 144:ef7eb2e8f9f7 934
<> 144:ef7eb2e8f9f7 935 /**
<> 144:ef7eb2e8f9f7 936 * @brief Returns the SYSCLK frequency
<> 144:ef7eb2e8f9f7 937 * @note The system frequency computed by this function is not the real
<> 144:ef7eb2e8f9f7 938 * frequency in the chip. It is calculated based on the predefined
<> 144:ef7eb2e8f9f7 939 * constant and the selected clock source:
<> 144:ef7eb2e8f9f7 940 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
<> 144:ef7eb2e8f9f7 941 * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE
<> 144:ef7eb2e8f9f7 942 * divided by PREDIV factor(**)
<> 144:ef7eb2e8f9f7 943 * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE
<> 144:ef7eb2e8f9f7 944 * divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor.
<> 144:ef7eb2e8f9f7 945 * @note (*) HSI_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
<> 144:ef7eb2e8f9f7 946 * 8 MHz) but the real value may vary depending on the variations
<> 144:ef7eb2e8f9f7 947 * in voltage and temperature.
<> 144:ef7eb2e8f9f7 948 * @note (**) HSE_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
<> 144:ef7eb2e8f9f7 949 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
<> 144:ef7eb2e8f9f7 950 * frequency of the crystal used. Otherwise, this function may
<> 144:ef7eb2e8f9f7 951 * have wrong result.
<> 144:ef7eb2e8f9f7 952 *
<> 144:ef7eb2e8f9f7 953 * @note The result of this function could be not correct when using fractional
<> 144:ef7eb2e8f9f7 954 * value for HSE crystal.
<> 144:ef7eb2e8f9f7 955 *
<> 144:ef7eb2e8f9f7 956 * @note This function can be used by the user application to compute the
<> 144:ef7eb2e8f9f7 957 * baud-rate for the communication peripherals or configure other parameters.
<> 144:ef7eb2e8f9f7 958 *
<> 144:ef7eb2e8f9f7 959 * @note Each time SYSCLK changes, this function must be called to update the
<> 144:ef7eb2e8f9f7 960 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
<> 144:ef7eb2e8f9f7 961 *
<> 144:ef7eb2e8f9f7 962 * @retval SYSCLK frequency
<> 144:ef7eb2e8f9f7 963 */
<> 144:ef7eb2e8f9f7 964 uint32_t HAL_RCC_GetSysClockFreq(void)
<> 144:ef7eb2e8f9f7 965 {
<> 144:ef7eb2e8f9f7 966 #if defined(RCC_CFGR2_PREDIV1SRC)
<> 144:ef7eb2e8f9f7 967 const uint8_t aPLLMULFactorTable[12] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 13};
<> 144:ef7eb2e8f9f7 968 const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 12, 13, 14, 15, 16};
<> 144:ef7eb2e8f9f7 969 #else
<> 144:ef7eb2e8f9f7 970 const uint8_t aPLLMULFactorTable[16] = { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
<> 144:ef7eb2e8f9f7 971 #if defined(RCC_CFGR2_PREDIV1)
<> 144:ef7eb2e8f9f7 972 const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 12, 13, 14, 15, 16};
<> 144:ef7eb2e8f9f7 973 #else
<> 144:ef7eb2e8f9f7 974 const uint8_t aPredivFactorTable[2] = { 1, 2};
<> 144:ef7eb2e8f9f7 975 #endif /*RCC_CFGR2_PREDIV1*/
<> 144:ef7eb2e8f9f7 976
<> 144:ef7eb2e8f9f7 977 #endif
<> 144:ef7eb2e8f9f7 978 uint32_t tmpreg = 0, prediv = 0, pllclk = 0, pllmul = 0;
<> 144:ef7eb2e8f9f7 979 uint32_t sysclockfreq = 0;
<> 144:ef7eb2e8f9f7 980 #if defined(RCC_CFGR2_PREDIV1SRC)
<> 144:ef7eb2e8f9f7 981 uint32_t prediv2 = 0, pll2mul = 0;
<> 144:ef7eb2e8f9f7 982 #endif /*RCC_CFGR2_PREDIV1SRC*/
<> 144:ef7eb2e8f9f7 983
<> 144:ef7eb2e8f9f7 984 tmpreg = RCC->CFGR;
<> 144:ef7eb2e8f9f7 985
<> 144:ef7eb2e8f9f7 986 /* Get SYSCLK source -------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 987 switch (tmpreg & RCC_CFGR_SWS)
<> 144:ef7eb2e8f9f7 988 {
<> 144:ef7eb2e8f9f7 989 case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
<> 144:ef7eb2e8f9f7 990 {
<> 144:ef7eb2e8f9f7 991 sysclockfreq = HSE_VALUE;
<> 144:ef7eb2e8f9f7 992 break;
<> 144:ef7eb2e8f9f7 993 }
<> 144:ef7eb2e8f9f7 994 case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
<> 144:ef7eb2e8f9f7 995 {
<> 144:ef7eb2e8f9f7 996 pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> POSITION_VAL(RCC_CFGR_PLLMULL)];
<> 144:ef7eb2e8f9f7 997 if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
<> 144:ef7eb2e8f9f7 998 {
<> 144:ef7eb2e8f9f7 999 #if defined(RCC_CFGR2_PREDIV1)
<> 144:ef7eb2e8f9f7 1000 prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> POSITION_VAL(RCC_CFGR2_PREDIV1)];
<> 144:ef7eb2e8f9f7 1001 #else
<> 144:ef7eb2e8f9f7 1002 prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> POSITION_VAL(RCC_CFGR_PLLXTPRE)];
<> 144:ef7eb2e8f9f7 1003 #endif /*RCC_CFGR2_PREDIV1*/
<> 144:ef7eb2e8f9f7 1004 #if defined(RCC_CFGR2_PREDIV1SRC)
<> 144:ef7eb2e8f9f7 1005
<> 144:ef7eb2e8f9f7 1006 if(HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC))
<> 144:ef7eb2e8f9f7 1007 {
<> 144:ef7eb2e8f9f7 1008 /* PLL2 selected as Prediv1 source */
<> 144:ef7eb2e8f9f7 1009 /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
<> 144:ef7eb2e8f9f7 1010 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1;
<> 144:ef7eb2e8f9f7 1011 pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> POSITION_VAL(RCC_CFGR2_PLL2MUL)) + 2;
<> 144:ef7eb2e8f9f7 1012 pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv) * pllmul);
<> 144:ef7eb2e8f9f7 1013 }
<> 144:ef7eb2e8f9f7 1014 else
<> 144:ef7eb2e8f9f7 1015 {
<> 144:ef7eb2e8f9f7 1016 /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
<> 144:ef7eb2e8f9f7 1017 pllclk = (uint32_t)((HSE_VALUE / prediv) * pllmul);
<> 144:ef7eb2e8f9f7 1018 }
<> 144:ef7eb2e8f9f7 1019
<> 144:ef7eb2e8f9f7 1020 /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
<> 144:ef7eb2e8f9f7 1021 /* In this case need to divide pllclk by 2 */
<> 144:ef7eb2e8f9f7 1022 if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> POSITION_VAL(RCC_CFGR_PLLMULL)])
<> 144:ef7eb2e8f9f7 1023 {
<> 144:ef7eb2e8f9f7 1024 pllclk = pllclk / 2;
<> 144:ef7eb2e8f9f7 1025 }
<> 144:ef7eb2e8f9f7 1026 #else
<> 144:ef7eb2e8f9f7 1027 /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
<> 144:ef7eb2e8f9f7 1028 pllclk = (uint32_t)((HSE_VALUE / prediv) * pllmul);
<> 144:ef7eb2e8f9f7 1029 #endif /*RCC_CFGR2_PREDIV1SRC*/
<> 144:ef7eb2e8f9f7 1030 }
<> 144:ef7eb2e8f9f7 1031 else
<> 144:ef7eb2e8f9f7 1032 {
<> 144:ef7eb2e8f9f7 1033 /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
<> 144:ef7eb2e8f9f7 1034 pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
<> 144:ef7eb2e8f9f7 1035 }
<> 144:ef7eb2e8f9f7 1036 sysclockfreq = pllclk;
<> 144:ef7eb2e8f9f7 1037 break;
<> 144:ef7eb2e8f9f7 1038 }
<> 144:ef7eb2e8f9f7 1039 case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
<> 144:ef7eb2e8f9f7 1040 default: /* HSI used as system clock */
<> 144:ef7eb2e8f9f7 1041 {
<> 144:ef7eb2e8f9f7 1042 sysclockfreq = HSI_VALUE;
<> 144:ef7eb2e8f9f7 1043 break;
<> 144:ef7eb2e8f9f7 1044 }
<> 144:ef7eb2e8f9f7 1045 }
<> 144:ef7eb2e8f9f7 1046 return sysclockfreq;
<> 144:ef7eb2e8f9f7 1047 }
<> 144:ef7eb2e8f9f7 1048
<> 144:ef7eb2e8f9f7 1049 /**
<> 144:ef7eb2e8f9f7 1050 * @brief Returns the HCLK frequency
<> 144:ef7eb2e8f9f7 1051 * @note Each time HCLK changes, this function must be called to update the
<> 144:ef7eb2e8f9f7 1052 * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
<> 144:ef7eb2e8f9f7 1053 *
<> 144:ef7eb2e8f9f7 1054 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
<> 144:ef7eb2e8f9f7 1055 * and updated within this function
<> 144:ef7eb2e8f9f7 1056 * @retval HCLK frequency
<> 144:ef7eb2e8f9f7 1057 */
<> 144:ef7eb2e8f9f7 1058 uint32_t HAL_RCC_GetHCLKFreq(void)
<> 144:ef7eb2e8f9f7 1059 {
<> 144:ef7eb2e8f9f7 1060 return SystemCoreClock;
<> 144:ef7eb2e8f9f7 1061 }
<> 144:ef7eb2e8f9f7 1062
<> 144:ef7eb2e8f9f7 1063 /**
<> 144:ef7eb2e8f9f7 1064 * @brief Returns the PCLK1 frequency
<> 144:ef7eb2e8f9f7 1065 * @note Each time PCLK1 changes, this function must be called to update the
<> 144:ef7eb2e8f9f7 1066 * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
<> 144:ef7eb2e8f9f7 1067 * @retval PCLK1 frequency
<> 144:ef7eb2e8f9f7 1068 */
<> 144:ef7eb2e8f9f7 1069 uint32_t HAL_RCC_GetPCLK1Freq(void)
<> 144:ef7eb2e8f9f7 1070 {
<> 144:ef7eb2e8f9f7 1071 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
<> 144:ef7eb2e8f9f7 1072 return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_BITNUMBER]);
<> 144:ef7eb2e8f9f7 1073 }
<> 144:ef7eb2e8f9f7 1074
<> 144:ef7eb2e8f9f7 1075 /**
<> 144:ef7eb2e8f9f7 1076 * @brief Returns the PCLK2 frequency
<> 144:ef7eb2e8f9f7 1077 * @note Each time PCLK2 changes, this function must be called to update the
<> 144:ef7eb2e8f9f7 1078 * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
<> 144:ef7eb2e8f9f7 1079 * @retval PCLK2 frequency
<> 144:ef7eb2e8f9f7 1080 */
<> 144:ef7eb2e8f9f7 1081 uint32_t HAL_RCC_GetPCLK2Freq(void)
<> 144:ef7eb2e8f9f7 1082 {
<> 144:ef7eb2e8f9f7 1083 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
<> 144:ef7eb2e8f9f7 1084 return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_BITNUMBER]);
<> 144:ef7eb2e8f9f7 1085 }
<> 144:ef7eb2e8f9f7 1086
<> 144:ef7eb2e8f9f7 1087 /**
<> 144:ef7eb2e8f9f7 1088 * @brief Configures the RCC_OscInitStruct according to the internal
<> 144:ef7eb2e8f9f7 1089 * RCC configuration registers.
<> 144:ef7eb2e8f9f7 1090 * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
<> 144:ef7eb2e8f9f7 1091 * will be configured.
<> 144:ef7eb2e8f9f7 1092 * @retval None
<> 144:ef7eb2e8f9f7 1093 */
<> 144:ef7eb2e8f9f7 1094 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
<> 144:ef7eb2e8f9f7 1095 {
<> 144:ef7eb2e8f9f7 1096 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1097 assert_param(RCC_OscInitStruct != NULL);
<> 144:ef7eb2e8f9f7 1098
<> 144:ef7eb2e8f9f7 1099 /* Set all possible values for the Oscillator type parameter ---------------*/
<> 144:ef7eb2e8f9f7 1100 RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \
<> 144:ef7eb2e8f9f7 1101 | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
<> 144:ef7eb2e8f9f7 1102
<> 144:ef7eb2e8f9f7 1103 #if defined(RCC_CFGR2_PREDIV1SRC)
<> 144:ef7eb2e8f9f7 1104 /* Get the Prediv1 source --------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1105 RCC_OscInitStruct->Prediv1Source = READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC);
<> 144:ef7eb2e8f9f7 1106 #endif /* RCC_CFGR2_PREDIV1SRC */
<> 144:ef7eb2e8f9f7 1107
<> 144:ef7eb2e8f9f7 1108 /* Get the HSE configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1109 if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
<> 144:ef7eb2e8f9f7 1110 {
<> 144:ef7eb2e8f9f7 1111 RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
<> 144:ef7eb2e8f9f7 1112 }
<> 144:ef7eb2e8f9f7 1113 else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
<> 144:ef7eb2e8f9f7 1114 {
<> 144:ef7eb2e8f9f7 1115 RCC_OscInitStruct->HSEState = RCC_HSE_ON;
<> 144:ef7eb2e8f9f7 1116 }
<> 144:ef7eb2e8f9f7 1117 else
<> 144:ef7eb2e8f9f7 1118 {
<> 144:ef7eb2e8f9f7 1119 RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
<> 144:ef7eb2e8f9f7 1120 }
<> 144:ef7eb2e8f9f7 1121 RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV();
<> 144:ef7eb2e8f9f7 1122
<> 144:ef7eb2e8f9f7 1123 /* Get the HSI configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1124 if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
<> 144:ef7eb2e8f9f7 1125 {
<> 144:ef7eb2e8f9f7 1126 RCC_OscInitStruct->HSIState = RCC_HSI_ON;
<> 144:ef7eb2e8f9f7 1127 }
<> 144:ef7eb2e8f9f7 1128 else
<> 144:ef7eb2e8f9f7 1129 {
<> 144:ef7eb2e8f9f7 1130 RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
<> 144:ef7eb2e8f9f7 1131 }
<> 144:ef7eb2e8f9f7 1132
<> 144:ef7eb2e8f9f7 1133 RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
<> 144:ef7eb2e8f9f7 1134
<> 144:ef7eb2e8f9f7 1135 /* Get the LSE configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1136 if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
<> 144:ef7eb2e8f9f7 1137 {
<> 144:ef7eb2e8f9f7 1138 RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
<> 144:ef7eb2e8f9f7 1139 }
<> 144:ef7eb2e8f9f7 1140 else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
<> 144:ef7eb2e8f9f7 1141 {
<> 144:ef7eb2e8f9f7 1142 RCC_OscInitStruct->LSEState = RCC_LSE_ON;
<> 144:ef7eb2e8f9f7 1143 }
<> 144:ef7eb2e8f9f7 1144 else
<> 144:ef7eb2e8f9f7 1145 {
<> 144:ef7eb2e8f9f7 1146 RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
<> 144:ef7eb2e8f9f7 1147 }
<> 144:ef7eb2e8f9f7 1148
<> 144:ef7eb2e8f9f7 1149 /* Get the LSI configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1150 if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
<> 144:ef7eb2e8f9f7 1151 {
<> 144:ef7eb2e8f9f7 1152 RCC_OscInitStruct->LSIState = RCC_LSI_ON;
<> 144:ef7eb2e8f9f7 1153 }
<> 144:ef7eb2e8f9f7 1154 else
<> 144:ef7eb2e8f9f7 1155 {
<> 144:ef7eb2e8f9f7 1156 RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
<> 144:ef7eb2e8f9f7 1157 }
<> 144:ef7eb2e8f9f7 1158
<> 144:ef7eb2e8f9f7 1159
<> 144:ef7eb2e8f9f7 1160 /* Get the PLL configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1161 if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
<> 144:ef7eb2e8f9f7 1162 {
<> 144:ef7eb2e8f9f7 1163 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
<> 144:ef7eb2e8f9f7 1164 }
<> 144:ef7eb2e8f9f7 1165 else
<> 144:ef7eb2e8f9f7 1166 {
<> 144:ef7eb2e8f9f7 1167 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
<> 144:ef7eb2e8f9f7 1168 }
<> 144:ef7eb2e8f9f7 1169 RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
<> 144:ef7eb2e8f9f7 1170 RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMULL);
<> 144:ef7eb2e8f9f7 1171 #if defined(RCC_CR_PLL2ON)
<> 144:ef7eb2e8f9f7 1172 /* Get the PLL2 configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1173 if((RCC->CR &RCC_CR_PLL2ON) == RCC_CR_PLL2ON)
<> 144:ef7eb2e8f9f7 1174 {
<> 144:ef7eb2e8f9f7 1175 RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_ON;
<> 144:ef7eb2e8f9f7 1176 }
<> 144:ef7eb2e8f9f7 1177 else
<> 144:ef7eb2e8f9f7 1178 {
<> 144:ef7eb2e8f9f7 1179 RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_OFF;
<> 144:ef7eb2e8f9f7 1180 }
<> 144:ef7eb2e8f9f7 1181 RCC_OscInitStruct->PLL2.HSEPrediv2Value = __HAL_RCC_HSE_GET_PREDIV2();
<> 144:ef7eb2e8f9f7 1182 RCC_OscInitStruct->PLL2.PLL2MUL = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PLL2MUL);
<> 144:ef7eb2e8f9f7 1183 #endif /* RCC_CR_PLL2ON */
<> 144:ef7eb2e8f9f7 1184 }
<> 144:ef7eb2e8f9f7 1185
<> 144:ef7eb2e8f9f7 1186 /**
<> 144:ef7eb2e8f9f7 1187 * @brief Get the RCC_ClkInitStruct according to the internal
<> 144:ef7eb2e8f9f7 1188 * RCC configuration registers.
<> 144:ef7eb2e8f9f7 1189 * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
<> 144:ef7eb2e8f9f7 1190 * contains the current clock configuration.
<> 144:ef7eb2e8f9f7 1191 * @param pFLatency Pointer on the Flash Latency.
<> 144:ef7eb2e8f9f7 1192 * @retval None
<> 144:ef7eb2e8f9f7 1193 */
<> 144:ef7eb2e8f9f7 1194 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
<> 144:ef7eb2e8f9f7 1195 {
<> 144:ef7eb2e8f9f7 1196 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1197 assert_param(RCC_ClkInitStruct != NULL);
<> 144:ef7eb2e8f9f7 1198 assert_param(pFLatency != NULL);
<> 144:ef7eb2e8f9f7 1199
<> 144:ef7eb2e8f9f7 1200 /* Set all possible values for the Clock type parameter --------------------*/
<> 144:ef7eb2e8f9f7 1201 RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
<> 144:ef7eb2e8f9f7 1202
<> 144:ef7eb2e8f9f7 1203 /* Get the SYSCLK configuration --------------------------------------------*/
<> 144:ef7eb2e8f9f7 1204 RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
<> 144:ef7eb2e8f9f7 1205
<> 144:ef7eb2e8f9f7 1206 /* Get the HCLK configuration ----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1207 RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
<> 144:ef7eb2e8f9f7 1208
<> 144:ef7eb2e8f9f7 1209 /* Get the APB1 configuration ----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1210 RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
<> 144:ef7eb2e8f9f7 1211
<> 144:ef7eb2e8f9f7 1212 /* Get the APB2 configuration ----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1213 RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
<> 144:ef7eb2e8f9f7 1214
<> 144:ef7eb2e8f9f7 1215 #if defined(FLASH_ACR_LATENCY)
<> 144:ef7eb2e8f9f7 1216 /* Get the Flash Wait State (Latency) configuration ------------------------*/
<> 144:ef7eb2e8f9f7 1217 *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
<> 144:ef7eb2e8f9f7 1218 #else
<> 144:ef7eb2e8f9f7 1219 /* For VALUE lines devices, only LATENCY_0 can be set*/
<> 144:ef7eb2e8f9f7 1220 *pFLatency = (uint32_t)FLASH_LATENCY_0;
<> 144:ef7eb2e8f9f7 1221 #endif
<> 144:ef7eb2e8f9f7 1222 }
<> 144:ef7eb2e8f9f7 1223
<> 144:ef7eb2e8f9f7 1224 /**
<> 144:ef7eb2e8f9f7 1225 * @brief This function handles the RCC CSS interrupt request.
<> 144:ef7eb2e8f9f7 1226 * @note This API should be called under the NMI_Handler().
<> 144:ef7eb2e8f9f7 1227 * @retval None
<> 144:ef7eb2e8f9f7 1228 */
<> 144:ef7eb2e8f9f7 1229 void HAL_RCC_NMI_IRQHandler(void)
<> 144:ef7eb2e8f9f7 1230 {
<> 144:ef7eb2e8f9f7 1231 /* Check RCC CSSF flag */
<> 144:ef7eb2e8f9f7 1232 if(__HAL_RCC_GET_IT(RCC_IT_CSS))
<> 144:ef7eb2e8f9f7 1233 {
<> 144:ef7eb2e8f9f7 1234 /* RCC Clock Security System interrupt user callback */
<> 144:ef7eb2e8f9f7 1235 HAL_RCC_CSSCallback();
<> 144:ef7eb2e8f9f7 1236
<> 144:ef7eb2e8f9f7 1237 /* Clear RCC CSS pending bit */
<> 144:ef7eb2e8f9f7 1238 __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
<> 144:ef7eb2e8f9f7 1239 }
<> 144:ef7eb2e8f9f7 1240 }
<> 144:ef7eb2e8f9f7 1241
<> 144:ef7eb2e8f9f7 1242 /**
<> 144:ef7eb2e8f9f7 1243 * @brief RCC Clock Security System interrupt callback
<> 144:ef7eb2e8f9f7 1244 * @retval none
<> 144:ef7eb2e8f9f7 1245 */
<> 144:ef7eb2e8f9f7 1246 __weak void HAL_RCC_CSSCallback(void)
<> 144:ef7eb2e8f9f7 1247 {
<> 144:ef7eb2e8f9f7 1248 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1249 the HAL_RCC_CSSCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1250 */
<> 144:ef7eb2e8f9f7 1251 }
<> 144:ef7eb2e8f9f7 1252
<> 144:ef7eb2e8f9f7 1253 /**
<> 144:ef7eb2e8f9f7 1254 * @}
<> 144:ef7eb2e8f9f7 1255 */
<> 144:ef7eb2e8f9f7 1256
<> 144:ef7eb2e8f9f7 1257 /**
<> 144:ef7eb2e8f9f7 1258 * @}
<> 144:ef7eb2e8f9f7 1259 */
<> 144:ef7eb2e8f9f7 1260
<> 144:ef7eb2e8f9f7 1261 #endif /* HAL_RCC_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1262 /**
<> 144:ef7eb2e8f9f7 1263 * @}
<> 144:ef7eb2e8f9f7 1264 */
<> 144:ef7eb2e8f9f7 1265
<> 144:ef7eb2e8f9f7 1266 /**
<> 144:ef7eb2e8f9f7 1267 * @}
<> 144:ef7eb2e8f9f7 1268 */
<> 144:ef7eb2e8f9f7 1269
<> 144:ef7eb2e8f9f7 1270 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/