stm32f4-discovery-CAN-Activation

Users » malvitor » Code » stm32f4-discovery-CAN-Activation

João Victor / stm32f4-discovery-CAN-Activation

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc_ex.c@161:2cc1468da177, 2017-03-30 (annotated)

Committer:: <>
Date:: Thu Mar 30 13:45:57 2017 +0100
Revision:: 161:2cc1468da177
Parent:: 157:ff67d9f36b67
Child:: 168:9672193075cf

This updates the lib to the mbed lib v139

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32f7xx_hal_rcc_ex.c
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	161:2cc1468da177	5	* @version V1.2.0
<>	161:2cc1468da177	6	* @date 30-December-2016
<>	144:ef7eb2e8f9f7	7	* @brief Extension RCC HAL module driver.
<>	144:ef7eb2e8f9f7	8	* This file provides firmware functions to manage the following
<>	144:ef7eb2e8f9f7	9	* functionalities RCC extension peripheral:
<>	144:ef7eb2e8f9f7	10	* + Extended Peripheral Control functions
<>	144:ef7eb2e8f9f7	11	*
<>	144:ef7eb2e8f9f7	12	******************************************************************************
<>	144:ef7eb2e8f9f7	13	* @attention
<>	144:ef7eb2e8f9f7	14	*
<>	144:ef7eb2e8f9f7	15	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	16	*
<>	144:ef7eb2e8f9f7	17	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	18	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	19	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	20	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	21	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	22	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	23	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	24	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	25	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	26	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	27	*
<>	144:ef7eb2e8f9f7	28	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	29	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	30	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	31	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	32	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	33	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	34	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	35	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	36	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	37	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	38	*
<>	144:ef7eb2e8f9f7	39	******************************************************************************
<>	144:ef7eb2e8f9f7	40	*/
<>	144:ef7eb2e8f9f7	41
<>	144:ef7eb2e8f9f7	42	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	43	#include "stm32f7xx_hal.h"
<>	144:ef7eb2e8f9f7	44
<>	144:ef7eb2e8f9f7	45	/** @addtogroup STM32F7xx_HAL_Driver
<>	144:ef7eb2e8f9f7	46	* @{
<>	144:ef7eb2e8f9f7	47	*/
<>	144:ef7eb2e8f9f7	48
<>	144:ef7eb2e8f9f7	49	/** @defgroup RCCEx RCCEx
<>	144:ef7eb2e8f9f7	50	* @brief RCCEx HAL module driver
<>	144:ef7eb2e8f9f7	51	* @{
<>	144:ef7eb2e8f9f7	52	*/
<>	144:ef7eb2e8f9f7	53
<>	144:ef7eb2e8f9f7	54	#ifdef HAL_RCC_MODULE_ENABLED
<>	144:ef7eb2e8f9f7	55
<>	144:ef7eb2e8f9f7	56	/* Private typedef -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	57	/* Private define ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	58	/** @defgroup RCCEx_Private_Defines RCCEx Private Defines
<>	144:ef7eb2e8f9f7	59	* @{
<>	144:ef7eb2e8f9f7	60	*/
<>	144:ef7eb2e8f9f7	61
<>	144:ef7eb2e8f9f7	62	#define PLLI2S_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */
<>	144:ef7eb2e8f9f7	63	#define PLLSAI_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */
<>	144:ef7eb2e8f9f7	64
<>	144:ef7eb2e8f9f7	65	/**
<>	144:ef7eb2e8f9f7	66	* @}
<>	144:ef7eb2e8f9f7	67	*/
<>	144:ef7eb2e8f9f7	68	/* Private macro -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	69	/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
<>	144:ef7eb2e8f9f7	70	* @{
<>	144:ef7eb2e8f9f7	71	*/
<>	144:ef7eb2e8f9f7	72	/**
<>	144:ef7eb2e8f9f7	73	* @}
<>	144:ef7eb2e8f9f7	74	*/
<>	144:ef7eb2e8f9f7	75
<>	144:ef7eb2e8f9f7	76	/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
<>	144:ef7eb2e8f9f7	77	* @{
<>	144:ef7eb2e8f9f7	78	*/
<>	144:ef7eb2e8f9f7	79
<>	144:ef7eb2e8f9f7	80	/**
<>	144:ef7eb2e8f9f7	81	* @}
<>	144:ef7eb2e8f9f7	82	*/
<>	144:ef7eb2e8f9f7	83
<>	144:ef7eb2e8f9f7	84
<>	144:ef7eb2e8f9f7	85	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	86	/* Private function prototypes -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	87	/* Private functions ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	88
<>	144:ef7eb2e8f9f7	89	/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
<>	144:ef7eb2e8f9f7	90	* @{
<>	144:ef7eb2e8f9f7	91	*/
<>	144:ef7eb2e8f9f7	92
<>	144:ef7eb2e8f9f7	93	/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
<>	144:ef7eb2e8f9f7	94	* @brief Extended Peripheral Control functions
<>	144:ef7eb2e8f9f7	95	*
<>	144:ef7eb2e8f9f7	96	@verbatim
<>	144:ef7eb2e8f9f7	97	===============================================================================
<>	144:ef7eb2e8f9f7	98	##### Extended Peripheral Control functions #####
<>	144:ef7eb2e8f9f7	99	===============================================================================
<>	144:ef7eb2e8f9f7	100	[..]
<>	144:ef7eb2e8f9f7	101	This subsection provides a set of functions allowing to control the RCC Clocks
<>	144:ef7eb2e8f9f7	102	frequencies.
<>	144:ef7eb2e8f9f7	103	[..]
<>	144:ef7eb2e8f9f7	104	(@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
<>	144:ef7eb2e8f9f7	105	select the RTC clock source; in this case the Backup domain will be reset in
<>	144:ef7eb2e8f9f7	106	order to modify the RTC Clock source, as consequence RTC registers (including
<>	144:ef7eb2e8f9f7	107	the backup registers) and RCC_BDCR register will be set to their reset values.
<>	144:ef7eb2e8f9f7	108
<>	144:ef7eb2e8f9f7	109	@endverbatim
<>	144:ef7eb2e8f9f7	110	* @{
<>	144:ef7eb2e8f9f7	111	*/
<>	157:ff67d9f36b67	112	#if defined (STM32F745xx) \|\| defined (STM32F746xx) \|\| defined (STM32F756xx) \|\| defined (STM32F765xx) \|\| \
<>	157:ff67d9f36b67	113	defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	114	/**
<>	144:ef7eb2e8f9f7	115	* @brief Initializes the RCC extended peripherals clocks according to the specified
<>	144:ef7eb2e8f9f7	116	* parameters in the RCC_PeriphCLKInitTypeDef.
<>	144:ef7eb2e8f9f7	117	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
<>	144:ef7eb2e8f9f7	118	* contains the configuration information for the Extended Peripherals
<>	144:ef7eb2e8f9f7	119	* clocks(I2S, SAI, LTDC, RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...).
<>	144:ef7eb2e8f9f7	120	*
<>	144:ef7eb2e8f9f7	121	* @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
<>	144:ef7eb2e8f9f7	122	* the RTC clock source; in this case the Backup domain will be reset in
<>	144:ef7eb2e8f9f7	123	* order to modify the RTC Clock source, as consequence RTC registers (including
<>	144:ef7eb2e8f9f7	124	* the backup registers) are set to their reset values.
<>	144:ef7eb2e8f9f7	125	*
<>	144:ef7eb2e8f9f7	126	* @retval HAL status
<>	144:ef7eb2e8f9f7	127	*/
<>	144:ef7eb2e8f9f7	128	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
<>	144:ef7eb2e8f9f7	129	{
<>	144:ef7eb2e8f9f7	130	uint32_t tickstart = 0;
<>	144:ef7eb2e8f9f7	131	uint32_t tmpreg0 = 0;
<>	144:ef7eb2e8f9f7	132	uint32_t tmpreg1 = 0;
<>	144:ef7eb2e8f9f7	133	uint32_t plli2sused = 0;
<>	144:ef7eb2e8f9f7	134	uint32_t pllsaiused = 0;
<>	144:ef7eb2e8f9f7	135
<>	144:ef7eb2e8f9f7	136	/* Check the parameters */
<>	144:ef7eb2e8f9f7	137	assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
<>	144:ef7eb2e8f9f7	138
<>	144:ef7eb2e8f9f7	139	/----------------------------------- I2S configuration ----------------------------------/
<>	144:ef7eb2e8f9f7	140	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
<>	144:ef7eb2e8f9f7	141	{
<>	144:ef7eb2e8f9f7	142	/* Check the parameters */
<>	144:ef7eb2e8f9f7	143	assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
<>	144:ef7eb2e8f9f7	144
<>	144:ef7eb2e8f9f7	145	/* Configure I2S Clock source */
<>	144:ef7eb2e8f9f7	146	__HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
<>	144:ef7eb2e8f9f7	147
<>	144:ef7eb2e8f9f7	148	/* Enable the PLLI2S when it's used as clock source for I2S */
<>	144:ef7eb2e8f9f7	149	if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)
<>	144:ef7eb2e8f9f7	150	{
<>	144:ef7eb2e8f9f7	151	plli2sused = 1;
<>	144:ef7eb2e8f9f7	152	}
<>	144:ef7eb2e8f9f7	153	}
<>	144:ef7eb2e8f9f7	154
<>	144:ef7eb2e8f9f7	155	/------------------------------------ SAI1 configuration --------------------------------------/
<>	144:ef7eb2e8f9f7	156	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
<>	144:ef7eb2e8f9f7	157	{
<>	144:ef7eb2e8f9f7	158	/* Check the parameters */
<>	144:ef7eb2e8f9f7	159	assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
<>	144:ef7eb2e8f9f7	160
<>	144:ef7eb2e8f9f7	161	/* Configure SAI1 Clock source */
<>	144:ef7eb2e8f9f7	162	__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
<>	144:ef7eb2e8f9f7	163	/* Enable the PLLI2S when it's used as clock source for SAI */
<>	144:ef7eb2e8f9f7	164	if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
<>	144:ef7eb2e8f9f7	165	{
<>	144:ef7eb2e8f9f7	166	plli2sused = 1;
<>	144:ef7eb2e8f9f7	167	}
<>	144:ef7eb2e8f9f7	168	/* Enable the PLLSAI when it's used as clock source for SAI */
<>	144:ef7eb2e8f9f7	169	if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
<>	144:ef7eb2e8f9f7	170	{
<>	144:ef7eb2e8f9f7	171	pllsaiused = 1;
<>	144:ef7eb2e8f9f7	172	}
<>	144:ef7eb2e8f9f7	173	}
<>	144:ef7eb2e8f9f7	174
<>	144:ef7eb2e8f9f7	175	/------------------------------------ SAI2 configuration --------------------------------------/
<>	144:ef7eb2e8f9f7	176	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
<>	144:ef7eb2e8f9f7	177	{
<>	144:ef7eb2e8f9f7	178	/* Check the parameters */
<>	144:ef7eb2e8f9f7	179	assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
<>	144:ef7eb2e8f9f7	180
<>	144:ef7eb2e8f9f7	181	/* Configure SAI2 Clock source */
<>	144:ef7eb2e8f9f7	182	__HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
<>	144:ef7eb2e8f9f7	183
<>	144:ef7eb2e8f9f7	184	/* Enable the PLLI2S when it's used as clock source for SAI */
<>	144:ef7eb2e8f9f7	185	if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
<>	144:ef7eb2e8f9f7	186	{
<>	144:ef7eb2e8f9f7	187	plli2sused = 1;
<>	144:ef7eb2e8f9f7	188	}
<>	144:ef7eb2e8f9f7	189	/* Enable the PLLSAI when it's used as clock source for SAI */
<>	144:ef7eb2e8f9f7	190	if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
<>	144:ef7eb2e8f9f7	191	{
<>	144:ef7eb2e8f9f7	192	pllsaiused = 1;
<>	144:ef7eb2e8f9f7	193	}
<>	144:ef7eb2e8f9f7	194	}
<>	144:ef7eb2e8f9f7	195
<>	144:ef7eb2e8f9f7	196	/-------------------------------------- SPDIF-RX Configuration -----------------------------------/
<>	144:ef7eb2e8f9f7	197	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
<>	144:ef7eb2e8f9f7	198	{
<>	144:ef7eb2e8f9f7	199	plli2sused = 1;
<>	144:ef7eb2e8f9f7	200	}
<>	144:ef7eb2e8f9f7	201
<>	144:ef7eb2e8f9f7	202	/------------------------------------ RTC configuration --------------------------------------/
<>	144:ef7eb2e8f9f7	203	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
<>	144:ef7eb2e8f9f7	204	{
<>	144:ef7eb2e8f9f7	205	/* Check for RTC Parameters used to output RTCCLK */
<>	144:ef7eb2e8f9f7	206	assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
<>	144:ef7eb2e8f9f7	207
<>	144:ef7eb2e8f9f7	208	/* Enable Power Clock*/
<>	144:ef7eb2e8f9f7	209	__HAL_RCC_PWR_CLK_ENABLE();
<>	144:ef7eb2e8f9f7	210
<>	144:ef7eb2e8f9f7	211	/* Enable write access to Backup domain */
<>	144:ef7eb2e8f9f7	212	PWR->CR1 \|= PWR_CR1_DBP;
<>	144:ef7eb2e8f9f7	213
<>	144:ef7eb2e8f9f7	214	/* Get Start Tick*/
<>	144:ef7eb2e8f9f7	215	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	216
<>	144:ef7eb2e8f9f7	217	/* Wait for Backup domain Write protection disable */
<>	144:ef7eb2e8f9f7	218	while((PWR->CR1 & PWR_CR1_DBP) == RESET)
<>	144:ef7eb2e8f9f7	219	{
<>	144:ef7eb2e8f9f7	220	if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	221	{
<>	144:ef7eb2e8f9f7	222	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	223	}
<>	144:ef7eb2e8f9f7	224	}
<>	144:ef7eb2e8f9f7	225
<>	144:ef7eb2e8f9f7	226	/* Reset the Backup domain only if the RTC Clock source selection is modified */
<>	144:ef7eb2e8f9f7	227	tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL);
<>	144:ef7eb2e8f9f7	228
<>	144:ef7eb2e8f9f7	229	if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
<>	144:ef7eb2e8f9f7	230	{
<>	144:ef7eb2e8f9f7	231	/* Store the content of BDCR register before the reset of Backup Domain */
<>	144:ef7eb2e8f9f7	232	tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
<>	144:ef7eb2e8f9f7	233
<>	144:ef7eb2e8f9f7	234	/* RTC Clock selection can be changed only if the Backup Domain is reset */
<>	144:ef7eb2e8f9f7	235	__HAL_RCC_BACKUPRESET_FORCE();
<>	144:ef7eb2e8f9f7	236	__HAL_RCC_BACKUPRESET_RELEASE();
<>	144:ef7eb2e8f9f7	237
<>	144:ef7eb2e8f9f7	238	/* Restore the Content of BDCR register */
<>	144:ef7eb2e8f9f7	239	RCC->BDCR = tmpreg0;
<>	144:ef7eb2e8f9f7	240
<>	144:ef7eb2e8f9f7	241	/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
<>	144:ef7eb2e8f9f7	242	if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
<>	144:ef7eb2e8f9f7	243	{
<>	144:ef7eb2e8f9f7	244	/* Get Start Tick*/
<>	144:ef7eb2e8f9f7	245	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	246
<>	144:ef7eb2e8f9f7	247	/* Wait till LSE is ready */
<>	144:ef7eb2e8f9f7	248	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
<>	144:ef7eb2e8f9f7	249	{
<>	144:ef7eb2e8f9f7	250	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	251	{
<>	144:ef7eb2e8f9f7	252	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	253	}
<>	144:ef7eb2e8f9f7	254	}
<>	144:ef7eb2e8f9f7	255	}
<>	144:ef7eb2e8f9f7	256	}
<>	144:ef7eb2e8f9f7	257	__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
<>	144:ef7eb2e8f9f7	258	}
<>	144:ef7eb2e8f9f7	259
<>	144:ef7eb2e8f9f7	260	/------------------------------------ TIM configuration --------------------------------------/
<>	144:ef7eb2e8f9f7	261	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
<>	144:ef7eb2e8f9f7	262	{
<>	144:ef7eb2e8f9f7	263	/* Check the parameters */
<>	144:ef7eb2e8f9f7	264	assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
<>	144:ef7eb2e8f9f7	265
<>	144:ef7eb2e8f9f7	266	/* Configure Timer Prescaler */
<>	144:ef7eb2e8f9f7	267	__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
<>	144:ef7eb2e8f9f7	268	}
<>	144:ef7eb2e8f9f7	269
<>	144:ef7eb2e8f9f7	270	/-------------------------------------- I2C1 Configuration -----------------------------------/
<>	144:ef7eb2e8f9f7	271	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
<>	144:ef7eb2e8f9f7	272	{
<>	144:ef7eb2e8f9f7	273	/* Check the parameters */
<>	144:ef7eb2e8f9f7	274	assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
<>	144:ef7eb2e8f9f7	275
<>	144:ef7eb2e8f9f7	276	/* Configure the I2C1 clock source */
<>	144:ef7eb2e8f9f7	277	__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
<>	144:ef7eb2e8f9f7	278	}
<>	144:ef7eb2e8f9f7	279
<>	144:ef7eb2e8f9f7	280	/-------------------------------------- I2C2 Configuration -----------------------------------/
<>	144:ef7eb2e8f9f7	281	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
<>	144:ef7eb2e8f9f7	282	{
<>	144:ef7eb2e8f9f7	283	/* Check the parameters */
<>	144:ef7eb2e8f9f7	284	assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
<>	144:ef7eb2e8f9f7	285
<>	144:ef7eb2e8f9f7	286	/* Configure the I2C2 clock source */
<>	144:ef7eb2e8f9f7	287	__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
<>	144:ef7eb2e8f9f7	288	}
<>	144:ef7eb2e8f9f7	289
<>	144:ef7eb2e8f9f7	290	/-------------------------------------- I2C3 Configuration -----------------------------------/
<>	144:ef7eb2e8f9f7	291	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
<>	144:ef7eb2e8f9f7	292	{
<>	144:ef7eb2e8f9f7	293	/* Check the parameters */
<>	144:ef7eb2e8f9f7	294	assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
<>	144:ef7eb2e8f9f7	295
<>	144:ef7eb2e8f9f7	296	/* Configure the I2C3 clock source */
<>	144:ef7eb2e8f9f7	297	__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
<>	144:ef7eb2e8f9f7	298	}
<>	144:ef7eb2e8f9f7	299
<>	144:ef7eb2e8f9f7	300	/-------------------------------------- I2C4 Configuration -----------------------------------/
<>	144:ef7eb2e8f9f7	301	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
<>	144:ef7eb2e8f9f7	302	{
<>	144:ef7eb2e8f9f7	303	/* Check the parameters */
<>	144:ef7eb2e8f9f7	304	assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
<>	144:ef7eb2e8f9f7	305
<>	144:ef7eb2e8f9f7	306	/* Configure the I2C4 clock source */
<>	144:ef7eb2e8f9f7	307	__HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
<>	144:ef7eb2e8f9f7	308	}
<>	144:ef7eb2e8f9f7	309
<>	144:ef7eb2e8f9f7	310	/-------------------------------------- USART1 Configuration -----------------------------------/
<>	144:ef7eb2e8f9f7	311	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
<>	144:ef7eb2e8f9f7	312	{
<>	144:ef7eb2e8f9f7	313	/* Check the parameters */
<>	144:ef7eb2e8f9f7	314	assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
<>	144:ef7eb2e8f9f7	315
<>	144:ef7eb2e8f9f7	316	/* Configure the USART1 clock source */
<>	144:ef7eb2e8f9f7	317	__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
<>	144:ef7eb2e8f9f7	318	}
<>	144:ef7eb2e8f9f7	319
<>	144:ef7eb2e8f9f7	320	/-------------------------------------- USART2 Configuration -----------------------------------/
<>	144:ef7eb2e8f9f7	321	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
<>	144:ef7eb2e8f9f7	322	{
<>	144:ef7eb2e8f9f7	323	/* Check the parameters */
<>	144:ef7eb2e8f9f7	324	assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
<>	144:ef7eb2e8f9f7	325
<>	144:ef7eb2e8f9f7	326	/* Configure the USART2 clock source */
<>	144:ef7eb2e8f9f7	327	__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
<>	144:ef7eb2e8f9f7	328	}
<>	144:ef7eb2e8f9f7	329
<>	144:ef7eb2e8f9f7	330	/-------------------------------------- USART3 Configuration -----------------------------------/
<>	144:ef7eb2e8f9f7	331	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
<>	144:ef7eb2e8f9f7	332	{
<>	144:ef7eb2e8f9f7	333	/* Check the parameters */
<>	144:ef7eb2e8f9f7	334	assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
<>	144:ef7eb2e8f9f7	335
<>	144:ef7eb2e8f9f7	336	/* Configure the USART3 clock source */
<>	144:ef7eb2e8f9f7	337	__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
<>	144:ef7eb2e8f9f7	338	}
<>	144:ef7eb2e8f9f7	339
<>	144:ef7eb2e8f9f7	340	/-------------------------------------- UART4 Configuration -----------------------------------/
<>	144:ef7eb2e8f9f7	341	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
<>	144:ef7eb2e8f9f7	342	{
<>	144:ef7eb2e8f9f7	343	/* Check the parameters */
<>	144:ef7eb2e8f9f7	344	assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
<>	144:ef7eb2e8f9f7	345
<>	144:ef7eb2e8f9f7	346	/* Configure the UART4 clock source */
<>	144:ef7eb2e8f9f7	347	__HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
<>	144:ef7eb2e8f9f7	348	}
<>	144:ef7eb2e8f9f7	349
<>	144:ef7eb2e8f9f7	350	/-------------------------------------- UART5 Configuration -----------------------------------/
<>	144:ef7eb2e8f9f7	351	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
<>	144:ef7eb2e8f9f7	352	{
<>	144:ef7eb2e8f9f7	353	/* Check the parameters */
<>	144:ef7eb2e8f9f7	354	assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
<>	144:ef7eb2e8f9f7	355
<>	144:ef7eb2e8f9f7	356	/* Configure the UART5 clock source */
<>	144:ef7eb2e8f9f7	357	__HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
<>	144:ef7eb2e8f9f7	358	}
<>	144:ef7eb2e8f9f7	359
<>	144:ef7eb2e8f9f7	360	/-------------------------------------- USART6 Configuration -----------------------------------/
<>	144:ef7eb2e8f9f7	361	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
<>	144:ef7eb2e8f9f7	362	{
<>	144:ef7eb2e8f9f7	363	/* Check the parameters */
<>	144:ef7eb2e8f9f7	364	assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));
<>	144:ef7eb2e8f9f7	365
<>	144:ef7eb2e8f9f7	366	/* Configure the USART6 clock source */
<>	144:ef7eb2e8f9f7	367	__HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);
<>	144:ef7eb2e8f9f7	368	}
<>	144:ef7eb2e8f9f7	369
<>	144:ef7eb2e8f9f7	370	/-------------------------------------- UART7 Configuration -----------------------------------/
<>	144:ef7eb2e8f9f7	371	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)
<>	144:ef7eb2e8f9f7	372	{
<>	144:ef7eb2e8f9f7	373	/* Check the parameters */
<>	144:ef7eb2e8f9f7	374	assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));
<>	144:ef7eb2e8f9f7	375
<>	144:ef7eb2e8f9f7	376	/* Configure the UART7 clock source */
<>	144:ef7eb2e8f9f7	377	__HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);
<>	144:ef7eb2e8f9f7	378	}
<>	144:ef7eb2e8f9f7	379
<>	144:ef7eb2e8f9f7	380	/-------------------------------------- UART8 Configuration -----------------------------------/
<>	144:ef7eb2e8f9f7	381	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)
<>	144:ef7eb2e8f9f7	382	{
<>	144:ef7eb2e8f9f7	383	/* Check the parameters */
<>	144:ef7eb2e8f9f7	384	assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));
<>	144:ef7eb2e8f9f7	385
<>	144:ef7eb2e8f9f7	386	/* Configure the UART8 clock source */
<>	144:ef7eb2e8f9f7	387	__HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);
<>	144:ef7eb2e8f9f7	388	}
<>	144:ef7eb2e8f9f7	389
<>	144:ef7eb2e8f9f7	390	/--------------------------------------- CEC Configuration -----------------------------------/
<>	144:ef7eb2e8f9f7	391	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
<>	144:ef7eb2e8f9f7	392	{
<>	144:ef7eb2e8f9f7	393	/* Check the parameters */
<>	144:ef7eb2e8f9f7	394	assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
<>	144:ef7eb2e8f9f7	395
<>	144:ef7eb2e8f9f7	396	/* Configure the CEC clock source */
<>	144:ef7eb2e8f9f7	397	__HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
<>	144:ef7eb2e8f9f7	398	}
<>	144:ef7eb2e8f9f7	399
<>	144:ef7eb2e8f9f7	400	/-------------------------------------- CK48 Configuration -----------------------------------/
<>	144:ef7eb2e8f9f7	401	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
<>	144:ef7eb2e8f9f7	402	{
<>	144:ef7eb2e8f9f7	403	/* Check the parameters */
<>	144:ef7eb2e8f9f7	404	assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));
<>	144:ef7eb2e8f9f7	405
<>	144:ef7eb2e8f9f7	406	/* Configure the CLK48 source */
<>	144:ef7eb2e8f9f7	407	__HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
<>	144:ef7eb2e8f9f7	408
<>	144:ef7eb2e8f9f7	409	/* Enable the PLLSAI when it's used as clock source for CK48 */
<>	144:ef7eb2e8f9f7	410	if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)
<>	144:ef7eb2e8f9f7	411	{
<>	144:ef7eb2e8f9f7	412	pllsaiused = 1;
<>	144:ef7eb2e8f9f7	413	}
<>	144:ef7eb2e8f9f7	414	}
<>	144:ef7eb2e8f9f7	415
<>	144:ef7eb2e8f9f7	416	/-------------------------------------- LTDC Configuration -----------------------------------/
<>	144:ef7eb2e8f9f7	417	#if defined(STM32F746xx) \|\| defined(STM32F756xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	418	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
<>	144:ef7eb2e8f9f7	419	{
<>	144:ef7eb2e8f9f7	420	pllsaiused = 1;
<>	144:ef7eb2e8f9f7	421	}
<>	144:ef7eb2e8f9f7	422	#endif /* STM32F746xx \|\| STM32F756xx \|\| STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	423
<>	144:ef7eb2e8f9f7	424	/-------------------------------------- LPTIM1 Configuration -----------------------------------/
<>	144:ef7eb2e8f9f7	425	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
<>	144:ef7eb2e8f9f7	426	{
<>	144:ef7eb2e8f9f7	427	/* Check the parameters */
<>	144:ef7eb2e8f9f7	428	assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
<>	144:ef7eb2e8f9f7	429
<>	144:ef7eb2e8f9f7	430	/* Configure the LTPIM1 clock source */
<>	144:ef7eb2e8f9f7	431	__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
<>	144:ef7eb2e8f9f7	432	}
<>	144:ef7eb2e8f9f7	433
<>	144:ef7eb2e8f9f7	434	/------------------------------------- SDMMC1 Configuration ------------------------------------/
<>	144:ef7eb2e8f9f7	435	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
<>	144:ef7eb2e8f9f7	436	{
<>	144:ef7eb2e8f9f7	437	/* Check the parameters */
<>	144:ef7eb2e8f9f7	438	assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
<>	144:ef7eb2e8f9f7	439
<>	144:ef7eb2e8f9f7	440	/* Configure the SDMMC1 clock source */
<>	144:ef7eb2e8f9f7	441	__HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
<>	144:ef7eb2e8f9f7	442	}
<>	144:ef7eb2e8f9f7	443
<>	144:ef7eb2e8f9f7	444	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	445	/------------------------------------- SDMMC2 Configuration ------------------------------------/
<>	144:ef7eb2e8f9f7	446	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2)
<>	144:ef7eb2e8f9f7	447	{
<>	144:ef7eb2e8f9f7	448	/* Check the parameters */
<>	144:ef7eb2e8f9f7	449	assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection));
<>	144:ef7eb2e8f9f7	450
<>	144:ef7eb2e8f9f7	451	/* Configure the SDMMC2 clock source */
<>	144:ef7eb2e8f9f7	452	__HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection);
<>	144:ef7eb2e8f9f7	453	}
<>	144:ef7eb2e8f9f7	454
<>	144:ef7eb2e8f9f7	455	/------------------------------------- DFSDM1 Configuration -------------------------------------/
<>	144:ef7eb2e8f9f7	456	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
<>	144:ef7eb2e8f9f7	457	{
<>	144:ef7eb2e8f9f7	458	/* Check the parameters */
<>	144:ef7eb2e8f9f7	459	assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
<>	144:ef7eb2e8f9f7	460
<>	144:ef7eb2e8f9f7	461	/* Configure the DFSDM1 interface clock source */
<>	144:ef7eb2e8f9f7	462	__HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
<>	144:ef7eb2e8f9f7	463	}
<>	144:ef7eb2e8f9f7	464
<>	144:ef7eb2e8f9f7	465	/------------------------------------- DFSDM AUDIO Configuration -------------------------------------/
<>	144:ef7eb2e8f9f7	466	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO)
<>	144:ef7eb2e8f9f7	467	{
<>	144:ef7eb2e8f9f7	468	/* Check the parameters */
<>	144:ef7eb2e8f9f7	469	assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection));
<>	144:ef7eb2e8f9f7	470
<>	144:ef7eb2e8f9f7	471	/* Configure the DFSDM interface clock source */
<>	144:ef7eb2e8f9f7	472	__HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection);
<>	144:ef7eb2e8f9f7	473	}
<>	144:ef7eb2e8f9f7	474	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	475
<>	144:ef7eb2e8f9f7	476	/-------------------------------------- PLLI2S Configuration ---------------------------------/
<>	144:ef7eb2e8f9f7	477	/* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */
<>	144:ef7eb2e8f9f7	478	if((plli2sused == 1) \|\| (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
<>	144:ef7eb2e8f9f7	479	{
<>	144:ef7eb2e8f9f7	480	/* Disable the PLLI2S */
<>	144:ef7eb2e8f9f7	481	__HAL_RCC_PLLI2S_DISABLE();
<>	144:ef7eb2e8f9f7	482
<>	144:ef7eb2e8f9f7	483	/* Get Start Tick*/
<>	144:ef7eb2e8f9f7	484	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	485
<>	144:ef7eb2e8f9f7	486	/* Wait till PLLI2S is disabled */
<>	144:ef7eb2e8f9f7	487	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
<>	144:ef7eb2e8f9f7	488	{
<>	144:ef7eb2e8f9f7	489	if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	490	{
<>	144:ef7eb2e8f9f7	491	/* return in case of Timeout detected */
<>	144:ef7eb2e8f9f7	492	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	493	}
<>	144:ef7eb2e8f9f7	494	}
<>	144:ef7eb2e8f9f7	495
<>	144:ef7eb2e8f9f7	496	/* check for common PLLI2S Parameters */
<>	144:ef7eb2e8f9f7	497	assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
<>	144:ef7eb2e8f9f7	498
<>	144:ef7eb2e8f9f7	499	/----------------- In Case of PLLI2S is selected as source clock for I2S -------------------/
<>	144:ef7eb2e8f9f7	500	if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)))
<>	144:ef7eb2e8f9f7	501	{
<>	144:ef7eb2e8f9f7	502	/* check for Parameters */
<>	144:ef7eb2e8f9f7	503	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
<>	144:ef7eb2e8f9f7	504
<>	144:ef7eb2e8f9f7	505	/* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
<>	144:ef7eb2e8f9f7	506	tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP));
<>	144:ef7eb2e8f9f7	507	tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
<>	144:ef7eb2e8f9f7	508	/* Configure the PLLI2S division factors */
<>	144:ef7eb2e8f9f7	509	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
<>	144:ef7eb2e8f9f7	510	/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
<>	144:ef7eb2e8f9f7	511	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR);
<>	144:ef7eb2e8f9f7	512	}
<>	144:ef7eb2e8f9f7	513
<>	144:ef7eb2e8f9f7	514	/----------------- In Case of PLLI2S is selected as source clock for SAI -------------------/
<>	144:ef7eb2e8f9f7	515	if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) \|\|
<>	144:ef7eb2e8f9f7	516	((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
<>	144:ef7eb2e8f9f7	517	{
<>	144:ef7eb2e8f9f7	518	/* Check for PLLI2S Parameters */
<>	144:ef7eb2e8f9f7	519	assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
<>	144:ef7eb2e8f9f7	520	/* Check for PLLI2S/DIVQ parameters */
<>	144:ef7eb2e8f9f7	521	assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
<>	144:ef7eb2e8f9f7	522
<>	144:ef7eb2e8f9f7	523	/* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */
<>	144:ef7eb2e8f9f7	524	tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP));
<>	144:ef7eb2e8f9f7	525	tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
<>	144:ef7eb2e8f9f7	526	/* Configure the PLLI2S division factors */
<>	144:ef7eb2e8f9f7	527	/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
<>	144:ef7eb2e8f9f7	528	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
<>	144:ef7eb2e8f9f7	529	/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
<>	144:ef7eb2e8f9f7	530	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1);
<>	144:ef7eb2e8f9f7	531
<>	144:ef7eb2e8f9f7	532	/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
<>	144:ef7eb2e8f9f7	533	__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
<>	144:ef7eb2e8f9f7	534	}
<>	144:ef7eb2e8f9f7	535
<>	144:ef7eb2e8f9f7	536	/----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------/
<>	144:ef7eb2e8f9f7	537	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
<>	144:ef7eb2e8f9f7	538	{
<>	144:ef7eb2e8f9f7	539	/* check for Parameters */
<>	144:ef7eb2e8f9f7	540	assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
<>	144:ef7eb2e8f9f7	541
<>	144:ef7eb2e8f9f7	542	/* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */
<>	144:ef7eb2e8f9f7	543	tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
<>	144:ef7eb2e8f9f7	544	tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
<>	144:ef7eb2e8f9f7	545	/* Configure the PLLI2S division factors */
<>	144:ef7eb2e8f9f7	546	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
<>	144:ef7eb2e8f9f7	547	/* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
<>	144:ef7eb2e8f9f7	548	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1);
<>	144:ef7eb2e8f9f7	549	}
<>	144:ef7eb2e8f9f7	550
<>	144:ef7eb2e8f9f7	551	/----------------- In Case of PLLI2S is just selected -----------------/
<>	144:ef7eb2e8f9f7	552	if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
<>	144:ef7eb2e8f9f7	553	{
<>	144:ef7eb2e8f9f7	554	/* Check for Parameters */
<>	144:ef7eb2e8f9f7	555	assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
<>	144:ef7eb2e8f9f7	556	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
<>	144:ef7eb2e8f9f7	557	assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
<>	144:ef7eb2e8f9f7	558
<>	144:ef7eb2e8f9f7	559	/* Configure the PLLI2S division factors */
<>	144:ef7eb2e8f9f7	560	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */
<>	144:ef7eb2e8f9f7	561	/* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
<>	144:ef7eb2e8f9f7	562	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
<>	144:ef7eb2e8f9f7	563	}
<>	144:ef7eb2e8f9f7	564
<>	144:ef7eb2e8f9f7	565	/* Enable the PLLI2S */
<>	144:ef7eb2e8f9f7	566	__HAL_RCC_PLLI2S_ENABLE();
<>	144:ef7eb2e8f9f7	567
<>	144:ef7eb2e8f9f7	568	/* Get Start Tick*/
<>	144:ef7eb2e8f9f7	569	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	570
<>	144:ef7eb2e8f9f7	571	/* Wait till PLLI2S is ready */
<>	144:ef7eb2e8f9f7	572	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
<>	144:ef7eb2e8f9f7	573	{
<>	144:ef7eb2e8f9f7	574	if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	575	{
<>	144:ef7eb2e8f9f7	576	/* return in case of Timeout detected */
<>	144:ef7eb2e8f9f7	577	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	578	}
<>	144:ef7eb2e8f9f7	579	}
<>	144:ef7eb2e8f9f7	580	}
<>	144:ef7eb2e8f9f7	581
<>	144:ef7eb2e8f9f7	582	/-------------------------------------- PLLSAI Configuration ---------------------------------/
<>	144:ef7eb2e8f9f7	583	/* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */
<>	144:ef7eb2e8f9f7	584	if(pllsaiused == 1)
<>	144:ef7eb2e8f9f7	585	{
<>	144:ef7eb2e8f9f7	586	/* Disable PLLSAI Clock */
<>	144:ef7eb2e8f9f7	587	__HAL_RCC_PLLSAI_DISABLE();
<>	144:ef7eb2e8f9f7	588
<>	144:ef7eb2e8f9f7	589	/* Get Start Tick*/
<>	144:ef7eb2e8f9f7	590	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	591
<>	144:ef7eb2e8f9f7	592	/* Wait till PLLSAI is disabled */
<>	144:ef7eb2e8f9f7	593	while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
<>	144:ef7eb2e8f9f7	594	{
<>	144:ef7eb2e8f9f7	595	if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	596	{
<>	144:ef7eb2e8f9f7	597	/* return in case of Timeout detected */
<>	144:ef7eb2e8f9f7	598	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	599	}
<>	144:ef7eb2e8f9f7	600	}
<>	144:ef7eb2e8f9f7	601
<>	144:ef7eb2e8f9f7	602	/* Check the PLLSAI division factors */
<>	144:ef7eb2e8f9f7	603	assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
<>	144:ef7eb2e8f9f7	604
<>	144:ef7eb2e8f9f7	605	/----------------- In Case of PLLSAI is selected as source clock for SAI -------------------/
<>	144:ef7eb2e8f9f7	606	if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) \|\|\
<>	144:ef7eb2e8f9f7	607	((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
<>	144:ef7eb2e8f9f7	608	{
<>	144:ef7eb2e8f9f7	609	/* check for PLLSAIQ Parameter */
<>	144:ef7eb2e8f9f7	610	assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
<>	144:ef7eb2e8f9f7	611	/* check for PLLSAI/DIVQ Parameter */
<>	144:ef7eb2e8f9f7	612	assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
<>	144:ef7eb2e8f9f7	613
<>	144:ef7eb2e8f9f7	614	/* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
<>	144:ef7eb2e8f9f7	615	tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP));
<>	144:ef7eb2e8f9f7	616	tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
<>	144:ef7eb2e8f9f7	617	/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
<>	144:ef7eb2e8f9f7	618	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
<>	144:ef7eb2e8f9f7	619	/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
<>	144:ef7eb2e8f9f7	620	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
<>	144:ef7eb2e8f9f7	621
<>	144:ef7eb2e8f9f7	622	/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
<>	144:ef7eb2e8f9f7	623	__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
<>	144:ef7eb2e8f9f7	624	}
<>	144:ef7eb2e8f9f7	625
<>	144:ef7eb2e8f9f7	626	/----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------/
<>	144:ef7eb2e8f9f7	627	/* In Case of PLLI2S is selected as source clock for CK48 */
<>	144:ef7eb2e8f9f7	628	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP))
<>	144:ef7eb2e8f9f7	629	{
<>	144:ef7eb2e8f9f7	630	/* check for Parameters */
<>	144:ef7eb2e8f9f7	631	assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
<>	144:ef7eb2e8f9f7	632	/* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */
<>	144:ef7eb2e8f9f7	633	tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
<>	144:ef7eb2e8f9f7	634	tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
<>	144:ef7eb2e8f9f7	635
<>	144:ef7eb2e8f9f7	636	/* Configure the PLLSAI division factors */
<>	144:ef7eb2e8f9f7	637	/* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */
<>	144:ef7eb2e8f9f7	638	/* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
<>	144:ef7eb2e8f9f7	639	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1);
<>	144:ef7eb2e8f9f7	640	}
<>	144:ef7eb2e8f9f7	641
<>	144:ef7eb2e8f9f7	642	#if defined(STM32F746xx) \|\| defined(STM32F756xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	643	/---------------------------- LTDC configuration -------------------------------/
<>	144:ef7eb2e8f9f7	644	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
<>	144:ef7eb2e8f9f7	645	{
<>	144:ef7eb2e8f9f7	646	assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
<>	144:ef7eb2e8f9f7	647	assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
<>	144:ef7eb2e8f9f7	648
<>	144:ef7eb2e8f9f7	649	/* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */
<>	144:ef7eb2e8f9f7	650	tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
<>	144:ef7eb2e8f9f7	651	tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP));
<>	144:ef7eb2e8f9f7	652
<>	144:ef7eb2e8f9f7	653	/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
<>	144:ef7eb2e8f9f7	654	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
<>	144:ef7eb2e8f9f7	655	/* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
<>	144:ef7eb2e8f9f7	656	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR);
<>	144:ef7eb2e8f9f7	657
<>	144:ef7eb2e8f9f7	658	/* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
<>	144:ef7eb2e8f9f7	659	__HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
<>	144:ef7eb2e8f9f7	660	}
<>	144:ef7eb2e8f9f7	661	#endif /* STM32F746xx \|\| STM32F756xx \|\| STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	662
<>	144:ef7eb2e8f9f7	663	/* Enable PLLSAI Clock */
<>	144:ef7eb2e8f9f7	664	__HAL_RCC_PLLSAI_ENABLE();
<>	144:ef7eb2e8f9f7	665
<>	144:ef7eb2e8f9f7	666	/* Get Start Tick*/
<>	144:ef7eb2e8f9f7	667	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	668
<>	144:ef7eb2e8f9f7	669	/* Wait till PLLSAI is ready */
<>	144:ef7eb2e8f9f7	670	while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
<>	144:ef7eb2e8f9f7	671	{
<>	144:ef7eb2e8f9f7	672	if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	673	{
<>	144:ef7eb2e8f9f7	674	/* return in case of Timeout detected */
<>	144:ef7eb2e8f9f7	675	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	676	}
<>	144:ef7eb2e8f9f7	677	}
<>	144:ef7eb2e8f9f7	678	}
<>	144:ef7eb2e8f9f7	679	return HAL_OK;
<>	144:ef7eb2e8f9f7	680	}
<>	144:ef7eb2e8f9f7	681
<>	144:ef7eb2e8f9f7	682	/**
<>	144:ef7eb2e8f9f7	683	* @brief Get the RCC_PeriphCLKInitTypeDef according to the internal
<>	144:ef7eb2e8f9f7	684	* RCC configuration registers.
<>	144:ef7eb2e8f9f7	685	* @param PeriphClkInit: pointer to the configured RCC_PeriphCLKInitTypeDef structure
<>	144:ef7eb2e8f9f7	686	* @retval None
<>	144:ef7eb2e8f9f7	687	*/
<>	144:ef7eb2e8f9f7	688	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
<>	144:ef7eb2e8f9f7	689	{
<>	144:ef7eb2e8f9f7	690	uint32_t tempreg = 0;
<>	144:ef7eb2e8f9f7	691
<>	144:ef7eb2e8f9f7	692	/* Set all possible values for the extended clock type parameter------------*/
<>	144:ef7eb2e8f9f7	693	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	694	PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_LPTIM1 \|\
<>	144:ef7eb2e8f9f7	695	RCC_PERIPHCLK_SAI1 \| RCC_PERIPHCLK_SAI2 \|\
<>	144:ef7eb2e8f9f7	696	RCC_PERIPHCLK_TIM \| RCC_PERIPHCLK_RTC \|\
<>	144:ef7eb2e8f9f7	697	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_I2C4 \|\
<>	144:ef7eb2e8f9f7	698	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \|\
<>	144:ef7eb2e8f9f7	699	RCC_PERIPHCLK_I2C3 \| RCC_PERIPHCLK_USART1 \|\
<>	144:ef7eb2e8f9f7	700	RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \|\
<>	144:ef7eb2e8f9f7	701	RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \|\
<>	144:ef7eb2e8f9f7	702	RCC_PERIPHCLK_USART6 \| RCC_PERIPHCLK_UART7 \|\
<>	144:ef7eb2e8f9f7	703	RCC_PERIPHCLK_UART8 \| RCC_PERIPHCLK_SDMMC1 \|\
<>	144:ef7eb2e8f9f7	704	RCC_PERIPHCLK_CLK48 \| RCC_PERIPHCLK_SDMMC2 \|\
<>	144:ef7eb2e8f9f7	705	RCC_PERIPHCLK_DFSDM1 \| RCC_PERIPHCLK_DFSDM1_AUDIO;
<>	144:ef7eb2e8f9f7	706	#else
<>	144:ef7eb2e8f9f7	707	PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_LPTIM1 \|\
<>	144:ef7eb2e8f9f7	708	RCC_PERIPHCLK_SAI1 \| RCC_PERIPHCLK_SAI2 \|\
<>	144:ef7eb2e8f9f7	709	RCC_PERIPHCLK_TIM \| RCC_PERIPHCLK_RTC \|\
<>	144:ef7eb2e8f9f7	710	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_I2C4 \|\
<>	144:ef7eb2e8f9f7	711	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \|\
<>	144:ef7eb2e8f9f7	712	RCC_PERIPHCLK_I2C3 \| RCC_PERIPHCLK_USART1 \|\
<>	144:ef7eb2e8f9f7	713	RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \|\
<>	144:ef7eb2e8f9f7	714	RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \|\
<>	144:ef7eb2e8f9f7	715	RCC_PERIPHCLK_USART6 \| RCC_PERIPHCLK_UART7 \|\
<>	144:ef7eb2e8f9f7	716	RCC_PERIPHCLK_UART8 \| RCC_PERIPHCLK_SDMMC1 \|\
<>	144:ef7eb2e8f9f7	717	RCC_PERIPHCLK_CLK48;
<>	144:ef7eb2e8f9f7	718	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	719
<>	144:ef7eb2e8f9f7	720	/* Get the PLLI2S Clock configuration -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	721	PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
<>	144:ef7eb2e8f9f7	722	PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP));
<>	144:ef7eb2e8f9f7	723	PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
<>	144:ef7eb2e8f9f7	724	PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
<>	144:ef7eb2e8f9f7	725
<>	144:ef7eb2e8f9f7	726	/* Get the PLLSAI Clock configuration -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	727	PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
<>	144:ef7eb2e8f9f7	728	PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP));
<>	144:ef7eb2e8f9f7	729	PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
<>	144:ef7eb2e8f9f7	730	PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
<>	144:ef7eb2e8f9f7	731
<>	144:ef7eb2e8f9f7	732	/* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/
<>	144:ef7eb2e8f9f7	733	PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR1_PLLI2SDIVQ));
<>	144:ef7eb2e8f9f7	734	PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR1_PLLSAIDIVQ));
<>	144:ef7eb2e8f9f7	735	PeriphClkInit->PLLSAIDivR = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVR) >> POSITION_VAL(RCC_DCKCFGR1_PLLSAIDIVR));
<>	144:ef7eb2e8f9f7	736
<>	144:ef7eb2e8f9f7	737	/* Get the SAI1 clock configuration ----------------------------------------------*/
<>	144:ef7eb2e8f9f7	738	PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
<>	144:ef7eb2e8f9f7	739
<>	144:ef7eb2e8f9f7	740	/* Get the SAI2 clock configuration ----------------------------------------------*/
<>	144:ef7eb2e8f9f7	741	PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
<>	144:ef7eb2e8f9f7	742
<>	144:ef7eb2e8f9f7	743	/* Get the I2S clock configuration ------------------------------------------*/
<>	144:ef7eb2e8f9f7	744	PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2SCLKSOURCE();
<>	144:ef7eb2e8f9f7	745
<>	144:ef7eb2e8f9f7	746	/* Get the I2C1 clock configuration ------------------------------------------*/
<>	144:ef7eb2e8f9f7	747	PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
<>	144:ef7eb2e8f9f7	748
<>	144:ef7eb2e8f9f7	749	/* Get the I2C2 clock configuration ------------------------------------------*/
<>	144:ef7eb2e8f9f7	750	PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
<>	144:ef7eb2e8f9f7	751
<>	144:ef7eb2e8f9f7	752	/* Get the I2C3 clock configuration ------------------------------------------*/
<>	144:ef7eb2e8f9f7	753	PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
<>	144:ef7eb2e8f9f7	754
<>	144:ef7eb2e8f9f7	755	/* Get the I2C4 clock configuration ------------------------------------------*/
<>	144:ef7eb2e8f9f7	756	PeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE();
<>	144:ef7eb2e8f9f7	757
<>	144:ef7eb2e8f9f7	758	/* Get the USART1 clock configuration ------------------------------------------*/
<>	144:ef7eb2e8f9f7	759	PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
<>	144:ef7eb2e8f9f7	760
<>	144:ef7eb2e8f9f7	761	/* Get the USART2 clock configuration ------------------------------------------*/
<>	144:ef7eb2e8f9f7	762	PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
<>	144:ef7eb2e8f9f7	763
<>	144:ef7eb2e8f9f7	764	/* Get the USART3 clock configuration ------------------------------------------*/
<>	144:ef7eb2e8f9f7	765	PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
<>	144:ef7eb2e8f9f7	766
<>	144:ef7eb2e8f9f7	767	/* Get the UART4 clock configuration ------------------------------------------*/
<>	144:ef7eb2e8f9f7	768	PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();
<>	144:ef7eb2e8f9f7	769
<>	144:ef7eb2e8f9f7	770	/* Get the UART5 clock configuration ------------------------------------------*/
<>	144:ef7eb2e8f9f7	771	PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();
<>	144:ef7eb2e8f9f7	772
<>	144:ef7eb2e8f9f7	773	/* Get the USART6 clock configuration ------------------------------------------*/
<>	144:ef7eb2e8f9f7	774	PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE();
<>	144:ef7eb2e8f9f7	775
<>	144:ef7eb2e8f9f7	776	/* Get the UART7 clock configuration ------------------------------------------*/
<>	144:ef7eb2e8f9f7	777	PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE();
<>	144:ef7eb2e8f9f7	778
<>	144:ef7eb2e8f9f7	779	/* Get the UART8 clock configuration ------------------------------------------*/
<>	144:ef7eb2e8f9f7	780	PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE();
<>	144:ef7eb2e8f9f7	781
<>	144:ef7eb2e8f9f7	782	/* Get the LPTIM1 clock configuration ------------------------------------------*/
<>	144:ef7eb2e8f9f7	783	PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
<>	144:ef7eb2e8f9f7	784
<>	144:ef7eb2e8f9f7	785	/* Get the CEC clock configuration -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	786	PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
<>	144:ef7eb2e8f9f7	787
<>	144:ef7eb2e8f9f7	788	/* Get the CK48 clock configuration -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	789	PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
<>	144:ef7eb2e8f9f7	790
<>	144:ef7eb2e8f9f7	791	/* Get the SDMMC1 clock configuration -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	792	PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE();
<>	144:ef7eb2e8f9f7	793
<>	144:ef7eb2e8f9f7	794	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	795	/* Get the SDMMC2 clock configuration -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	796	PeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE();
<>	144:ef7eb2e8f9f7	797
<>	144:ef7eb2e8f9f7	798	/* Get the DFSDM clock configuration -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	799	PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE();
<>	144:ef7eb2e8f9f7	800
<>	144:ef7eb2e8f9f7	801	/* Get the DFSDM AUDIO clock configuration -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	802	PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE();
<>	144:ef7eb2e8f9f7	803	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	804
<>	144:ef7eb2e8f9f7	805	/* Get the RTC Clock configuration -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	806	tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
<>	144:ef7eb2e8f9f7	807	PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) \| (RCC->BDCR & RCC_BDCR_RTCSEL));
<>	144:ef7eb2e8f9f7	808
<>	144:ef7eb2e8f9f7	809	/* Get the TIM Prescaler configuration --------------------------------------------*/
<>	144:ef7eb2e8f9f7	810	if ((RCC->DCKCFGR1 & RCC_DCKCFGR1_TIMPRE) == RESET)
<>	144:ef7eb2e8f9f7	811	{
<>	144:ef7eb2e8f9f7	812	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
<>	144:ef7eb2e8f9f7	813	}
<>	144:ef7eb2e8f9f7	814	else
<>	144:ef7eb2e8f9f7	815	{
<>	144:ef7eb2e8f9f7	816	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
<>	144:ef7eb2e8f9f7	817	}
<>	144:ef7eb2e8f9f7	818	}
<>	157:ff67d9f36b67	819	#endif /* STM32F745xx \|\| STM32F746xx \|\| STM32F756xx \|\| STM32F765xx \|\| STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	820
<>	161:2cc1468da177	821	#if defined (STM32F722xx) \|\| defined (STM32F723xx) \|\| defined (STM32F732xx) \|\| defined (STM32F733xx)
<>	161:2cc1468da177	822	/**
<>	161:2cc1468da177	823	* @brief Initializes the RCC extended peripherals clocks according to the specified
<>	161:2cc1468da177	824	* parameters in the RCC_PeriphCLKInitTypeDef.
<>	161:2cc1468da177	825	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
<>	161:2cc1468da177	826	* contains the configuration information for the Extended Peripherals
<>	161:2cc1468da177	827	* clocks(I2S, SAI, RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...).
<>	161:2cc1468da177	828	*
<>	161:2cc1468da177	829	* @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
<>	161:2cc1468da177	830	* the RTC clock source; in this case the Backup domain will be reset in
<>	161:2cc1468da177	831	* order to modify the RTC Clock source, as consequence RTC registers (including
<>	161:2cc1468da177	832	* the backup registers) are set to their reset values.
<>	161:2cc1468da177	833	*
<>	161:2cc1468da177	834	* @retval HAL status
<>	161:2cc1468da177	835	*/
<>	161:2cc1468da177	836	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
<>	161:2cc1468da177	837	{
<>	161:2cc1468da177	838	uint32_t tickstart = 0;
<>	161:2cc1468da177	839	uint32_t tmpreg0 = 0;
<>	161:2cc1468da177	840	uint32_t plli2sused = 0;
<>	161:2cc1468da177	841	uint32_t pllsaiused = 0;
<>	161:2cc1468da177	842
<>	161:2cc1468da177	843	/* Check the parameters */
<>	161:2cc1468da177	844	assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
<>	161:2cc1468da177	845
<>	161:2cc1468da177	846	/----------------------------------- I2S configuration ----------------------------------/
<>	161:2cc1468da177	847	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
<>	161:2cc1468da177	848	{
<>	161:2cc1468da177	849	/* Check the parameters */
<>	161:2cc1468da177	850	assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
<>	161:2cc1468da177	851
<>	161:2cc1468da177	852	/* Configure I2S Clock source */
<>	161:2cc1468da177	853	__HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
<>	161:2cc1468da177	854
<>	161:2cc1468da177	855	/* Enable the PLLI2S when it's used as clock source for I2S */
<>	161:2cc1468da177	856	if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)
<>	161:2cc1468da177	857	{
<>	161:2cc1468da177	858	plli2sused = 1;
<>	161:2cc1468da177	859	}
<>	161:2cc1468da177	860	}
<>	161:2cc1468da177	861
<>	161:2cc1468da177	862	/------------------------------------ SAI1 configuration --------------------------------------/
<>	161:2cc1468da177	863	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
<>	161:2cc1468da177	864	{
<>	161:2cc1468da177	865	/* Check the parameters */
<>	161:2cc1468da177	866	assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
<>	161:2cc1468da177	867
<>	161:2cc1468da177	868	/* Configure SAI1 Clock source */
<>	161:2cc1468da177	869	__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
<>	161:2cc1468da177	870	/* Enable the PLLI2S when it's used as clock source for SAI */
<>	161:2cc1468da177	871	if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
<>	161:2cc1468da177	872	{
<>	161:2cc1468da177	873	plli2sused = 1;
<>	161:2cc1468da177	874	}
<>	161:2cc1468da177	875	/* Enable the PLLSAI when it's used as clock source for SAI */
<>	161:2cc1468da177	876	if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
<>	161:2cc1468da177	877	{
<>	161:2cc1468da177	878	pllsaiused = 1;
<>	161:2cc1468da177	879	}
<>	161:2cc1468da177	880	}
<>	161:2cc1468da177	881
<>	161:2cc1468da177	882	/------------------------------------ SAI2 configuration --------------------------------------/
<>	161:2cc1468da177	883	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
<>	161:2cc1468da177	884	{
<>	161:2cc1468da177	885	/* Check the parameters */
<>	161:2cc1468da177	886	assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
<>	161:2cc1468da177	887
<>	161:2cc1468da177	888	/* Configure SAI2 Clock source */
<>	161:2cc1468da177	889	__HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
<>	161:2cc1468da177	890
<>	161:2cc1468da177	891	/* Enable the PLLI2S when it's used as clock source for SAI */
<>	161:2cc1468da177	892	if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
<>	161:2cc1468da177	893	{
<>	161:2cc1468da177	894	plli2sused = 1;
<>	161:2cc1468da177	895	}
<>	161:2cc1468da177	896	/* Enable the PLLSAI when it's used as clock source for SAI */
<>	161:2cc1468da177	897	if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
<>	161:2cc1468da177	898	{
<>	161:2cc1468da177	899	pllsaiused = 1;
<>	161:2cc1468da177	900	}
<>	161:2cc1468da177	901	}
<>	161:2cc1468da177	902
<>	161:2cc1468da177	903	/------------------------------------ RTC configuration --------------------------------------/
<>	161:2cc1468da177	904	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
<>	161:2cc1468da177	905	{
<>	161:2cc1468da177	906	/* Check for RTC Parameters used to output RTCCLK */
<>	161:2cc1468da177	907	assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
<>	161:2cc1468da177	908
<>	161:2cc1468da177	909	/* Enable Power Clock*/
<>	161:2cc1468da177	910	__HAL_RCC_PWR_CLK_ENABLE();
<>	161:2cc1468da177	911
<>	161:2cc1468da177	912	/* Enable write access to Backup domain */
<>	161:2cc1468da177	913	PWR->CR1 \|= PWR_CR1_DBP;
<>	161:2cc1468da177	914
<>	161:2cc1468da177	915	/* Get Start Tick*/
<>	161:2cc1468da177	916	tickstart = HAL_GetTick();
<>	161:2cc1468da177	917
<>	161:2cc1468da177	918	/* Wait for Backup domain Write protection disable */
<>	161:2cc1468da177	919	while((PWR->CR1 & PWR_CR1_DBP) == RESET)
<>	161:2cc1468da177	920	{
<>	161:2cc1468da177	921	if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
<>	161:2cc1468da177	922	{
<>	161:2cc1468da177	923	return HAL_TIMEOUT;
<>	161:2cc1468da177	924	}
<>	161:2cc1468da177	925	}
<>	161:2cc1468da177	926
<>	161:2cc1468da177	927	/* Reset the Backup domain only if the RTC Clock source selection is modified */
<>	161:2cc1468da177	928	tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL);
<>	161:2cc1468da177	929
<>	161:2cc1468da177	930	if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
<>	161:2cc1468da177	931	{
<>	161:2cc1468da177	932	/* Store the content of BDCR register before the reset of Backup Domain */
<>	161:2cc1468da177	933	tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
<>	161:2cc1468da177	934
<>	161:2cc1468da177	935	/* RTC Clock selection can be changed only if the Backup Domain is reset */
<>	161:2cc1468da177	936	__HAL_RCC_BACKUPRESET_FORCE();
<>	161:2cc1468da177	937	__HAL_RCC_BACKUPRESET_RELEASE();
<>	161:2cc1468da177	938
<>	161:2cc1468da177	939	/* Restore the Content of BDCR register */
<>	161:2cc1468da177	940	RCC->BDCR = tmpreg0;
<>	161:2cc1468da177	941
<>	161:2cc1468da177	942	/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
<>	161:2cc1468da177	943	if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
<>	161:2cc1468da177	944	{
<>	161:2cc1468da177	945	/* Get Start Tick*/
<>	161:2cc1468da177	946	tickstart = HAL_GetTick();
<>	161:2cc1468da177	947
<>	161:2cc1468da177	948	/* Wait till LSE is ready */
<>	161:2cc1468da177	949	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
<>	161:2cc1468da177	950	{
<>	161:2cc1468da177	951	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
<>	161:2cc1468da177	952	{
<>	161:2cc1468da177	953	return HAL_TIMEOUT;
<>	161:2cc1468da177	954	}
<>	161:2cc1468da177	955	}
<>	161:2cc1468da177	956	}
<>	161:2cc1468da177	957	}
<>	161:2cc1468da177	958	__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
<>	161:2cc1468da177	959	}
<>	161:2cc1468da177	960
<>	161:2cc1468da177	961	/------------------------------------ TIM configuration --------------------------------------/
<>	161:2cc1468da177	962	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
<>	161:2cc1468da177	963	{
<>	161:2cc1468da177	964	/* Check the parameters */
<>	161:2cc1468da177	965	assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
<>	161:2cc1468da177	966
<>	161:2cc1468da177	967	/* Configure Timer Prescaler */
<>	161:2cc1468da177	968	__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
<>	161:2cc1468da177	969	}
<>	161:2cc1468da177	970
<>	161:2cc1468da177	971	/-------------------------------------- I2C1 Configuration -----------------------------------/
<>	161:2cc1468da177	972	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
<>	161:2cc1468da177	973	{
<>	161:2cc1468da177	974	/* Check the parameters */
<>	161:2cc1468da177	975	assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
<>	161:2cc1468da177	976
<>	161:2cc1468da177	977	/* Configure the I2C1 clock source */
<>	161:2cc1468da177	978	__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
<>	161:2cc1468da177	979	}
<>	161:2cc1468da177	980
<>	161:2cc1468da177	981	/-------------------------------------- I2C2 Configuration -----------------------------------/
<>	161:2cc1468da177	982	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
<>	161:2cc1468da177	983	{
<>	161:2cc1468da177	984	/* Check the parameters */
<>	161:2cc1468da177	985	assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
<>	161:2cc1468da177	986
<>	161:2cc1468da177	987	/* Configure the I2C2 clock source */
<>	161:2cc1468da177	988	__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
<>	161:2cc1468da177	989	}
<>	161:2cc1468da177	990
<>	161:2cc1468da177	991	/-------------------------------------- I2C3 Configuration -----------------------------------/
<>	161:2cc1468da177	992	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
<>	161:2cc1468da177	993	{
<>	161:2cc1468da177	994	/* Check the parameters */
<>	161:2cc1468da177	995	assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
<>	161:2cc1468da177	996
<>	161:2cc1468da177	997	/* Configure the I2C3 clock source */
<>	161:2cc1468da177	998	__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
<>	161:2cc1468da177	999	}
<>	161:2cc1468da177	1000
<>	161:2cc1468da177	1001	/-------------------------------------- USART1 Configuration -----------------------------------/
<>	161:2cc1468da177	1002	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
<>	161:2cc1468da177	1003	{
<>	161:2cc1468da177	1004	/* Check the parameters */
<>	161:2cc1468da177	1005	assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
<>	161:2cc1468da177	1006
<>	161:2cc1468da177	1007	/* Configure the USART1 clock source */
<>	161:2cc1468da177	1008	__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
<>	161:2cc1468da177	1009	}
<>	161:2cc1468da177	1010
<>	161:2cc1468da177	1011	/-------------------------------------- USART2 Configuration -----------------------------------/
<>	161:2cc1468da177	1012	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
<>	161:2cc1468da177	1013	{
<>	161:2cc1468da177	1014	/* Check the parameters */
<>	161:2cc1468da177	1015	assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
<>	161:2cc1468da177	1016
<>	161:2cc1468da177	1017	/* Configure the USART2 clock source */
<>	161:2cc1468da177	1018	__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
<>	161:2cc1468da177	1019	}
<>	161:2cc1468da177	1020
<>	161:2cc1468da177	1021	/-------------------------------------- USART3 Configuration -----------------------------------/
<>	161:2cc1468da177	1022	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
<>	161:2cc1468da177	1023	{
<>	161:2cc1468da177	1024	/* Check the parameters */
<>	161:2cc1468da177	1025	assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
<>	161:2cc1468da177	1026
<>	161:2cc1468da177	1027	/* Configure the USART3 clock source */
<>	161:2cc1468da177	1028	__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
<>	161:2cc1468da177	1029	}
<>	161:2cc1468da177	1030
<>	161:2cc1468da177	1031	/-------------------------------------- UART4 Configuration -----------------------------------/
<>	161:2cc1468da177	1032	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
<>	161:2cc1468da177	1033	{
<>	161:2cc1468da177	1034	/* Check the parameters */
<>	161:2cc1468da177	1035	assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
<>	161:2cc1468da177	1036
<>	161:2cc1468da177	1037	/* Configure the UART4 clock source */
<>	161:2cc1468da177	1038	__HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
<>	161:2cc1468da177	1039	}
<>	161:2cc1468da177	1040
<>	161:2cc1468da177	1041	/-------------------------------------- UART5 Configuration -----------------------------------/
<>	161:2cc1468da177	1042	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
<>	161:2cc1468da177	1043	{
<>	161:2cc1468da177	1044	/* Check the parameters */
<>	161:2cc1468da177	1045	assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
<>	161:2cc1468da177	1046
<>	161:2cc1468da177	1047	/* Configure the UART5 clock source */
<>	161:2cc1468da177	1048	__HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
<>	161:2cc1468da177	1049	}
<>	161:2cc1468da177	1050
<>	161:2cc1468da177	1051	/-------------------------------------- USART6 Configuration -----------------------------------/
<>	161:2cc1468da177	1052	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
<>	161:2cc1468da177	1053	{
<>	161:2cc1468da177	1054	/* Check the parameters */
<>	161:2cc1468da177	1055	assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));
<>	161:2cc1468da177	1056
<>	161:2cc1468da177	1057	/* Configure the USART6 clock source */
<>	161:2cc1468da177	1058	__HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);
<>	161:2cc1468da177	1059	}
<>	161:2cc1468da177	1060
<>	161:2cc1468da177	1061	/-------------------------------------- UART7 Configuration -----------------------------------/
<>	161:2cc1468da177	1062	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)
<>	161:2cc1468da177	1063	{
<>	161:2cc1468da177	1064	/* Check the parameters */
<>	161:2cc1468da177	1065	assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));
<>	161:2cc1468da177	1066
<>	161:2cc1468da177	1067	/* Configure the UART7 clock source */
<>	161:2cc1468da177	1068	__HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);
<>	161:2cc1468da177	1069	}
<>	161:2cc1468da177	1070
<>	161:2cc1468da177	1071	/-------------------------------------- UART8 Configuration -----------------------------------/
<>	161:2cc1468da177	1072	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)
<>	161:2cc1468da177	1073	{
<>	161:2cc1468da177	1074	/* Check the parameters */
<>	161:2cc1468da177	1075	assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));
<>	161:2cc1468da177	1076
<>	161:2cc1468da177	1077	/* Configure the UART8 clock source */
<>	161:2cc1468da177	1078	__HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);
<>	161:2cc1468da177	1079	}
<>	161:2cc1468da177	1080
<>	161:2cc1468da177	1081	/-------------------------------------- CK48 Configuration -----------------------------------/
<>	161:2cc1468da177	1082	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
<>	161:2cc1468da177	1083	{
<>	161:2cc1468da177	1084	/* Check the parameters */
<>	161:2cc1468da177	1085	assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));
<>	161:2cc1468da177	1086
<>	161:2cc1468da177	1087	/* Configure the CLK48 source */
<>	161:2cc1468da177	1088	__HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
<>	161:2cc1468da177	1089
<>	161:2cc1468da177	1090	/* Enable the PLLSAI when it's used as clock source for CK48 */
<>	161:2cc1468da177	1091	if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)
<>	161:2cc1468da177	1092	{
<>	161:2cc1468da177	1093	pllsaiused = 1;
<>	161:2cc1468da177	1094	}
<>	161:2cc1468da177	1095	}
<>	161:2cc1468da177	1096
<>	161:2cc1468da177	1097	/-------------------------------------- LPTIM1 Configuration -----------------------------------/
<>	161:2cc1468da177	1098	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
<>	161:2cc1468da177	1099	{
<>	161:2cc1468da177	1100	/* Check the parameters */
<>	161:2cc1468da177	1101	assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
<>	161:2cc1468da177	1102
<>	161:2cc1468da177	1103	/* Configure the LTPIM1 clock source */
<>	161:2cc1468da177	1104	__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
<>	161:2cc1468da177	1105	}
<>	161:2cc1468da177	1106
<>	161:2cc1468da177	1107	/------------------------------------- SDMMC1 Configuration ------------------------------------/
<>	161:2cc1468da177	1108	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
<>	161:2cc1468da177	1109	{
<>	161:2cc1468da177	1110	/* Check the parameters */
<>	161:2cc1468da177	1111	assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
<>	161:2cc1468da177	1112
<>	161:2cc1468da177	1113	/* Configure the SDMMC1 clock source */
<>	161:2cc1468da177	1114	__HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
<>	161:2cc1468da177	1115	}
<>	161:2cc1468da177	1116
<>	161:2cc1468da177	1117	/------------------------------------- SDMMC2 Configuration ------------------------------------/
<>	161:2cc1468da177	1118	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2)
<>	161:2cc1468da177	1119	{
<>	161:2cc1468da177	1120	/* Check the parameters */
<>	161:2cc1468da177	1121	assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection));
<>	161:2cc1468da177	1122
<>	161:2cc1468da177	1123	/* Configure the SDMMC2 clock source */
<>	161:2cc1468da177	1124	__HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection);
<>	161:2cc1468da177	1125	}
<>	161:2cc1468da177	1126
<>	161:2cc1468da177	1127	/-------------------------------------- PLLI2S Configuration ---------------------------------/
<>	161:2cc1468da177	1128	/* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2 or I2S */
<>	161:2cc1468da177	1129	if((plli2sused == 1) \|\| (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
<>	161:2cc1468da177	1130	{
<>	161:2cc1468da177	1131	/* Disable the PLLI2S */
<>	161:2cc1468da177	1132	__HAL_RCC_PLLI2S_DISABLE();
<>	161:2cc1468da177	1133
<>	161:2cc1468da177	1134	/* Get Start Tick*/
<>	161:2cc1468da177	1135	tickstart = HAL_GetTick();
<>	161:2cc1468da177	1136
<>	161:2cc1468da177	1137	/* Wait till PLLI2S is disabled */
<>	161:2cc1468da177	1138	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
<>	161:2cc1468da177	1139	{
<>	161:2cc1468da177	1140	if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
<>	161:2cc1468da177	1141	{
<>	161:2cc1468da177	1142	/* return in case of Timeout detected */
<>	161:2cc1468da177	1143	return HAL_TIMEOUT;
<>	161:2cc1468da177	1144	}
<>	161:2cc1468da177	1145	}
<>	161:2cc1468da177	1146
<>	161:2cc1468da177	1147	/* check for common PLLI2S Parameters */
<>	161:2cc1468da177	1148	assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
<>	161:2cc1468da177	1149
<>	161:2cc1468da177	1150	/----------------- In Case of PLLI2S is selected as source clock for I2S -------------------/
<>	161:2cc1468da177	1151	if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)))
<>	161:2cc1468da177	1152	{
<>	161:2cc1468da177	1153	/* check for Parameters */
<>	161:2cc1468da177	1154	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
<>	161:2cc1468da177	1155
<>	161:2cc1468da177	1156	/* Read PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
<>	161:2cc1468da177	1157	tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
<>	161:2cc1468da177	1158	/* Configure the PLLI2S division factors */
<>	161:2cc1468da177	1159	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
<>	161:2cc1468da177	1160	/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
<>	161:2cc1468da177	1161	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, PeriphClkInit->PLLI2S.PLLI2SR);
<>	161:2cc1468da177	1162	}
<>	161:2cc1468da177	1163
<>	161:2cc1468da177	1164	/----------------- In Case of PLLI2S is selected as source clock for SAI -------------------/
<>	161:2cc1468da177	1165	if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) \|\|
<>	161:2cc1468da177	1166	((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
<>	161:2cc1468da177	1167	{
<>	161:2cc1468da177	1168	/* Check for PLLI2S Parameters */
<>	161:2cc1468da177	1169	assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
<>	161:2cc1468da177	1170	/* Check for PLLI2S/DIVQ parameters */
<>	161:2cc1468da177	1171	assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
<>	161:2cc1468da177	1172
<>	161:2cc1468da177	1173	/* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */
<>	161:2cc1468da177	1174	tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
<>	161:2cc1468da177	1175	/* Configure the PLLI2S division factors */
<>	161:2cc1468da177	1176	/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
<>	161:2cc1468da177	1177	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
<>	161:2cc1468da177	1178	/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
<>	161:2cc1468da177	1179	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg0);
<>	161:2cc1468da177	1180
<>	161:2cc1468da177	1181	/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
<>	161:2cc1468da177	1182	__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
<>	161:2cc1468da177	1183	}
<>	161:2cc1468da177	1184
<>	161:2cc1468da177	1185	/----------------- In Case of PLLI2S is just selected -----------------/
<>	161:2cc1468da177	1186	if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
<>	161:2cc1468da177	1187	{
<>	161:2cc1468da177	1188	/* Check for Parameters */
<>	161:2cc1468da177	1189	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
<>	161:2cc1468da177	1190	assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
<>	161:2cc1468da177	1191
<>	161:2cc1468da177	1192	/* Configure the PLLI2S division factors */
<>	161:2cc1468da177	1193	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */
<>	161:2cc1468da177	1194	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
<>	161:2cc1468da177	1195	}
<>	161:2cc1468da177	1196
<>	161:2cc1468da177	1197	/* Enable the PLLI2S */
<>	161:2cc1468da177	1198	__HAL_RCC_PLLI2S_ENABLE();
<>	161:2cc1468da177	1199
<>	161:2cc1468da177	1200	/* Get Start Tick*/
<>	161:2cc1468da177	1201	tickstart = HAL_GetTick();
<>	161:2cc1468da177	1202
<>	161:2cc1468da177	1203	/* Wait till PLLI2S is ready */
<>	161:2cc1468da177	1204	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
<>	161:2cc1468da177	1205	{
<>	161:2cc1468da177	1206	if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
<>	161:2cc1468da177	1207	{
<>	161:2cc1468da177	1208	/* return in case of Timeout detected */
<>	161:2cc1468da177	1209	return HAL_TIMEOUT;
<>	161:2cc1468da177	1210	}
<>	161:2cc1468da177	1211	}
<>	161:2cc1468da177	1212	}
<>	161:2cc1468da177	1213
<>	161:2cc1468da177	1214	/-------------------------------------- PLLSAI Configuration ---------------------------------/
<>	161:2cc1468da177	1215	/* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */
<>	161:2cc1468da177	1216	if(pllsaiused == 1)
<>	161:2cc1468da177	1217	{
<>	161:2cc1468da177	1218	/* Disable PLLSAI Clock */
<>	161:2cc1468da177	1219	__HAL_RCC_PLLSAI_DISABLE();
<>	161:2cc1468da177	1220
<>	161:2cc1468da177	1221	/* Get Start Tick*/
<>	161:2cc1468da177	1222	tickstart = HAL_GetTick();
<>	161:2cc1468da177	1223
<>	161:2cc1468da177	1224	/* Wait till PLLSAI is disabled */
<>	161:2cc1468da177	1225	while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
<>	161:2cc1468da177	1226	{
<>	161:2cc1468da177	1227	if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
<>	161:2cc1468da177	1228	{
<>	161:2cc1468da177	1229	/* return in case of Timeout detected */
<>	161:2cc1468da177	1230	return HAL_TIMEOUT;
<>	161:2cc1468da177	1231	}
<>	161:2cc1468da177	1232	}
<>	161:2cc1468da177	1233
<>	161:2cc1468da177	1234	/* Check the PLLSAI division factors */
<>	161:2cc1468da177	1235	assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
<>	161:2cc1468da177	1236
<>	161:2cc1468da177	1237	/----------------- In Case of PLLSAI is selected as source clock for SAI -------------------/
<>	161:2cc1468da177	1238	if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) \|\|\
<>	161:2cc1468da177	1239	((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
<>	161:2cc1468da177	1240	{
<>	161:2cc1468da177	1241	/* check for PLLSAIQ Parameter */
<>	161:2cc1468da177	1242	assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
<>	161:2cc1468da177	1243	/* check for PLLSAI/DIVQ Parameter */
<>	161:2cc1468da177	1244	assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
<>	161:2cc1468da177	1245
<>	161:2cc1468da177	1246	/* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
<>	161:2cc1468da177	1247	tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP));
<>	161:2cc1468da177	1248	/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
<>	161:2cc1468da177	1249	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
<>	161:2cc1468da177	1250	/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
<>	161:2cc1468da177	1251	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ);
<>	161:2cc1468da177	1252
<>	161:2cc1468da177	1253	/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
<>	161:2cc1468da177	1254	__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
<>	161:2cc1468da177	1255	}
<>	161:2cc1468da177	1256
<>	161:2cc1468da177	1257	/----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------/
<>	161:2cc1468da177	1258	/* In Case of PLLI2S is selected as source clock for CK48 */
<>	161:2cc1468da177	1259	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP))
<>	161:2cc1468da177	1260	{
<>	161:2cc1468da177	1261	/* check for Parameters */
<>	161:2cc1468da177	1262	assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
<>	161:2cc1468da177	1263	/* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */
<>	161:2cc1468da177	1264	tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
<>	161:2cc1468da177	1265
<>	161:2cc1468da177	1266	/* Configure the PLLSAI division factors */
<>	161:2cc1468da177	1267	/* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */
<>	161:2cc1468da177	1268	/* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
<>	161:2cc1468da177	1269	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0);
<>	161:2cc1468da177	1270	}
<>	161:2cc1468da177	1271
<>	161:2cc1468da177	1272	/* Enable PLLSAI Clock */
<>	161:2cc1468da177	1273	__HAL_RCC_PLLSAI_ENABLE();
<>	161:2cc1468da177	1274
<>	161:2cc1468da177	1275	/* Get Start Tick*/
<>	161:2cc1468da177	1276	tickstart = HAL_GetTick();
<>	161:2cc1468da177	1277
<>	161:2cc1468da177	1278	/* Wait till PLLSAI is ready */
<>	161:2cc1468da177	1279	while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
<>	161:2cc1468da177	1280	{
<>	161:2cc1468da177	1281	if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
<>	161:2cc1468da177	1282	{
<>	161:2cc1468da177	1283	/* return in case of Timeout detected */
<>	161:2cc1468da177	1284	return HAL_TIMEOUT;
<>	161:2cc1468da177	1285	}
<>	161:2cc1468da177	1286	}
<>	161:2cc1468da177	1287	}
<>	161:2cc1468da177	1288	return HAL_OK;
<>	161:2cc1468da177	1289	}
<>	161:2cc1468da177	1290
<>	161:2cc1468da177	1291	/**
<>	161:2cc1468da177	1292	* @brief Get the RCC_PeriphCLKInitTypeDef according to the internal
<>	161:2cc1468da177	1293	* RCC configuration registers.
<>	161:2cc1468da177	1294	* @param PeriphClkInit: pointer to the configured RCC_PeriphCLKInitTypeDef structure
<>	161:2cc1468da177	1295	* @retval None
<>	161:2cc1468da177	1296	*/
<>	161:2cc1468da177	1297	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
<>	161:2cc1468da177	1298	{
<>	161:2cc1468da177	1299	uint32_t tempreg = 0;
<>	161:2cc1468da177	1300
<>	161:2cc1468da177	1301	/* Set all possible values for the extended clock type parameter------------*/
<>	161:2cc1468da177	1302	PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_LPTIM1 \|\
<>	161:2cc1468da177	1303	RCC_PERIPHCLK_SAI1 \| RCC_PERIPHCLK_SAI2 \|\
<>	161:2cc1468da177	1304	RCC_PERIPHCLK_TIM \| RCC_PERIPHCLK_RTC \|\
<>	161:2cc1468da177	1305	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \|\
<>	161:2cc1468da177	1306	RCC_PERIPHCLK_I2C3 \| RCC_PERIPHCLK_USART1 \|\
<>	161:2cc1468da177	1307	RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \|\
<>	161:2cc1468da177	1308	RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \|\
<>	161:2cc1468da177	1309	RCC_PERIPHCLK_USART6 \| RCC_PERIPHCLK_UART7 \|\
<>	161:2cc1468da177	1310	RCC_PERIPHCLK_UART8 \| RCC_PERIPHCLK_SDMMC1 \|\
<>	161:2cc1468da177	1311	RCC_PERIPHCLK_CLK48 \| RCC_PERIPHCLK_SDMMC2;
<>	161:2cc1468da177	1312
<>	161:2cc1468da177	1313	/* Get the PLLI2S Clock configuration -----------------------------------------------*/
<>	161:2cc1468da177	1314	PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
<>	161:2cc1468da177	1315	PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
<>	161:2cc1468da177	1316	PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
<>	161:2cc1468da177	1317
<>	161:2cc1468da177	1318	/* Get the PLLSAI Clock configuration -----------------------------------------------*/
<>	161:2cc1468da177	1319	PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
<>	161:2cc1468da177	1320	PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP));
<>	161:2cc1468da177	1321	PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
<>	161:2cc1468da177	1322
<>	161:2cc1468da177	1323	/* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/
<>	161:2cc1468da177	1324	PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR1_PLLI2SDIVQ));
<>	161:2cc1468da177	1325	PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR1_PLLSAIDIVQ));
<>	161:2cc1468da177	1326
<>	161:2cc1468da177	1327	/* Get the SAI1 clock configuration ----------------------------------------------*/
<>	161:2cc1468da177	1328	PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
<>	161:2cc1468da177	1329
<>	161:2cc1468da177	1330	/* Get the SAI2 clock configuration ----------------------------------------------*/
<>	161:2cc1468da177	1331	PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
<>	161:2cc1468da177	1332
<>	161:2cc1468da177	1333	/* Get the I2S clock configuration ------------------------------------------*/
<>	161:2cc1468da177	1334	PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2SCLKSOURCE();
<>	161:2cc1468da177	1335
<>	161:2cc1468da177	1336	/* Get the I2C1 clock configuration ------------------------------------------*/
<>	161:2cc1468da177	1337	PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
<>	161:2cc1468da177	1338
<>	161:2cc1468da177	1339	/* Get the I2C2 clock configuration ------------------------------------------*/
<>	161:2cc1468da177	1340	PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
<>	161:2cc1468da177	1341
<>	161:2cc1468da177	1342	/* Get the I2C3 clock configuration ------------------------------------------*/
<>	161:2cc1468da177	1343	PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
<>	161:2cc1468da177	1344
<>	161:2cc1468da177	1345	/* Get the USART1 clock configuration ------------------------------------------*/
<>	161:2cc1468da177	1346	PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
<>	161:2cc1468da177	1347
<>	161:2cc1468da177	1348	/* Get the USART2 clock configuration ------------------------------------------*/
<>	161:2cc1468da177	1349	PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
<>	161:2cc1468da177	1350
<>	161:2cc1468da177	1351	/* Get the USART3 clock configuration ------------------------------------------*/
<>	161:2cc1468da177	1352	PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
<>	161:2cc1468da177	1353
<>	161:2cc1468da177	1354	/* Get the UART4 clock configuration ------------------------------------------*/
<>	161:2cc1468da177	1355	PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();
<>	161:2cc1468da177	1356
<>	161:2cc1468da177	1357	/* Get the UART5 clock configuration ------------------------------------------*/
<>	161:2cc1468da177	1358	PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();
<>	161:2cc1468da177	1359
<>	161:2cc1468da177	1360	/* Get the USART6 clock configuration ------------------------------------------*/
<>	161:2cc1468da177	1361	PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE();
<>	161:2cc1468da177	1362
<>	161:2cc1468da177	1363	/* Get the UART7 clock configuration ------------------------------------------*/
<>	161:2cc1468da177	1364	PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE();
<>	161:2cc1468da177	1365
<>	161:2cc1468da177	1366	/* Get the UART8 clock configuration ------------------------------------------*/
<>	161:2cc1468da177	1367	PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE();
<>	161:2cc1468da177	1368
<>	161:2cc1468da177	1369	/* Get the LPTIM1 clock configuration ------------------------------------------*/
<>	161:2cc1468da177	1370	PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
<>	161:2cc1468da177	1371
<>	161:2cc1468da177	1372	/* Get the CK48 clock configuration -----------------------------------------------*/
<>	161:2cc1468da177	1373	PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
<>	161:2cc1468da177	1374
<>	161:2cc1468da177	1375	/* Get the SDMMC1 clock configuration -----------------------------------------------*/
<>	161:2cc1468da177	1376	PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE();
<>	161:2cc1468da177	1377
<>	161:2cc1468da177	1378	/* Get the SDMMC2 clock configuration -----------------------------------------------*/
<>	161:2cc1468da177	1379	PeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE();
<>	161:2cc1468da177	1380
<>	161:2cc1468da177	1381	/* Get the RTC Clock configuration -----------------------------------------------*/
<>	161:2cc1468da177	1382	tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
<>	161:2cc1468da177	1383	PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) \| (RCC->BDCR & RCC_BDCR_RTCSEL));
<>	161:2cc1468da177	1384
<>	161:2cc1468da177	1385	/* Get the TIM Prescaler configuration --------------------------------------------*/
<>	161:2cc1468da177	1386	if ((RCC->DCKCFGR1 & RCC_DCKCFGR1_TIMPRE) == RESET)
<>	161:2cc1468da177	1387	{
<>	161:2cc1468da177	1388	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
<>	161:2cc1468da177	1389	}
<>	161:2cc1468da177	1390	else
<>	161:2cc1468da177	1391	{
<>	161:2cc1468da177	1392	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
<>	161:2cc1468da177	1393	}
<>	161:2cc1468da177	1394	}
<>	161:2cc1468da177	1395	#endif /* STM32F722xx \|\| STM32F723xx \|\| STM32F732xx \|\| STM32F733xx */
<>	161:2cc1468da177	1396
<>	144:ef7eb2e8f9f7	1397	/**
<>	144:ef7eb2e8f9f7	1398	* @brief Return the peripheral clock frequency for a given peripheral(SAI..)
<>	144:ef7eb2e8f9f7	1399	* @note Return 0 if peripheral clock identifier not managed by this API
<>	144:ef7eb2e8f9f7	1400	* @param PeriphClk: Peripheral clock identifier
<>	144:ef7eb2e8f9f7	1401	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1402	* @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock
<>	144:ef7eb2e8f9f7	1403	* @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock
<>	144:ef7eb2e8f9f7	1404	* @retval Frequency in KHz
<>	144:ef7eb2e8f9f7	1405	*/
<>	144:ef7eb2e8f9f7	1406	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
<>	144:ef7eb2e8f9f7	1407	{
<>	144:ef7eb2e8f9f7	1408	uint32_t tmpreg = 0;
<>	144:ef7eb2e8f9f7	1409	/* This variable is used to store the SAI clock frequency (value in Hz) */
<>	144:ef7eb2e8f9f7	1410	uint32_t frequency = 0;
<>	144:ef7eb2e8f9f7	1411	/* This variable is used to store the VCO Input (value in Hz) */
<>	144:ef7eb2e8f9f7	1412	uint32_t vcoinput = 0;
<>	144:ef7eb2e8f9f7	1413	/* This variable is used to store the SAI clock source */
<>	144:ef7eb2e8f9f7	1414	uint32_t saiclocksource = 0;
<>	144:ef7eb2e8f9f7	1415
<>	144:ef7eb2e8f9f7	1416	if (PeriphClk == RCC_PERIPHCLK_SAI1)
<>	144:ef7eb2e8f9f7	1417	{
<>	144:ef7eb2e8f9f7	1418	saiclocksource = RCC->DCKCFGR1;
<>	144:ef7eb2e8f9f7	1419	saiclocksource &= RCC_DCKCFGR1_SAI1SEL;
<>	144:ef7eb2e8f9f7	1420	switch (saiclocksource)
<>	144:ef7eb2e8f9f7	1421	{
<>	144:ef7eb2e8f9f7	1422	case 0: /* PLLSAI is the clock source for SAI1 */
<>	144:ef7eb2e8f9f7	1423	{
<>	144:ef7eb2e8f9f7	1424	/* Configure the PLLSAI division factor */
<>	144:ef7eb2e8f9f7	1425	/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
<>	144:ef7eb2e8f9f7	1426	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
<>	144:ef7eb2e8f9f7	1427	{
<>	144:ef7eb2e8f9f7	1428	/* In Case the PLL Source is HSI (Internal Clock) */
<>	144:ef7eb2e8f9f7	1429	vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
<>	144:ef7eb2e8f9f7	1430	}
<>	144:ef7eb2e8f9f7	1431	else
<>	144:ef7eb2e8f9f7	1432	{
<>	144:ef7eb2e8f9f7	1433	/* In Case the PLL Source is HSE (External Clock) */
<>	144:ef7eb2e8f9f7	1434	vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
<>	144:ef7eb2e8f9f7	1435	}
<>	144:ef7eb2e8f9f7	1436	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
<>	144:ef7eb2e8f9f7	1437	/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
<>	144:ef7eb2e8f9f7	1438	tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;
<>	144:ef7eb2e8f9f7	1439	frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);
<>	144:ef7eb2e8f9f7	1440
<>	144:ef7eb2e8f9f7	1441	/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
<>	144:ef7eb2e8f9f7	1442	tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1);
<>	144:ef7eb2e8f9f7	1443	frequency = frequency/(tmpreg);
<>	144:ef7eb2e8f9f7	1444	break;
<>	144:ef7eb2e8f9f7	1445	}
<>	144:ef7eb2e8f9f7	1446	case RCC_DCKCFGR1_SAI1SEL_0: /* PLLI2S is the clock source for SAI1 */
<>	144:ef7eb2e8f9f7	1447	{
<>	144:ef7eb2e8f9f7	1448	/* Configure the PLLI2S division factor */
<>	144:ef7eb2e8f9f7	1449	/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
<>	144:ef7eb2e8f9f7	1450	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
<>	144:ef7eb2e8f9f7	1451	{
<>	144:ef7eb2e8f9f7	1452	/* In Case the PLL Source is HSI (Internal Clock) */
<>	144:ef7eb2e8f9f7	1453	vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
<>	144:ef7eb2e8f9f7	1454	}
<>	144:ef7eb2e8f9f7	1455	else
<>	144:ef7eb2e8f9f7	1456	{
<>	144:ef7eb2e8f9f7	1457	/* In Case the PLL Source is HSE (External Clock) */
<>	144:ef7eb2e8f9f7	1458	vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
<>	144:ef7eb2e8f9f7	1459	}
<>	144:ef7eb2e8f9f7	1460
<>	144:ef7eb2e8f9f7	1461	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
<>	144:ef7eb2e8f9f7	1462	/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
<>	144:ef7eb2e8f9f7	1463	tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;
<>	144:ef7eb2e8f9f7	1464	frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);
<>	144:ef7eb2e8f9f7	1465
<>	144:ef7eb2e8f9f7	1466	/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
<>	144:ef7eb2e8f9f7	1467	tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1);
<>	144:ef7eb2e8f9f7	1468	frequency = frequency/(tmpreg);
<>	144:ef7eb2e8f9f7	1469	break;
<>	144:ef7eb2e8f9f7	1470	}
<>	144:ef7eb2e8f9f7	1471	case RCC_DCKCFGR1_SAI1SEL_1: /* External clock is the clock source for SAI1 */
<>	144:ef7eb2e8f9f7	1472	{
<>	144:ef7eb2e8f9f7	1473	frequency = EXTERNAL_CLOCK_VALUE;
<>	144:ef7eb2e8f9f7	1474	break;
<>	144:ef7eb2e8f9f7	1475	}
<>	144:ef7eb2e8f9f7	1476	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	1477	case RCC_DCKCFGR1_SAI1SEL: /* HSI or HSE is the clock source for SAI*/
<>	144:ef7eb2e8f9f7	1478	{
<>	144:ef7eb2e8f9f7	1479	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
<>	144:ef7eb2e8f9f7	1480	{
<>	144:ef7eb2e8f9f7	1481	/* In Case the main PLL Source is HSI */
<>	144:ef7eb2e8f9f7	1482	frequency = HSI_VALUE;
<>	144:ef7eb2e8f9f7	1483	}
<>	144:ef7eb2e8f9f7	1484	else
<>	144:ef7eb2e8f9f7	1485	{
<>	144:ef7eb2e8f9f7	1486	/* In Case the main PLL Source is HSE */
<>	144:ef7eb2e8f9f7	1487	frequency = HSE_VALUE;
<>	144:ef7eb2e8f9f7	1488	}
<>	144:ef7eb2e8f9f7	1489	break;
<>	144:ef7eb2e8f9f7	1490	}
<>	144:ef7eb2e8f9f7	1491	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	1492	default :
<>	144:ef7eb2e8f9f7	1493	{
<>	144:ef7eb2e8f9f7	1494	break;
<>	144:ef7eb2e8f9f7	1495	}
<>	144:ef7eb2e8f9f7	1496	}
<>	144:ef7eb2e8f9f7	1497	}
<>	144:ef7eb2e8f9f7	1498
<>	144:ef7eb2e8f9f7	1499	if (PeriphClk == RCC_PERIPHCLK_SAI2)
<>	144:ef7eb2e8f9f7	1500	{
<>	144:ef7eb2e8f9f7	1501	saiclocksource = RCC->DCKCFGR1;
<>	144:ef7eb2e8f9f7	1502	saiclocksource &= RCC_DCKCFGR1_SAI2SEL;
<>	144:ef7eb2e8f9f7	1503	switch (saiclocksource)
<>	144:ef7eb2e8f9f7	1504	{
<>	144:ef7eb2e8f9f7	1505	case 0: /* PLLSAI is the clock source for SAI*/
<>	144:ef7eb2e8f9f7	1506	{
<>	144:ef7eb2e8f9f7	1507	/* Configure the PLLSAI division factor */
<>	144:ef7eb2e8f9f7	1508	/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
<>	144:ef7eb2e8f9f7	1509	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
<>	144:ef7eb2e8f9f7	1510	{
<>	144:ef7eb2e8f9f7	1511	/* In Case the PLL Source is HSI (Internal Clock) */
<>	144:ef7eb2e8f9f7	1512	vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
<>	144:ef7eb2e8f9f7	1513	}
<>	144:ef7eb2e8f9f7	1514	else
<>	144:ef7eb2e8f9f7	1515	{
<>	144:ef7eb2e8f9f7	1516	/* In Case the PLL Source is HSE (External Clock) */
<>	144:ef7eb2e8f9f7	1517	vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
<>	144:ef7eb2e8f9f7	1518	}
<>	144:ef7eb2e8f9f7	1519	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
<>	144:ef7eb2e8f9f7	1520	/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
<>	144:ef7eb2e8f9f7	1521	tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;
<>	144:ef7eb2e8f9f7	1522	frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);
<>	144:ef7eb2e8f9f7	1523
<>	144:ef7eb2e8f9f7	1524	/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
<>	144:ef7eb2e8f9f7	1525	tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1);
<>	144:ef7eb2e8f9f7	1526	frequency = frequency/(tmpreg);
<>	144:ef7eb2e8f9f7	1527	break;
<>	144:ef7eb2e8f9f7	1528	}
<>	144:ef7eb2e8f9f7	1529	case RCC_DCKCFGR1_SAI2SEL_0: /* PLLI2S is the clock source for SAI2 */
<>	144:ef7eb2e8f9f7	1530	{
<>	144:ef7eb2e8f9f7	1531	/* Configure the PLLI2S division factor */
<>	144:ef7eb2e8f9f7	1532	/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
<>	144:ef7eb2e8f9f7	1533	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
<>	144:ef7eb2e8f9f7	1534	{
<>	144:ef7eb2e8f9f7	1535	/* In Case the PLL Source is HSI (Internal Clock) */
<>	144:ef7eb2e8f9f7	1536	vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
<>	144:ef7eb2e8f9f7	1537	}
<>	144:ef7eb2e8f9f7	1538	else
<>	144:ef7eb2e8f9f7	1539	{
<>	144:ef7eb2e8f9f7	1540	/* In Case the PLL Source is HSE (External Clock) */
<>	144:ef7eb2e8f9f7	1541	vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
<>	144:ef7eb2e8f9f7	1542	}
<>	144:ef7eb2e8f9f7	1543
<>	144:ef7eb2e8f9f7	1544	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
<>	144:ef7eb2e8f9f7	1545	/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
<>	144:ef7eb2e8f9f7	1546	tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;
<>	144:ef7eb2e8f9f7	1547	frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);
<>	144:ef7eb2e8f9f7	1548
<>	144:ef7eb2e8f9f7	1549	/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
<>	144:ef7eb2e8f9f7	1550	tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1);
<>	144:ef7eb2e8f9f7	1551	frequency = frequency/(tmpreg);
<>	144:ef7eb2e8f9f7	1552	break;
<>	144:ef7eb2e8f9f7	1553	}
<>	144:ef7eb2e8f9f7	1554	case RCC_DCKCFGR1_SAI2SEL_1: /* External clock is the clock source for SAI2 */
<>	144:ef7eb2e8f9f7	1555	{
<>	144:ef7eb2e8f9f7	1556	frequency = EXTERNAL_CLOCK_VALUE;
<>	144:ef7eb2e8f9f7	1557	break;
<>	144:ef7eb2e8f9f7	1558	}
<>	144:ef7eb2e8f9f7	1559	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	1560	case RCC_DCKCFGR1_SAI2SEL: /* HSI or HSE is the clock source for SAI2 */
<>	144:ef7eb2e8f9f7	1561	{
<>	144:ef7eb2e8f9f7	1562	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
<>	144:ef7eb2e8f9f7	1563	{
<>	144:ef7eb2e8f9f7	1564	/* In Case the main PLL Source is HSI */
<>	144:ef7eb2e8f9f7	1565	frequency = HSI_VALUE;
<>	144:ef7eb2e8f9f7	1566	}
<>	144:ef7eb2e8f9f7	1567	else
<>	144:ef7eb2e8f9f7	1568	{
<>	144:ef7eb2e8f9f7	1569	/* In Case the main PLL Source is HSE */
<>	144:ef7eb2e8f9f7	1570	frequency = HSE_VALUE;
<>	144:ef7eb2e8f9f7	1571	}
<>	144:ef7eb2e8f9f7	1572	break;
<>	144:ef7eb2e8f9f7	1573	}
<>	144:ef7eb2e8f9f7	1574	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	1575	default :
<>	144:ef7eb2e8f9f7	1576	{
<>	144:ef7eb2e8f9f7	1577	break;
<>	144:ef7eb2e8f9f7	1578	}
<>	144:ef7eb2e8f9f7	1579	}
<>	144:ef7eb2e8f9f7	1580	}
<>	144:ef7eb2e8f9f7	1581
<>	144:ef7eb2e8f9f7	1582	return frequency;
<>	144:ef7eb2e8f9f7	1583	}
<>	144:ef7eb2e8f9f7	1584
<>	144:ef7eb2e8f9f7	1585	/**
<>	144:ef7eb2e8f9f7	1586	* @}
<>	144:ef7eb2e8f9f7	1587	*/
<>	144:ef7eb2e8f9f7	1588
<>	144:ef7eb2e8f9f7	1589	/**
<>	144:ef7eb2e8f9f7	1590	* @}
<>	144:ef7eb2e8f9f7	1591	*/
<>	144:ef7eb2e8f9f7	1592
<>	144:ef7eb2e8f9f7	1593	#endif /* HAL_RCC_MODULE_ENABLED */
<>	144:ef7eb2e8f9f7	1594	/**
<>	144:ef7eb2e8f9f7	1595	* @}
<>	144:ef7eb2e8f9f7	1596	*/
<>	144:ef7eb2e8f9f7	1597
<>	144:ef7eb2e8f9f7	1598	/**
<>	144:ef7eb2e8f9f7	1599	* @}
<>	144:ef7eb2e8f9f7	1600	*/
<>	144:ef7eb2e8f9f7	1601
<>	144:ef7eb2e8f9f7	1602	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

Repository toolbox

Repository details

Type:	Library
Created:	30 Jul 2017
Imports:	2
Forks:	0
Commits:	171
Dependents:	0
Dependencies:	0
Followers:	1

The code in this repository is MIT licensed.

Important changes to repositories hosted on mbed.com

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc_ex.c@161:2cc1468da177, 2017-03-30 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Important changes to repositories hosted on mbed.com

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc_ex.c@161:2cc1468da177, 2017-03-30 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Access Warning