Mark Vandermeulen / FYDP_Final

Code for our FYDP -only one IMU works right now -RTOS is working

Dependencies:   mbed

drivers/nRF24L01P/nRF24L01P.cpp@0:964eb6a2ef00, 2015-03-18 (annotated)

Committer:
majik
Date:
Wed Mar 18 22:23:48 2015 +0000
Revision:
0:964eb6a2ef00
This is our FYDP code, but only one IMU works with the RTOS.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
majik 0:964eb6a2ef00 1 /**
majik 0:964eb6a2ef00 2 * @file nRF24L01P.cpp
majik 0:964eb6a2ef00 3 *
majik 0:964eb6a2ef00 4 * @author Owen Edwards
majik 0:964eb6a2ef00 5 *
majik 0:964eb6a2ef00 6 * @section LICENSE
majik 0:964eb6a2ef00 7 *
majik 0:964eb6a2ef00 8 * Copyright (c) 2010 Owen Edwards
majik 0:964eb6a2ef00 9 *
majik 0:964eb6a2ef00 10 * This program is free software: you can redistribute it and/or modify
majik 0:964eb6a2ef00 11 * it under the terms of the GNU General Public License as published by
majik 0:964eb6a2ef00 12 * the Free Software Foundation, either version 3 of the License, or
majik 0:964eb6a2ef00 13 * (at your option) any later version.
majik 0:964eb6a2ef00 14 *
majik 0:964eb6a2ef00 15 * This program is distributed in the hope that it will be useful,
majik 0:964eb6a2ef00 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
majik 0:964eb6a2ef00 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
majik 0:964eb6a2ef00 18 * GNU General Public License for more details.
majik 0:964eb6a2ef00 19 *
majik 0:964eb6a2ef00 20 * You should have received a copy of the GNU General Public License
majik 0:964eb6a2ef00 21 * along with this program. If not, see <http://www.gnu.org/licenses/>.
majik 0:964eb6a2ef00 22 *
majik 0:964eb6a2ef00 23 * The above copyright notice and this permission notice shall be included in
majik 0:964eb6a2ef00 24 * all copies or substantial portions of the Software.
majik 0:964eb6a2ef00 25 *
majik 0:964eb6a2ef00 26 * @section DESCRIPTION
majik 0:964eb6a2ef00 27 *
majik 0:964eb6a2ef00 28 * nRF24L01+ Single Chip 2.4GHz Transceiver from Nordic Semiconductor.
majik 0:964eb6a2ef00 29 *
majik 0:964eb6a2ef00 30 * Datasheet:
majik 0:964eb6a2ef00 31 *
majik 0:964eb6a2ef00 32 * http://www.nordicsemi.no/files/Product/data_sheet/nRF24L01P_Product_Specification_1_0.pdf
majik 0:964eb6a2ef00 33 */
majik 0:964eb6a2ef00 34
majik 0:964eb6a2ef00 35 /**
majik 0:964eb6a2ef00 36 * Includes
majik 0:964eb6a2ef00 37 */
majik 0:964eb6a2ef00 38 #include "nRF24L01P.h"
majik 0:964eb6a2ef00 39
majik 0:964eb6a2ef00 40 /**
majik 0:964eb6a2ef00 41 * Defines
majik 0:964eb6a2ef00 42 *
majik 0:964eb6a2ef00 43 * (Note that all defines here start with an underscore, e.g. '_NRF24L01P_MODE_UNKNOWN',
majik 0:964eb6a2ef00 44 * and are local to this library. The defines in the nRF24L01P.h file do not start
majik 0:964eb6a2ef00 45 * with the underscore, and can be used by code to access this library.)
majik 0:964eb6a2ef00 46 */
majik 0:964eb6a2ef00 47
majik 0:964eb6a2ef00 48 typedef enum {
majik 0:964eb6a2ef00 49 _NRF24L01P_MODE_UNKNOWN,
majik 0:964eb6a2ef00 50 _NRF24L01P_MODE_POWER_DOWN,
majik 0:964eb6a2ef00 51 _NRF24L01P_MODE_STANDBY,
majik 0:964eb6a2ef00 52 _NRF24L01P_MODE_RX,
majik 0:964eb6a2ef00 53 _NRF24L01P_MODE_TX,
majik 0:964eb6a2ef00 54 } nRF24L01P_Mode_Type;
majik 0:964eb6a2ef00 55
majik 0:964eb6a2ef00 56 /*
majik 0:964eb6a2ef00 57 * The following FIFOs are present in nRF24L01+:
majik 0:964eb6a2ef00 58 * TX three level, 32 byte FIFO
majik 0:964eb6a2ef00 59 * RX three level, 32 byte FIFO
majik 0:964eb6a2ef00 60 */
majik 0:964eb6a2ef00 61 #define _NRF24L01P_TX_FIFO_COUNT 3
majik 0:964eb6a2ef00 62 #define _NRF24L01P_RX_FIFO_COUNT 3
majik 0:964eb6a2ef00 63
majik 0:964eb6a2ef00 64 #define _NRF24L01P_TX_FIFO_SIZE 32
majik 0:964eb6a2ef00 65 #define _NRF24L01P_RX_FIFO_SIZE 32
majik 0:964eb6a2ef00 66
majik 0:964eb6a2ef00 67 #define _NRF24L01P_SPI_MAX_DATA_RATE 10000000
majik 0:964eb6a2ef00 68
majik 0:964eb6a2ef00 69 #define _NRF24L01P_SPI_CMD_RD_REG 0x00
majik 0:964eb6a2ef00 70 #define _NRF24L01P_SPI_CMD_WR_REG 0x20
majik 0:964eb6a2ef00 71 #define _NRF24L01P_SPI_CMD_RD_RX_PAYLOAD 0x61
majik 0:964eb6a2ef00 72 #define _NRF24L01P_SPI_CMD_WR_TX_PAYLOAD 0xa0
majik 0:964eb6a2ef00 73 #define _NRF24L01P_SPI_CMD_FLUSH_TX 0xe1
majik 0:964eb6a2ef00 74 #define _NRF24L01P_SPI_CMD_FLUSH_RX 0xe2
majik 0:964eb6a2ef00 75 #define _NRF24L01P_SPI_CMD_REUSE_TX_PL 0xe3
majik 0:964eb6a2ef00 76 #define _NRF24L01P_SPI_CMD_R_RX_PL_WID 0x60
majik 0:964eb6a2ef00 77 #define _NRF24L01P_SPI_CMD_W_ACK_PAYLOAD 0xa8
majik 0:964eb6a2ef00 78 #define _NRF24L01P_SPI_CMD_W_TX_PYLD_NO_ACK 0xb0
majik 0:964eb6a2ef00 79 #define _NRF24L01P_SPI_CMD_NOP 0xff
majik 0:964eb6a2ef00 80
majik 0:964eb6a2ef00 81
majik 0:964eb6a2ef00 82 #define _NRF24L01P_REG_CONFIG 0x00
majik 0:964eb6a2ef00 83 #define _NRF24L01P_REG_EN_AA 0x01
majik 0:964eb6a2ef00 84 #define _NRF24L01P_REG_EN_RXADDR 0x02
majik 0:964eb6a2ef00 85 #define _NRF24L01P_REG_SETUP_AW 0x03
majik 0:964eb6a2ef00 86 #define _NRF24L01P_REG_SETUP_RETR 0x04
majik 0:964eb6a2ef00 87 #define _NRF24L01P_REG_RF_CH 0x05
majik 0:964eb6a2ef00 88 #define _NRF24L01P_REG_RF_SETUP 0x06
majik 0:964eb6a2ef00 89 #define _NRF24L01P_REG_STATUS 0x07
majik 0:964eb6a2ef00 90 #define _NRF24L01P_REG_OBSERVE_TX 0x08
majik 0:964eb6a2ef00 91 #define _NRF24L01P_REG_RPD 0x09
majik 0:964eb6a2ef00 92 #define _NRF24L01P_REG_RX_ADDR_P0 0x0a
majik 0:964eb6a2ef00 93 #define _NRF24L01P_REG_RX_ADDR_P1 0x0b
majik 0:964eb6a2ef00 94 #define _NRF24L01P_REG_RX_ADDR_P2 0x0c
majik 0:964eb6a2ef00 95 #define _NRF24L01P_REG_RX_ADDR_P3 0x0d
majik 0:964eb6a2ef00 96 #define _NRF24L01P_REG_RX_ADDR_P4 0x0e
majik 0:964eb6a2ef00 97 #define _NRF24L01P_REG_RX_ADDR_P5 0x0f
majik 0:964eb6a2ef00 98 #define _NRF24L01P_REG_TX_ADDR 0x10
majik 0:964eb6a2ef00 99 #define _NRF24L01P_REG_RX_PW_P0 0x11
majik 0:964eb6a2ef00 100 #define _NRF24L01P_REG_RX_PW_P1 0x12
majik 0:964eb6a2ef00 101 #define _NRF24L01P_REG_RX_PW_P2 0x13
majik 0:964eb6a2ef00 102 #define _NRF24L01P_REG_RX_PW_P3 0x14
majik 0:964eb6a2ef00 103 #define _NRF24L01P_REG_RX_PW_P4 0x15
majik 0:964eb6a2ef00 104 #define _NRF24L01P_REG_RX_PW_P5 0x16
majik 0:964eb6a2ef00 105 #define _NRF24L01P_REG_FIFO_STATUS 0x17
majik 0:964eb6a2ef00 106 #define _NRF24L01P_REG_DYNPD 0x1c
majik 0:964eb6a2ef00 107 #define _NRF24L01P_REG_FEATURE 0x1d
majik 0:964eb6a2ef00 108
majik 0:964eb6a2ef00 109 #define _NRF24L01P_REG_ADDRESS_MASK 0x1f
majik 0:964eb6a2ef00 110
majik 0:964eb6a2ef00 111 // CONFIG register:
majik 0:964eb6a2ef00 112 #define _NRF24L01P_CONFIG_PRIM_RX (1<<0)
majik 0:964eb6a2ef00 113 #define _NRF24L01P_CONFIG_PWR_UP (1<<1)
majik 0:964eb6a2ef00 114 #define _NRF24L01P_CONFIG_CRC0 (1<<2)
majik 0:964eb6a2ef00 115 #define _NRF24L01P_CONFIG_EN_CRC (1<<3)
majik 0:964eb6a2ef00 116 #define _NRF24L01P_CONFIG_MASK_MAX_RT (1<<4)
majik 0:964eb6a2ef00 117 #define _NRF24L01P_CONFIG_MASK_TX_DS (1<<5)
majik 0:964eb6a2ef00 118 #define _NRF24L01P_CONFIG_MASK_RX_DR (1<<6)
majik 0:964eb6a2ef00 119
majik 0:964eb6a2ef00 120 #define _NRF24L01P_CONFIG_CRC_MASK (_NRF24L01P_CONFIG_EN_CRC|_NRF24L01P_CONFIG_CRC0)
majik 0:964eb6a2ef00 121 #define _NRF24L01P_CONFIG_CRC_NONE (0)
majik 0:964eb6a2ef00 122 #define _NRF24L01P_CONFIG_CRC_8BIT (_NRF24L01P_CONFIG_EN_CRC)
majik 0:964eb6a2ef00 123 #define _NRF24L01P_CONFIG_CRC_16BIT (_NRF24L01P_CONFIG_EN_CRC|_NRF24L01P_CONFIG_CRC0)
majik 0:964eb6a2ef00 124
majik 0:964eb6a2ef00 125 // EN_AA register:
majik 0:964eb6a2ef00 126 #define _NRF24L01P_EN_AA_NONE 0
majik 0:964eb6a2ef00 127
majik 0:964eb6a2ef00 128 // EN_RXADDR register:
majik 0:964eb6a2ef00 129 #define _NRF24L01P_EN_RXADDR_NONE 0
majik 0:964eb6a2ef00 130
majik 0:964eb6a2ef00 131 // SETUP_AW register:
majik 0:964eb6a2ef00 132 #define _NRF24L01P_SETUP_AW_AW_MASK (0x3<<0)
majik 0:964eb6a2ef00 133 #define _NRF24L01P_SETUP_AW_AW_3BYTE (0x1<<0)
majik 0:964eb6a2ef00 134 #define _NRF24L01P_SETUP_AW_AW_4BYTE (0x2<<0)
majik 0:964eb6a2ef00 135 #define _NRF24L01P_SETUP_AW_AW_5BYTE (0x3<<0)
majik 0:964eb6a2ef00 136
majik 0:964eb6a2ef00 137 // SETUP_RETR register:
majik 0:964eb6a2ef00 138 #define _NRF24L01P_SETUP_RETR_NONE 0
majik 0:964eb6a2ef00 139
majik 0:964eb6a2ef00 140 // RF_SETUP register:
majik 0:964eb6a2ef00 141 #define _NRF24L01P_RF_SETUP_RF_PWR_MASK (0x3<<1)
majik 0:964eb6a2ef00 142 #define _NRF24L01P_RF_SETUP_RF_PWR_0DBM (0x3<<1)
majik 0:964eb6a2ef00 143 #define _NRF24L01P_RF_SETUP_RF_PWR_MINUS_6DBM (0x2<<1)
majik 0:964eb6a2ef00 144 #define _NRF24L01P_RF_SETUP_RF_PWR_MINUS_12DBM (0x1<<1)
majik 0:964eb6a2ef00 145 #define _NRF24L01P_RF_SETUP_RF_PWR_MINUS_18DBM (0x0<<1)
majik 0:964eb6a2ef00 146
majik 0:964eb6a2ef00 147 #define _NRF24L01P_RF_SETUP_RF_DR_HIGH_BIT (1 << 3)
majik 0:964eb6a2ef00 148 #define _NRF24L01P_RF_SETUP_RF_DR_LOW_BIT (1 << 5)
majik 0:964eb6a2ef00 149 #define _NRF24L01P_RF_SETUP_RF_DR_MASK (_NRF24L01P_RF_SETUP_RF_DR_LOW_BIT|_NRF24L01P_RF_SETUP_RF_DR_HIGH_BIT)
majik 0:964eb6a2ef00 150 #define _NRF24L01P_RF_SETUP_RF_DR_250KBPS (_NRF24L01P_RF_SETUP_RF_DR_LOW_BIT)
majik 0:964eb6a2ef00 151 #define _NRF24L01P_RF_SETUP_RF_DR_1MBPS (0)
majik 0:964eb6a2ef00 152 #define _NRF24L01P_RF_SETUP_RF_DR_2MBPS (_NRF24L01P_RF_SETUP_RF_DR_HIGH_BIT)
majik 0:964eb6a2ef00 153
majik 0:964eb6a2ef00 154 // STATUS register:
majik 0:964eb6a2ef00 155 #define _NRF24L01P_STATUS_TX_FULL (1<<0)
majik 0:964eb6a2ef00 156 #define _NRF24L01P_STATUS_RX_P_NO (0x7<<1)
majik 0:964eb6a2ef00 157 #define _NRF24L01P_STATUS_MAX_RT (1<<4)
majik 0:964eb6a2ef00 158 #define _NRF24L01P_STATUS_TX_DS (1<<5)
majik 0:964eb6a2ef00 159 #define _NRF24L01P_STATUS_RX_DR (1<<6)
majik 0:964eb6a2ef00 160
majik 0:964eb6a2ef00 161 // RX_PW_P0..RX_PW_P5 registers:
majik 0:964eb6a2ef00 162 #define _NRF24L01P_RX_PW_Px_MASK 0x3F
majik 0:964eb6a2ef00 163
majik 0:964eb6a2ef00 164 #define _NRF24L01P_TIMING_Tundef2pd_us 100000 // 100mS
majik 0:964eb6a2ef00 165 #define _NRF24L01P_TIMING_Tstby2a_us 130 // 130uS
majik 0:964eb6a2ef00 166 #define _NRF24L01P_TIMING_Thce_us 10 // 10uS
majik 0:964eb6a2ef00 167 #define _NRF24L01P_TIMING_Tpd2stby_us 4500 // 4.5mS worst case
majik 0:964eb6a2ef00 168 #define _NRF24L01P_TIMING_Tpece2csn_us 4 // 4uS
majik 0:964eb6a2ef00 169
majik 0:964eb6a2ef00 170 /**
majik 0:964eb6a2ef00 171 * Methods
majik 0:964eb6a2ef00 172 */
majik 0:964eb6a2ef00 173
majik 0:964eb6a2ef00 174 nRF24L01P::nRF24L01P(PinName mosi,
majik 0:964eb6a2ef00 175 PinName miso,
majik 0:964eb6a2ef00 176 PinName sck,
majik 0:964eb6a2ef00 177 PinName csn,
majik 0:964eb6a2ef00 178 PinName ce,
majik 0:964eb6a2ef00 179 PinName irq) : spi_(mosi, miso, sck), nCS_(csn), ce_(ce), nIRQ_(irq) {
majik 0:964eb6a2ef00 180
majik 0:964eb6a2ef00 181 mode = _NRF24L01P_MODE_UNKNOWN;
majik 0:964eb6a2ef00 182
majik 0:964eb6a2ef00 183 disable();
majik 0:964eb6a2ef00 184
majik 0:964eb6a2ef00 185 nCS_ = 1;
majik 0:964eb6a2ef00 186
majik 0:964eb6a2ef00 187 spi_.frequency(_NRF24L01P_SPI_MAX_DATA_RATE/5); // 2Mbit, 1/5th the maximum transfer rate for the SPI bus
majik 0:964eb6a2ef00 188 spi_.format(8,0); // 8-bit, ClockPhase = 0, ClockPolarity = 0
majik 0:964eb6a2ef00 189
majik 0:964eb6a2ef00 190 wait_us(_NRF24L01P_TIMING_Tundef2pd_us); // Wait for Power-on reset
majik 0:964eb6a2ef00 191
majik 0:964eb6a2ef00 192 setRegister(_NRF24L01P_REG_CONFIG, 0); // Power Down
majik 0:964eb6a2ef00 193
majik 0:964eb6a2ef00 194 setRegister(_NRF24L01P_REG_STATUS, _NRF24L01P_STATUS_MAX_RT|_NRF24L01P_STATUS_TX_DS|_NRF24L01P_STATUS_RX_DR); // Clear any pending interrupts
majik 0:964eb6a2ef00 195
majik 0:964eb6a2ef00 196 //
majik 0:964eb6a2ef00 197 // Setup default configuration
majik 0:964eb6a2ef00 198 //
majik 0:964eb6a2ef00 199 disableAllRxPipes();
majik 0:964eb6a2ef00 200 setRfFrequency();
majik 0:964eb6a2ef00 201 setRfOutputPower();
majik 0:964eb6a2ef00 202 setAirDataRate();
majik 0:964eb6a2ef00 203 setCrcWidth();
majik 0:964eb6a2ef00 204 setTxAddress();
majik 0:964eb6a2ef00 205 setRxAddress();
majik 0:964eb6a2ef00 206 disableAutoAcknowledge();
majik 0:964eb6a2ef00 207 disableAutoRetransmit();
majik 0:964eb6a2ef00 208 setTransferSize();
majik 0:964eb6a2ef00 209
majik 0:964eb6a2ef00 210 mode = _NRF24L01P_MODE_POWER_DOWN;
majik 0:964eb6a2ef00 211
majik 0:964eb6a2ef00 212 }
majik 0:964eb6a2ef00 213
majik 0:964eb6a2ef00 214
majik 0:964eb6a2ef00 215 void nRF24L01P::powerUp(void) {
majik 0:964eb6a2ef00 216
majik 0:964eb6a2ef00 217 int config = getRegister(_NRF24L01P_REG_CONFIG);
majik 0:964eb6a2ef00 218
majik 0:964eb6a2ef00 219 config |= _NRF24L01P_CONFIG_PWR_UP;
majik 0:964eb6a2ef00 220
majik 0:964eb6a2ef00 221 setRegister(_NRF24L01P_REG_CONFIG, config);
majik 0:964eb6a2ef00 222
majik 0:964eb6a2ef00 223 // Wait until the nRF24L01+ powers up
majik 0:964eb6a2ef00 224 wait_us( _NRF24L01P_TIMING_Tpd2stby_us );
majik 0:964eb6a2ef00 225
majik 0:964eb6a2ef00 226 mode = _NRF24L01P_MODE_STANDBY;
majik 0:964eb6a2ef00 227
majik 0:964eb6a2ef00 228 }
majik 0:964eb6a2ef00 229
majik 0:964eb6a2ef00 230
majik 0:964eb6a2ef00 231 void nRF24L01P::powerDown(void) {
majik 0:964eb6a2ef00 232
majik 0:964eb6a2ef00 233 int config = getRegister(_NRF24L01P_REG_CONFIG);
majik 0:964eb6a2ef00 234
majik 0:964eb6a2ef00 235 config &= ~_NRF24L01P_CONFIG_PWR_UP;
majik 0:964eb6a2ef00 236
majik 0:964eb6a2ef00 237 setRegister(_NRF24L01P_REG_CONFIG, config);
majik 0:964eb6a2ef00 238
majik 0:964eb6a2ef00 239 // Wait until the nRF24L01+ powers down
majik 0:964eb6a2ef00 240 wait_us( _NRF24L01P_TIMING_Tpd2stby_us ); // This *may* not be necessary (no timing is shown in the Datasheet), but just to be safe
majik 0:964eb6a2ef00 241
majik 0:964eb6a2ef00 242 mode = _NRF24L01P_MODE_POWER_DOWN;
majik 0:964eb6a2ef00 243
majik 0:964eb6a2ef00 244 }
majik 0:964eb6a2ef00 245
majik 0:964eb6a2ef00 246
majik 0:964eb6a2ef00 247 void nRF24L01P::setReceiveMode(void) {
majik 0:964eb6a2ef00 248
majik 0:964eb6a2ef00 249 if ( _NRF24L01P_MODE_POWER_DOWN == mode ) powerUp();
majik 0:964eb6a2ef00 250
majik 0:964eb6a2ef00 251 int config = getRegister(_NRF24L01P_REG_CONFIG);
majik 0:964eb6a2ef00 252
majik 0:964eb6a2ef00 253 config |= _NRF24L01P_CONFIG_PRIM_RX;
majik 0:964eb6a2ef00 254
majik 0:964eb6a2ef00 255 setRegister(_NRF24L01P_REG_CONFIG, config);
majik 0:964eb6a2ef00 256
majik 0:964eb6a2ef00 257 mode = _NRF24L01P_MODE_RX;
majik 0:964eb6a2ef00 258
majik 0:964eb6a2ef00 259 }
majik 0:964eb6a2ef00 260
majik 0:964eb6a2ef00 261
majik 0:964eb6a2ef00 262 void nRF24L01P::setTransmitMode(void) {
majik 0:964eb6a2ef00 263
majik 0:964eb6a2ef00 264 if ( _NRF24L01P_MODE_POWER_DOWN == mode ) powerUp();
majik 0:964eb6a2ef00 265
majik 0:964eb6a2ef00 266 int config = getRegister(_NRF24L01P_REG_CONFIG);
majik 0:964eb6a2ef00 267
majik 0:964eb6a2ef00 268 config &= ~_NRF24L01P_CONFIG_PRIM_RX;
majik 0:964eb6a2ef00 269
majik 0:964eb6a2ef00 270 setRegister(_NRF24L01P_REG_CONFIG, config);
majik 0:964eb6a2ef00 271
majik 0:964eb6a2ef00 272 mode = _NRF24L01P_MODE_TX;
majik 0:964eb6a2ef00 273
majik 0:964eb6a2ef00 274 }
majik 0:964eb6a2ef00 275
majik 0:964eb6a2ef00 276
majik 0:964eb6a2ef00 277 void nRF24L01P::enable(void) {
majik 0:964eb6a2ef00 278
majik 0:964eb6a2ef00 279 ce_ = 1;
majik 0:964eb6a2ef00 280 wait_us( _NRF24L01P_TIMING_Tpece2csn_us );
majik 0:964eb6a2ef00 281
majik 0:964eb6a2ef00 282 }
majik 0:964eb6a2ef00 283
majik 0:964eb6a2ef00 284
majik 0:964eb6a2ef00 285 void nRF24L01P::disable(void) {
majik 0:964eb6a2ef00 286
majik 0:964eb6a2ef00 287 ce_ = 0;
majik 0:964eb6a2ef00 288
majik 0:964eb6a2ef00 289 }
majik 0:964eb6a2ef00 290
majik 0:964eb6a2ef00 291 void nRF24L01P::setRfFrequency(int frequency) {
majik 0:964eb6a2ef00 292
majik 0:964eb6a2ef00 293 if ( ( frequency < NRF24L01P_MIN_RF_FREQUENCY ) || ( frequency > NRF24L01P_MAX_RF_FREQUENCY ) ) {
majik 0:964eb6a2ef00 294
majik 0:964eb6a2ef00 295 error( "nRF24L01P: Invalid RF Frequency setting %d\r\n", frequency );
majik 0:964eb6a2ef00 296 return;
majik 0:964eb6a2ef00 297
majik 0:964eb6a2ef00 298 }
majik 0:964eb6a2ef00 299
majik 0:964eb6a2ef00 300 int channel = ( frequency - NRF24L01P_MIN_RF_FREQUENCY ) & 0x7F;
majik 0:964eb6a2ef00 301
majik 0:964eb6a2ef00 302 setRegister(_NRF24L01P_REG_RF_CH, channel);
majik 0:964eb6a2ef00 303
majik 0:964eb6a2ef00 304 }
majik 0:964eb6a2ef00 305
majik 0:964eb6a2ef00 306
majik 0:964eb6a2ef00 307 int nRF24L01P::getRfFrequency(void) {
majik 0:964eb6a2ef00 308
majik 0:964eb6a2ef00 309 int channel = getRegister(_NRF24L01P_REG_RF_CH) & 0x7F;
majik 0:964eb6a2ef00 310
majik 0:964eb6a2ef00 311 return ( channel + NRF24L01P_MIN_RF_FREQUENCY );
majik 0:964eb6a2ef00 312
majik 0:964eb6a2ef00 313 }
majik 0:964eb6a2ef00 314
majik 0:964eb6a2ef00 315
majik 0:964eb6a2ef00 316 void nRF24L01P::setRfOutputPower(int power) {
majik 0:964eb6a2ef00 317
majik 0:964eb6a2ef00 318 int rfSetup = getRegister(_NRF24L01P_REG_RF_SETUP) & ~_NRF24L01P_RF_SETUP_RF_PWR_MASK;
majik 0:964eb6a2ef00 319
majik 0:964eb6a2ef00 320 switch ( power ) {
majik 0:964eb6a2ef00 321
majik 0:964eb6a2ef00 322 case NRF24L01P_TX_PWR_ZERO_DB:
majik 0:964eb6a2ef00 323 rfSetup |= _NRF24L01P_RF_SETUP_RF_PWR_0DBM;
majik 0:964eb6a2ef00 324 break;
majik 0:964eb6a2ef00 325
majik 0:964eb6a2ef00 326 case NRF24L01P_TX_PWR_MINUS_6_DB:
majik 0:964eb6a2ef00 327 rfSetup |= _NRF24L01P_RF_SETUP_RF_PWR_MINUS_6DBM;
majik 0:964eb6a2ef00 328 break;
majik 0:964eb6a2ef00 329
majik 0:964eb6a2ef00 330 case NRF24L01P_TX_PWR_MINUS_12_DB:
majik 0:964eb6a2ef00 331 rfSetup |= _NRF24L01P_RF_SETUP_RF_PWR_MINUS_12DBM;
majik 0:964eb6a2ef00 332 break;
majik 0:964eb6a2ef00 333
majik 0:964eb6a2ef00 334 case NRF24L01P_TX_PWR_MINUS_18_DB:
majik 0:964eb6a2ef00 335 rfSetup |= _NRF24L01P_RF_SETUP_RF_PWR_MINUS_18DBM;
majik 0:964eb6a2ef00 336 break;
majik 0:964eb6a2ef00 337
majik 0:964eb6a2ef00 338 default:
majik 0:964eb6a2ef00 339 error( "nRF24L01P: Invalid RF Output Power setting %d\r\n", power );
majik 0:964eb6a2ef00 340 return;
majik 0:964eb6a2ef00 341
majik 0:964eb6a2ef00 342 }
majik 0:964eb6a2ef00 343
majik 0:964eb6a2ef00 344 setRegister(_NRF24L01P_REG_RF_SETUP, rfSetup);
majik 0:964eb6a2ef00 345
majik 0:964eb6a2ef00 346 }
majik 0:964eb6a2ef00 347
majik 0:964eb6a2ef00 348
majik 0:964eb6a2ef00 349 int nRF24L01P::getRfOutputPower(void) {
majik 0:964eb6a2ef00 350
majik 0:964eb6a2ef00 351 int rfPwr = getRegister(_NRF24L01P_REG_RF_SETUP) & _NRF24L01P_RF_SETUP_RF_PWR_MASK;
majik 0:964eb6a2ef00 352
majik 0:964eb6a2ef00 353 switch ( rfPwr ) {
majik 0:964eb6a2ef00 354
majik 0:964eb6a2ef00 355 case _NRF24L01P_RF_SETUP_RF_PWR_0DBM:
majik 0:964eb6a2ef00 356 return NRF24L01P_TX_PWR_ZERO_DB;
majik 0:964eb6a2ef00 357
majik 0:964eb6a2ef00 358 case _NRF24L01P_RF_SETUP_RF_PWR_MINUS_6DBM:
majik 0:964eb6a2ef00 359 return NRF24L01P_TX_PWR_MINUS_6_DB;
majik 0:964eb6a2ef00 360
majik 0:964eb6a2ef00 361 case _NRF24L01P_RF_SETUP_RF_PWR_MINUS_12DBM:
majik 0:964eb6a2ef00 362 return NRF24L01P_TX_PWR_MINUS_12_DB;
majik 0:964eb6a2ef00 363
majik 0:964eb6a2ef00 364 case _NRF24L01P_RF_SETUP_RF_PWR_MINUS_18DBM:
majik 0:964eb6a2ef00 365 return NRF24L01P_TX_PWR_MINUS_18_DB;
majik 0:964eb6a2ef00 366
majik 0:964eb6a2ef00 367 default:
majik 0:964eb6a2ef00 368 error( "nRF24L01P: Unknown RF Output Power value %d\r\n", rfPwr );
majik 0:964eb6a2ef00 369 return 0;
majik 0:964eb6a2ef00 370
majik 0:964eb6a2ef00 371 }
majik 0:964eb6a2ef00 372 }
majik 0:964eb6a2ef00 373
majik 0:964eb6a2ef00 374
majik 0:964eb6a2ef00 375 void nRF24L01P::setAirDataRate(int rate) {
majik 0:964eb6a2ef00 376
majik 0:964eb6a2ef00 377 int rfSetup = getRegister(_NRF24L01P_REG_RF_SETUP) & ~_NRF24L01P_RF_SETUP_RF_DR_MASK;
majik 0:964eb6a2ef00 378
majik 0:964eb6a2ef00 379 switch ( rate ) {
majik 0:964eb6a2ef00 380
majik 0:964eb6a2ef00 381 case NRF24L01P_DATARATE_250_KBPS:
majik 0:964eb6a2ef00 382 rfSetup |= _NRF24L01P_RF_SETUP_RF_DR_250KBPS;
majik 0:964eb6a2ef00 383 break;
majik 0:964eb6a2ef00 384
majik 0:964eb6a2ef00 385 case NRF24L01P_DATARATE_1_MBPS:
majik 0:964eb6a2ef00 386 rfSetup |= _NRF24L01P_RF_SETUP_RF_DR_1MBPS;
majik 0:964eb6a2ef00 387 break;
majik 0:964eb6a2ef00 388
majik 0:964eb6a2ef00 389 case NRF24L01P_DATARATE_2_MBPS:
majik 0:964eb6a2ef00 390 rfSetup |= _NRF24L01P_RF_SETUP_RF_DR_2MBPS;
majik 0:964eb6a2ef00 391 break;
majik 0:964eb6a2ef00 392
majik 0:964eb6a2ef00 393 default:
majik 0:964eb6a2ef00 394 error( "nRF24L01P: Invalid Air Data Rate setting %d\r\n", rate );
majik 0:964eb6a2ef00 395 return;
majik 0:964eb6a2ef00 396
majik 0:964eb6a2ef00 397 }
majik 0:964eb6a2ef00 398
majik 0:964eb6a2ef00 399 setRegister(_NRF24L01P_REG_RF_SETUP, rfSetup);
majik 0:964eb6a2ef00 400
majik 0:964eb6a2ef00 401 }
majik 0:964eb6a2ef00 402
majik 0:964eb6a2ef00 403
majik 0:964eb6a2ef00 404 int nRF24L01P::getAirDataRate(void) {
majik 0:964eb6a2ef00 405
majik 0:964eb6a2ef00 406 int rfDataRate = getRegister(_NRF24L01P_REG_RF_SETUP) & _NRF24L01P_RF_SETUP_RF_DR_MASK;
majik 0:964eb6a2ef00 407
majik 0:964eb6a2ef00 408 switch ( rfDataRate ) {
majik 0:964eb6a2ef00 409
majik 0:964eb6a2ef00 410 case _NRF24L01P_RF_SETUP_RF_DR_250KBPS:
majik 0:964eb6a2ef00 411 return NRF24L01P_DATARATE_250_KBPS;
majik 0:964eb6a2ef00 412
majik 0:964eb6a2ef00 413 case _NRF24L01P_RF_SETUP_RF_DR_1MBPS:
majik 0:964eb6a2ef00 414 return NRF24L01P_DATARATE_1_MBPS;
majik 0:964eb6a2ef00 415
majik 0:964eb6a2ef00 416 case _NRF24L01P_RF_SETUP_RF_DR_2MBPS:
majik 0:964eb6a2ef00 417 return NRF24L01P_DATARATE_2_MBPS;
majik 0:964eb6a2ef00 418
majik 0:964eb6a2ef00 419 default:
majik 0:964eb6a2ef00 420 error( "nRF24L01P: Unknown Air Data Rate value %d\r\n", rfDataRate );
majik 0:964eb6a2ef00 421 return 0;
majik 0:964eb6a2ef00 422
majik 0:964eb6a2ef00 423 }
majik 0:964eb6a2ef00 424 }
majik 0:964eb6a2ef00 425
majik 0:964eb6a2ef00 426
majik 0:964eb6a2ef00 427 void nRF24L01P::setCrcWidth(int width) {
majik 0:964eb6a2ef00 428
majik 0:964eb6a2ef00 429 int config = getRegister(_NRF24L01P_REG_CONFIG) & ~_NRF24L01P_CONFIG_CRC_MASK;
majik 0:964eb6a2ef00 430
majik 0:964eb6a2ef00 431 switch ( width ) {
majik 0:964eb6a2ef00 432
majik 0:964eb6a2ef00 433 case NRF24L01P_CRC_NONE:
majik 0:964eb6a2ef00 434 config |= _NRF24L01P_CONFIG_CRC_NONE;
majik 0:964eb6a2ef00 435 break;
majik 0:964eb6a2ef00 436
majik 0:964eb6a2ef00 437 case NRF24L01P_CRC_8_BIT:
majik 0:964eb6a2ef00 438 config |= _NRF24L01P_CONFIG_CRC_8BIT;
majik 0:964eb6a2ef00 439 break;
majik 0:964eb6a2ef00 440
majik 0:964eb6a2ef00 441 case NRF24L01P_CRC_16_BIT:
majik 0:964eb6a2ef00 442 config |= _NRF24L01P_CONFIG_CRC_16BIT;
majik 0:964eb6a2ef00 443 break;
majik 0:964eb6a2ef00 444
majik 0:964eb6a2ef00 445 default:
majik 0:964eb6a2ef00 446 error( "nRF24L01P: Invalid CRC Width setting %d\r\n", width );
majik 0:964eb6a2ef00 447 return;
majik 0:964eb6a2ef00 448
majik 0:964eb6a2ef00 449 }
majik 0:964eb6a2ef00 450
majik 0:964eb6a2ef00 451 setRegister(_NRF24L01P_REG_CONFIG, config);
majik 0:964eb6a2ef00 452
majik 0:964eb6a2ef00 453 }
majik 0:964eb6a2ef00 454
majik 0:964eb6a2ef00 455
majik 0:964eb6a2ef00 456 int nRF24L01P::getCrcWidth(void) {
majik 0:964eb6a2ef00 457
majik 0:964eb6a2ef00 458 int crcWidth = getRegister(_NRF24L01P_REG_CONFIG) & _NRF24L01P_CONFIG_CRC_MASK;
majik 0:964eb6a2ef00 459
majik 0:964eb6a2ef00 460 switch ( crcWidth ) {
majik 0:964eb6a2ef00 461
majik 0:964eb6a2ef00 462 case _NRF24L01P_CONFIG_CRC_NONE:
majik 0:964eb6a2ef00 463 return NRF24L01P_CRC_NONE;
majik 0:964eb6a2ef00 464
majik 0:964eb6a2ef00 465 case _NRF24L01P_CONFIG_CRC_8BIT:
majik 0:964eb6a2ef00 466 return NRF24L01P_CRC_8_BIT;
majik 0:964eb6a2ef00 467
majik 0:964eb6a2ef00 468 case _NRF24L01P_CONFIG_CRC_16BIT:
majik 0:964eb6a2ef00 469 return NRF24L01P_CRC_16_BIT;
majik 0:964eb6a2ef00 470
majik 0:964eb6a2ef00 471 default:
majik 0:964eb6a2ef00 472 error( "nRF24L01P: Unknown CRC Width value %d\r\n", crcWidth );
majik 0:964eb6a2ef00 473 return 0;
majik 0:964eb6a2ef00 474
majik 0:964eb6a2ef00 475 }
majik 0:964eb6a2ef00 476 }
majik 0:964eb6a2ef00 477
majik 0:964eb6a2ef00 478
majik 0:964eb6a2ef00 479 void nRF24L01P::setTransferSize(int size, int pipe) {
majik 0:964eb6a2ef00 480
majik 0:964eb6a2ef00 481 if ( ( pipe < NRF24L01P_PIPE_P0 ) || ( pipe > NRF24L01P_PIPE_P5 ) ) {
majik 0:964eb6a2ef00 482
majik 0:964eb6a2ef00 483 error( "nRF24L01P: Invalid Transfer Size pipe number %d\r\n", pipe );
majik 0:964eb6a2ef00 484 return;
majik 0:964eb6a2ef00 485
majik 0:964eb6a2ef00 486 }
majik 0:964eb6a2ef00 487
majik 0:964eb6a2ef00 488 if ( ( size < 0 ) || ( size > _NRF24L01P_RX_FIFO_SIZE ) ) {
majik 0:964eb6a2ef00 489
majik 0:964eb6a2ef00 490 error( "nRF24L01P: Invalid Transfer Size setting %d\r\n", size );
majik 0:964eb6a2ef00 491 return;
majik 0:964eb6a2ef00 492
majik 0:964eb6a2ef00 493 }
majik 0:964eb6a2ef00 494
majik 0:964eb6a2ef00 495 int rxPwPxRegister = _NRF24L01P_REG_RX_PW_P0 + ( pipe - NRF24L01P_PIPE_P0 );
majik 0:964eb6a2ef00 496
majik 0:964eb6a2ef00 497 setRegister(rxPwPxRegister, ( size & _NRF24L01P_RX_PW_Px_MASK ) );
majik 0:964eb6a2ef00 498
majik 0:964eb6a2ef00 499 }
majik 0:964eb6a2ef00 500
majik 0:964eb6a2ef00 501
majik 0:964eb6a2ef00 502 int nRF24L01P::getTransferSize(int pipe) {
majik 0:964eb6a2ef00 503
majik 0:964eb6a2ef00 504 if ( ( pipe < NRF24L01P_PIPE_P0 ) || ( pipe > NRF24L01P_PIPE_P5 ) ) {
majik 0:964eb6a2ef00 505
majik 0:964eb6a2ef00 506 error( "nRF24L01P: Invalid Transfer Size pipe number %d\r\n", pipe );
majik 0:964eb6a2ef00 507 return 0;
majik 0:964eb6a2ef00 508
majik 0:964eb6a2ef00 509 }
majik 0:964eb6a2ef00 510
majik 0:964eb6a2ef00 511 int rxPwPxRegister = _NRF24L01P_REG_RX_PW_P0 + ( pipe - NRF24L01P_PIPE_P0 );
majik 0:964eb6a2ef00 512
majik 0:964eb6a2ef00 513 int size = getRegister(rxPwPxRegister);
majik 0:964eb6a2ef00 514
majik 0:964eb6a2ef00 515 return ( size & _NRF24L01P_RX_PW_Px_MASK );
majik 0:964eb6a2ef00 516
majik 0:964eb6a2ef00 517 }
majik 0:964eb6a2ef00 518
majik 0:964eb6a2ef00 519
majik 0:964eb6a2ef00 520 void nRF24L01P::disableAllRxPipes(void) {
majik 0:964eb6a2ef00 521
majik 0:964eb6a2ef00 522 setRegister(_NRF24L01P_REG_EN_RXADDR, _NRF24L01P_EN_RXADDR_NONE);
majik 0:964eb6a2ef00 523
majik 0:964eb6a2ef00 524 }
majik 0:964eb6a2ef00 525
majik 0:964eb6a2ef00 526
majik 0:964eb6a2ef00 527 void nRF24L01P::disableAutoAcknowledge(void) {
majik 0:964eb6a2ef00 528
majik 0:964eb6a2ef00 529 setRegister(_NRF24L01P_REG_EN_AA, _NRF24L01P_EN_AA_NONE);
majik 0:964eb6a2ef00 530
majik 0:964eb6a2ef00 531 }
majik 0:964eb6a2ef00 532
majik 0:964eb6a2ef00 533
majik 0:964eb6a2ef00 534 void nRF24L01P::enableAutoAcknowledge(int pipe) {
majik 0:964eb6a2ef00 535
majik 0:964eb6a2ef00 536 if ( ( pipe < NRF24L01P_PIPE_P0 ) || ( pipe > NRF24L01P_PIPE_P5 ) ) {
majik 0:964eb6a2ef00 537
majik 0:964eb6a2ef00 538 error( "nRF24L01P: Invalid Enable AutoAcknowledge pipe number %d\r\n", pipe );
majik 0:964eb6a2ef00 539 return;
majik 0:964eb6a2ef00 540
majik 0:964eb6a2ef00 541 }
majik 0:964eb6a2ef00 542
majik 0:964eb6a2ef00 543 int enAA = getRegister(_NRF24L01P_REG_EN_AA);
majik 0:964eb6a2ef00 544
majik 0:964eb6a2ef00 545 enAA |= ( 1 << (pipe - NRF24L01P_PIPE_P0) );
majik 0:964eb6a2ef00 546
majik 0:964eb6a2ef00 547 setRegister(_NRF24L01P_REG_EN_AA, enAA);
majik 0:964eb6a2ef00 548
majik 0:964eb6a2ef00 549 }
majik 0:964eb6a2ef00 550
majik 0:964eb6a2ef00 551
majik 0:964eb6a2ef00 552 void nRF24L01P::disableAutoRetransmit(void) {
majik 0:964eb6a2ef00 553
majik 0:964eb6a2ef00 554 setRegister(_NRF24L01P_REG_SETUP_RETR, _NRF24L01P_SETUP_RETR_NONE);
majik 0:964eb6a2ef00 555
majik 0:964eb6a2ef00 556 }
majik 0:964eb6a2ef00 557
majik 0:964eb6a2ef00 558 void nRF24L01P::setRxAddress(unsigned long long address, int width, int pipe) {
majik 0:964eb6a2ef00 559
majik 0:964eb6a2ef00 560 if ( ( pipe < NRF24L01P_PIPE_P0 ) || ( pipe > NRF24L01P_PIPE_P5 ) ) {
majik 0:964eb6a2ef00 561
majik 0:964eb6a2ef00 562 error( "nRF24L01P: Invalid setRxAddress pipe number %d\r\n", pipe );
majik 0:964eb6a2ef00 563 return;
majik 0:964eb6a2ef00 564
majik 0:964eb6a2ef00 565 }
majik 0:964eb6a2ef00 566
majik 0:964eb6a2ef00 567 if ( ( pipe == NRF24L01P_PIPE_P0 ) || ( pipe == NRF24L01P_PIPE_P1 ) ) {
majik 0:964eb6a2ef00 568
majik 0:964eb6a2ef00 569 int setupAw = getRegister(_NRF24L01P_REG_SETUP_AW) & ~_NRF24L01P_SETUP_AW_AW_MASK;
majik 0:964eb6a2ef00 570
majik 0:964eb6a2ef00 571 switch ( width ) {
majik 0:964eb6a2ef00 572
majik 0:964eb6a2ef00 573 case 3:
majik 0:964eb6a2ef00 574 setupAw |= _NRF24L01P_SETUP_AW_AW_3BYTE;
majik 0:964eb6a2ef00 575 break;
majik 0:964eb6a2ef00 576
majik 0:964eb6a2ef00 577 case 4:
majik 0:964eb6a2ef00 578 setupAw |= _NRF24L01P_SETUP_AW_AW_4BYTE;
majik 0:964eb6a2ef00 579 break;
majik 0:964eb6a2ef00 580
majik 0:964eb6a2ef00 581 case 5:
majik 0:964eb6a2ef00 582 setupAw |= _NRF24L01P_SETUP_AW_AW_5BYTE;
majik 0:964eb6a2ef00 583 break;
majik 0:964eb6a2ef00 584
majik 0:964eb6a2ef00 585 default:
majik 0:964eb6a2ef00 586 error( "nRF24L01P: Invalid setRxAddress width setting %d\r\n", width );
majik 0:964eb6a2ef00 587 return;
majik 0:964eb6a2ef00 588
majik 0:964eb6a2ef00 589 }
majik 0:964eb6a2ef00 590
majik 0:964eb6a2ef00 591 setRegister(_NRF24L01P_REG_SETUP_AW, setupAw);
majik 0:964eb6a2ef00 592
majik 0:964eb6a2ef00 593 } else {
majik 0:964eb6a2ef00 594
majik 0:964eb6a2ef00 595 width = 1;
majik 0:964eb6a2ef00 596
majik 0:964eb6a2ef00 597 }
majik 0:964eb6a2ef00 598
majik 0:964eb6a2ef00 599 int rxAddrPxRegister = _NRF24L01P_REG_RX_ADDR_P0 + ( pipe - NRF24L01P_PIPE_P0 );
majik 0:964eb6a2ef00 600
majik 0:964eb6a2ef00 601 int cn = (_NRF24L01P_SPI_CMD_WR_REG | (rxAddrPxRegister & _NRF24L01P_REG_ADDRESS_MASK));
majik 0:964eb6a2ef00 602
majik 0:964eb6a2ef00 603 nCS_ = 0;
majik 0:964eb6a2ef00 604
majik 0:964eb6a2ef00 605 int status = spi_.write(cn);
majik 0:964eb6a2ef00 606
majik 0:964eb6a2ef00 607 while ( width-- > 0 ) {
majik 0:964eb6a2ef00 608
majik 0:964eb6a2ef00 609 //
majik 0:964eb6a2ef00 610 // LSByte first
majik 0:964eb6a2ef00 611 //
majik 0:964eb6a2ef00 612 spi_.write((int) (address & 0xFF));
majik 0:964eb6a2ef00 613 address >>= 8;
majik 0:964eb6a2ef00 614
majik 0:964eb6a2ef00 615 }
majik 0:964eb6a2ef00 616
majik 0:964eb6a2ef00 617 nCS_ = 1;
majik 0:964eb6a2ef00 618
majik 0:964eb6a2ef00 619 int enRxAddr = getRegister(_NRF24L01P_REG_EN_RXADDR);
majik 0:964eb6a2ef00 620
majik 0:964eb6a2ef00 621 enRxAddr |= (1 << ( pipe - NRF24L01P_PIPE_P0 ) );
majik 0:964eb6a2ef00 622
majik 0:964eb6a2ef00 623 setRegister(_NRF24L01P_REG_EN_RXADDR, enRxAddr);
majik 0:964eb6a2ef00 624 }
majik 0:964eb6a2ef00 625
majik 0:964eb6a2ef00 626 /*
majik 0:964eb6a2ef00 627 * This version of setRxAddress is just a wrapper for the version that takes 'long long's,
majik 0:964eb6a2ef00 628 * in case the main code doesn't want to deal with long long's.
majik 0:964eb6a2ef00 629 */
majik 0:964eb6a2ef00 630 void nRF24L01P::setRxAddress(unsigned long msb_address, unsigned long lsb_address, int width, int pipe) {
majik 0:964eb6a2ef00 631
majik 0:964eb6a2ef00 632 unsigned long long address = ( ( (unsigned long long) msb_address ) << 32 ) | ( ( (unsigned long long) lsb_address ) << 0 );
majik 0:964eb6a2ef00 633
majik 0:964eb6a2ef00 634 setRxAddress(address, width, pipe);
majik 0:964eb6a2ef00 635
majik 0:964eb6a2ef00 636 }
majik 0:964eb6a2ef00 637
majik 0:964eb6a2ef00 638
majik 0:964eb6a2ef00 639 /*
majik 0:964eb6a2ef00 640 * This version of setTxAddress is just a wrapper for the version that takes 'long long's,
majik 0:964eb6a2ef00 641 * in case the main code doesn't want to deal with long long's.
majik 0:964eb6a2ef00 642 */
majik 0:964eb6a2ef00 643 void nRF24L01P::setTxAddress(unsigned long msb_address, unsigned long lsb_address, int width) {
majik 0:964eb6a2ef00 644
majik 0:964eb6a2ef00 645 unsigned long long address = ( ( (unsigned long long) msb_address ) << 32 ) | ( ( (unsigned long long) lsb_address ) << 0 );
majik 0:964eb6a2ef00 646
majik 0:964eb6a2ef00 647 setTxAddress(address, width);
majik 0:964eb6a2ef00 648
majik 0:964eb6a2ef00 649 }
majik 0:964eb6a2ef00 650
majik 0:964eb6a2ef00 651
majik 0:964eb6a2ef00 652 void nRF24L01P::setTxAddress(unsigned long long address, int width) {
majik 0:964eb6a2ef00 653
majik 0:964eb6a2ef00 654 int setupAw = getRegister(_NRF24L01P_REG_SETUP_AW) & ~_NRF24L01P_SETUP_AW_AW_MASK;
majik 0:964eb6a2ef00 655
majik 0:964eb6a2ef00 656 switch ( width ) {
majik 0:964eb6a2ef00 657
majik 0:964eb6a2ef00 658 case 3:
majik 0:964eb6a2ef00 659 setupAw |= _NRF24L01P_SETUP_AW_AW_3BYTE;
majik 0:964eb6a2ef00 660 break;
majik 0:964eb6a2ef00 661
majik 0:964eb6a2ef00 662 case 4:
majik 0:964eb6a2ef00 663 setupAw |= _NRF24L01P_SETUP_AW_AW_4BYTE;
majik 0:964eb6a2ef00 664 break;
majik 0:964eb6a2ef00 665
majik 0:964eb6a2ef00 666 case 5:
majik 0:964eb6a2ef00 667 setupAw |= _NRF24L01P_SETUP_AW_AW_5BYTE;
majik 0:964eb6a2ef00 668 break;
majik 0:964eb6a2ef00 669
majik 0:964eb6a2ef00 670 default:
majik 0:964eb6a2ef00 671 error( "nRF24L01P: Invalid setTxAddress width setting %d\r\n", width );
majik 0:964eb6a2ef00 672 return;
majik 0:964eb6a2ef00 673
majik 0:964eb6a2ef00 674 }
majik 0:964eb6a2ef00 675
majik 0:964eb6a2ef00 676 setRegister(_NRF24L01P_REG_SETUP_AW, setupAw);
majik 0:964eb6a2ef00 677
majik 0:964eb6a2ef00 678 int cn = (_NRF24L01P_SPI_CMD_WR_REG | (_NRF24L01P_REG_TX_ADDR & _NRF24L01P_REG_ADDRESS_MASK));
majik 0:964eb6a2ef00 679
majik 0:964eb6a2ef00 680 nCS_ = 0;
majik 0:964eb6a2ef00 681
majik 0:964eb6a2ef00 682 int status = spi_.write(cn);
majik 0:964eb6a2ef00 683
majik 0:964eb6a2ef00 684 while ( width-- > 0 ) {
majik 0:964eb6a2ef00 685
majik 0:964eb6a2ef00 686 //
majik 0:964eb6a2ef00 687 // LSByte first
majik 0:964eb6a2ef00 688 //
majik 0:964eb6a2ef00 689 spi_.write((int) (address & 0xFF));
majik 0:964eb6a2ef00 690 address >>= 8;
majik 0:964eb6a2ef00 691
majik 0:964eb6a2ef00 692 }
majik 0:964eb6a2ef00 693
majik 0:964eb6a2ef00 694 nCS_ = 1;
majik 0:964eb6a2ef00 695
majik 0:964eb6a2ef00 696 }
majik 0:964eb6a2ef00 697
majik 0:964eb6a2ef00 698
majik 0:964eb6a2ef00 699 unsigned long long nRF24L01P::getRxAddress(int pipe) {
majik 0:964eb6a2ef00 700
majik 0:964eb6a2ef00 701 if ( ( pipe < NRF24L01P_PIPE_P0 ) || ( pipe > NRF24L01P_PIPE_P5 ) ) {
majik 0:964eb6a2ef00 702
majik 0:964eb6a2ef00 703 error( "nRF24L01P: Invalid setRxAddress pipe number %d\r\n", pipe );
majik 0:964eb6a2ef00 704 return 0;
majik 0:964eb6a2ef00 705
majik 0:964eb6a2ef00 706 }
majik 0:964eb6a2ef00 707
majik 0:964eb6a2ef00 708 int width;
majik 0:964eb6a2ef00 709
majik 0:964eb6a2ef00 710 if ( ( pipe == NRF24L01P_PIPE_P0 ) || ( pipe == NRF24L01P_PIPE_P1 ) ) {
majik 0:964eb6a2ef00 711
majik 0:964eb6a2ef00 712 int setupAw = getRegister(_NRF24L01P_REG_SETUP_AW) & _NRF24L01P_SETUP_AW_AW_MASK;
majik 0:964eb6a2ef00 713
majik 0:964eb6a2ef00 714 switch ( setupAw ) {
majik 0:964eb6a2ef00 715
majik 0:964eb6a2ef00 716 case _NRF24L01P_SETUP_AW_AW_3BYTE:
majik 0:964eb6a2ef00 717 width = 3;
majik 0:964eb6a2ef00 718 break;
majik 0:964eb6a2ef00 719
majik 0:964eb6a2ef00 720 case _NRF24L01P_SETUP_AW_AW_4BYTE:
majik 0:964eb6a2ef00 721 width = 4;
majik 0:964eb6a2ef00 722 break;
majik 0:964eb6a2ef00 723
majik 0:964eb6a2ef00 724 case _NRF24L01P_SETUP_AW_AW_5BYTE:
majik 0:964eb6a2ef00 725 width = 5;
majik 0:964eb6a2ef00 726 break;
majik 0:964eb6a2ef00 727
majik 0:964eb6a2ef00 728 default:
majik 0:964eb6a2ef00 729 error( "nRF24L01P: Unknown getRxAddress width value %d\r\n", setupAw );
majik 0:964eb6a2ef00 730 return 0;
majik 0:964eb6a2ef00 731
majik 0:964eb6a2ef00 732 }
majik 0:964eb6a2ef00 733
majik 0:964eb6a2ef00 734 } else {
majik 0:964eb6a2ef00 735
majik 0:964eb6a2ef00 736 width = 1;
majik 0:964eb6a2ef00 737
majik 0:964eb6a2ef00 738 }
majik 0:964eb6a2ef00 739
majik 0:964eb6a2ef00 740 int rxAddrPxRegister = _NRF24L01P_REG_RX_ADDR_P0 + ( pipe - NRF24L01P_PIPE_P0 );
majik 0:964eb6a2ef00 741
majik 0:964eb6a2ef00 742 int cn = (_NRF24L01P_SPI_CMD_RD_REG | (rxAddrPxRegister & _NRF24L01P_REG_ADDRESS_MASK));
majik 0:964eb6a2ef00 743
majik 0:964eb6a2ef00 744 unsigned long long address = 0;
majik 0:964eb6a2ef00 745
majik 0:964eb6a2ef00 746 nCS_ = 0;
majik 0:964eb6a2ef00 747
majik 0:964eb6a2ef00 748 int status = spi_.write(cn);
majik 0:964eb6a2ef00 749
majik 0:964eb6a2ef00 750 for ( int i=0; i<width; i++ ) {
majik 0:964eb6a2ef00 751
majik 0:964eb6a2ef00 752 //
majik 0:964eb6a2ef00 753 // LSByte first
majik 0:964eb6a2ef00 754 //
majik 0:964eb6a2ef00 755 address |= ( ( (unsigned long long)( spi_.write(_NRF24L01P_SPI_CMD_NOP) & 0xFF ) ) << (i*8) );
majik 0:964eb6a2ef00 756
majik 0:964eb6a2ef00 757 }
majik 0:964eb6a2ef00 758
majik 0:964eb6a2ef00 759 nCS_ = 1;
majik 0:964eb6a2ef00 760
majik 0:964eb6a2ef00 761 if ( !( ( pipe == NRF24L01P_PIPE_P0 ) || ( pipe == NRF24L01P_PIPE_P1 ) ) ) {
majik 0:964eb6a2ef00 762
majik 0:964eb6a2ef00 763 address |= ( getRxAddress(NRF24L01P_PIPE_P1) & ~((unsigned long long) 0xFF) );
majik 0:964eb6a2ef00 764
majik 0:964eb6a2ef00 765 }
majik 0:964eb6a2ef00 766
majik 0:964eb6a2ef00 767 return address;
majik 0:964eb6a2ef00 768
majik 0:964eb6a2ef00 769 }
majik 0:964eb6a2ef00 770
majik 0:964eb6a2ef00 771
majik 0:964eb6a2ef00 772 unsigned long long nRF24L01P::getTxAddress(void) {
majik 0:964eb6a2ef00 773
majik 0:964eb6a2ef00 774 int setupAw = getRegister(_NRF24L01P_REG_SETUP_AW) & _NRF24L01P_SETUP_AW_AW_MASK;
majik 0:964eb6a2ef00 775
majik 0:964eb6a2ef00 776 int width;
majik 0:964eb6a2ef00 777
majik 0:964eb6a2ef00 778 switch ( setupAw ) {
majik 0:964eb6a2ef00 779
majik 0:964eb6a2ef00 780 case _NRF24L01P_SETUP_AW_AW_3BYTE:
majik 0:964eb6a2ef00 781 width = 3;
majik 0:964eb6a2ef00 782 break;
majik 0:964eb6a2ef00 783
majik 0:964eb6a2ef00 784 case _NRF24L01P_SETUP_AW_AW_4BYTE:
majik 0:964eb6a2ef00 785 width = 4;
majik 0:964eb6a2ef00 786 break;
majik 0:964eb6a2ef00 787
majik 0:964eb6a2ef00 788 case _NRF24L01P_SETUP_AW_AW_5BYTE:
majik 0:964eb6a2ef00 789 width = 5;
majik 0:964eb6a2ef00 790 break;
majik 0:964eb6a2ef00 791
majik 0:964eb6a2ef00 792 default:
majik 0:964eb6a2ef00 793 error( "nRF24L01P: Unknown getTxAddress width value %d\r\n", setupAw );
majik 0:964eb6a2ef00 794 return 0;
majik 0:964eb6a2ef00 795
majik 0:964eb6a2ef00 796 }
majik 0:964eb6a2ef00 797
majik 0:964eb6a2ef00 798 int cn = (_NRF24L01P_SPI_CMD_RD_REG | (_NRF24L01P_REG_TX_ADDR & _NRF24L01P_REG_ADDRESS_MASK));
majik 0:964eb6a2ef00 799
majik 0:964eb6a2ef00 800 unsigned long long address = 0;
majik 0:964eb6a2ef00 801
majik 0:964eb6a2ef00 802 nCS_ = 0;
majik 0:964eb6a2ef00 803
majik 0:964eb6a2ef00 804 int status = spi_.write(cn);
majik 0:964eb6a2ef00 805
majik 0:964eb6a2ef00 806 for ( int i=0; i<width; i++ ) {
majik 0:964eb6a2ef00 807
majik 0:964eb6a2ef00 808 //
majik 0:964eb6a2ef00 809 // LSByte first
majik 0:964eb6a2ef00 810 //
majik 0:964eb6a2ef00 811 address |= ( ( (unsigned long long)( spi_.write(_NRF24L01P_SPI_CMD_NOP) & 0xFF ) ) << (i*8) );
majik 0:964eb6a2ef00 812
majik 0:964eb6a2ef00 813 }
majik 0:964eb6a2ef00 814
majik 0:964eb6a2ef00 815 nCS_ = 1;
majik 0:964eb6a2ef00 816
majik 0:964eb6a2ef00 817 return address;
majik 0:964eb6a2ef00 818 }
majik 0:964eb6a2ef00 819
majik 0:964eb6a2ef00 820
majik 0:964eb6a2ef00 821 bool nRF24L01P::readable(int pipe) {
majik 0:964eb6a2ef00 822
majik 0:964eb6a2ef00 823 if ( ( pipe < NRF24L01P_PIPE_P0 ) || ( pipe > NRF24L01P_PIPE_P5 ) ) {
majik 0:964eb6a2ef00 824
majik 0:964eb6a2ef00 825 error( "nRF24L01P: Invalid readable pipe number %d\r\n", pipe );
majik 0:964eb6a2ef00 826 return false;
majik 0:964eb6a2ef00 827
majik 0:964eb6a2ef00 828 }
majik 0:964eb6a2ef00 829
majik 0:964eb6a2ef00 830 int status = getStatusRegister();
majik 0:964eb6a2ef00 831
majik 0:964eb6a2ef00 832 return ( ( status & _NRF24L01P_STATUS_RX_DR ) && ( ( ( status & _NRF24L01P_STATUS_RX_P_NO ) >> 1 ) == ( pipe & 0x7 ) ) );
majik 0:964eb6a2ef00 833
majik 0:964eb6a2ef00 834 }
majik 0:964eb6a2ef00 835
majik 0:964eb6a2ef00 836
majik 0:964eb6a2ef00 837 int nRF24L01P::write(int pipe, char *data, int count) {
majik 0:964eb6a2ef00 838
majik 0:964eb6a2ef00 839 // Note: the pipe number is ignored in a Transmit / write
majik 0:964eb6a2ef00 840
majik 0:964eb6a2ef00 841 //
majik 0:964eb6a2ef00 842 // Save the CE state
majik 0:964eb6a2ef00 843 //
majik 0:964eb6a2ef00 844 int originalCe = ce_;
majik 0:964eb6a2ef00 845 disable();
majik 0:964eb6a2ef00 846
majik 0:964eb6a2ef00 847 if ( count <= 0 ) return 0;
majik 0:964eb6a2ef00 848
majik 0:964eb6a2ef00 849 if ( count > _NRF24L01P_TX_FIFO_SIZE ) count = _NRF24L01P_TX_FIFO_SIZE;
majik 0:964eb6a2ef00 850
majik 0:964eb6a2ef00 851 // Clear the Status bit
majik 0:964eb6a2ef00 852 setRegister(_NRF24L01P_REG_STATUS, _NRF24L01P_STATUS_TX_DS);
majik 0:964eb6a2ef00 853
majik 0:964eb6a2ef00 854 nCS_ = 0;
majik 0:964eb6a2ef00 855
majik 0:964eb6a2ef00 856 int status = spi_.write(_NRF24L01P_SPI_CMD_WR_TX_PAYLOAD);
majik 0:964eb6a2ef00 857
majik 0:964eb6a2ef00 858 for ( int i = 0; i < count; i++ ) {
majik 0:964eb6a2ef00 859
majik 0:964eb6a2ef00 860 spi_.write(*data++);
majik 0:964eb6a2ef00 861
majik 0:964eb6a2ef00 862 }
majik 0:964eb6a2ef00 863
majik 0:964eb6a2ef00 864 nCS_ = 1;
majik 0:964eb6a2ef00 865
majik 0:964eb6a2ef00 866 int originalMode = mode;
majik 0:964eb6a2ef00 867 setTransmitMode();
majik 0:964eb6a2ef00 868
majik 0:964eb6a2ef00 869 enable();
majik 0:964eb6a2ef00 870 wait_us(_NRF24L01P_TIMING_Thce_us);
majik 0:964eb6a2ef00 871 disable();
majik 0:964eb6a2ef00 872
majik 0:964eb6a2ef00 873 while ( !( getStatusRegister() & _NRF24L01P_STATUS_TX_DS ) ) {
majik 0:964eb6a2ef00 874
majik 0:964eb6a2ef00 875 // Wait for the transfer to complete
majik 0:964eb6a2ef00 876
majik 0:964eb6a2ef00 877 }
majik 0:964eb6a2ef00 878
majik 0:964eb6a2ef00 879 // Clear the Status bit
majik 0:964eb6a2ef00 880 setRegister(_NRF24L01P_REG_STATUS, _NRF24L01P_STATUS_TX_DS);
majik 0:964eb6a2ef00 881
majik 0:964eb6a2ef00 882 if ( originalMode == _NRF24L01P_MODE_RX ) {
majik 0:964eb6a2ef00 883
majik 0:964eb6a2ef00 884 setReceiveMode();
majik 0:964eb6a2ef00 885
majik 0:964eb6a2ef00 886 }
majik 0:964eb6a2ef00 887
majik 0:964eb6a2ef00 888 ce_ = originalCe;
majik 0:964eb6a2ef00 889 wait_us( _NRF24L01P_TIMING_Tpece2csn_us );
majik 0:964eb6a2ef00 890
majik 0:964eb6a2ef00 891 return count;
majik 0:964eb6a2ef00 892
majik 0:964eb6a2ef00 893 }
majik 0:964eb6a2ef00 894
majik 0:964eb6a2ef00 895
majik 0:964eb6a2ef00 896 int nRF24L01P::read(int pipe, char *data, int count) {
majik 0:964eb6a2ef00 897
majik 0:964eb6a2ef00 898 if ( ( pipe < NRF24L01P_PIPE_P0 ) || ( pipe > NRF24L01P_PIPE_P5 ) ) {
majik 0:964eb6a2ef00 899
majik 0:964eb6a2ef00 900 error( "nRF24L01P: Invalid read pipe number %d\r\n", pipe );
majik 0:964eb6a2ef00 901 return -1;
majik 0:964eb6a2ef00 902
majik 0:964eb6a2ef00 903 }
majik 0:964eb6a2ef00 904
majik 0:964eb6a2ef00 905 if ( count <= 0 ) return 0;
majik 0:964eb6a2ef00 906
majik 0:964eb6a2ef00 907 if ( count > _NRF24L01P_RX_FIFO_SIZE ) count = _NRF24L01P_RX_FIFO_SIZE;
majik 0:964eb6a2ef00 908
majik 0:964eb6a2ef00 909 if ( readable(pipe) ) {
majik 0:964eb6a2ef00 910
majik 0:964eb6a2ef00 911 nCS_ = 0;
majik 0:964eb6a2ef00 912
majik 0:964eb6a2ef00 913 int status = spi_.write(_NRF24L01P_SPI_CMD_R_RX_PL_WID);
majik 0:964eb6a2ef00 914
majik 0:964eb6a2ef00 915 int rxPayloadWidth = spi_.write(_NRF24L01P_SPI_CMD_NOP);
majik 0:964eb6a2ef00 916
majik 0:964eb6a2ef00 917 nCS_ = 1;
majik 0:964eb6a2ef00 918
majik 0:964eb6a2ef00 919 if ( ( rxPayloadWidth < 0 ) || ( rxPayloadWidth > _NRF24L01P_RX_FIFO_SIZE ) ) {
majik 0:964eb6a2ef00 920
majik 0:964eb6a2ef00 921 // Received payload error: need to flush the FIFO
majik 0:964eb6a2ef00 922
majik 0:964eb6a2ef00 923 nCS_ = 0;
majik 0:964eb6a2ef00 924
majik 0:964eb6a2ef00 925 int status = spi_.write(_NRF24L01P_SPI_CMD_FLUSH_RX);
majik 0:964eb6a2ef00 926
majik 0:964eb6a2ef00 927 int rxPayloadWidth = spi_.write(_NRF24L01P_SPI_CMD_NOP);
majik 0:964eb6a2ef00 928
majik 0:964eb6a2ef00 929 nCS_ = 1;
majik 0:964eb6a2ef00 930
majik 0:964eb6a2ef00 931 //
majik 0:964eb6a2ef00 932 // At this point, we should retry the reception,
majik 0:964eb6a2ef00 933 // but for now we'll just fall through...
majik 0:964eb6a2ef00 934 //
majik 0:964eb6a2ef00 935
majik 0:964eb6a2ef00 936 } else {
majik 0:964eb6a2ef00 937
majik 0:964eb6a2ef00 938 if ( rxPayloadWidth < count ) count = rxPayloadWidth;
majik 0:964eb6a2ef00 939
majik 0:964eb6a2ef00 940 nCS_ = 0;
majik 0:964eb6a2ef00 941
majik 0:964eb6a2ef00 942 int status = spi_.write(_NRF24L01P_SPI_CMD_RD_RX_PAYLOAD);
majik 0:964eb6a2ef00 943
majik 0:964eb6a2ef00 944 for ( int i = 0; i < count; i++ ) {
majik 0:964eb6a2ef00 945
majik 0:964eb6a2ef00 946 *data++ = spi_.write(_NRF24L01P_SPI_CMD_NOP);
majik 0:964eb6a2ef00 947
majik 0:964eb6a2ef00 948 }
majik 0:964eb6a2ef00 949
majik 0:964eb6a2ef00 950 nCS_ = 1;
majik 0:964eb6a2ef00 951
majik 0:964eb6a2ef00 952 // Clear the Status bit
majik 0:964eb6a2ef00 953 setRegister(_NRF24L01P_REG_STATUS, _NRF24L01P_STATUS_RX_DR);
majik 0:964eb6a2ef00 954
majik 0:964eb6a2ef00 955 return count;
majik 0:964eb6a2ef00 956
majik 0:964eb6a2ef00 957 }
majik 0:964eb6a2ef00 958
majik 0:964eb6a2ef00 959 } else {
majik 0:964eb6a2ef00 960
majik 0:964eb6a2ef00 961 //
majik 0:964eb6a2ef00 962 // What should we do if there is no 'readable' data?
majik 0:964eb6a2ef00 963 // We could wait for data to arrive, but for now, we'll
majik 0:964eb6a2ef00 964 // just return with no data.
majik 0:964eb6a2ef00 965 //
majik 0:964eb6a2ef00 966 return 0;
majik 0:964eb6a2ef00 967
majik 0:964eb6a2ef00 968 }
majik 0:964eb6a2ef00 969
majik 0:964eb6a2ef00 970 //
majik 0:964eb6a2ef00 971 // We get here because an error condition occured;
majik 0:964eb6a2ef00 972 // We could wait for data to arrive, but for now, we'll
majik 0:964eb6a2ef00 973 // just return with no data.
majik 0:964eb6a2ef00 974 //
majik 0:964eb6a2ef00 975 return -1;
majik 0:964eb6a2ef00 976
majik 0:964eb6a2ef00 977 }
majik 0:964eb6a2ef00 978
majik 0:964eb6a2ef00 979 void nRF24L01P::setRegister(int regAddress, int regData) {
majik 0:964eb6a2ef00 980
majik 0:964eb6a2ef00 981 //
majik 0:964eb6a2ef00 982 // Save the CE state
majik 0:964eb6a2ef00 983 //
majik 0:964eb6a2ef00 984 int originalCe = ce_;
majik 0:964eb6a2ef00 985 disable();
majik 0:964eb6a2ef00 986
majik 0:964eb6a2ef00 987 int cn = (_NRF24L01P_SPI_CMD_WR_REG | (regAddress & _NRF24L01P_REG_ADDRESS_MASK));
majik 0:964eb6a2ef00 988
majik 0:964eb6a2ef00 989 nCS_ = 0;
majik 0:964eb6a2ef00 990
majik 0:964eb6a2ef00 991 int status = spi_.write(cn);
majik 0:964eb6a2ef00 992
majik 0:964eb6a2ef00 993 spi_.write(regData & 0xFF);
majik 0:964eb6a2ef00 994
majik 0:964eb6a2ef00 995 nCS_ = 1;
majik 0:964eb6a2ef00 996
majik 0:964eb6a2ef00 997 ce_ = originalCe;
majik 0:964eb6a2ef00 998 wait_us( _NRF24L01P_TIMING_Tpece2csn_us );
majik 0:964eb6a2ef00 999
majik 0:964eb6a2ef00 1000 }
majik 0:964eb6a2ef00 1001
majik 0:964eb6a2ef00 1002
majik 0:964eb6a2ef00 1003 int nRF24L01P::getRegister(int regAddress) {
majik 0:964eb6a2ef00 1004
majik 0:964eb6a2ef00 1005 int cn = (_NRF24L01P_SPI_CMD_RD_REG | (regAddress & _NRF24L01P_REG_ADDRESS_MASK));
majik 0:964eb6a2ef00 1006
majik 0:964eb6a2ef00 1007 nCS_ = 0;
majik 0:964eb6a2ef00 1008
majik 0:964eb6a2ef00 1009 int status = spi_.write(cn);
majik 0:964eb6a2ef00 1010
majik 0:964eb6a2ef00 1011 int dn = spi_.write(_NRF24L01P_SPI_CMD_NOP);
majik 0:964eb6a2ef00 1012
majik 0:964eb6a2ef00 1013 nCS_ = 1;
majik 0:964eb6a2ef00 1014
majik 0:964eb6a2ef00 1015 return dn;
majik 0:964eb6a2ef00 1016
majik 0:964eb6a2ef00 1017 }
majik 0:964eb6a2ef00 1018
majik 0:964eb6a2ef00 1019 int nRF24L01P::getStatusRegister(void) {
majik 0:964eb6a2ef00 1020
majik 0:964eb6a2ef00 1021 nCS_ = 0;
majik 0:964eb6a2ef00 1022
majik 0:964eb6a2ef00 1023 int status = spi_.write(_NRF24L01P_SPI_CMD_NOP);
majik 0:964eb6a2ef00 1024
majik 0:964eb6a2ef00 1025 nCS_ = 1;
majik 0:964eb6a2ef00 1026
majik 0:964eb6a2ef00 1027 return status;
majik 0:964eb6a2ef00 1028
majik 0:964eb6a2ef00 1029 }