Lorenzo Maiorfi
SX1276Lib updated in order to be RTOS aware
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sx1276.cpp
00001 /* 00002 / _____) _ | | 00003 ( (____ _____ ____ _| |_ _____ ____| |__ 00004 \____ \| ___ | (_ _) ___ |/ ___) _ \ 00005 _____) ) ____| | | || |_| ____( (___| | | | 00006 (______/|_____)_|_|_| \__)_____)\____)_| |_| 00007 (C) 2014 Semtech 00008 00009 Description: Actual implementation of a SX1276 radio, inherits Radio 00010 00011 License: Revised BSD License, see LICENSE.TXT file include in the project 00012 00013 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin 00014 */ 00015 #include "sx1276.h" 00016 00017 const FskBandwidth_t SX1276::FskBandwidths[] = 00018 { 00019 { 2600 , 0x17 }, 00020 { 3100 , 0x0F }, 00021 { 3900 , 0x07 }, 00022 { 5200 , 0x16 }, 00023 { 6300 , 0x0E }, 00024 { 7800 , 0x06 }, 00025 { 10400 , 0x15 }, 00026 { 12500 , 0x0D }, 00027 { 15600 , 0x05 }, 00028 { 20800 , 0x14 }, 00029 { 25000 , 0x0C }, 00030 { 31300 , 0x04 }, 00031 { 41700 , 0x13 }, 00032 { 50000 , 0x0B }, 00033 { 62500 , 0x03 }, 00034 { 83333 , 0x12 }, 00035 { 100000, 0x0A }, 00036 { 125000, 0x02 }, 00037 { 166700, 0x11 }, 00038 { 200000, 0x09 }, 00039 { 250000, 0x01 }, 00040 { 300000, 0x00 }, // Invalid Bandwidth 00041 }; 00042 00043 00044 SX1276::SX1276( RadioEvents_t *events, 00045 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset, 00046 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5 ) 00047 : Radio ( events ), 00048 spi( mosi, miso, sclk ), 00049 nss( nss ), 00050 reset( reset ), 00051 dio0( dio0 ), dio1( dio1 ), dio2( dio2 ), dio3( dio3 ), dio4( dio4 ), dio5( dio5 ), 00052 isRadioActive( false ) 00053 { 00054 wait_ms( 10 ); 00055 this->rxtxBuffer = new uint8_t[RX_BUFFER_SIZE]; 00056 00057 this->RadioEvents = events; 00058 00059 this->dioIrq = new DioIrqHandler[6]; 00060 00061 this->dioIrq [0] = &SX1276::enqueueOnDio0Irq; /*&SX1276::OnDio0Irq;*/ 00062 this->dioIrq [1] = &SX1276::enqueueOnDio1Irq; /*&SX1276::OnDio1Irq;*/ 00063 this->dioIrq [2] = &SX1276::enqueueOnDio2Irq; /*&SX1276::OnDio2Irq;*/ 00064 this->dioIrq [3] = &SX1276::enqueueOnDio3Irq; /*&SX1276::OnDio3Irq;*/ 00065 this->dioIrq [4] = &SX1276::enqueueOnDio4Irq; /*&SX1276::OnDio4Irq;*/ 00066 this->dioIrq [5] = &SX1276::enqueueOnDio5Irq; /*NULL;*/ 00067 00068 this->settings.State = RF_IDLE; 00069 } 00070 00071 SX1276::~SX1276( ) 00072 { 00073 delete this->rxtxBuffer; 00074 delete this->dioIrq ; 00075 } 00076 00077 void SX1276::Init( RadioEvents_t *events ) 00078 { 00079 this->RadioEvents = events; 00080 00081 // <RTOS> 00082 //_thread_events_queue->start(callback(_eq_events, &EventQueue::dispatch_forever)); 00083 // </RTOS> 00084 } 00085 00086 RadioState SX1276::GetStatus ( void ) 00087 { 00088 return this->settings.State; 00089 } 00090 00091 void SX1276::SetChannel( uint32_t freq ) 00092 { 00093 this->settings.Channel = freq; 00094 freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP ); 00095 Write( REG_FRFMSB, ( uint8_t )( ( freq >> 16 ) & 0xFF ) ); 00096 Write( REG_FRFMID, ( uint8_t )( ( freq >> 8 ) & 0xFF ) ); 00097 Write( REG_FRFLSB, ( uint8_t )( freq & 0xFF ) ); 00098 } 00099 00100 bool SX1276::IsChannelFree( RadioModems_t modem, uint32_t freq, int16_t rssiThresh ) 00101 { 00102 int16_t rssi = 0; 00103 00104 SetModem( modem ); 00105 00106 SetChannel( freq ); 00107 00108 SetOpMode( RF_OPMODE_RECEIVER ); 00109 00110 wait_ms( 1 ); 00111 00112 rssi = GetRssi( modem ); 00113 00114 Sleep( ); 00115 00116 if( rssi > rssiThresh ) 00117 { 00118 return false; 00119 } 00120 return true; 00121 } 00122 00123 uint32_t SX1276::Random( void ) 00124 { 00125 uint8_t i; 00126 uint32_t rnd = 0; 00127 00128 /* 00129 * Radio setup for random number generation 00130 */ 00131 // Set LoRa modem ON 00132 SetModem( MODEM_LORA ); 00133 00134 // Disable LoRa modem interrupts 00135 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT | 00136 RFLR_IRQFLAGS_RXDONE | 00137 RFLR_IRQFLAGS_PAYLOADCRCERROR | 00138 RFLR_IRQFLAGS_VALIDHEADER | 00139 RFLR_IRQFLAGS_TXDONE | 00140 RFLR_IRQFLAGS_CADDONE | 00141 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | 00142 RFLR_IRQFLAGS_CADDETECTED ); 00143 00144 // Set radio in continuous reception 00145 SetOpMode( RF_OPMODE_RECEIVER ); 00146 00147 for( i = 0; i < 32; i++ ) 00148 { 00149 wait_ms( 1 ); 00150 // Unfiltered RSSI value reading. Only takes the LSB value 00151 rnd |= ( ( uint32_t )Read( REG_LR_RSSIWIDEBAND ) & 0x01 ) << i; 00152 } 00153 00154 Sleep( ); 00155 00156 return rnd; 00157 } 00158 00159 /*! 00160 * Performs the Rx chain calibration for LF and HF bands 00161 * \remark Must be called just after the reset so all registers are at their 00162 * default values 00163 */ 00164 void SX1276::RxChainCalibration ( void ) 00165 { 00166 uint8_t regPaConfigInitVal; 00167 uint32_t initialFreq; 00168 00169 // Save context 00170 regPaConfigInitVal = this->Read( REG_PACONFIG ); 00171 initialFreq = ( double )( ( ( uint32_t )this->Read( REG_FRFMSB ) << 16 ) | 00172 ( ( uint32_t )this->Read( REG_FRFMID ) << 8 ) | 00173 ( ( uint32_t )this->Read( REG_FRFLSB ) ) ) * ( double )FREQ_STEP; 00174 00175 // Cut the PA just in case, RFO output, power = -1 dBm 00176 this->Write( REG_PACONFIG, 0x00 ); 00177 00178 // Launch Rx chain calibration for LF band 00179 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START ); 00180 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING ) 00181 { 00182 } 00183 00184 // Sets a Frequency in HF band 00185 SetChannel( 868000000 ); 00186 00187 // Launch Rx chain calibration for HF band 00188 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START ); 00189 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING ) 00190 { 00191 } 00192 00193 // Restore context 00194 this->Write( REG_PACONFIG, regPaConfigInitVal ); 00195 SetChannel( initialFreq ); 00196 } 00197 00198 /*! 00199 * Returns the known FSK bandwidth registers value 00200 * 00201 * \param [IN] bandwidth Bandwidth value in Hz 00202 * \retval regValue Bandwidth register value. 00203 */ 00204 uint8_t SX1276::GetFskBandwidthRegValue ( uint32_t bandwidth ) 00205 { 00206 uint8_t i; 00207 00208 for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ) - 1; i++ ) 00209 { 00210 if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandwidth ) ) 00211 { 00212 return FskBandwidths[i].RegValue; 00213 } 00214 } 00215 // ERROR: Value not found 00216 while( 1 ); 00217 } 00218 00219 void SX1276::SetRxConfig( RadioModems_t modem, uint32_t bandwidth, 00220 uint32_t datarate, uint8_t coderate, 00221 uint32_t bandwidthAfc, uint16_t preambleLen, 00222 uint16_t symbTimeout, bool fixLen, 00223 uint8_t payloadLen, 00224 bool crcOn, bool freqHopOn, uint8_t hopPeriod, 00225 bool iqInverted, bool rxContinuous ) 00226 { 00227 SetModem( modem ); 00228 00229 switch( modem ) 00230 { 00231 case MODEM_FSK: 00232 { 00233 this->settings.Fsk.Bandwidth = bandwidth; 00234 this->settings.Fsk.Datarate = datarate; 00235 this->settings.Fsk.BandwidthAfc = bandwidthAfc; 00236 this->settings.Fsk.FixLen = fixLen; 00237 this->settings.Fsk.PayloadLen = payloadLen; 00238 this->settings.Fsk.CrcOn = crcOn; 00239 this->settings.Fsk.IqInverted = iqInverted; 00240 this->settings.Fsk.RxContinuous = rxContinuous; 00241 this->settings.Fsk.PreambleLen = preambleLen; 00242 this->settings.Fsk.RxSingleTimeout = symbTimeout * ( ( 1.0 / ( double )datarate ) * 8.0 ) * 1e3; 00243 00244 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate ); 00245 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) ); 00246 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) ); 00247 00248 Write( REG_RXBW, GetFskBandwidthRegValue ( bandwidth ) ); 00249 Write( REG_AFCBW, GetFskBandwidthRegValue ( bandwidthAfc ) ); 00250 00251 Write( REG_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) ); 00252 Write( REG_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) ); 00253 00254 if( fixLen == 1 ) 00255 { 00256 Write( REG_PAYLOADLENGTH, payloadLen ); 00257 } 00258 else 00259 { 00260 Write( REG_PAYLOADLENGTH, 0xFF ); // Set payload length to the maximum 00261 } 00262 00263 Write( REG_PACKETCONFIG1, 00264 ( Read( REG_PACKETCONFIG1 ) & 00265 RF_PACKETCONFIG1_CRC_MASK & 00266 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) | 00267 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) | 00268 ( crcOn << 4 ) ); 00269 Write( REG_PACKETCONFIG2, ( Read( REG_PACKETCONFIG2 ) | RF_PACKETCONFIG2_DATAMODE_PACKET ) ); 00270 } 00271 break; 00272 case MODEM_LORA: 00273 { 00274 if( bandwidth > 2 ) 00275 { 00276 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported 00277 while( 1 ); 00278 } 00279 bandwidth += 7; 00280 this->settings.LoRa.Bandwidth = bandwidth; 00281 this->settings.LoRa.Datarate = datarate; 00282 this->settings.LoRa.Coderate = coderate; 00283 this->settings.LoRa.PreambleLen = preambleLen; 00284 this->settings.LoRa.FixLen = fixLen; 00285 this->settings.LoRa.PayloadLen = payloadLen; 00286 this->settings.LoRa.CrcOn = crcOn; 00287 this->settings.LoRa.FreqHopOn = freqHopOn; 00288 this->settings.LoRa.HopPeriod = hopPeriod; 00289 this->settings.LoRa.IqInverted = iqInverted; 00290 this->settings.LoRa.RxContinuous = rxContinuous; 00291 00292 if( datarate > 12 ) 00293 { 00294 datarate = 12; 00295 } 00296 else if( datarate < 6 ) 00297 { 00298 datarate = 6; 00299 } 00300 00301 if( ( ( bandwidth == 7 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) || 00302 ( ( bandwidth == 8 ) && ( datarate == 12 ) ) ) 00303 { 00304 this->settings.LoRa.LowDatarateOptimize = 0x01; 00305 } 00306 else 00307 { 00308 this->settings.LoRa.LowDatarateOptimize = 0x00; 00309 } 00310 00311 Write( REG_LR_MODEMCONFIG1, 00312 ( Read( REG_LR_MODEMCONFIG1 ) & 00313 RFLR_MODEMCONFIG1_BW_MASK & 00314 RFLR_MODEMCONFIG1_CODINGRATE_MASK & 00315 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) | 00316 ( bandwidth << 4 ) | ( coderate << 1 ) | 00317 fixLen ); 00318 00319 Write( REG_LR_MODEMCONFIG2, 00320 ( Read( REG_LR_MODEMCONFIG2 ) & 00321 RFLR_MODEMCONFIG2_SF_MASK & 00322 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK & 00323 RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) | 00324 ( datarate << 4 ) | ( crcOn << 2 ) | 00325 ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) ); 00326 00327 Write( REG_LR_MODEMCONFIG3, 00328 ( Read( REG_LR_MODEMCONFIG3 ) & 00329 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) | 00330 ( this->settings.LoRa.LowDatarateOptimize << 3 ) ); 00331 00332 Write( REG_LR_SYMBTIMEOUTLSB, ( uint8_t )( symbTimeout & 0xFF ) ); 00333 00334 Write( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) ); 00335 Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) ); 00336 00337 if( fixLen == 1 ) 00338 { 00339 Write( REG_LR_PAYLOADLENGTH, payloadLen ); 00340 } 00341 00342 if( this->settings.LoRa.FreqHopOn == true ) 00343 { 00344 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON ); 00345 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod ); 00346 } 00347 00348 if( ( bandwidth == 9 ) && ( this->settings.Channel > RF_MID_BAND_THRESH ) ) 00349 { 00350 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth 00351 Write( REG_LR_TEST36, 0x02 ); 00352 Write( REG_LR_TEST3A, 0x64 ); 00353 } 00354 else if( bandwidth == 9 ) 00355 { 00356 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth 00357 Write( REG_LR_TEST36, 0x02 ); 00358 Write( REG_LR_TEST3A, 0x7F ); 00359 } 00360 else 00361 { 00362 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth 00363 Write( REG_LR_TEST36, 0x03 ); 00364 } 00365 00366 if( datarate == 6 ) 00367 { 00368 Write( REG_LR_DETECTOPTIMIZE, 00369 ( Read( REG_LR_DETECTOPTIMIZE ) & 00370 RFLR_DETECTIONOPTIMIZE_MASK ) | 00371 RFLR_DETECTIONOPTIMIZE_SF6 ); 00372 Write( REG_LR_DETECTIONTHRESHOLD, 00373 RFLR_DETECTIONTHRESH_SF6 ); 00374 } 00375 else 00376 { 00377 Write( REG_LR_DETECTOPTIMIZE, 00378 ( Read( REG_LR_DETECTOPTIMIZE ) & 00379 RFLR_DETECTIONOPTIMIZE_MASK ) | 00380 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 ); 00381 Write( REG_LR_DETECTIONTHRESHOLD, 00382 RFLR_DETECTIONTHRESH_SF7_TO_SF12 ); 00383 } 00384 } 00385 break; 00386 } 00387 } 00388 00389 void SX1276::SetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev, 00390 uint32_t bandwidth, uint32_t datarate, 00391 uint8_t coderate, uint16_t preambleLen, 00392 bool fixLen, bool crcOn, bool freqHopOn, 00393 uint8_t hopPeriod, bool iqInverted, uint32_t timeout ) 00394 { 00395 SetModem( modem ); 00396 00397 SetRfTxPower( power ); 00398 00399 switch( modem ) 00400 { 00401 case MODEM_FSK: 00402 { 00403 this->settings.Fsk.Power = power; 00404 this->settings.Fsk.Fdev = fdev; 00405 this->settings.Fsk.Bandwidth = bandwidth; 00406 this->settings.Fsk.Datarate = datarate; 00407 this->settings.Fsk.PreambleLen = preambleLen; 00408 this->settings.Fsk.FixLen = fixLen; 00409 this->settings.Fsk.CrcOn = crcOn; 00410 this->settings.Fsk.IqInverted = iqInverted; 00411 this->settings.Fsk.TxTimeout = timeout; 00412 00413 fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP ); 00414 Write( REG_FDEVMSB, ( uint8_t )( fdev >> 8 ) ); 00415 Write( REG_FDEVLSB, ( uint8_t )( fdev & 0xFF ) ); 00416 00417 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate ); 00418 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) ); 00419 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) ); 00420 00421 Write( REG_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF ); 00422 Write( REG_PREAMBLELSB, preambleLen & 0xFF ); 00423 00424 Write( REG_PACKETCONFIG1, 00425 ( Read( REG_PACKETCONFIG1 ) & 00426 RF_PACKETCONFIG1_CRC_MASK & 00427 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) | 00428 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) | 00429 ( crcOn << 4 ) ); 00430 Write( REG_PACKETCONFIG2, ( Read( REG_PACKETCONFIG2 ) | RF_PACKETCONFIG2_DATAMODE_PACKET ) ); 00431 } 00432 break; 00433 case MODEM_LORA: 00434 { 00435 this->settings.LoRa.Power = power; 00436 if( bandwidth > 2 ) 00437 { 00438 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported 00439 while( 1 ); 00440 } 00441 bandwidth += 7; 00442 this->settings.LoRa.Bandwidth = bandwidth; 00443 this->settings.LoRa.Datarate = datarate; 00444 this->settings.LoRa.Coderate = coderate; 00445 this->settings.LoRa.PreambleLen = preambleLen; 00446 this->settings.LoRa.FixLen = fixLen; 00447 this->settings.LoRa.FreqHopOn = freqHopOn; 00448 this->settings.LoRa.HopPeriod = hopPeriod; 00449 this->settings.LoRa.CrcOn = crcOn; 00450 this->settings.LoRa.IqInverted = iqInverted; 00451 this->settings.LoRa.TxTimeout = timeout; 00452 00453 if( datarate > 12 ) 00454 { 00455 datarate = 12; 00456 } 00457 else if( datarate < 6 ) 00458 { 00459 datarate = 6; 00460 } 00461 if( ( ( bandwidth == 7 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) || 00462 ( ( bandwidth == 8 ) && ( datarate == 12 ) ) ) 00463 { 00464 this->settings.LoRa.LowDatarateOptimize = 0x01; 00465 } 00466 else 00467 { 00468 this->settings.LoRa.LowDatarateOptimize = 0x00; 00469 } 00470 00471 if( this->settings.LoRa.FreqHopOn == true ) 00472 { 00473 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON ); 00474 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod ); 00475 } 00476 00477 Write( REG_LR_MODEMCONFIG1, 00478 ( Read( REG_LR_MODEMCONFIG1 ) & 00479 RFLR_MODEMCONFIG1_BW_MASK & 00480 RFLR_MODEMCONFIG1_CODINGRATE_MASK & 00481 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) | 00482 ( bandwidth << 4 ) | ( coderate << 1 ) | 00483 fixLen ); 00484 00485 Write( REG_LR_MODEMCONFIG2, 00486 ( Read( REG_LR_MODEMCONFIG2 ) & 00487 RFLR_MODEMCONFIG2_SF_MASK & 00488 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK ) | 00489 ( datarate << 4 ) | ( crcOn << 2 ) ); 00490 00491 Write( REG_LR_MODEMCONFIG3, 00492 ( Read( REG_LR_MODEMCONFIG3 ) & 00493 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) | 00494 ( this->settings.LoRa.LowDatarateOptimize << 3 ) ); 00495 00496 Write( REG_LR_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF ); 00497 Write( REG_LR_PREAMBLELSB, preambleLen & 0xFF ); 00498 00499 if( datarate == 6 ) 00500 { 00501 Write( REG_LR_DETECTOPTIMIZE, 00502 ( Read( REG_LR_DETECTOPTIMIZE ) & 00503 RFLR_DETECTIONOPTIMIZE_MASK ) | 00504 RFLR_DETECTIONOPTIMIZE_SF6 ); 00505 Write( REG_LR_DETECTIONTHRESHOLD, 00506 RFLR_DETECTIONTHRESH_SF6 ); 00507 } 00508 else 00509 { 00510 Write( REG_LR_DETECTOPTIMIZE, 00511 ( Read( REG_LR_DETECTOPTIMIZE ) & 00512 RFLR_DETECTIONOPTIMIZE_MASK ) | 00513 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 ); 00514 Write( REG_LR_DETECTIONTHRESHOLD, 00515 RFLR_DETECTIONTHRESH_SF7_TO_SF12 ); 00516 } 00517 } 00518 break; 00519 } 00520 } 00521 00522 uint32_t SX1276::TimeOnAir( RadioModems_t modem, uint8_t pktLen ) 00523 { 00524 uint32_t airTime = 0; 00525 00526 switch( modem ) 00527 { 00528 case MODEM_FSK: 00529 { 00530 airTime = rint( ( 8 * ( this->settings.Fsk.PreambleLen + 00531 ( ( Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + 1 ) + 00532 ( ( this->settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) + 00533 ( ( ( Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK ) != 0x00 ) ? 1.0 : 0 ) + 00534 pktLen + 00535 ( ( this->settings.Fsk.CrcOn == 0x01 ) ? 2.0 : 0 ) ) / 00536 this->settings.Fsk.Datarate ) * 1e3 ); 00537 } 00538 break; 00539 case MODEM_LORA: 00540 { 00541 double bw = 0.0; 00542 // REMARK: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported 00543 switch( this->settings.LoRa.Bandwidth ) 00544 { 00545 //case 0: // 7.8 kHz 00546 // bw = 78e2; 00547 // break; 00548 //case 1: // 10.4 kHz 00549 // bw = 104e2; 00550 // break; 00551 //case 2: // 15.6 kHz 00552 // bw = 156e2; 00553 // break; 00554 //case 3: // 20.8 kHz 00555 // bw = 208e2; 00556 // break; 00557 //case 4: // 31.2 kHz 00558 // bw = 312e2; 00559 // break; 00560 //case 5: // 41.4 kHz 00561 // bw = 414e2; 00562 // break; 00563 //case 6: // 62.5 kHz 00564 // bw = 625e2; 00565 // break; 00566 case 7: // 125 kHz 00567 bw = 125e3; 00568 break; 00569 case 8: // 250 kHz 00570 bw = 250e3; 00571 break; 00572 case 9: // 500 kHz 00573 bw = 500e3; 00574 break; 00575 } 00576 00577 // Symbol rate : time for one symbol (secs) 00578 double rs = bw / ( 1 << this->settings.LoRa.Datarate ); 00579 double ts = 1 / rs; 00580 // time of preamble 00581 double tPreamble = ( this->settings.LoRa.PreambleLen + 4.25 ) * ts; 00582 // Symbol length of payload and time 00583 double tmp = ceil( ( 8 * pktLen - 4 * this->settings.LoRa.Datarate + 00584 28 + 16 * this->settings.LoRa.CrcOn - 00585 ( this->settings.LoRa.FixLen ? 20 : 0 ) ) / 00586 ( double )( 4 * ( this->settings.LoRa.Datarate - 00587 ( ( this->settings.LoRa.LowDatarateOptimize > 0 ) ? 2 : 0 ) ) ) ) * 00588 ( this->settings.LoRa.Coderate + 4 ); 00589 double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 ); 00590 double tPayload = nPayload * ts; 00591 // Time on air 00592 double tOnAir = tPreamble + tPayload; 00593 // return ms secs 00594 airTime = floor( tOnAir * 1e3 + 0.999 ); 00595 } 00596 break; 00597 } 00598 return airTime; 00599 } 00600 00601 void SX1276::Send( uint8_t *buffer, uint8_t size ) 00602 { 00603 uint32_t txTimeout = 0; 00604 00605 switch( this->settings.Modem ) 00606 { 00607 case MODEM_FSK: 00608 { 00609 this->settings.FskPacketHandler.NbBytes = 0; 00610 this->settings.FskPacketHandler.Size = size; 00611 00612 if( this->settings.Fsk.FixLen == false ) 00613 { 00614 WriteFifo( ( uint8_t* )&size, 1 ); 00615 } 00616 else 00617 { 00618 Write( REG_PAYLOADLENGTH, size ); 00619 } 00620 00621 if( ( size > 0 ) && ( size <= 64 ) ) 00622 { 00623 this->settings.FskPacketHandler.ChunkSize = size; 00624 } 00625 else 00626 { 00627 memcpy( rxtxBuffer, buffer, size ); 00628 this->settings.FskPacketHandler.ChunkSize = 32; 00629 } 00630 00631 // Write payload buffer 00632 WriteFifo( buffer, this->settings.FskPacketHandler.ChunkSize ); 00633 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize; 00634 txTimeout = this->settings.Fsk.TxTimeout; 00635 } 00636 break; 00637 case MODEM_LORA: 00638 { 00639 if( this->settings.LoRa.IqInverted == true ) 00640 { 00641 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON ) ); 00642 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON ); 00643 } 00644 else 00645 { 00646 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) ); 00647 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF ); 00648 } 00649 00650 this->settings.LoRaPacketHandler.Size = size; 00651 00652 // Initializes the payload size 00653 Write( REG_LR_PAYLOADLENGTH, size ); 00654 00655 // Full buffer used for Tx 00656 Write( REG_LR_FIFOTXBASEADDR, 0 ); 00657 Write( REG_LR_FIFOADDRPTR, 0 ); 00658 00659 // FIFO operations can not take place in Sleep mode 00660 if( ( Read( REG_OPMODE ) & ~RF_OPMODE_MASK ) == RF_OPMODE_SLEEP ) 00661 { 00662 Standby( ); 00663 wait_ms( 1 ); 00664 } 00665 // Write payload buffer 00666 WriteFifo( buffer, size ); 00667 txTimeout = this->settings.LoRa.TxTimeout; 00668 } 00669 break; 00670 } 00671 00672 Tx( txTimeout ); 00673 } 00674 00675 void SX1276::Sleep( void ) 00676 { 00677 txTimeoutTimer .detach( ); 00678 rxTimeoutTimer.detach( ); 00679 00680 SetOpMode( RF_OPMODE_SLEEP ); 00681 this->settings.State = RF_IDLE; 00682 } 00683 00684 void SX1276::Standby( void ) 00685 { 00686 txTimeoutTimer .detach( ); 00687 rxTimeoutTimer.detach( ); 00688 00689 SetOpMode( RF_OPMODE_STANDBY ); 00690 this->settings.State = RF_IDLE; 00691 } 00692 00693 void SX1276::Rx( uint32_t timeout ) 00694 { 00695 bool rxContinuous = false; 00696 00697 switch( this->settings.Modem ) 00698 { 00699 case MODEM_FSK: 00700 { 00701 rxContinuous = this->settings.Fsk.RxContinuous; 00702 00703 // DIO0=PayloadReady 00704 // DIO1=FifoLevel 00705 // DIO2=SyncAddr 00706 // DIO3=FifoEmpty 00707 // DIO4=Preamble 00708 // DIO5=ModeReady 00709 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK & 00710 RF_DIOMAPPING1_DIO1_MASK & 00711 RF_DIOMAPPING1_DIO2_MASK ) | 00712 RF_DIOMAPPING1_DIO0_00 | 00713 RF_DIOMAPPING1_DIO1_00 | 00714 RF_DIOMAPPING1_DIO2_11 ); 00715 00716 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK & 00717 RF_DIOMAPPING2_MAP_MASK ) | 00718 RF_DIOMAPPING2_DIO4_11 | 00719 RF_DIOMAPPING2_MAP_PREAMBLEDETECT ); 00720 00721 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F; 00722 00723 Write( REG_RXCONFIG, RF_RXCONFIG_AFCAUTO_ON | RF_RXCONFIG_AGCAUTO_ON | RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT ); 00724 00725 this->settings.FskPacketHandler.PreambleDetected = false; 00726 this->settings.FskPacketHandler.SyncWordDetected = false; 00727 this->settings.FskPacketHandler.NbBytes = 0; 00728 this->settings.FskPacketHandler.Size = 0; 00729 } 00730 break; 00731 case MODEM_LORA: 00732 { 00733 if( this->settings.LoRa.IqInverted == true ) 00734 { 00735 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF ) ); 00736 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON ); 00737 } 00738 else 00739 { 00740 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) ); 00741 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF ); 00742 } 00743 00744 // ERRATA 2.3 - Receiver Spurious Reception of a LoRa Signal 00745 if( this->settings.LoRa.Bandwidth < 9 ) 00746 { 00747 Write( REG_LR_DETECTOPTIMIZE, Read( REG_LR_DETECTOPTIMIZE ) & 0x7F ); 00748 Write( REG_LR_TEST30, 0x00 ); 00749 switch( this->settings.LoRa.Bandwidth ) 00750 { 00751 case 0: // 7.8 kHz 00752 Write( REG_LR_TEST2F, 0x48 ); 00753 SetChannel(this->settings.Channel + 7.81e3 ); 00754 break; 00755 case 1: // 10.4 kHz 00756 Write( REG_LR_TEST2F, 0x44 ); 00757 SetChannel(this->settings.Channel + 10.42e3 ); 00758 break; 00759 case 2: // 15.6 kHz 00760 Write( REG_LR_TEST2F, 0x44 ); 00761 SetChannel(this->settings.Channel + 15.62e3 ); 00762 break; 00763 case 3: // 20.8 kHz 00764 Write( REG_LR_TEST2F, 0x44 ); 00765 SetChannel(this->settings.Channel + 20.83e3 ); 00766 break; 00767 case 4: // 31.2 kHz 00768 Write( REG_LR_TEST2F, 0x44 ); 00769 SetChannel(this->settings.Channel + 31.25e3 ); 00770 break; 00771 case 5: // 41.4 kHz 00772 Write( REG_LR_TEST2F, 0x44 ); 00773 SetChannel(this->settings.Channel + 41.67e3 ); 00774 break; 00775 case 6: // 62.5 kHz 00776 Write( REG_LR_TEST2F, 0x40 ); 00777 break; 00778 case 7: // 125 kHz 00779 Write( REG_LR_TEST2F, 0x40 ); 00780 break; 00781 case 8: // 250 kHz 00782 Write( REG_LR_TEST2F, 0x40 ); 00783 break; 00784 } 00785 } 00786 else 00787 { 00788 Write( REG_LR_DETECTOPTIMIZE, Read( REG_LR_DETECTOPTIMIZE ) | 0x80 ); 00789 } 00790 00791 rxContinuous = this->settings.LoRa.RxContinuous; 00792 00793 if( this->settings.LoRa.FreqHopOn == true ) 00794 { 00795 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT | 00796 //RFLR_IRQFLAGS_RXDONE | 00797 //RFLR_IRQFLAGS_PAYLOADCRCERROR | 00798 RFLR_IRQFLAGS_VALIDHEADER | 00799 RFLR_IRQFLAGS_TXDONE | 00800 RFLR_IRQFLAGS_CADDONE | 00801 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | 00802 RFLR_IRQFLAGS_CADDETECTED ); 00803 00804 // DIO0=RxDone, DIO2=FhssChangeChannel 00805 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO2_00 ); 00806 } 00807 else 00808 { 00809 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT | 00810 //RFLR_IRQFLAGS_RXDONE | 00811 //RFLR_IRQFLAGS_PAYLOADCRCERROR | 00812 RFLR_IRQFLAGS_VALIDHEADER | 00813 RFLR_IRQFLAGS_TXDONE | 00814 RFLR_IRQFLAGS_CADDONE | 00815 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | 00816 RFLR_IRQFLAGS_CADDETECTED ); 00817 00818 // DIO0=RxDone 00819 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 ); 00820 } 00821 Write( REG_LR_FIFORXBASEADDR, 0 ); 00822 Write( REG_LR_FIFOADDRPTR, 0 ); 00823 } 00824 break; 00825 } 00826 00827 memset( rxtxBuffer, 0, ( size_t )RX_BUFFER_SIZE ); 00828 00829 this->settings.State = RF_RX_RUNNING; 00830 if( timeout != 0 ) 00831 { 00832 rxTimeoutTimer.attach_us(mbed::callback( this, &SX1276::enqueueOnTimeoutIrq /*&SX1276::OnTimeoutIrq*/ ), timeout * 1e3 ); 00833 } 00834 00835 if( this->settings.Modem == MODEM_FSK ) 00836 { 00837 SetOpMode( RF_OPMODE_RECEIVER ); 00838 00839 if( rxContinuous == false ) 00840 { 00841 rxTimeoutSyncWord.attach_us( mbed::callback( this, &SX1276::enqueueOnTimeoutIrq /*&SX1276::OnTimeoutIrq*/ ), 00842 this->settings.Fsk.RxSingleTimeout * 1e3 ); 00843 } 00844 } 00845 else 00846 { 00847 if( rxContinuous == true ) 00848 { 00849 SetOpMode( RFLR_OPMODE_RECEIVER ); 00850 } 00851 else 00852 { 00853 SetOpMode( RFLR_OPMODE_RECEIVER_SINGLE ); 00854 } 00855 } 00856 } 00857 00858 void SX1276::Tx( uint32_t timeout ) 00859 { 00860 00861 switch( this->settings.Modem ) 00862 { 00863 case MODEM_FSK: 00864 { 00865 // DIO0=PacketSent 00866 // DIO1=FifoEmpty 00867 // DIO2=FifoFull 00868 // DIO3=FifoEmpty 00869 // DIO4=LowBat 00870 // DIO5=ModeReady 00871 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK & 00872 RF_DIOMAPPING1_DIO1_MASK & 00873 RF_DIOMAPPING1_DIO2_MASK ) | 00874 RF_DIOMAPPING1_DIO1_01 ); 00875 00876 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK & 00877 RF_DIOMAPPING2_MAP_MASK ) ); 00878 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F; 00879 } 00880 break; 00881 case MODEM_LORA: 00882 { 00883 if( this->settings.LoRa.FreqHopOn == true ) 00884 { 00885 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT | 00886 RFLR_IRQFLAGS_RXDONE | 00887 RFLR_IRQFLAGS_PAYLOADCRCERROR | 00888 RFLR_IRQFLAGS_VALIDHEADER | 00889 //RFLR_IRQFLAGS_TXDONE | 00890 RFLR_IRQFLAGS_CADDONE | 00891 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | 00892 RFLR_IRQFLAGS_CADDETECTED ); 00893 00894 // DIO0=TxDone, DIO2=FhssChangeChannel 00895 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_01 | RFLR_DIOMAPPING1_DIO2_00 ); 00896 } 00897 else 00898 { 00899 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT | 00900 RFLR_IRQFLAGS_RXDONE | 00901 RFLR_IRQFLAGS_PAYLOADCRCERROR | 00902 RFLR_IRQFLAGS_VALIDHEADER | 00903 //RFLR_IRQFLAGS_TXDONE | 00904 RFLR_IRQFLAGS_CADDONE | 00905 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | 00906 RFLR_IRQFLAGS_CADDETECTED ); 00907 00908 // DIO0=TxDone 00909 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 ); 00910 } 00911 } 00912 break; 00913 } 00914 00915 this->settings.State = RF_TX_RUNNING; 00916 txTimeoutTimer .attach_us( mbed::callback( this, &SX1276::enqueueOnTimeoutIrq /*&SX1276::OnTimeoutIrq*/ ), timeout * 1e3 ); 00917 SetOpMode( RF_OPMODE_TRANSMITTER ); 00918 } 00919 00920 void SX1276::StartCad( void ) 00921 { 00922 switch( this->settings.Modem ) 00923 { 00924 case MODEM_FSK: 00925 { 00926 00927 } 00928 break; 00929 case MODEM_LORA: 00930 { 00931 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT | 00932 RFLR_IRQFLAGS_RXDONE | 00933 RFLR_IRQFLAGS_PAYLOADCRCERROR | 00934 RFLR_IRQFLAGS_VALIDHEADER | 00935 RFLR_IRQFLAGS_TXDONE | 00936 //RFLR_IRQFLAGS_CADDONE | 00937 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL // | 00938 //RFLR_IRQFLAGS_CADDETECTED 00939 ); 00940 00941 // DIO3=CADDone 00942 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO3_MASK ) | RFLR_DIOMAPPING1_DIO3_00 ); 00943 00944 this->settings.State = RF_CAD; 00945 SetOpMode( RFLR_OPMODE_CAD ); 00946 } 00947 break; 00948 default: 00949 break; 00950 } 00951 } 00952 00953 void SX1276::SetTxContinuousWave( uint32_t freq, int8_t power, uint16_t time ) 00954 { 00955 uint32_t timeout = ( uint32_t )( time * 1e6 ); 00956 00957 SetChannel( freq ); 00958 00959 SetTxConfig( MODEM_FSK, power, 0, 0, 4800, 0, 5, false, false, 0, 0, 0, timeout ); 00960 00961 Write( REG_PACKETCONFIG2, ( Read( REG_PACKETCONFIG2 ) & RF_PACKETCONFIG2_DATAMODE_MASK ) ); 00962 // Disable radio interrupts 00963 Write( REG_DIOMAPPING1, RF_DIOMAPPING1_DIO0_11 | RF_DIOMAPPING1_DIO1_11 ); 00964 Write( REG_DIOMAPPING2, RF_DIOMAPPING2_DIO4_10 | RF_DIOMAPPING2_DIO5_10 ); 00965 00966 this->settings.State = RF_TX_RUNNING; 00967 txTimeoutTimer .attach_us( mbed::callback( this, &SX1276::enqueueOnTimeoutIrq /*&SX1276::OnTimeoutIrq*/ ), timeout ); 00968 SetOpMode( RF_OPMODE_TRANSMITTER ); 00969 } 00970 00971 int16_t SX1276::GetRssi( RadioModems_t modem ) 00972 { 00973 int16_t rssi = 0; 00974 00975 switch( modem ) 00976 { 00977 case MODEM_FSK: 00978 rssi = -( Read( REG_RSSIVALUE ) >> 1 ); 00979 break; 00980 case MODEM_LORA: 00981 if( this->settings.Channel > RF_MID_BAND_THRESH ) 00982 { 00983 rssi = RSSI_OFFSET_HF + Read( REG_LR_RSSIVALUE ); 00984 } 00985 else 00986 { 00987 rssi = RSSI_OFFSET_LF + Read( REG_LR_RSSIVALUE ); 00988 } 00989 break; 00990 default: 00991 rssi = -1; 00992 break; 00993 } 00994 return rssi; 00995 } 00996 00997 void SX1276::SetOpMode( uint8_t opMode ) 00998 { 00999 if( opMode == RF_OPMODE_SLEEP ) 01000 { 01001 SetAntSwLowPower( true ); 01002 } 01003 else 01004 { 01005 SetAntSwLowPower( false ); 01006 SetAntSw( opMode ); 01007 } 01008 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RF_OPMODE_MASK ) | opMode ); 01009 } 01010 01011 void SX1276::SetModem( RadioModems_t modem ) 01012 { 01013 if( ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_ON ) != 0 ) 01014 { 01015 this->settings.Modem = MODEM_LORA; 01016 } 01017 else 01018 { 01019 this->settings.Modem = MODEM_FSK; 01020 } 01021 01022 if( this->settings.Modem == modem ) 01023 { 01024 return; 01025 } 01026 01027 this->settings.Modem = modem; 01028 switch( this->settings.Modem ) 01029 { 01030 default: 01031 case MODEM_FSK: 01032 Sleep( ); 01033 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF ); 01034 01035 Write( REG_DIOMAPPING1, 0x00 ); 01036 Write( REG_DIOMAPPING2, 0x30 ); // DIO5=ModeReady 01037 break; 01038 case MODEM_LORA: 01039 Sleep( ); 01040 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON ); 01041 01042 Write( REG_DIOMAPPING1, 0x00 ); 01043 Write( REG_DIOMAPPING2, 0x00 ); 01044 break; 01045 } 01046 } 01047 01048 void SX1276::SetMaxPayloadLength( RadioModems_t modem, uint8_t max ) 01049 { 01050 this->SetModem( modem ); 01051 01052 switch( modem ) 01053 { 01054 case MODEM_FSK: 01055 if( this->settings.Fsk.FixLen == false ) 01056 { 01057 this->Write( REG_PAYLOADLENGTH, max ); 01058 } 01059 break; 01060 case MODEM_LORA: 01061 this->Write( REG_LR_PAYLOADMAXLENGTH, max ); 01062 break; 01063 } 01064 } 01065 01066 void SX1276::SetPublicNetwork( bool enable ) 01067 { 01068 SetModem( MODEM_LORA ); 01069 this->settings.LoRa.PublicNetwork = enable; 01070 if( enable == true ) 01071 { 01072 // Change LoRa modem SyncWord 01073 Write( REG_LR_SYNCWORD, LORA_MAC_PUBLIC_SYNCWORD ); 01074 } 01075 else 01076 { 01077 // Change LoRa modem SyncWord 01078 Write( REG_LR_SYNCWORD, LORA_MAC_PRIVATE_SYNCWORD ); 01079 } 01080 } 01081 01082 void SX1276::OnTimeoutIrq( void ) 01083 { 01084 switch( this->settings.State ) 01085 { 01086 case RF_RX_RUNNING: 01087 if( this->settings.Modem == MODEM_FSK ) 01088 { 01089 this->settings.FskPacketHandler.PreambleDetected = false; 01090 this->settings.FskPacketHandler.SyncWordDetected = false; 01091 this->settings.FskPacketHandler.NbBytes = 0; 01092 this->settings.FskPacketHandler.Size = 0; 01093 01094 // Clear Irqs 01095 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI | 01096 RF_IRQFLAGS1_PREAMBLEDETECT | 01097 RF_IRQFLAGS1_SYNCADDRESSMATCH ); 01098 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN ); 01099 01100 if( this->settings.Fsk.RxContinuous == true ) 01101 { 01102 // Continuous mode restart Rx chain 01103 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK ); 01104 rxTimeoutSyncWord.attach_us( mbed::callback( this, &SX1276::enqueueOnTimeoutIrq /*&SX1276::OnTimeoutIrq*/ ), 01105 this->settings.Fsk.RxSingleTimeout * 1e3 ); 01106 } 01107 else 01108 { 01109 this->settings.State = RF_IDLE; 01110 rxTimeoutSyncWord.detach( ); 01111 } 01112 } 01113 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) ) 01114 { 01115 /*this->RadioEvents->RxTimeout( );*/ 01116 enqueueRadioEvent_RxTimeout(); 01117 } 01118 break; 01119 case RF_TX_RUNNING: 01120 // Tx timeout shouldn't happen. 01121 // But it has been observed that when it happens it is a result of a corrupted SPI transfer 01122 // it depends on the platform design. 01123 // 01124 // The workaround is to put the radio in a known state. Thus, we re-initialize it. 01125 01126 // BEGIN WORKAROUND 01127 01128 // Reset the radio 01129 Reset( ); 01130 01131 // Calibrate Rx chain 01132 RxChainCalibration ( ); 01133 01134 // Initialize radio default values 01135 SetOpMode( RF_OPMODE_SLEEP ); 01136 01137 RadioRegistersInit( ); 01138 01139 SetModem( MODEM_FSK ); 01140 01141 // Restore previous network type setting. 01142 SetPublicNetwork( this->settings.LoRa.PublicNetwork ); 01143 // END WORKAROUND 01144 01145 this->settings.State = RF_IDLE; 01146 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxTimeout != NULL ) ) 01147 { 01148 /*this->RadioEvents->TxTimeout( );*/ 01149 enqueueRadioEvent_TxTimeout(); 01150 } 01151 break; 01152 default: 01153 break; 01154 } 01155 } 01156 01157 void SX1276::OnDio0Irq( void ) 01158 { 01159 volatile uint8_t irqFlags = 0; 01160 01161 switch( this->settings.State ) 01162 { 01163 case RF_RX_RUNNING: 01164 //TimerStop( &RxTimeoutTimer ); 01165 // RxDone interrupt 01166 switch( this->settings.Modem ) 01167 { 01168 case MODEM_FSK: 01169 if( this->settings.Fsk.CrcOn == true ) 01170 { 01171 irqFlags = Read( REG_IRQFLAGS2 ); 01172 if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK ) 01173 { 01174 // Clear Irqs 01175 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI | 01176 RF_IRQFLAGS1_PREAMBLEDETECT | 01177 RF_IRQFLAGS1_SYNCADDRESSMATCH ); 01178 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN ); 01179 01180 rxTimeoutTimer.detach( ); 01181 01182 if( this->settings.Fsk.RxContinuous == false ) 01183 { 01184 rxTimeoutSyncWord.detach( ); 01185 this->settings.State = RF_IDLE; 01186 } 01187 else 01188 { 01189 // Continuous mode restart Rx chain 01190 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK ); 01191 rxTimeoutSyncWord.attach_us( mbed::callback( this, &SX1276::enqueueOnTimeoutIrq /*&SX1276::OnTimeoutIrq*/ ), 01192 this->settings.Fsk.RxSingleTimeout * 1e3 ); 01193 } 01194 01195 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) ) 01196 { 01197 /*this->RadioEvents->RxError( );*/ 01198 enqueueRadioEvent_RxError(); 01199 } 01200 this->settings.FskPacketHandler.PreambleDetected = false; 01201 this->settings.FskPacketHandler.SyncWordDetected = false; 01202 this->settings.FskPacketHandler.NbBytes = 0; 01203 this->settings.FskPacketHandler.Size = 0; 01204 break; 01205 } 01206 } 01207 01208 // Read received packet size 01209 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) ) 01210 { 01211 if( this->settings.Fsk.FixLen == false ) 01212 { 01213 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 ); 01214 } 01215 else 01216 { 01217 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH ); 01218 } 01219 ReadFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ); 01220 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ); 01221 } 01222 else 01223 { 01224 ReadFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ); 01225 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ); 01226 } 01227 01228 rxTimeoutTimer.detach( ); 01229 01230 if( this->settings.Fsk.RxContinuous == false ) 01231 { 01232 this->settings.State = RF_IDLE; 01233 rxTimeoutSyncWord.detach( ); 01234 } 01235 else 01236 { 01237 // Continuous mode restart Rx chain 01238 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK ); 01239 rxTimeoutSyncWord.attach_us( mbed::callback( this, &SX1276::enqueueOnTimeoutIrq /*&SX1276::OnTimeoutIrq*/ ), 01240 this->settings.Fsk.RxSingleTimeout * 1e3 ); 01241 } 01242 01243 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) ) 01244 { 01245 /*this->RadioEvents->RxDone( rxtxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0 );*/ 01246 enqueueRadioEvent_RxDone(rxtxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0); 01247 } 01248 this->settings.FskPacketHandler.PreambleDetected = false; 01249 this->settings.FskPacketHandler.SyncWordDetected = false; 01250 this->settings.FskPacketHandler.NbBytes = 0; 01251 this->settings.FskPacketHandler.Size = 0; 01252 break; 01253 case MODEM_LORA: 01254 { 01255 int8_t snr = 0; 01256 01257 // Clear Irq 01258 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE ); 01259 01260 irqFlags = Read( REG_LR_IRQFLAGS ); 01261 if( ( irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK ) == RFLR_IRQFLAGS_PAYLOADCRCERROR ) 01262 { 01263 // Clear Irq 01264 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR ); 01265 01266 if( this->settings.LoRa.RxContinuous == false ) 01267 { 01268 this->settings.State = RF_IDLE; 01269 } 01270 rxTimeoutTimer.detach( ); 01271 01272 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) ) 01273 { 01274 /*this->RadioEvents->RxError( );*/ 01275 enqueueRadioEvent_RxError(); 01276 } 01277 break; 01278 } 01279 01280 this->settings.LoRaPacketHandler.SnrValue = Read( REG_LR_PKTSNRVALUE ); 01281 if( this->settings.LoRaPacketHandler.SnrValue & 0x80 ) // The SNR sign bit is 1 01282 { 01283 // Invert and divide by 4 01284 snr = ( ( ~this->settings.LoRaPacketHandler.SnrValue + 1 ) & 0xFF ) >> 2; 01285 snr = -snr; 01286 } 01287 else 01288 { 01289 // Divide by 4 01290 snr = ( this->settings.LoRaPacketHandler.SnrValue & 0xFF ) >> 2; 01291 } 01292 01293 int16_t rssi = Read( REG_LR_PKTRSSIVALUE ); 01294 if( snr < 0 ) 01295 { 01296 if( this->settings.Channel > RF_MID_BAND_THRESH ) 01297 { 01298 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 ) + 01299 snr; 01300 } 01301 else 01302 { 01303 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 ) + 01304 snr; 01305 } 01306 } 01307 else 01308 { 01309 if( this->settings.Channel > RF_MID_BAND_THRESH ) 01310 { 01311 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 ); 01312 } 01313 else 01314 { 01315 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 ); 01316 } 01317 } 01318 01319 this->settings.LoRaPacketHandler.Size = Read( REG_LR_RXNBBYTES ); 01320 ReadFifo( rxtxBuffer, this->settings.LoRaPacketHandler.Size ); 01321 01322 if( this->settings.LoRa.RxContinuous == false ) 01323 { 01324 this->settings.State = RF_IDLE; 01325 } 01326 rxTimeoutTimer.detach( ); 01327 01328 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) ) 01329 { 01330 /*this->RadioEvents->RxDone( rxtxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue, this->settings.LoRaPacketHandler.SnrValue );*/ 01331 enqueueRadioEvent_RxDone(rxtxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue, this->settings.LoRaPacketHandler.SnrValue); 01332 } 01333 } 01334 break; 01335 default: 01336 break; 01337 } 01338 break; 01339 case RF_TX_RUNNING: 01340 txTimeoutTimer .detach( ); 01341 // TxDone interrupt 01342 switch( this->settings.Modem ) 01343 { 01344 case MODEM_LORA: 01345 // Clear Irq 01346 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE ); 01347 // Intentional fall through 01348 case MODEM_FSK: 01349 default: 01350 this->settings.State = RF_IDLE; 01351 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxDone != NULL ) ) 01352 { 01353 /*this->RadioEvents->TxDone( );*/ 01354 enqueueRadioEvent_TxDone(); 01355 } 01356 break; 01357 } 01358 break; 01359 default: 01360 break; 01361 } 01362 } 01363 01364 void SX1276::OnDio1Irq( void ) 01365 { 01366 switch( this->settings.State ) 01367 { 01368 case RF_RX_RUNNING: 01369 switch( this->settings.Modem ) 01370 { 01371 case MODEM_FSK: 01372 // FifoLevel interrupt 01373 // Read received packet size 01374 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) ) 01375 { 01376 if( this->settings.Fsk.FixLen == false ) 01377 { 01378 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 ); 01379 } 01380 else 01381 { 01382 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH ); 01383 } 01384 } 01385 01386 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.FifoThresh ) 01387 { 01388 ReadFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.FifoThresh ); 01389 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.FifoThresh; 01390 } 01391 else 01392 { 01393 ReadFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ); 01394 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ); 01395 } 01396 break; 01397 case MODEM_LORA: 01398 // Sync time out 01399 rxTimeoutTimer.detach( ); 01400 // Clear Irq 01401 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXTIMEOUT ); 01402 01403 this->settings.State = RF_IDLE; 01404 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) ) 01405 { 01406 /*this->RadioEvents->RxTimeout( );*/ 01407 enqueueRadioEvent_RxTimeout(); 01408 } 01409 break; 01410 default: 01411 break; 01412 } 01413 break; 01414 case RF_TX_RUNNING: 01415 switch( this->settings.Modem ) 01416 { 01417 case MODEM_FSK: 01418 // FifoEmpty interrupt 01419 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.ChunkSize ) 01420 { 01421 WriteFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.ChunkSize ); 01422 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize; 01423 } 01424 else 01425 { 01426 // Write the last chunk of data 01427 WriteFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ); 01428 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes; 01429 } 01430 break; 01431 case MODEM_LORA: 01432 break; 01433 default: 01434 break; 01435 } 01436 break; 01437 default: 01438 break; 01439 } 01440 } 01441 01442 void SX1276::OnDio2Irq( void ) 01443 { 01444 switch( this->settings.State ) 01445 { 01446 case RF_RX_RUNNING: 01447 switch( this->settings.Modem ) 01448 { 01449 case MODEM_FSK: 01450 // Checks if DIO4 is connected. If it is not PreambleDtected is set to true. 01451 if( this->dioIrq [4] == NULL ) 01452 { 01453 this->settings.FskPacketHandler.PreambleDetected = true; 01454 } 01455 01456 if( ( this->settings.FskPacketHandler.PreambleDetected == true ) && ( this->settings.FskPacketHandler.SyncWordDetected == false ) ) 01457 { 01458 rxTimeoutSyncWord.detach( ); 01459 01460 this->settings.FskPacketHandler.SyncWordDetected = true; 01461 01462 this->settings.FskPacketHandler.RssiValue = -( Read( REG_RSSIVALUE ) >> 1 ); 01463 01464 this->settings.FskPacketHandler.AfcValue = ( int32_t )( double )( ( ( uint16_t )Read( REG_AFCMSB ) << 8 ) | 01465 ( uint16_t )Read( REG_AFCLSB ) ) * 01466 ( double )FREQ_STEP; 01467 this->settings.FskPacketHandler.RxGain = ( Read( REG_LNA ) >> 5 ) & 0x07; 01468 } 01469 break; 01470 case MODEM_LORA: 01471 if( this->settings.LoRa.FreqHopOn == true ) 01472 { 01473 // Clear Irq 01474 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL ); 01475 01476 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) ) 01477 { 01478 /*this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );*/ 01479 enqueueRadioEvent_FhssChangeChannel(( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) ); 01480 } 01481 } 01482 break; 01483 default: 01484 break; 01485 } 01486 break; 01487 case RF_TX_RUNNING: 01488 switch( this->settings.Modem ) 01489 { 01490 case MODEM_FSK: 01491 break; 01492 case MODEM_LORA: 01493 if( this->settings.LoRa.FreqHopOn == true ) 01494 { 01495 // Clear Irq 01496 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL ); 01497 01498 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) ) 01499 { 01500 /*this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );*/ 01501 enqueueRadioEvent_FhssChangeChannel(( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK )); 01502 } 01503 } 01504 break; 01505 default: 01506 break; 01507 } 01508 break; 01509 default: 01510 break; 01511 } 01512 } 01513 01514 void SX1276::OnDio3Irq( void ) 01515 { 01516 switch( this->settings.Modem ) 01517 { 01518 case MODEM_FSK: 01519 break; 01520 case MODEM_LORA: 01521 if( ( Read( REG_LR_IRQFLAGS ) & RFLR_IRQFLAGS_CADDETECTED ) == RFLR_IRQFLAGS_CADDETECTED ) 01522 { 01523 // Clear Irq 01524 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED | RFLR_IRQFLAGS_CADDONE ); 01525 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) ) 01526 { 01527 /*this->RadioEvents->CadDone( true );*/ 01528 enqueueRadioEvent_CadDone(true); 01529 } 01530 } 01531 else 01532 { 01533 // Clear Irq 01534 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE ); 01535 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) ) 01536 { 01537 /*this->RadioEvents->CadDone( false );*/ 01538 enqueueRadioEvent_CadDone(false); 01539 } 01540 } 01541 break; 01542 default: 01543 break; 01544 } 01545 } 01546 01547 void SX1276::OnDio4Irq( void ) 01548 { 01549 switch( this->settings.Modem ) 01550 { 01551 case MODEM_FSK: 01552 { 01553 if( this->settings.FskPacketHandler.PreambleDetected == false ) 01554 { 01555 this->settings.FskPacketHandler.PreambleDetected = true; 01556 } 01557 } 01558 break; 01559 case MODEM_LORA: 01560 break; 01561 default: 01562 break; 01563 } 01564 } 01565 01566 void SX1276::OnDio5Irq( void ) 01567 { 01568 switch( this->settings.Modem ) 01569 { 01570 case MODEM_FSK: 01571 break; 01572 case MODEM_LORA: 01573 break; 01574 default: 01575 break; 01576 } 01577 } 01578 01579 // Inizio nuova parte per RTOS 01580 01581 void SX1276::enqueueOnTimeoutIrq() 01582 { 01583 _eq_events->call(this, &SX1276::OnTimeoutIrq); 01584 } 01585 01586 void SX1276::radioEvent_RxTimeout() 01587 { 01588 this->RadioEvents->RxTimeout( ); 01589 } 01590 01591 void SX1276::enqueueRadioEvent_RxTimeout() 01592 { 01593 _eq_events->call(this, &SX1276::radioEvent_RxTimeout); 01594 } 01595 01596 void SX1276::radioEvent_TxTimeout() 01597 { 01598 this->RadioEvents->TxTimeout( ); 01599 } 01600 01601 void SX1276::enqueueRadioEvent_TxTimeout() 01602 { 01603 _eq_events->call(this, &SX1276::radioEvent_TxTimeout); 01604 } 01605 01606 void SX1276::radioEvent_RxError() 01607 { 01608 this->RadioEvents->RxError( ); 01609 } 01610 01611 void SX1276::enqueueRadioEvent_RxError() 01612 { 01613 _eq_events->call(this, &SX1276::radioEvent_RxError); 01614 } 01615 01616 void SX1276::radioEvent_RxDone(uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr) 01617 { 01618 this->RadioEvents->RxDone(payload, size, rssi, snr); 01619 } 01620 01621 void SX1276::enqueueRadioEvent_RxDone(uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr) 01622 { 01623 _eq_events->call(this, &SX1276::radioEvent_RxDone, payload, size, rssi, snr); 01624 } 01625 01626 void SX1276::radioEvent_TxDone() 01627 { 01628 this->RadioEvents->TxDone(); 01629 } 01630 01631 void SX1276::enqueueRadioEvent_TxDone() 01632 { 01633 _eq_events->call(this, &SX1276::radioEvent_TxDone); 01634 } 01635 01636 void SX1276::radioEvent_FhssChangeChannel(uint8_t currentChannel) 01637 { 01638 this->RadioEvents->FhssChangeChannel(currentChannel); 01639 } 01640 01641 void SX1276::enqueueRadioEvent_FhssChangeChannel(uint8_t currentChannel) 01642 { 01643 _eq_events->call(this, &SX1276::radioEvent_FhssChangeChannel, currentChannel); 01644 } 01645 01646 void SX1276::radioEvent_CadDone(bool channelActivityDetected) 01647 { 01648 this->RadioEvents->CadDone(channelActivityDetected); 01649 } 01650 01651 void SX1276::enqueueRadioEvent_CadDone(bool channelActivityDetected) 01652 { 01653 _eq_events->call(this, &SX1276::radioEvent_CadDone, channelActivityDetected); 01654 } 01655 01656 void SX1276::enqueueOnDio0Irq() 01657 { 01658 _eq_events->call(this, &SX1276::OnDio0Irq); 01659 } 01660 01661 void SX1276::enqueueOnDio1Irq() 01662 { 01663 _eq_events->call(this, &SX1276::OnDio1Irq); 01664 } 01665 01666 void SX1276::enqueueOnDio2Irq() 01667 { 01668 _eq_events->call(this, &SX1276::OnDio2Irq); 01669 } 01670 01671 void SX1276::enqueueOnDio3Irq() 01672 { 01673 _eq_events->call(this, &SX1276::OnDio3Irq); 01674 } 01675 01676 void SX1276::enqueueOnDio4Irq() 01677 { 01678 _eq_events->call(this, &SX1276::OnDio4Irq); 01679 } 01680 01681 void SX1276::enqueueOnDio5Irq() 01682 { 01683 /* NULL */ 01684 } 01685 01686 // Fine nuova parte per RTOS
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