sx1272.cpp

00001 /*
00002  / _____)             _              | |
00003 ( (____  _____ ____ _| |_ _____  ____| |__
00004  \____ \| ___ |    (_   _) ___ |/ ___)  _ \
00005  _____) ) ____| | | || |_| ____( (___| | | |
00006 (______/|_____)_|_|_| \__)_____)\____)_| |_|
00007     (C) 2015 Semtech
00008 
00009 Description: Actual implementation of a SX1272 radio, inherits Radio
00010 
00011 License: Revised BSD License, see LICENSE.TXT file include in the project
00012 
00013 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
00014 */
00015 #include "sx1272.h"
00016 
00017 const FskBandwidth_t  SX1272::FskBandwidths[] =
00018 {
00019     { 2600  , 0x17 },
00020     { 3100  , 0x0F },
00021     { 3900  , 0x07 },
00022     { 5200  , 0x16 },
00023     { 6300  , 0x0E },
00024     { 7800  , 0x06 },
00025     { 10400 , 0x15 },
00026     { 12500 , 0x0D },
00027     { 15600 , 0x05 },
00028     { 20800 , 0x14 },
00029     { 25000 , 0x0C },
00030     { 31300 , 0x04 },
00031     { 41700 , 0x13 },
00032     { 50000 , 0x0B },
00033     { 62500 , 0x03 },
00034     { 83333 , 0x12 },
00035     { 100000, 0x0A },
00036     { 125000, 0x02 },
00037     { 166700, 0x11 },
00038     { 200000, 0x09 },
00039     { 250000, 0x01 },
00040     { 300000, 0x00 }, // Invalid Bandwidth
00041 };
00042 
00043 
00044 SX1272::SX1272( RadioEvents_t *events,
00045                 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
00046                 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5 )
00047             :   Radio ( events ),
00048                 spi( mosi, miso, sclk ),
00049                 nss( nss ),
00050                 reset( reset ),
00051                 dio0( dio0 ), dio1( dio1 ), dio2( dio2 ), dio3( dio3 ), dio4( dio4 ), dio5( dio5 ),
00052                 isRadioActive( false )
00053 {
00054     wait_ms( 10 );
00055     this->rxtxBuffer = new uint8_t[RX_BUFFER_SIZE];
00056 
00057     this->RadioEvents = events;
00058 
00059     this->dioIrq  = new DioIrqHandler[6];
00060 
00061     this->dioIrq [0] = &SX1272::enqueueOnDio0Irq; /*&SX1272::OnDio0Irq;*/
00062     this->dioIrq [1] = &SX1272::enqueueOnDio1Irq; /*&SX1272::OnDio1Irq;*/
00063     this->dioIrq [2] = &SX1272::enqueueOnDio2Irq; /*&SX1272::OnDio2Irq;*/
00064     this->dioIrq [3] = &SX1272::enqueueOnDio3Irq; /*&SX1272::OnDio3Irq;*/
00065     this->dioIrq [4] = &SX1272::enqueueOnDio4Irq; /*&SX1272::OnDio4Irq;*/
00066     this->dioIrq [5] = &SX1272::enqueueOnDio5Irq; /*NULL;*/
00067 
00068     this->settings.State = RF_IDLE;
00069 }
00070 
00071 SX1272::~SX1272( )
00072 {
00073     delete this->rxtxBuffer;
00074     delete this->dioIrq ;
00075 }
00076 
00077 void SX1272::Init( RadioEvents_t *events )
00078 {
00079     this->RadioEvents = events;
00080 
00081     // <RTOS>
00082     //_thread_events_queue->start(callback(_eq_events, &EventQueue::dispatch_forever));
00083     // </RTOS>
00084 }
00085 
00086 RadioState SX1272::GetStatus ( void )
00087 {
00088     return this->settings.State;
00089 }
00090 
00091 void SX1272::SetChannel( uint32_t freq )
00092 {
00093     this->settings.Channel = freq;
00094     freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP );
00095     Write( REG_FRFMSB, ( uint8_t )( ( freq >> 16 ) & 0xFF ) );
00096     Write( REG_FRFMID, ( uint8_t )( ( freq >> 8 ) & 0xFF ) );
00097     Write( REG_FRFLSB, ( uint8_t )( freq & 0xFF ) );
00098 }
00099 
00100 bool SX1272::IsChannelFree( RadioModems_t modem, uint32_t freq, int16_t rssiThresh )
00101 {
00102     int16_t rssi = 0;
00103 
00104     SetModem( modem );
00105 
00106     SetChannel( freq );
00107 
00108     SetOpMode( RF_OPMODE_RECEIVER );
00109 
00110     wait_ms( 1 );
00111 
00112     rssi = GetRssi( modem );
00113 
00114     Sleep( );
00115 
00116     if( rssi > rssiThresh )
00117     {
00118         return false;
00119     }
00120     return true;
00121 }
00122 
00123 uint32_t SX1272::Random( void )
00124 {
00125     uint8_t i;
00126     uint32_t rnd = 0;
00127 
00128     /*
00129      * Radio setup for random number generation
00130      */
00131     // Set LoRa modem ON
00132     SetModem( MODEM_LORA );
00133 
00134     // Disable LoRa modem interrupts
00135     Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
00136                   RFLR_IRQFLAGS_RXDONE |
00137                   RFLR_IRQFLAGS_PAYLOADCRCERROR |
00138                   RFLR_IRQFLAGS_VALIDHEADER |
00139                   RFLR_IRQFLAGS_TXDONE |
00140                   RFLR_IRQFLAGS_CADDONE |
00141                   RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
00142                   RFLR_IRQFLAGS_CADDETECTED );
00143 
00144     // Set radio in continuous reception
00145     SetOpMode( RF_OPMODE_RECEIVER );
00146 
00147     for( i = 0; i < 32; i++ )
00148     {
00149         wait_ms( 1 );
00150         // Unfiltered RSSI value reading. Only takes the LSB value
00151         rnd |= ( ( uint32_t )Read( REG_LR_RSSIWIDEBAND ) & 0x01 ) << i;
00152     }
00153 
00154     Sleep( );
00155 
00156     return rnd;
00157 }
00158 
00159 /*!
00160  * Returns the known FSK bandwidth registers value
00161  *
00162  * \param [IN] bandwidth Bandwidth value in Hz
00163  * \retval regValue Bandwidth register value.
00164  */
00165 uint8_t SX1272::GetFskBandwidthRegValue ( uint32_t bandwidth )
00166 {
00167     uint8_t i;
00168 
00169     for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t  ) ) - 1; i++ )
00170     {
00171         if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandwidth ) )
00172         {
00173             return FskBandwidths[i].RegValue;
00174         }
00175     }
00176     // ERROR: Value not found
00177     while( 1 );
00178 }
00179 
00180 void SX1272::SetRxConfig( RadioModems_t modem, uint32_t bandwidth,
00181                          uint32_t datarate, uint8_t coderate,
00182                          uint32_t bandwidthAfc, uint16_t preambleLen,
00183                          uint16_t symbTimeout, bool fixLen,
00184                          uint8_t payloadLen,
00185                          bool crcOn, bool freqHopOn, uint8_t hopPeriod,
00186                          bool iqInverted, bool rxContinuous )
00187 {
00188     SetModem( modem );
00189 
00190     switch( modem )
00191     {
00192     case MODEM_FSK:
00193         {
00194             this->settings.Fsk.Bandwidth = bandwidth;
00195             this->settings.Fsk.Datarate = datarate;
00196             this->settings.Fsk.BandwidthAfc = bandwidthAfc;
00197             this->settings.Fsk.FixLen = fixLen;
00198             this->settings.Fsk.PayloadLen = payloadLen;
00199             this->settings.Fsk.CrcOn = crcOn;
00200             this->settings.Fsk.IqInverted = iqInverted;
00201             this->settings.Fsk.RxContinuous = rxContinuous;
00202             this->settings.Fsk.PreambleLen = preambleLen;
00203             this->settings.Fsk.RxSingleTimeout = symbTimeout * ( ( 1.0 / ( double )datarate ) * 8.0 ) * 1e3;
00204 
00205             datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
00206             Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
00207             Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
00208 
00209             Write( REG_RXBW, GetFskBandwidthRegValue ( bandwidth ) );
00210             Write( REG_AFCBW, GetFskBandwidthRegValue ( bandwidthAfc ) );
00211 
00212             Write( REG_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
00213             Write( REG_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
00214 
00215             if( fixLen == 1 )
00216             {
00217                 Write( REG_PAYLOADLENGTH, payloadLen );
00218             }
00219             else
00220             {
00221                 Write( REG_PAYLOADLENGTH, 0xFF ); // Set payload length to the maximum
00222             }
00223             
00224             Write( REG_PACKETCONFIG1,
00225                          ( Read( REG_PACKETCONFIG1 ) &
00226                            RF_PACKETCONFIG1_CRC_MASK &
00227                            RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
00228                            ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
00229                            ( crcOn << 4 ) );
00230             Write( REG_PACKETCONFIG2, ( Read( REG_PACKETCONFIG2 ) | RF_PACKETCONFIG2_DATAMODE_PACKET ) );
00231         }
00232         break;
00233     case MODEM_LORA:
00234         {
00235             this->settings.LoRa.Bandwidth = bandwidth;
00236             this->settings.LoRa.Datarate = datarate;
00237             this->settings.LoRa.Coderate = coderate;
00238             this->settings.LoRa.PreambleLen = preambleLen;
00239             this->settings.LoRa.FixLen = fixLen;
00240             this->settings.LoRa.PayloadLen = payloadLen;
00241             this->settings.LoRa.CrcOn = crcOn;
00242             this->settings.LoRa.FreqHopOn = freqHopOn;
00243             this->settings.LoRa.HopPeriod = hopPeriod;
00244             this->settings.LoRa.IqInverted = iqInverted;
00245             this->settings.LoRa.RxContinuous = rxContinuous;
00246 
00247             if( datarate > 12 )
00248             {
00249                 datarate = 12;
00250             }
00251             else if( datarate < 6 )
00252             {
00253                 datarate = 6;
00254             }
00255 
00256             if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
00257                 ( ( bandwidth == 1 ) && ( datarate == 12 ) ) )
00258             {
00259                 this->settings.LoRa.LowDatarateOptimize = 0x01;
00260             }
00261             else
00262             {
00263                 this->settings.LoRa.LowDatarateOptimize = 0x00;
00264             }
00265 
00266             Write( REG_LR_MODEMCONFIG1,
00267                          ( Read( REG_LR_MODEMCONFIG1 ) &
00268                            RFLR_MODEMCONFIG1_BW_MASK &
00269                            RFLR_MODEMCONFIG1_CODINGRATE_MASK &
00270                            RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK &
00271                            RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK &
00272                            RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK ) |
00273                            ( bandwidth << 6 ) | ( coderate << 3 ) |
00274                            ( fixLen << 2 ) | ( crcOn << 1 ) |
00275                            this->settings.LoRa.LowDatarateOptimize );
00276 
00277             Write( REG_LR_MODEMCONFIG2,
00278                          ( Read( REG_LR_MODEMCONFIG2 ) &
00279                            RFLR_MODEMCONFIG2_SF_MASK &
00280                            RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) |
00281                            ( datarate << 4 ) |
00282                            ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) );
00283 
00284             Write( REG_LR_SYMBTIMEOUTLSB, ( uint8_t )( symbTimeout & 0xFF ) );
00285 
00286             Write( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
00287             Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
00288 
00289             if( fixLen == 1 )
00290             {
00291                 Write( REG_LR_PAYLOADLENGTH, payloadLen );
00292             }
00293 
00294             if( this->settings.LoRa.FreqHopOn == true )
00295             {
00296                 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
00297                 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
00298             }
00299 
00300             if( datarate == 6 )
00301             {
00302                 Write( REG_LR_DETECTOPTIMIZE,
00303                              ( Read( REG_LR_DETECTOPTIMIZE ) &
00304                                RFLR_DETECTIONOPTIMIZE_MASK ) |
00305                                RFLR_DETECTIONOPTIMIZE_SF6 );
00306                 Write( REG_LR_DETECTIONTHRESHOLD,
00307                              RFLR_DETECTIONTHRESH_SF6 );
00308             }
00309             else
00310             {
00311                 Write( REG_LR_DETECTOPTIMIZE,
00312                              ( Read( REG_LR_DETECTOPTIMIZE ) &
00313                              RFLR_DETECTIONOPTIMIZE_MASK ) |
00314                              RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
00315                 Write( REG_LR_DETECTIONTHRESHOLD,
00316                              RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
00317             }
00318         }
00319         break;
00320     }
00321 }
00322 
00323 void SX1272::SetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev,
00324                         uint32_t bandwidth, uint32_t datarate,
00325                         uint8_t coderate, uint16_t preambleLen,
00326                         bool fixLen, bool crcOn, bool freqHopOn,
00327                         uint8_t hopPeriod, bool iqInverted, uint32_t timeout )
00328 {
00329     SetModem( modem );
00330 
00331     SetRfTxPower( power );
00332 
00333     switch( modem )
00334     {
00335     case MODEM_FSK:
00336         {
00337             this->settings.Fsk.Power = power;
00338             this->settings.Fsk.Fdev = fdev;
00339             this->settings.Fsk.Bandwidth = bandwidth;
00340             this->settings.Fsk.Datarate = datarate;
00341             this->settings.Fsk.PreambleLen = preambleLen;
00342             this->settings.Fsk.FixLen = fixLen;
00343             this->settings.Fsk.CrcOn = crcOn;
00344             this->settings.Fsk.IqInverted = iqInverted;
00345             this->settings.Fsk.TxTimeout = timeout;
00346 
00347             fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP );
00348             Write( REG_FDEVMSB, ( uint8_t )( fdev >> 8 ) );
00349             Write( REG_FDEVLSB, ( uint8_t )( fdev & 0xFF ) );
00350 
00351             datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
00352             Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
00353             Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
00354 
00355             Write( REG_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
00356             Write( REG_PREAMBLELSB, preambleLen & 0xFF );
00357 
00358             Write( REG_PACKETCONFIG1,
00359                          ( Read( REG_PACKETCONFIG1 ) &
00360                            RF_PACKETCONFIG1_CRC_MASK &
00361                            RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
00362                            ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
00363                            ( crcOn << 4 ) );
00364             Write( REG_PACKETCONFIG2, ( Read( REG_PACKETCONFIG2 ) | RF_PACKETCONFIG2_DATAMODE_PACKET ) );
00365         }
00366         break;
00367     case MODEM_LORA:
00368         {
00369             this->settings.LoRa.Power = power;
00370             this->settings.LoRa.Bandwidth = bandwidth;
00371             this->settings.LoRa.Datarate = datarate;
00372             this->settings.LoRa.Coderate = coderate;
00373             this->settings.LoRa.PreambleLen = preambleLen;
00374             this->settings.LoRa.FixLen = fixLen;
00375             this->settings.LoRa.FreqHopOn = freqHopOn;
00376             this->settings.LoRa.HopPeriod = hopPeriod;
00377             this->settings.LoRa.CrcOn = crcOn;
00378             this->settings.LoRa.IqInverted = iqInverted;
00379             this->settings.LoRa.TxTimeout = timeout;
00380 
00381             if( datarate > 12 )
00382             {
00383                 datarate = 12;
00384             }
00385             else if( datarate < 6 )
00386             {
00387                 datarate = 6;
00388             }
00389             if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
00390                 ( ( bandwidth == 1 ) && ( datarate == 12 ) ) )
00391             {
00392                 this->settings.LoRa.LowDatarateOptimize = 0x01;
00393             }
00394             else
00395             {
00396                 this->settings.LoRa.LowDatarateOptimize = 0x00;
00397             }
00398 
00399             if( this->settings.LoRa.FreqHopOn == true )
00400             {
00401                 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
00402                 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
00403             }
00404 
00405             Write( REG_LR_MODEMCONFIG1,
00406                          ( Read( REG_LR_MODEMCONFIG1 ) &
00407                            RFLR_MODEMCONFIG1_BW_MASK &
00408                            RFLR_MODEMCONFIG1_CODINGRATE_MASK &
00409                            RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK &
00410                            RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK &
00411                            RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK ) |
00412                            ( bandwidth << 6 ) | ( coderate << 3 ) |
00413                            ( fixLen << 2 ) | ( crcOn << 1 ) |
00414                            this->settings.LoRa.LowDatarateOptimize );
00415 
00416             Write( REG_LR_MODEMCONFIG2,
00417                         ( Read( REG_LR_MODEMCONFIG2 ) &
00418                           RFLR_MODEMCONFIG2_SF_MASK ) |
00419                           ( datarate << 4 ) );
00420 
00421 
00422             Write( REG_LR_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
00423             Write( REG_LR_PREAMBLELSB, preambleLen & 0xFF );
00424 
00425             if( datarate == 6 )
00426             {
00427                 Write( REG_LR_DETECTOPTIMIZE,
00428                              ( Read( REG_LR_DETECTOPTIMIZE ) &
00429                                RFLR_DETECTIONOPTIMIZE_MASK ) |
00430                                RFLR_DETECTIONOPTIMIZE_SF6 );
00431                 Write( REG_LR_DETECTIONTHRESHOLD,
00432                              RFLR_DETECTIONTHRESH_SF6 );
00433             }
00434             else
00435             {
00436                 Write( REG_LR_DETECTOPTIMIZE,
00437                              ( Read( REG_LR_DETECTOPTIMIZE ) &
00438                              RFLR_DETECTIONOPTIMIZE_MASK ) |
00439                              RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
00440                 Write( REG_LR_DETECTIONTHRESHOLD,
00441                              RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
00442             }
00443         }
00444         break;
00445     }
00446 }
00447 
00448 uint32_t SX1272::TimeOnAir( RadioModems_t modem, uint8_t pktLen )
00449 {
00450     uint32_t airTime = 0;
00451 
00452     switch( modem )
00453     {
00454     case MODEM_FSK:
00455         {
00456             airTime = rint( ( 8 * ( this->settings.Fsk.PreambleLen +
00457                                      ( ( Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + 1 ) +
00458                                      ( ( this->settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) +
00459                                      ( ( ( Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK ) != 0x00 ) ? 1.0 : 0 ) +
00460                                      pktLen +
00461                                      ( ( this->settings.Fsk.CrcOn == 0x01 ) ? 2.0 : 0 ) ) /
00462                                      this->settings.Fsk.Datarate ) * 1e3 );
00463         }
00464         break;
00465     case MODEM_LORA:
00466         {
00467             double bw = 0.0;
00468             switch( this->settings.LoRa.Bandwidth )
00469             {
00470             case 0: // 125 kHz
00471                 bw = 125e3;
00472                 break;
00473             case 1: // 250 kHz
00474                 bw = 250e3;
00475                 break;
00476             case 2: // 500 kHz
00477                 bw = 500e3;
00478                 break;
00479             }
00480 
00481             // Symbol rate : time for one symbol (secs)
00482             double rs = bw / ( 1 << this->settings.LoRa.Datarate );
00483             double ts = 1 / rs;
00484             // time of preamble
00485             double tPreamble = ( this->settings.LoRa.PreambleLen + 4.25 ) * ts;
00486             // Symbol length of payload and time
00487             double tmp = ceil( ( 8 * pktLen - 4 * this->settings.LoRa.Datarate +
00488                                  28 + 16 * this->settings.LoRa.CrcOn -
00489                                  ( this->settings.LoRa.FixLen ? 20 : 0 ) ) /
00490                                  ( double )( 4 * ( this->settings.LoRa.Datarate -
00491                                  ( ( this->settings.LoRa.LowDatarateOptimize > 0 ) ? 2 : 0 ) ) ) ) *
00492                                  ( this->settings.LoRa.Coderate + 4 );
00493             double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 );
00494             double tPayload = nPayload * ts;
00495             // Time on air
00496             double tOnAir = tPreamble + tPayload;
00497             // return ms secs
00498             airTime = floor( tOnAir * 1e3 + 0.999 );
00499         }
00500         break;
00501     }
00502     return airTime;
00503 }
00504 
00505 void SX1272::Send( uint8_t *buffer, uint8_t size )
00506 {
00507     uint32_t txTimeout = 0;
00508 
00509     switch( this->settings.Modem )
00510     {
00511     case MODEM_FSK:
00512         {
00513             this->settings.FskPacketHandler.NbBytes = 0;
00514             this->settings.FskPacketHandler.Size = size;
00515 
00516             if( this->settings.Fsk.FixLen == false )
00517             {
00518                 WriteFifo( ( uint8_t* )&size, 1 );
00519             }
00520             else
00521             {
00522                 Write( REG_PAYLOADLENGTH, size );
00523             }
00524 
00525             if( ( size > 0 ) && ( size <= 64 ) )
00526             {
00527                 this->settings.FskPacketHandler.ChunkSize = size;
00528             }
00529             else
00530             {
00531                 memcpy( rxtxBuffer, buffer, size );
00532                 this->settings.FskPacketHandler.ChunkSize = 32;
00533             }
00534 
00535             // Write payload buffer
00536             WriteFifo( buffer, this->settings.FskPacketHandler.ChunkSize );
00537             this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
00538             txTimeout = this->settings.Fsk.TxTimeout;
00539         }
00540         break;
00541     case MODEM_LORA:
00542         {
00543             if( this->settings.LoRa.IqInverted == true )
00544             {
00545                 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON ) );
00546                 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
00547             }
00548             else
00549             {
00550                 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
00551                 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
00552             }
00553 
00554             this->settings.LoRaPacketHandler.Size = size;
00555 
00556             // Initializes the payload size
00557             Write( REG_LR_PAYLOADLENGTH, size );
00558 
00559             // Full buffer used for Tx
00560             Write( REG_LR_FIFOTXBASEADDR, 0 );
00561             Write( REG_LR_FIFOADDRPTR, 0 );
00562 
00563             // FIFO operations can not take place in Sleep mode
00564             if( ( Read( REG_OPMODE ) & ~RF_OPMODE_MASK ) == RF_OPMODE_SLEEP )
00565             {
00566                 Standby( );
00567                 wait_ms( 1 );
00568             }
00569             // Write payload buffer
00570             WriteFifo( buffer, size );
00571             txTimeout = this->settings.LoRa.TxTimeout;
00572         }
00573         break;
00574     }
00575 
00576     Tx( txTimeout );
00577 }
00578 
00579 void SX1272::Sleep( void )
00580 {
00581     txTimeoutTimer .detach( );
00582     rxTimeoutTimer.detach( );
00583 
00584     SetOpMode( RF_OPMODE_SLEEP );
00585     this->settings.State = RF_IDLE;
00586 }
00587 
00588 void SX1272::Standby( void )
00589 {
00590     txTimeoutTimer .detach( );
00591     rxTimeoutTimer.detach( );
00592 
00593     SetOpMode( RF_OPMODE_STANDBY );
00594     this->settings.State = RF_IDLE;
00595 }
00596 
00597 void SX1272::Rx( uint32_t timeout )
00598 {
00599     bool rxContinuous = false;
00600 
00601     switch( this->settings.Modem )
00602     {
00603     case MODEM_FSK:
00604         {
00605             rxContinuous = this->settings.Fsk.RxContinuous;
00606 
00607             // DIO0=PayloadReady
00608             // DIO1=FifoLevel
00609             // DIO2=SyncAddr
00610             // DIO3=FifoEmpty
00611             // DIO4=Preamble
00612             // DIO5=ModeReady
00613             Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
00614                                                                             RF_DIOMAPPING1_DIO1_MASK &
00615                                                                             RF_DIOMAPPING1_DIO2_MASK ) |
00616                                                                             RF_DIOMAPPING1_DIO0_00 |
00617                                                                             RF_DIOMAPPING1_DIO1_00 |
00618                                                                             RF_DIOMAPPING1_DIO2_11 );
00619 
00620             Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
00621                                                                             RF_DIOMAPPING2_MAP_MASK ) |
00622                                                                             RF_DIOMAPPING2_DIO4_11 |
00623                                                                             RF_DIOMAPPING2_MAP_PREAMBLEDETECT );
00624 
00625             this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
00626 
00627             Write( REG_RXCONFIG, RF_RXCONFIG_AFCAUTO_ON | RF_RXCONFIG_AGCAUTO_ON | RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT );
00628 
00629             this->settings.FskPacketHandler.PreambleDetected = false;
00630             this->settings.FskPacketHandler.SyncWordDetected = false;
00631             this->settings.FskPacketHandler.NbBytes = 0;
00632             this->settings.FskPacketHandler.Size = 0;
00633         }
00634         break;
00635     case MODEM_LORA:
00636         {
00637             if( this->settings.LoRa.IqInverted == true )
00638             {
00639                 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF ) );
00640                 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
00641             }
00642             else
00643             {
00644                 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
00645                 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
00646             }
00647 
00648             rxContinuous = this->settings.LoRa.RxContinuous;
00649 
00650             if( this->settings.LoRa.FreqHopOn == true )
00651             {
00652                 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
00653                                                   //RFLR_IRQFLAGS_RXDONE |
00654                                                   //RFLR_IRQFLAGS_PAYLOADCRCERROR |
00655                                                   RFLR_IRQFLAGS_VALIDHEADER |
00656                                                   RFLR_IRQFLAGS_TXDONE |
00657                                                   RFLR_IRQFLAGS_CADDONE |
00658                                                   //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
00659                                                   RFLR_IRQFLAGS_CADDETECTED );
00660 
00661                 // DIO0=RxDone, DIO2=FhssChangeChannel
00662                 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK  ) | RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO2_00 );
00663             }
00664             else
00665             {
00666                 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
00667                                                   //RFLR_IRQFLAGS_RXDONE |
00668                                                   //RFLR_IRQFLAGS_PAYLOADCRCERROR |
00669                                                   RFLR_IRQFLAGS_VALIDHEADER |
00670                                                   RFLR_IRQFLAGS_TXDONE |
00671                                                   RFLR_IRQFLAGS_CADDONE |
00672                                                   RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
00673                                                   RFLR_IRQFLAGS_CADDETECTED );
00674 
00675                 // DIO0=RxDone
00676                 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
00677             }
00678             Write( REG_LR_FIFORXBASEADDR, 0 );
00679             Write( REG_LR_FIFOADDRPTR, 0 );
00680         }
00681         break;
00682     }
00683 
00684     memset( rxtxBuffer, 0, ( size_t )RX_BUFFER_SIZE );
00685 
00686     this->settings.State = RF_RX_RUNNING;
00687     if( timeout != 0 )
00688     {
00689         rxTimeoutTimer.attach_us(mbed::callback( this, &SX1272::enqueueOnTimeoutIrq /*&SX1272::OnTimeoutIrq*/ ), timeout * 1e3 );
00690     }
00691 
00692     if( this->settings.Modem == MODEM_FSK )
00693     {
00694         SetOpMode( RF_OPMODE_RECEIVER );
00695 
00696         if( rxContinuous == false )
00697         {
00698             rxTimeoutSyncWord.attach_us( mbed::callback( this, &SX1272::enqueueOnTimeoutIrq /*&SX1272::OnTimeoutIrq*/ ),
00699                                          this->settings.Fsk.RxSingleTimeout * 1e3 );
00700         }
00701     }
00702     else
00703     {
00704         if( rxContinuous == true )
00705         {
00706             SetOpMode( RFLR_OPMODE_RECEIVER );
00707         }
00708         else
00709         {
00710             SetOpMode( RFLR_OPMODE_RECEIVER_SINGLE );
00711         }
00712     }
00713 }
00714 
00715 void SX1272::Tx( uint32_t timeout )
00716 {
00717 
00718     switch( this->settings.Modem )
00719     {
00720     case MODEM_FSK:
00721         {
00722             // DIO0=PacketSent
00723             // DIO1=FifoEmpty
00724             // DIO2=FifoFull
00725             // DIO3=FifoEmpty
00726             // DIO4=LowBat
00727             // DIO5=ModeReady
00728             Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
00729                                                                             RF_DIOMAPPING1_DIO1_MASK &
00730                                                                             RF_DIOMAPPING1_DIO2_MASK ) |
00731                                                                             RF_DIOMAPPING1_DIO1_01 );
00732 
00733             Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
00734                                                                             RF_DIOMAPPING2_MAP_MASK ) );
00735             this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
00736         }
00737         break;
00738     case MODEM_LORA:
00739         {
00740             if( this->settings.LoRa.FreqHopOn == true )
00741             {
00742                 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
00743                                                   RFLR_IRQFLAGS_RXDONE |
00744                                                   RFLR_IRQFLAGS_PAYLOADCRCERROR |
00745                                                   RFLR_IRQFLAGS_VALIDHEADER |
00746                                                   //RFLR_IRQFLAGS_TXDONE |
00747                                                   RFLR_IRQFLAGS_CADDONE |
00748                                                   //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
00749                                                   RFLR_IRQFLAGS_CADDETECTED );
00750 
00751                 // DIO0=TxDone, DIO2=FhssChangeChannel
00752                 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_01 | RFLR_DIOMAPPING1_DIO2_00 );
00753             }
00754             else
00755             {
00756                 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
00757                                                   RFLR_IRQFLAGS_RXDONE |
00758                                                   RFLR_IRQFLAGS_PAYLOADCRCERROR |
00759                                                   RFLR_IRQFLAGS_VALIDHEADER |
00760                                                   //RFLR_IRQFLAGS_TXDONE |
00761                                                   RFLR_IRQFLAGS_CADDONE |
00762                                                   RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
00763                                                   RFLR_IRQFLAGS_CADDETECTED );
00764 
00765                 // DIO0=TxDone
00766                 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
00767             }
00768         }
00769         break;
00770     }
00771 
00772     this->settings.State = RF_TX_RUNNING;
00773     txTimeoutTimer .attach_us( mbed::callback( this, &SX1272::enqueueOnTimeoutIrq /*&SX1272::OnTimeoutIrq*/ ), timeout * 1e3 );
00774     SetOpMode( RF_OPMODE_TRANSMITTER );
00775 }
00776 
00777 void SX1272::StartCad( void )
00778 {
00779     switch( this->settings.Modem )
00780     {
00781     case MODEM_FSK:
00782         {
00783 
00784         }
00785         break;
00786     case MODEM_LORA:
00787         {
00788             Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
00789                                         RFLR_IRQFLAGS_RXDONE |
00790                                         RFLR_IRQFLAGS_PAYLOADCRCERROR |
00791                                         RFLR_IRQFLAGS_VALIDHEADER |
00792                                         RFLR_IRQFLAGS_TXDONE |
00793                                         //RFLR_IRQFLAGS_CADDONE |
00794                                         RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL // |
00795                                         //RFLR_IRQFLAGS_CADDETECTED
00796                                         );
00797 
00798             // DIO3=CADDone
00799             Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO3_MASK ) | RFLR_DIOMAPPING1_DIO3_00 );
00800 
00801             this->settings.State = RF_CAD;
00802             SetOpMode( RFLR_OPMODE_CAD );
00803         }
00804         break;
00805     default:
00806         break;
00807     }
00808 }
00809 
00810 void SX1272::SetTxContinuousWave( uint32_t freq, int8_t power, uint16_t time )
00811 {
00812     uint32_t timeout = ( uint32_t )( time * 1e6 );
00813 
00814     SetChannel( freq );
00815 
00816     SetTxConfig( MODEM_FSK, power, 0, 0, 4800, 0, 5, false, false, 0, 0, 0, timeout );
00817 
00818     Write( REG_PACKETCONFIG2, ( Read( REG_PACKETCONFIG2 ) & RF_PACKETCONFIG2_DATAMODE_MASK ) );
00819     // Disable radio interrupts
00820     Write( REG_DIOMAPPING1, RF_DIOMAPPING1_DIO0_11 | RF_DIOMAPPING1_DIO1_11 );
00821     Write( REG_DIOMAPPING2, RF_DIOMAPPING2_DIO4_10 | RF_DIOMAPPING2_DIO5_10 );
00822 
00823     this->settings.State = RF_TX_RUNNING;
00824     txTimeoutTimer .attach_us( mbed::callback( this, &SX1272::enqueueOnTimeoutIrq /*&SX1272::OnTimeoutIrq*/ ), timeout );
00825     SetOpMode( RF_OPMODE_TRANSMITTER );
00826 }
00827 
00828 int16_t SX1272::GetRssi( RadioModems_t modem )
00829 {
00830     int16_t rssi = 0;
00831 
00832     switch( modem )
00833     {
00834     case MODEM_FSK:
00835         rssi = -( Read( REG_RSSIVALUE ) >> 1 );
00836         break;
00837     case MODEM_LORA:
00838         rssi = RSSI_OFFSET + Read( REG_LR_RSSIVALUE );
00839         break;
00840     default:
00841         rssi = -1;
00842         break;
00843     }
00844     return rssi;
00845 }
00846 
00847 void SX1272::SetOpMode( uint8_t opMode )
00848 {
00849     if( opMode == RF_OPMODE_SLEEP )
00850     {
00851         SetAntSwLowPower( true );
00852     }
00853     else
00854     {
00855         SetAntSwLowPower( false );
00856         SetAntSw( opMode );
00857     }
00858     Write( REG_OPMODE, ( Read( REG_OPMODE ) & RF_OPMODE_MASK ) | opMode );
00859 }
00860 
00861 void SX1272::SetModem( RadioModems_t modem )
00862 {
00863     if( ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_ON ) != 0 )
00864     {
00865         this->settings.Modem = MODEM_LORA;
00866     }
00867     else
00868     {
00869         this->settings.Modem = MODEM_FSK;
00870     }
00871 
00872     if( this->settings.Modem == modem )
00873     {
00874         return;
00875     }
00876 
00877     this->settings.Modem = modem;
00878     switch( this->settings.Modem )
00879     {
00880     default:
00881     case MODEM_FSK:
00882         Sleep( );
00883         Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF );
00884 
00885         Write( REG_DIOMAPPING1, 0x00 );
00886         Write( REG_DIOMAPPING2, 0x30 ); // DIO5=ModeReady
00887         break;
00888     case MODEM_LORA:
00889         Sleep( );
00890         Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON );
00891 
00892         Write( REG_DIOMAPPING1, 0x00 );
00893         Write( REG_DIOMAPPING2, 0x00 );
00894         break;
00895     }
00896 }
00897 
00898 void SX1272::SetMaxPayloadLength( RadioModems_t modem, uint8_t max )
00899 {
00900     this->SetModem( modem );
00901 
00902     switch( modem )
00903     {
00904     case MODEM_FSK:
00905         if( this->settings.Fsk.FixLen == false )
00906         {
00907             this->Write( REG_PAYLOADLENGTH, max );
00908         }
00909         break;
00910     case MODEM_LORA:
00911         this->Write( REG_LR_PAYLOADMAXLENGTH, max );
00912         break;
00913     }
00914 }
00915 
00916 void SX1272::SetPublicNetwork( bool enable )
00917 {
00918     SetModem( MODEM_LORA );
00919     this->settings.LoRa.PublicNetwork = enable;
00920     if( enable == true )
00921     {
00922         // Change LoRa modem SyncWord
00923         Write( REG_LR_SYNCWORD, LORA_MAC_PUBLIC_SYNCWORD );
00924     }
00925     else
00926     {
00927         // Change LoRa modem SyncWord
00928         Write( REG_LR_SYNCWORD, LORA_MAC_PRIVATE_SYNCWORD );
00929     }
00930 }
00931 
00932 void SX1272::OnTimeoutIrq( void )
00933 {
00934     switch( this->settings.State )
00935     {
00936     case RF_RX_RUNNING:
00937         if( this->settings.Modem == MODEM_FSK )
00938         {
00939             this->settings.FskPacketHandler.PreambleDetected = false;
00940             this->settings.FskPacketHandler.SyncWordDetected = false;
00941             this->settings.FskPacketHandler.NbBytes = 0;
00942             this->settings.FskPacketHandler.Size = 0;
00943 
00944             // Clear Irqs
00945             Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
00946                                         RF_IRQFLAGS1_PREAMBLEDETECT |
00947                                         RF_IRQFLAGS1_SYNCADDRESSMATCH );
00948             Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
00949 
00950             if( this->settings.Fsk.RxContinuous == true )
00951             {
00952                 // Continuous mode restart Rx chain
00953                 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
00954                 rxTimeoutSyncWord.attach_us( mbed::callback( this, &SX1272::enqueueOnTimeoutIrq /*&SX1272::OnTimeoutIrq*/ ),
00955                                              this->settings.Fsk.RxSingleTimeout * 1e3 );
00956             }
00957             else
00958             {
00959                 this->settings.State = RF_IDLE;
00960                 rxTimeoutSyncWord.detach( );
00961             }
00962         }
00963         if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) )
00964         {
00965             /*this->RadioEvents->RxTimeout( );*/
00966             enqueueRadioEvent_RxTimeout();
00967         }
00968         break;
00969     case RF_TX_RUNNING:
00970         // Tx timeout shouldn't happen.
00971         // But it has been observed that when it happens it is a result of a corrupted SPI transfer
00972         // it depends on the platform design.
00973         // 
00974         // The workaround is to put the radio in a known state. Thus, we re-initialize it.
00975 
00976         // BEGIN WORKAROUND
00977 
00978         // Reset the radio
00979         Reset( );
00980 
00981         // Initialize radio default values
00982         SetOpMode( RF_OPMODE_SLEEP );
00983 
00984         RadioRegistersInit( );
00985 
00986         SetModem( MODEM_FSK );
00987 
00988         // Restore previous network type setting.
00989         SetPublicNetwork( this->settings.LoRa.PublicNetwork );
00990         // END WORKAROUND
00991 
00992         this->settings.State = RF_IDLE;
00993         if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxTimeout != NULL ) )
00994         {
00995             /*this->RadioEvents->TxTimeout( );*/
00996             enqueueRadioEvent_TxTimeout();
00997         }
00998         break;
00999     default:
01000         break;
01001     }
01002 }
01003 
01004 void SX1272::OnDio0Irq( void )
01005 {
01006     volatile uint8_t irqFlags = 0;
01007 
01008     switch( this->settings.State )
01009     {
01010         case RF_RX_RUNNING:
01011             //TimerStop( &RxTimeoutTimer );
01012             // RxDone interrupt
01013             switch( this->settings.Modem )
01014             {
01015             case MODEM_FSK:
01016                 if( this->settings.Fsk.CrcOn == true )
01017                 {
01018                     irqFlags = Read( REG_IRQFLAGS2 );
01019                     if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK )
01020                     {
01021                         // Clear Irqs
01022                         Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
01023                                                     RF_IRQFLAGS1_PREAMBLEDETECT |
01024                                                     RF_IRQFLAGS1_SYNCADDRESSMATCH );
01025                         Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
01026 
01027                         rxTimeoutTimer.detach( );
01028 
01029                         if( this->settings.Fsk.RxContinuous == false )
01030                         {
01031                             rxTimeoutSyncWord.detach( );
01032                             this->settings.State = RF_IDLE;
01033                         }
01034                         else
01035                         {
01036                             // Continuous mode restart Rx chain
01037                             Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
01038                             rxTimeoutSyncWord.attach_us( mbed::callback( this, &SX1272::enqueueOnTimeoutIrq /*&SX1272::OnTimeoutIrq*/ ),
01039                                                          this->settings.Fsk.RxSingleTimeout * 1e3 );
01040                         }
01041 
01042                         if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) )
01043                         {
01044                             /*this->RadioEvents->RxError( );*/
01045                             enqueueRadioEvent_RxError();
01046                         }
01047                         this->settings.FskPacketHandler.PreambleDetected = false;
01048                         this->settings.FskPacketHandler.SyncWordDetected = false;
01049                         this->settings.FskPacketHandler.NbBytes = 0;
01050                         this->settings.FskPacketHandler.Size = 0;
01051                         break;
01052                     }
01053                 }
01054 
01055                 // Read received packet size
01056                 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
01057                 {
01058                     if( this->settings.Fsk.FixLen == false )
01059                     {
01060                         ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
01061                     }
01062                     else
01063                     {
01064                         this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
01065                     }
01066                     ReadFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
01067                     this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
01068                 }
01069                 else
01070                 {
01071                     ReadFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
01072                     this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
01073                 }
01074 
01075                 rxTimeoutTimer.detach( );
01076 
01077                 if( this->settings.Fsk.RxContinuous == false )
01078                 {
01079                     this->settings.State = RF_IDLE;
01080                     rxTimeoutSyncWord.detach( );
01081                 }
01082                 else
01083                 {
01084                     // Continuous mode restart Rx chain
01085                     Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
01086                     rxTimeoutSyncWord.attach_us( mbed::callback( this, &SX1272::enqueueOnTimeoutIrq /*&SX1272::OnTimeoutIrq*/ ),
01087                                                  this->settings.Fsk.RxSingleTimeout * 1e3 );
01088                 }
01089 
01090                 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) )
01091                 {
01092                     /*this->RadioEvents->RxDone( rxtxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0 );*/
01093                     enqueueRadioEvent_RxDone(rxtxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0);
01094                 }
01095                 this->settings.FskPacketHandler.PreambleDetected = false;
01096                 this->settings.FskPacketHandler.SyncWordDetected = false;
01097                 this->settings.FskPacketHandler.NbBytes = 0;
01098                 this->settings.FskPacketHandler.Size = 0;
01099                 break;
01100             case MODEM_LORA:
01101                 {
01102                     int8_t snr = 0;
01103 
01104                     // Clear Irq
01105                     Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE );
01106 
01107                     irqFlags = Read( REG_LR_IRQFLAGS );
01108                     if( ( irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK ) == RFLR_IRQFLAGS_PAYLOADCRCERROR )
01109                     {
01110                         // Clear Irq
01111                         Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR );
01112 
01113                         if( this->settings.LoRa.RxContinuous == false )
01114                         {
01115                             this->settings.State = RF_IDLE;
01116                         }
01117                         rxTimeoutTimer.detach( );
01118 
01119                         if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) )
01120                         {
01121                             /*this->RadioEvents->RxError( );*/
01122                             enqueueRadioEvent_RxError();
01123                         }
01124                         break;
01125                     }
01126 
01127                     this->settings.LoRaPacketHandler.SnrValue = Read( REG_LR_PKTSNRVALUE );
01128                     if( this->settings.LoRaPacketHandler.SnrValue & 0x80 ) // The SNR sign bit is 1
01129                     {
01130                         // Invert and divide by 4
01131                         snr = ( ( ~this->settings.LoRaPacketHandler.SnrValue + 1 ) & 0xFF ) >> 2;
01132                         snr = -snr;
01133                     }
01134                     else
01135                     {
01136                         // Divide by 4
01137                         snr = ( this->settings.LoRaPacketHandler.SnrValue & 0xFF ) >> 2;
01138                     }
01139 
01140                     int16_t rssi = Read( REG_LR_PKTRSSIVALUE );
01141                     if( snr < 0 )
01142                     {
01143                         this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET + rssi + ( rssi >> 4 ) +
01144                                                                       snr;
01145                     }
01146                     else
01147                     {
01148                         this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET + rssi + ( rssi >> 4 );
01149                     }
01150 
01151                     this->settings.LoRaPacketHandler.Size = Read( REG_LR_RXNBBYTES );
01152                     ReadFifo( rxtxBuffer, this->settings.LoRaPacketHandler.Size );
01153 
01154                     if( this->settings.LoRa.RxContinuous == false )
01155                     {
01156                         this->settings.State = RF_IDLE;
01157                     }
01158                     rxTimeoutTimer.detach( );
01159 
01160                     if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) )
01161                     {
01162                         /*this->RadioEvents->RxDone( rxtxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue, this->settings.LoRaPacketHandler.SnrValue );*/
01163                         enqueueRadioEvent_RxDone(rxtxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue, this->settings.LoRaPacketHandler.SnrValue);
01164                     }
01165                 }
01166                 break;
01167             default:
01168                 break;
01169             }
01170             break;
01171         case RF_TX_RUNNING:
01172             txTimeoutTimer .detach( );
01173             // TxDone interrupt
01174             switch( this->settings.Modem )
01175             {
01176             case MODEM_LORA:
01177                 // Clear Irq
01178                 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE );
01179                 // Intentional fall through
01180             case MODEM_FSK:
01181             default:
01182                 this->settings.State = RF_IDLE;
01183                 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxDone != NULL ) )
01184                 {
01185                     /*this->RadioEvents->TxDone( );*/
01186                     enqueueRadioEvent_TxDone();
01187                 }
01188                 break;
01189             }
01190             break;
01191         default:
01192             break;
01193     }
01194 }
01195 
01196 void SX1272::OnDio1Irq( void )
01197 {
01198     switch( this->settings.State )
01199     {
01200         case RF_RX_RUNNING:
01201             switch( this->settings.Modem )
01202             {
01203             case MODEM_FSK:
01204                 // FifoLevel interrupt
01205                 // Read received packet size
01206                 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
01207                 {
01208                     if( this->settings.Fsk.FixLen == false )
01209                     {
01210                         ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
01211                     }
01212                     else
01213                     {
01214                         this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
01215                     }
01216                 }
01217 
01218                 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.FifoThresh )
01219                 {
01220                     ReadFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.FifoThresh );
01221                     this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.FifoThresh;
01222                 }
01223                 else
01224                 {
01225                     ReadFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
01226                     this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
01227                 }
01228                 break;
01229             case MODEM_LORA:
01230                 // Sync time out
01231                 rxTimeoutTimer.detach( );
01232                 // Clear Irq
01233                 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXTIMEOUT );
01234 
01235                 this->settings.State = RF_IDLE;
01236                 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) )
01237                 {
01238                     /*this->RadioEvents->RxTimeout( );*/
01239                     enqueueRadioEvent_RxTimeout();
01240                 }
01241                 break;
01242             default:
01243                 break;
01244             }
01245             break;
01246         case RF_TX_RUNNING:
01247             switch( this->settings.Modem )
01248             {
01249             case MODEM_FSK:
01250                 // FifoEmpty interrupt
01251                 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.ChunkSize )
01252                 {
01253                     WriteFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.ChunkSize );
01254                     this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
01255                 }
01256                 else
01257                 {
01258                     // Write the last chunk of data
01259                     WriteFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
01260                     this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes;
01261                 }
01262                 break;
01263             case MODEM_LORA:
01264                 break;
01265             default:
01266                 break;
01267             }
01268             break;
01269         default:
01270             break;
01271     }
01272 }
01273 
01274 void SX1272::OnDio2Irq( void )
01275 {
01276     switch( this->settings.State )
01277     {
01278         case RF_RX_RUNNING:
01279             switch( this->settings.Modem )
01280             {
01281             case MODEM_FSK:
01282                 // Checks if DIO4 is connected. If it is not PreambleDtected is set to true.
01283                 if( this->dioIrq [4] == NULL )
01284                 {
01285                     this->settings.FskPacketHandler.PreambleDetected = true;
01286                 }
01287 
01288                 if( ( this->settings.FskPacketHandler.PreambleDetected == true ) && ( this->settings.FskPacketHandler.SyncWordDetected == false ) )
01289                 {
01290                     rxTimeoutSyncWord.detach( );
01291 
01292                     this->settings.FskPacketHandler.SyncWordDetected = true;
01293 
01294                     this->settings.FskPacketHandler.RssiValue = -( Read( REG_RSSIVALUE ) >> 1 );
01295 
01296                     this->settings.FskPacketHandler.AfcValue = ( int32_t )( double )( ( ( uint16_t )Read( REG_AFCMSB ) << 8 ) |
01297                                                                            ( uint16_t )Read( REG_AFCLSB ) ) *
01298                                                                            ( double )FREQ_STEP;
01299                     this->settings.FskPacketHandler.RxGain = ( Read( REG_LNA ) >> 5 ) & 0x07;
01300                 }
01301                 break;
01302             case MODEM_LORA:
01303                 if( this->settings.LoRa.FreqHopOn == true )
01304                 {
01305                     // Clear Irq
01306                     Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
01307 
01308                     if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) )
01309                     {
01310                         /*this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );*/
01311                         enqueueRadioEvent_FhssChangeChannel(( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
01312                     }
01313                 }
01314                 break;
01315             default:
01316                 break;
01317             }
01318             break;
01319         case RF_TX_RUNNING:
01320             switch( this->settings.Modem )
01321             {
01322             case MODEM_FSK:
01323                 break;
01324             case MODEM_LORA:
01325                 if( this->settings.LoRa.FreqHopOn == true )
01326                 {
01327                     // Clear Irq
01328                     Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
01329 
01330                     if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) )
01331                     {
01332                         /*this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );*/
01333                         enqueueRadioEvent_FhssChangeChannel(( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ));
01334                     }
01335                 }
01336                 break;
01337             default:
01338                 break;
01339             }
01340             break;
01341         default:
01342             break;
01343     }
01344 }
01345 
01346 void SX1272::OnDio3Irq( void )
01347 {
01348     switch( this->settings.Modem )
01349     {
01350     case MODEM_FSK:
01351         break;
01352     case MODEM_LORA:
01353         if( ( Read( REG_LR_IRQFLAGS ) & RFLR_IRQFLAGS_CADDETECTED ) == RFLR_IRQFLAGS_CADDETECTED )
01354         {
01355             // Clear Irq
01356             Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED | RFLR_IRQFLAGS_CADDONE );
01357             if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) )
01358             {
01359                 /*this->RadioEvents->CadDone( true );*/
01360                 enqueueRadioEvent_CadDone(true);
01361             }
01362         }
01363         else
01364         {
01365             // Clear Irq
01366             Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE );
01367             if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) )
01368             {
01369                 /*this->RadioEvents->CadDone( false );*/
01370                 enqueueRadioEvent_CadDone(false);
01371             }
01372         }
01373         break;
01374     default:
01375         break;
01376     }
01377 }
01378 
01379 void SX1272::OnDio4Irq( void )
01380 {
01381     switch( this->settings.Modem )
01382     {
01383     case MODEM_FSK:
01384         {
01385             if( this->settings.FskPacketHandler.PreambleDetected == false )
01386             {
01387                 this->settings.FskPacketHandler.PreambleDetected = true;
01388             }
01389         }
01390         break;
01391     case MODEM_LORA:
01392         break;
01393     default:
01394         break;
01395     }
01396 }
01397 
01398 void SX1272::OnDio5Irq( void )
01399 {
01400     switch( this->settings.Modem )
01401     {
01402     case MODEM_FSK:
01403         break;
01404     case MODEM_LORA:
01405         break;
01406     default:
01407         break;
01408     }
01409 }
01410 
01411 // Inizio nuova parte per RTOS
01412 
01413 void SX1272::enqueueOnTimeoutIrq()
01414 {
01415     _eq_events->call(this, &SX1272::OnTimeoutIrq);
01416 }
01417 
01418 void SX1272::radioEvent_RxTimeout()
01419 {
01420     this->RadioEvents->RxTimeout( );
01421 }
01422 
01423 void SX1272::enqueueRadioEvent_RxTimeout()
01424 {
01425      _eq_events->call(this, &SX1272::radioEvent_RxTimeout);
01426 }
01427 
01428 void SX1272::radioEvent_TxTimeout()
01429 {
01430     this->RadioEvents->TxTimeout( );
01431 }
01432 
01433 void SX1272::enqueueRadioEvent_TxTimeout()
01434 {
01435      _eq_events->call(this, &SX1272::radioEvent_TxTimeout);
01436 }
01437 
01438 void SX1272::radioEvent_RxError()
01439 {
01440     this->RadioEvents->RxError( );
01441 }
01442 
01443 void SX1272::enqueueRadioEvent_RxError()
01444 {
01445      _eq_events->call(this, &SX1272::radioEvent_RxError);
01446 }
01447 
01448 void SX1272::radioEvent_RxDone(uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr)
01449 {
01450     this->RadioEvents->RxDone(payload, size, rssi, snr);
01451 }
01452 
01453 void SX1272::enqueueRadioEvent_RxDone(uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr)
01454 {
01455      _eq_events->call(this, &SX1272::radioEvent_RxDone, payload, size, rssi, snr);
01456 }
01457 
01458 void SX1272::radioEvent_TxDone()
01459 {
01460     this->RadioEvents->TxDone();
01461 }
01462 
01463 void SX1272::enqueueRadioEvent_TxDone()
01464 {
01465      _eq_events->call(this, &SX1272::radioEvent_TxDone);
01466 }
01467 
01468 void SX1272::radioEvent_FhssChangeChannel(uint8_t currentChannel)
01469 {
01470     this->RadioEvents->FhssChangeChannel(currentChannel);
01471 }
01472 
01473 void SX1272::enqueueRadioEvent_FhssChangeChannel(uint8_t currentChannel)
01474 {
01475     _eq_events->call(this, &SX1272::radioEvent_FhssChangeChannel, currentChannel);
01476 }
01477 
01478 void SX1272::radioEvent_CadDone(bool channelActivityDetected)
01479 {
01480     this->RadioEvents->CadDone(channelActivityDetected);
01481 }
01482 
01483 void SX1272::enqueueRadioEvent_CadDone(bool channelActivityDetected)
01484 {
01485     _eq_events->call(this, &SX1272::radioEvent_CadDone, channelActivityDetected);
01486 }
01487 
01488 void SX1272::enqueueOnDio0Irq()
01489 {
01490     _eq_events->call(this, &SX1272::OnDio0Irq);
01491 }
01492 
01493 void SX1272::enqueueOnDio1Irq()
01494 {
01495     _eq_events->call(this, &SX1272::OnDio1Irq);
01496 }
01497 
01498 void SX1272::enqueueOnDio2Irq()
01499 {
01500     _eq_events->call(this, &SX1272::OnDio2Irq);
01501 }
01502 
01503 void SX1272::enqueueOnDio3Irq()
01504 {
01505     _eq_events->call(this, &SX1272::OnDio3Irq);
01506 }
01507 
01508 void SX1272::enqueueOnDio4Irq()
01509 {
01510     _eq_events->call(this, &SX1272::OnDio4Irq);
01511 }
01512 
01513 void SX1272::enqueueOnDio5Irq()
01514 {
01515     /* NULL */
01516 }
01517 
01518 // Fine nuova parte per RTOS