Mac Lobdell / FXOS8700CQ

An in-development library to provide effective access to all features of the FXOS8700CQ on the FRDM-K64F mbed-enabled development board. As of 28 May 2014 1325EDT, the code should be generally usable and modifiable.

Dependents:   FXOS8700CQ_Int_example 4_accelerometer 4_accelerometer shake_to_wake

Fork of FXOS8700CQ by Thomas Murphy

FXOS8700CQ.h@5:7bdb0d5e5287, 2016-01-10 (annotated)

Committer:
maclobdell
Date:
Sun Jan 10 17:45:05 2016 +0000
Revision:
5:7bdb0d5e5287
Parent:
4:e2fe752b881e 
added interrupt and motion detection support

Who changed what in which revision?

UserRevisionLine numberNew contents of line
trm 0:cf6299acfe98 1 #ifndef FXOS8700CQ_H
trm 0:cf6299acfe98 2 #define FXOS8700CQ_H
trm 0:cf6299acfe98 3
trm 0:cf6299acfe98 4 #include "mbed.h" // Building this for the mbed platform
trm 0:cf6299acfe98 5
trm 0:cf6299acfe98 6 #define I2C_400K 400000
trm 0:cf6299acfe98 7
trm 0:cf6299acfe98 8 // FXOS8700CQ I2C address
trm 0:cf6299acfe98 9 #define FXOS8700CQ_SLAVE_ADDR0 (0x1E<<1) // with pins SA0=0, SA1=0
trm 0:cf6299acfe98 10 #define FXOS8700CQ_SLAVE_ADDR1 (0x1D<<1) // with pins SA0=1, SA1=0
trm 0:cf6299acfe98 11 #define FXOS8700CQ_SLAVE_ADDR2 (0x1C<<1) // with pins SA0=0, SA1=1
trm 0:cf6299acfe98 12 #define FXOS8700CQ_SLAVE_ADDR3 (0x1F<<1) // with pins SA0=1, SA1=1
trm 0:cf6299acfe98 13
trm 0:cf6299acfe98 14 // FXOS8700CQ internal register addresses
trm 0:cf6299acfe98 15 #define FXOS8700CQ_STATUS 0x00
trm 0:cf6299acfe98 16 #define FXOS8700CQ_OUT_X_MSB 0x01
trm 0:cf6299acfe98 17 #define FXOS8700CQ_WHOAMI 0x0D
trm 2:4c2f8a3549a9 18 #define FXOS8700CQ_M_OUT_X_MSB 0x33
trm 2:4c2f8a3549a9 19
trm 0:cf6299acfe98 20 #define FXOS8700CQ_XYZ_DATA_CFG 0x0E
trm 2:4c2f8a3549a9 21
trm 0:cf6299acfe98 22 #define FXOS8700CQ_CTRL_REG1 0x2A
trm 0:cf6299acfe98 23 #define FXOS8700CQ_CTRL_REG2 0x2B
trm 0:cf6299acfe98 24 #define FXOS8700CQ_CTRL_REG3 0x2C
trm 0:cf6299acfe98 25 #define FXOS8700CQ_CTRL_REG4 0x2D
trm 0:cf6299acfe98 26 #define FXOS8700CQ_CTRL_REG5 0x2E
trm 0:cf6299acfe98 27
trm 0:cf6299acfe98 28 #define FXOS8700CQ_M_CTRL_REG1 0x5B
trm 0:cf6299acfe98 29 #define FXOS8700CQ_M_CTRL_REG2 0x5C
trm 0:cf6299acfe98 30 #define FXOS8700CQ_M_CTRL_REG3 0x5D
trm 0:cf6299acfe98 31
maclobdell 5:7bdb0d5e5287 32 /* start MPL additions */
maclobdell 5:7bdb0d5e5287 33 //MPL interrupts
maclobdell 5:7bdb0d5e5287 34 #define FXOS8700CQ_INT_SOURCE 0x0C
maclobdell 5:7bdb0d5e5287 35 //#define FXOS8700CQ_CTRL_REG2 0x2B //bit 2 turns on auto-sleep
maclobdell 5:7bdb0d5e5287 36 //#define FXOS8700CQ_CTRL_REG3 0x2C //interrupt control register
maclobdell 5:7bdb0d5e5287 37 //#define FXOS8700CQ_CTRL_REG4 0x2D //interrupt enable register
maclobdell 5:7bdb0d5e5287 38 //#define FXOS8700CQ_CTRL_REG5 0x2E //interrupt routing config register, by default all routed to INT2
maclobdell 5:7bdb0d5e5287 39
maclobdell 5:7bdb0d5e5287 40 //MPL motion detection
maclobdell 5:7bdb0d5e5287 41 #define FXOS8700CQ_A_FFMT_CFG 0x15
maclobdell 5:7bdb0d5e5287 42 #define FXOS8700CQ_A_FFMT_SRC 0x16
maclobdell 5:7bdb0d5e5287 43 #define FXOS8700CQ_A_FFMT_THS 0x17
maclobdell 5:7bdb0d5e5287 44 #define FXOS8700CQ_A_FFMT_COUNT 0x18
maclobdell 5:7bdb0d5e5287 45 #define FXOS8700CQ_A_FFMT_THS_X_MSB 0x73
maclobdell 5:7bdb0d5e5287 46 #define FXOS8700CQ_A_FFMT_THS_X_LSB 0x74
maclobdell 5:7bdb0d5e5287 47 #define FXOS8700CQ_A_FFMT_THS_Y_MSB 0x75
maclobdell 5:7bdb0d5e5287 48 #define FXOS8700CQ_A_FFMT_THS_Y_LSB 0x76
maclobdell 5:7bdb0d5e5287 49 #define FXOS8700CQ_A_FFMT_THS_Z_MSB 0x77
maclobdell 5:7bdb0d5e5287 50 #define FXOS8700CQ_A_FFMT_THS_Z_LSB 0x78
maclobdell 5:7bdb0d5e5287 51 /* end MPL additions */
maclobdell 5:7bdb0d5e5287 52
trm 2:4c2f8a3549a9 53 // FXOS8700CQ configuration macros, per register
trm 2:4c2f8a3549a9 54
trm 2:4c2f8a3549a9 55 #define FXOS8700CQ_CTRL_REG1_ASLP_RATE2(x) (x << 6) // x is 2-bit
trm 2:4c2f8a3549a9 56 #define FXOS8700CQ_CTRL_REG1_DR3(x) (x << 3) // x is 3-bit
trm 2:4c2f8a3549a9 57 #define FXOS8700CQ_CTRL_REG1_LNOISE (1 << 2)
trm 2:4c2f8a3549a9 58 #define FXOS8700CQ_CTRL_REG1_F_READ (1 << 1)
trm 2:4c2f8a3549a9 59 #define FXOS8700CQ_CTRL_REG1_ACTIVE (1 << 0)
trm 2:4c2f8a3549a9 60
trm 2:4c2f8a3549a9 61 #define FXOS8700CQ_CTRL_REG2_ST (1 << 7)
trm 2:4c2f8a3549a9 62 #define FXOS8700CQ_CTRL_REG2_RST (1 << 6)
trm 2:4c2f8a3549a9 63 #define FXOS8700CQ_CTRL_REG2_SMODS2(x) (x << 3) // x is 2-bit
trm 2:4c2f8a3549a9 64 #define FXOS8700CQ_CTRL_REG2_SLPE (1 << 2)
trm 2:4c2f8a3549a9 65 #define FXOS8700CQ_CTRL_REG2_MODS2(x) (x << 0) // x is 2-bit
trm 2:4c2f8a3549a9 66
trm 2:4c2f8a3549a9 67 #define FXOS8700CQ_CTRL_REG3_FIFO_GATE (1 << 7)
trm 2:4c2f8a3549a9 68 #define FXOS8700CQ_CTRL_REG3_WAKE_TRANS (1 << 6)
trm 2:4c2f8a3549a9 69 #define FXOS8700CQ_CTRL_REG3_WAKE_LNDPRT (1 << 5)
trm 2:4c2f8a3549a9 70 #define FXOS8700CQ_CTRL_REG3_WAKE_PULSE (1 << 4)
trm 2:4c2f8a3549a9 71 #define FXOS8700CQ_CTRL_REG3_WAKE_FFMT (1 << 3)
trm 2:4c2f8a3549a9 72 #define FXOS8700CQ_CTRL_REG3_WAKE_A_VECM (1 << 2)
trm 2:4c2f8a3549a9 73 #define FXOS8700CQ_CTRL_REG3_IPOL (1 << 1)
trm 2:4c2f8a3549a9 74 #define FXOS8700CQ_CTRL_REG3_PP_OD (1 << 0)
trm 2:4c2f8a3549a9 75
trm 2:4c2f8a3549a9 76 #define FXOS8700CQ_CTRL_REG4_INT_EN_ASLP (1 << 7)
trm 2:4c2f8a3549a9 77 #define FXOS8700CQ_CTRL_REG4_INT_EN_FIFO (1 << 6)
trm 2:4c2f8a3549a9 78 #define FXOS8700CQ_CTRL_REG4_INT_EN_TRANS (1 << 5)
trm 2:4c2f8a3549a9 79 #define FXOS8700CQ_CTRL_REG4_INT_EN_LNDPRT (1 << 4)
trm 2:4c2f8a3549a9 80 #define FXOS8700CQ_CTRL_REG4_INT_EN_PULSE (1 << 3)
trm 2:4c2f8a3549a9 81 #define FXOS8700CQ_CTRL_REG4_INT_EN_FFMT (1 << 2)
trm 2:4c2f8a3549a9 82 #define FXOS8700CQ_CTRL_REG4_INT_EN_A_VECM (1 << 1)
trm 2:4c2f8a3549a9 83 #define FXOS8700CQ_CTRL_REG4_INT_EN_DRDY (1 << 0)
trm 2:4c2f8a3549a9 84
trm 2:4c2f8a3549a9 85 #define FXOS8700CQ_CTRL_REG5_INT_CFG_ASLP (1 << 7)
trm 2:4c2f8a3549a9 86 #define FXOS8700CQ_CTRL_REG5_INT_CFG_FIFO (1 << 6)
trm 2:4c2f8a3549a9 87 #define FXOS8700CQ_CTRL_REG5_INT_CFG_TRANS (1 << 5)
trm 2:4c2f8a3549a9 88 #define FXOS8700CQ_CTRL_REG5_INT_CFG_LNDPRT (1 << 4)
trm 2:4c2f8a3549a9 89 #define FXOS8700CQ_CTRL_REG5_INT_CFG_PULSE (1 << 3)
trm 2:4c2f8a3549a9 90 #define FXOS8700CQ_CTRL_REG5_INT_CFG_FFMT (1 << 2)
trm 2:4c2f8a3549a9 91 #define FXOS8700CQ_CTRL_REG5_INT_CFG_A_VECM (1 << 1)
trm 2:4c2f8a3549a9 92 #define FXOS8700CQ_CTRL_REG5_INT_CFG_DRDY (1 << 0)
trm 2:4c2f8a3549a9 93
trm 2:4c2f8a3549a9 94 #define FXOS8700CQ_XYZ_DATA_CFG_HPF_OUT (1 << 4)
trm 2:4c2f8a3549a9 95 #define FXOS8700CQ_XYZ_DATA_CFG_FS2(x) (x << 0) // x is 2-bit
trm 2:4c2f8a3549a9 96
trm 2:4c2f8a3549a9 97 #define FXOS8700CQ_M_CTRL_REG1_M_ACAL (1 << 7)
trm 2:4c2f8a3549a9 98 #define FXOS8700CQ_M_CTRL_REG1_M_RST (1 << 6)
trm 2:4c2f8a3549a9 99 #define FXOS8700CQ_M_CTRL_REG1_M_OST (1 << 5)
trm 2:4c2f8a3549a9 100 #define FXOS8700CQ_M_CTRL_REG1_MO_OS3(x) (x << 2) // x is 3-bit
trm 2:4c2f8a3549a9 101 #define FXOS8700CQ_M_CTRL_REG1_M_HMS2(x) (x << 0) // x is 2-bit
trm 2:4c2f8a3549a9 102
trm 2:4c2f8a3549a9 103 #define FXOS8700CQ_M_CTRL_REG2_HYB_AUTOINC_MODE (1 << 5)
trm 2:4c2f8a3549a9 104 #define FXOS8700CQ_M_CTRL_REG2_M_MAXMIN_DIS (1 << 4)
trm 2:4c2f8a3549a9 105 #define FXOS8700CQ_M_CTRL_REG2_M_MAXMIN_DIS_THS (1 << 3)
trm 2:4c2f8a3549a9 106 #define FXOS8700CQ_M_CTRL_REG2_M_MAXMIN_RST (1 << 2)
trm 2:4c2f8a3549a9 107 #define FXOS8700CQ_M_CTRL_REG2_M_RST_CNT2(x) (x << 0) // x is 2-bit
trm 2:4c2f8a3549a9 108
trm 2:4c2f8a3549a9 109 #define FXOS8700CQ_M_CTRL_REG3_M_RAW (1 << 7)
trm 2:4c2f8a3549a9 110 #define FXOS8700CQ_M_CTRL_REG3_M_ASLP_OS3(x) (x << 4) // x is 3-bit
trm 2:4c2f8a3549a9 111 #define FXOS8700CQ_M_CTRL_REG3_M_THS_XYZ_UPDATE (1 << 3)
trm 2:4c2f8a3549a9 112 #define FXOS8700CQ_M_CTRL_REG3_M_ST_Z (1 << 2)
trm 2:4c2f8a3549a9 113 #define FXOS8700CQ_M_CTRL_REG3_M_ST_XY2(x) (x << 0) // x is 2-bit
trm 2:4c2f8a3549a9 114
trm 0:cf6299acfe98 115 // FXOS8700CQ WHOAMI production register value
trm 0:cf6299acfe98 116 #define FXOS8700CQ_WHOAMI_VAL 0xC7
trm 0:cf6299acfe98 117
trm 0:cf6299acfe98 118 // 6 channels of two bytes = 12 bytes; read from FXOS8700CQ_OUT_X_MSB
trm 0:cf6299acfe98 119 #define FXOS8700CQ_READ_LEN 12
trm 0:cf6299acfe98 120
trm 0:cf6299acfe98 121 // For processing the accelerometer data to right-justified 2's complement
trm 0:cf6299acfe98 122 #define UINT14_MAX 16383
trm 0:cf6299acfe98 123
trm 0:cf6299acfe98 124 // TODO: struct to hold the data out of the sensor
trm 0:cf6299acfe98 125 typedef struct {
trm 0:cf6299acfe98 126 int16_t x;
trm 0:cf6299acfe98 127 int16_t y;
trm 0:cf6299acfe98 128 int16_t z;
trm 0:cf6299acfe98 129 } SRAWDATA;
trm 0:cf6299acfe98 130
trm 1:3ec7e2676e48 131
trm 1:3ec7e2676e48 132 /**
trm 1:3ec7e2676e48 133 * A driver on top of mbed-I2C to operate the FXOS8700CQ accelerometer/magnetometer
trm 1:3ec7e2676e48 134 * on the FRDM-K64F.
trm 1:3ec7e2676e48 135 *
trm 3:2ce85aa45d7d 136 * Code has been completed, but likely not optimized and potentially buggy.
trm 1:3ec7e2676e48 137 */
trm 0:cf6299acfe98 138 class FXOS8700CQ
trm 0:cf6299acfe98 139 {
trm 0:cf6299acfe98 140 public:
trm 0:cf6299acfe98 141 /**
trm 0:cf6299acfe98 142 * FXOS8700CQ constructor
trm 0:cf6299acfe98 143 *
trm 0:cf6299acfe98 144 * @param sda SDA pin
trm 0:cf6299acfe98 145 * @param sdl SCL pin
trm 0:cf6299acfe98 146 * @param addr address of the I2C peripheral in (7-bit << 1) form
trm 0:cf6299acfe98 147 */
trm 0:cf6299acfe98 148 FXOS8700CQ(PinName sda, PinName scl, int addr);
trm 0:cf6299acfe98 149
trm 0:cf6299acfe98 150 /**
trm 0:cf6299acfe98 151 * FXOS8700CQ destructor
trm 0:cf6299acfe98 152 */
trm 2:4c2f8a3549a9 153 ~FXOS8700CQ(void);
trm 0:cf6299acfe98 154
trm 0:cf6299acfe98 155 void enable(void);
trm 0:cf6299acfe98 156 void disable(void);
trm 3:2ce85aa45d7d 157
trm 3:2ce85aa45d7d 158 /**
trm 3:2ce85aa45d7d 159 * @return the contents of device register FXOS8700CQ_WHOAMI 0x0D,
trm 3:2ce85aa45d7d 160 * should be FXOS8700CQ_WHOAMI_VAL 0xC7
trm 3:2ce85aa45d7d 161 */
trm 0:cf6299acfe98 162 uint8_t get_whoami(void);
trm 3:2ce85aa45d7d 163
trm 3:2ce85aa45d7d 164 /**
trm 3:2ce85aa45d7d 165 * @return the contents of device register FXOS8700CQ_STATUS 0x00
trm 3:2ce85aa45d7d 166 */
trm 0:cf6299acfe98 167 uint8_t status(void);
trm 3:2ce85aa45d7d 168
trm 1:3ec7e2676e48 169 /**
trm 1:3ec7e2676e48 170 * Data retrieval from the FXOS8700CQ
trm 1:3ec7e2676e48 171 *
trm 1:3ec7e2676e48 172 * @param accel_data destination XYZ accelerometer data struct
trm 1:3ec7e2676e48 173 * @param magn_data destination XYZ magnetometer data struct
trm 2:4c2f8a3549a9 174 * @return 0 on success, non-zero on failure
trm 1:3ec7e2676e48 175 */
trm 2:4c2f8a3549a9 176 uint8_t get_data(SRAWDATA *accel_data, SRAWDATA *magn_data);
trm 3:2ce85aa45d7d 177
trm 2:4c2f8a3549a9 178 /**
trm 2:4c2f8a3549a9 179 * Retrieve the full-range scale value of the accelerometer
trm 3:2ce85aa45d7d 180 *
trm 2:4c2f8a3549a9 181 * @return 2, 4, or 8, depending on part configuration; 0 on error
trm 2:4c2f8a3549a9 182 */
trm 2:4c2f8a3549a9 183 uint8_t get_accel_scale(void);
trm 0:cf6299acfe98 184
maclobdell 5:7bdb0d5e5287 185 /**
maclobdell 5:7bdb0d5e5287 186 * configure external interrupts
maclobdell 5:7bdb0d5e5287 187 *
maclobdell 5:7bdb0d5e5287 188 * @return 2, 4, or 8, depending on part configuration; 0 on error
maclobdell 5:7bdb0d5e5287 189 */
maclobdell 5:7bdb0d5e5287 190 uint8_t config_int(void);
maclobdell 5:7bdb0d5e5287 191
maclobdell 5:7bdb0d5e5287 192 /**
maclobdell 5:7bdb0d5e5287 193 * configure feature (tap detection, motion detection, etc)
maclobdell 5:7bdb0d5e5287 194 *
maclobdell 5:7bdb0d5e5287 195 * @return 2, 4, or 8, depending on part configuration; 0 on error
maclobdell 5:7bdb0d5e5287 196 */
maclobdell 5:7bdb0d5e5287 197 uint8_t config_feature(void);
trm 0:cf6299acfe98 198
maclobdell 5:7bdb0d5e5287 199 /**
maclobdell 5:7bdb0d5e5287 200 * clear interrupt
maclobdell 5:7bdb0d5e5287 201 *
maclobdell 5:7bdb0d5e5287 202 * @return 2, 4, or 8, depending on part configuration; 0 on error
maclobdell 5:7bdb0d5e5287 203 */
maclobdell 5:7bdb0d5e5287 204 void clear_int(void);
trm 0:cf6299acfe98 205
trm 0:cf6299acfe98 206 private:
trm 0:cf6299acfe98 207 I2C dev_i2c; // instance of the mbed I2C class
trm 0:cf6299acfe98 208 uint8_t dev_addr; // Device I2C address, in (7-bit << 1) form
trm 3:2ce85aa45d7d 209 bool enabled; // keep track of enable bit of device
trm 0:cf6299acfe98 210
trm 0:cf6299acfe98 211 // I2C helper methods
trm 0:cf6299acfe98 212 void read_regs(int reg_addr, uint8_t* data, int len);
trm 0:cf6299acfe98 213 void write_regs(uint8_t* data, int len);
trm 0:cf6299acfe98 214
trm 0:cf6299acfe98 215 };
trm 0:cf6299acfe98 216
trm 0:cf6299acfe98 217 #endif