Zhen Liu / Mbed 2 deprecated HW1_extraD

Extra problem 4 for HW 1

Dependencies:   mbed

PowerControl/EthernetPowerControl.h@0:febabd1da7f4, 2015-02-18 (annotated)

Committer:
lzzcd001
Date:
Wed Feb 18 14:49:06 2015 +0000
Revision:
0:febabd1da7f4
Extra problem 4 for HW 1

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lzzcd001 0:febabd1da7f4 1 /* mbed PowerControl Library
lzzcd001 0:febabd1da7f4 2 * Copyright (c) 2010 Michael Wei
lzzcd001 0:febabd1da7f4 3 */
lzzcd001 0:febabd1da7f4 4
lzzcd001 0:febabd1da7f4 5 #ifndef MBED_POWERCONTROL_ETH_H
lzzcd001 0:febabd1da7f4 6 #define MBED_POWERCONTROL_ETH_H
lzzcd001 0:febabd1da7f4 7
lzzcd001 0:febabd1da7f4 8 #include "mbed.h"
lzzcd001 0:febabd1da7f4 9 #include "PowerControl.h"
lzzcd001 0:febabd1da7f4 10
lzzcd001 0:febabd1da7f4 11 #define PHY_REG_BMCR_POWERDOWN 0xB
lzzcd001 0:febabd1da7f4 12 #define PHY_REG_EDCR_ENABLE 0xF
lzzcd001 0:febabd1da7f4 13
lzzcd001 0:febabd1da7f4 14
lzzcd001 0:febabd1da7f4 15 void EMAC_Init();
lzzcd001 0:febabd1da7f4 16 static unsigned short read_PHY (unsigned int PhyReg);
lzzcd001 0:febabd1da7f4 17 static void write_PHY (unsigned int PhyReg, unsigned short Value);
lzzcd001 0:febabd1da7f4 18
lzzcd001 0:febabd1da7f4 19 void PHY_PowerDown(void);
lzzcd001 0:febabd1da7f4 20 void PHY_PowerUp(void);
lzzcd001 0:febabd1da7f4 21 void PHY_EnergyDetect_Enable(void);
lzzcd001 0:febabd1da7f4 22 void PHY_EnergyDetect_Disable(void);
lzzcd001 0:febabd1da7f4 23
lzzcd001 0:febabd1da7f4 24 //From NXP Sample Code .... Probably from KEIL sample code
lzzcd001 0:febabd1da7f4 25 /* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
lzzcd001 0:febabd1da7f4 26 #define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */
lzzcd001 0:febabd1da7f4 27 #define NUM_TX_FRAG 3 /* Num.of TX Fragments 3*1536= 4.6kB */
lzzcd001 0:febabd1da7f4 28 #define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */
lzzcd001 0:febabd1da7f4 29
lzzcd001 0:febabd1da7f4 30 #define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */
lzzcd001 0:febabd1da7f4 31
lzzcd001 0:febabd1da7f4 32 /* EMAC variables located in 16K Ethernet SRAM */
lzzcd001 0:febabd1da7f4 33 #define RX_DESC_BASE 0x20080000
lzzcd001 0:febabd1da7f4 34 #define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8)
lzzcd001 0:febabd1da7f4 35 #define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8)
lzzcd001 0:febabd1da7f4 36 #define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8)
lzzcd001 0:febabd1da7f4 37 #define RX_BUF_BASE (TX_STAT_BASE + NUM_TX_FRAG*4)
lzzcd001 0:febabd1da7f4 38 #define TX_BUF_BASE (RX_BUF_BASE + NUM_RX_FRAG*ETH_FRAG_SIZE)
lzzcd001 0:febabd1da7f4 39
lzzcd001 0:febabd1da7f4 40 /* RX and TX descriptor and status definitions. */
lzzcd001 0:febabd1da7f4 41 #define RX_DESC_PACKET(i) (*(unsigned int *)(RX_DESC_BASE + 8*i))
lzzcd001 0:febabd1da7f4 42 #define RX_DESC_CTRL(i) (*(unsigned int *)(RX_DESC_BASE+4 + 8*i))
lzzcd001 0:febabd1da7f4 43 #define RX_STAT_INFO(i) (*(unsigned int *)(RX_STAT_BASE + 8*i))
lzzcd001 0:febabd1da7f4 44 #define RX_STAT_HASHCRC(i) (*(unsigned int *)(RX_STAT_BASE+4 + 8*i))
lzzcd001 0:febabd1da7f4 45 #define TX_DESC_PACKET(i) (*(unsigned int *)(TX_DESC_BASE + 8*i))
lzzcd001 0:febabd1da7f4 46 #define TX_DESC_CTRL(i) (*(unsigned int *)(TX_DESC_BASE+4 + 8*i))
lzzcd001 0:febabd1da7f4 47 #define TX_STAT_INFO(i) (*(unsigned int *)(TX_STAT_BASE + 4*i))
lzzcd001 0:febabd1da7f4 48 #define RX_BUF(i) (RX_BUF_BASE + ETH_FRAG_SIZE*i)
lzzcd001 0:febabd1da7f4 49 #define TX_BUF(i) (TX_BUF_BASE + ETH_FRAG_SIZE*i)
lzzcd001 0:febabd1da7f4 50
lzzcd001 0:febabd1da7f4 51 /* MAC Configuration Register 1 */
lzzcd001 0:febabd1da7f4 52 #define MAC1_REC_EN 0x00000001 /* Receive Enable */
lzzcd001 0:febabd1da7f4 53 #define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */
lzzcd001 0:febabd1da7f4 54 #define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */
lzzcd001 0:febabd1da7f4 55 #define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */
lzzcd001 0:febabd1da7f4 56 #define MAC1_LOOPB 0x00000010 /* Loop Back Mode */
lzzcd001 0:febabd1da7f4 57 #define MAC1_RES_TX 0x00000100 /* Reset TX Logic */
lzzcd001 0:febabd1da7f4 58 #define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */
lzzcd001 0:febabd1da7f4 59 #define MAC1_RES_RX 0x00000400 /* Reset RX Logic */
lzzcd001 0:febabd1da7f4 60 #define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */
lzzcd001 0:febabd1da7f4 61 #define MAC1_SIM_RES 0x00004000 /* Simulation Reset */
lzzcd001 0:febabd1da7f4 62 #define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */
lzzcd001 0:febabd1da7f4 63
lzzcd001 0:febabd1da7f4 64 /* MAC Configuration Register 2 */
lzzcd001 0:febabd1da7f4 65 #define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */
lzzcd001 0:febabd1da7f4 66 #define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */
lzzcd001 0:febabd1da7f4 67 #define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */
lzzcd001 0:febabd1da7f4 68 #define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */
lzzcd001 0:febabd1da7f4 69 #define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */
lzzcd001 0:febabd1da7f4 70 #define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */
lzzcd001 0:febabd1da7f4 71 #define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */
lzzcd001 0:febabd1da7f4 72 #define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */
lzzcd001 0:febabd1da7f4 73 #define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */
lzzcd001 0:febabd1da7f4 74 #define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */
lzzcd001 0:febabd1da7f4 75 #define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */
lzzcd001 0:febabd1da7f4 76 #define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */
lzzcd001 0:febabd1da7f4 77 #define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */
lzzcd001 0:febabd1da7f4 78
lzzcd001 0:febabd1da7f4 79 /* Back-to-Back Inter-Packet-Gap Register */
lzzcd001 0:febabd1da7f4 80 #define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */
lzzcd001 0:febabd1da7f4 81 #define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */
lzzcd001 0:febabd1da7f4 82
lzzcd001 0:febabd1da7f4 83 /* Non Back-to-Back Inter-Packet-Gap Register */
lzzcd001 0:febabd1da7f4 84 #define IPGR_DEF 0x00000012 /* Recommended value */
lzzcd001 0:febabd1da7f4 85
lzzcd001 0:febabd1da7f4 86 /* Collision Window/Retry Register */
lzzcd001 0:febabd1da7f4 87 #define CLRT_DEF 0x0000370F /* Default value */
lzzcd001 0:febabd1da7f4 88
lzzcd001 0:febabd1da7f4 89 /* PHY Support Register */
lzzcd001 0:febabd1da7f4 90 #define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */
lzzcd001 0:febabd1da7f4 91 #define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */
lzzcd001 0:febabd1da7f4 92
lzzcd001 0:febabd1da7f4 93 /* Test Register */
lzzcd001 0:febabd1da7f4 94 #define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */
lzzcd001 0:febabd1da7f4 95 #define TEST_TST_PAUSE 0x00000002 /* Test Pause */
lzzcd001 0:febabd1da7f4 96 #define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */
lzzcd001 0:febabd1da7f4 97
lzzcd001 0:febabd1da7f4 98 /* MII Management Configuration Register */
lzzcd001 0:febabd1da7f4 99 #define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */
lzzcd001 0:febabd1da7f4 100 #define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */
lzzcd001 0:febabd1da7f4 101 #define MCFG_CLK_SEL 0x0000001C /* Clock Select Mask */
lzzcd001 0:febabd1da7f4 102 #define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */
lzzcd001 0:febabd1da7f4 103
lzzcd001 0:febabd1da7f4 104 /* MII Management Command Register */
lzzcd001 0:febabd1da7f4 105 #define MCMD_READ 0x00000001 /* MII Read */
lzzcd001 0:febabd1da7f4 106 #define MCMD_SCAN 0x00000002 /* MII Scan continuously */
lzzcd001 0:febabd1da7f4 107
lzzcd001 0:febabd1da7f4 108 #define MII_WR_TOUT 0x00050000 /* MII Write timeout count */
lzzcd001 0:febabd1da7f4 109 #define MII_RD_TOUT 0x00050000 /* MII Read timeout count */
lzzcd001 0:febabd1da7f4 110
lzzcd001 0:febabd1da7f4 111 /* MII Management Address Register */
lzzcd001 0:febabd1da7f4 112 #define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */
lzzcd001 0:febabd1da7f4 113 #define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */
lzzcd001 0:febabd1da7f4 114
lzzcd001 0:febabd1da7f4 115 /* MII Management Indicators Register */
lzzcd001 0:febabd1da7f4 116 #define MIND_BUSY 0x00000001 /* MII is Busy */
lzzcd001 0:febabd1da7f4 117 #define MIND_SCAN 0x00000002 /* MII Scanning in Progress */
lzzcd001 0:febabd1da7f4 118 #define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */
lzzcd001 0:febabd1da7f4 119 #define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */
lzzcd001 0:febabd1da7f4 120
lzzcd001 0:febabd1da7f4 121 /* Command Register */
lzzcd001 0:febabd1da7f4 122 #define CR_RX_EN 0x00000001 /* Enable Receive */
lzzcd001 0:febabd1da7f4 123 #define CR_TX_EN 0x00000002 /* Enable Transmit */
lzzcd001 0:febabd1da7f4 124 #define CR_REG_RES 0x00000008 /* Reset Host Registers */
lzzcd001 0:febabd1da7f4 125 #define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */
lzzcd001 0:febabd1da7f4 126 #define CR_RX_RES 0x00000020 /* Reset Receive Datapath */
lzzcd001 0:febabd1da7f4 127 #define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */
lzzcd001 0:febabd1da7f4 128 #define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */
lzzcd001 0:febabd1da7f4 129 #define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */
lzzcd001 0:febabd1da7f4 130 #define CR_RMII 0x00000200 /* Reduced MII Interface */
lzzcd001 0:febabd1da7f4 131 #define CR_FULL_DUP 0x00000400 /* Full Duplex */
lzzcd001 0:febabd1da7f4 132
lzzcd001 0:febabd1da7f4 133 /* Status Register */
lzzcd001 0:febabd1da7f4 134 #define SR_RX_EN 0x00000001 /* Enable Receive */
lzzcd001 0:febabd1da7f4 135 #define SR_TX_EN 0x00000002 /* Enable Transmit */
lzzcd001 0:febabd1da7f4 136
lzzcd001 0:febabd1da7f4 137 /* Transmit Status Vector 0 Register */
lzzcd001 0:febabd1da7f4 138 #define TSV0_CRC_ERR 0x00000001 /* CRC error */
lzzcd001 0:febabd1da7f4 139 #define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */
lzzcd001 0:febabd1da7f4 140 #define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */
lzzcd001 0:febabd1da7f4 141 #define TSV0_DONE 0x00000008 /* Tramsmission Completed */
lzzcd001 0:febabd1da7f4 142 #define TSV0_MCAST 0x00000010 /* Multicast Destination */
lzzcd001 0:febabd1da7f4 143 #define TSV0_BCAST 0x00000020 /* Broadcast Destination */
lzzcd001 0:febabd1da7f4 144 #define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */
lzzcd001 0:febabd1da7f4 145 #define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */
lzzcd001 0:febabd1da7f4 146 #define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */
lzzcd001 0:febabd1da7f4 147 #define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */
lzzcd001 0:febabd1da7f4 148 #define TSV0_GIANT 0x00000400 /* Giant Frame */
lzzcd001 0:febabd1da7f4 149 #define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */
lzzcd001 0:febabd1da7f4 150 #define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */
lzzcd001 0:febabd1da7f4 151 #define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */
lzzcd001 0:febabd1da7f4 152 #define TSV0_PAUSE 0x20000000 /* Pause Frame */
lzzcd001 0:febabd1da7f4 153 #define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */
lzzcd001 0:febabd1da7f4 154 #define TSV0_VLAN 0x80000000 /* VLAN Frame */
lzzcd001 0:febabd1da7f4 155
lzzcd001 0:febabd1da7f4 156 /* Transmit Status Vector 1 Register */
lzzcd001 0:febabd1da7f4 157 #define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */
lzzcd001 0:febabd1da7f4 158 #define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */
lzzcd001 0:febabd1da7f4 159
lzzcd001 0:febabd1da7f4 160 /* Receive Status Vector Register */
lzzcd001 0:febabd1da7f4 161 #define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */
lzzcd001 0:febabd1da7f4 162 #define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */
lzzcd001 0:febabd1da7f4 163 #define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */
lzzcd001 0:febabd1da7f4 164 #define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */
lzzcd001 0:febabd1da7f4 165 #define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */
lzzcd001 0:febabd1da7f4 166 #define RSV_CRC_ERR 0x00100000 /* CRC Error */
lzzcd001 0:febabd1da7f4 167 #define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */
lzzcd001 0:febabd1da7f4 168 #define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */
lzzcd001 0:febabd1da7f4 169 #define RSV_REC_OK 0x00800000 /* Frame Received OK */
lzzcd001 0:febabd1da7f4 170 #define RSV_MCAST 0x01000000 /* Multicast Frame */
lzzcd001 0:febabd1da7f4 171 #define RSV_BCAST 0x02000000 /* Broadcast Frame */
lzzcd001 0:febabd1da7f4 172 #define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */
lzzcd001 0:febabd1da7f4 173 #define RSV_CTRL_FRAME 0x08000000 /* Control Frame */
lzzcd001 0:febabd1da7f4 174 #define RSV_PAUSE 0x10000000 /* Pause Frame */
lzzcd001 0:febabd1da7f4 175 #define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */
lzzcd001 0:febabd1da7f4 176 #define RSV_VLAN 0x40000000 /* VLAN Frame */
lzzcd001 0:febabd1da7f4 177
lzzcd001 0:febabd1da7f4 178 /* Flow Control Counter Register */
lzzcd001 0:febabd1da7f4 179 #define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */
lzzcd001 0:febabd1da7f4 180 #define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */
lzzcd001 0:febabd1da7f4 181
lzzcd001 0:febabd1da7f4 182 /* Flow Control Status Register */
lzzcd001 0:febabd1da7f4 183 #define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */
lzzcd001 0:febabd1da7f4 184
lzzcd001 0:febabd1da7f4 185 /* Receive Filter Control Register */
lzzcd001 0:febabd1da7f4 186 #define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */
lzzcd001 0:febabd1da7f4 187 #define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */
lzzcd001 0:febabd1da7f4 188 #define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */
lzzcd001 0:febabd1da7f4 189 #define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */
lzzcd001 0:febabd1da7f4 190 #define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/
lzzcd001 0:febabd1da7f4 191 #define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */
lzzcd001 0:febabd1da7f4 192 #define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */
lzzcd001 0:febabd1da7f4 193 #define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */
lzzcd001 0:febabd1da7f4 194
lzzcd001 0:febabd1da7f4 195 /* Receive Filter WoL Status/Clear Registers */
lzzcd001 0:febabd1da7f4 196 #define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */
lzzcd001 0:febabd1da7f4 197 #define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */
lzzcd001 0:febabd1da7f4 198 #define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */
lzzcd001 0:febabd1da7f4 199 #define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */
lzzcd001 0:febabd1da7f4 200 #define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */
lzzcd001 0:febabd1da7f4 201 #define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */
lzzcd001 0:febabd1da7f4 202 #define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */
lzzcd001 0:febabd1da7f4 203 #define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */
lzzcd001 0:febabd1da7f4 204
lzzcd001 0:febabd1da7f4 205 /* Interrupt Status/Enable/Clear/Set Registers */
lzzcd001 0:febabd1da7f4 206 #define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */
lzzcd001 0:febabd1da7f4 207 #define INT_RX_ERR 0x00000002 /* Receive Error */
lzzcd001 0:febabd1da7f4 208 #define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */
lzzcd001 0:febabd1da7f4 209 #define INT_RX_DONE 0x00000008 /* Receive Done */
lzzcd001 0:febabd1da7f4 210 #define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */
lzzcd001 0:febabd1da7f4 211 #define INT_TX_ERR 0x00000020 /* Transmit Error */
lzzcd001 0:febabd1da7f4 212 #define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */
lzzcd001 0:febabd1da7f4 213 #define INT_TX_DONE 0x00000080 /* Transmit Done */
lzzcd001 0:febabd1da7f4 214 #define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */
lzzcd001 0:febabd1da7f4 215 #define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */
lzzcd001 0:febabd1da7f4 216
lzzcd001 0:febabd1da7f4 217 /* Power Down Register */
lzzcd001 0:febabd1da7f4 218 #define PD_POWER_DOWN 0x80000000 /* Power Down MAC */
lzzcd001 0:febabd1da7f4 219
lzzcd001 0:febabd1da7f4 220 /* RX Descriptor Control Word */
lzzcd001 0:febabd1da7f4 221 #define RCTRL_SIZE 0x000007FF /* Buffer size mask */
lzzcd001 0:febabd1da7f4 222 #define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */
lzzcd001 0:febabd1da7f4 223
lzzcd001 0:febabd1da7f4 224 /* RX Status Hash CRC Word */
lzzcd001 0:febabd1da7f4 225 #define RHASH_SA 0x000001FF /* Hash CRC for Source Address */
lzzcd001 0:febabd1da7f4 226 #define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */
lzzcd001 0:febabd1da7f4 227
lzzcd001 0:febabd1da7f4 228 /* RX Status Information Word */
lzzcd001 0:febabd1da7f4 229 #define RINFO_SIZE 0x000007FF /* Data size in bytes */
lzzcd001 0:febabd1da7f4 230 #define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */
lzzcd001 0:febabd1da7f4 231 #define RINFO_VLAN 0x00080000 /* VLAN Frame */
lzzcd001 0:febabd1da7f4 232 #define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */
lzzcd001 0:febabd1da7f4 233 #define RINFO_MCAST 0x00200000 /* Multicast Frame */
lzzcd001 0:febabd1da7f4 234 #define RINFO_BCAST 0x00400000 /* Broadcast Frame */
lzzcd001 0:febabd1da7f4 235 #define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */
lzzcd001 0:febabd1da7f4 236 #define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */
lzzcd001 0:febabd1da7f4 237 #define RINFO_LEN_ERR 0x02000000 /* Length Error */
lzzcd001 0:febabd1da7f4 238 #define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */
lzzcd001 0:febabd1da7f4 239 #define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */
lzzcd001 0:febabd1da7f4 240 #define RINFO_OVERRUN 0x10000000 /* Receive overrun */
lzzcd001 0:febabd1da7f4 241 #define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */
lzzcd001 0:febabd1da7f4 242 #define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */
lzzcd001 0:febabd1da7f4 243 #define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
lzzcd001 0:febabd1da7f4 244
lzzcd001 0:febabd1da7f4 245 #define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | \
lzzcd001 0:febabd1da7f4 246 RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN)
lzzcd001 0:febabd1da7f4 247
lzzcd001 0:febabd1da7f4 248 /* TX Descriptor Control Word */
lzzcd001 0:febabd1da7f4 249 #define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */
lzzcd001 0:febabd1da7f4 250 #define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */
lzzcd001 0:febabd1da7f4 251 #define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */
lzzcd001 0:febabd1da7f4 252 #define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */
lzzcd001 0:febabd1da7f4 253 #define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */
lzzcd001 0:febabd1da7f4 254 #define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */
lzzcd001 0:febabd1da7f4 255 #define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */
lzzcd001 0:febabd1da7f4 256
lzzcd001 0:febabd1da7f4 257 /* TX Status Information Word */
lzzcd001 0:febabd1da7f4 258 #define TINFO_COL_CNT 0x01E00000 /* Collision Count */
lzzcd001 0:febabd1da7f4 259 #define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */
lzzcd001 0:febabd1da7f4 260 #define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */
lzzcd001 0:febabd1da7f4 261 #define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */
lzzcd001 0:febabd1da7f4 262 #define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */
lzzcd001 0:febabd1da7f4 263 #define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */
lzzcd001 0:febabd1da7f4 264 #define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */
lzzcd001 0:febabd1da7f4 265 #define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
lzzcd001 0:febabd1da7f4 266
lzzcd001 0:febabd1da7f4 267 /* DP83848C PHY Registers */
lzzcd001 0:febabd1da7f4 268 #define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */
lzzcd001 0:febabd1da7f4 269 #define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */
lzzcd001 0:febabd1da7f4 270 #define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */
lzzcd001 0:febabd1da7f4 271 #define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */
lzzcd001 0:febabd1da7f4 272 #define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */
lzzcd001 0:febabd1da7f4 273 #define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */
lzzcd001 0:febabd1da7f4 274 #define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */
lzzcd001 0:febabd1da7f4 275 #define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */
lzzcd001 0:febabd1da7f4 276
lzzcd001 0:febabd1da7f4 277 /* PHY Extended Registers */
lzzcd001 0:febabd1da7f4 278 #define PHY_REG_STS 0x10 /* Status Register */
lzzcd001 0:febabd1da7f4 279 #define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */
lzzcd001 0:febabd1da7f4 280 #define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */
lzzcd001 0:febabd1da7f4 281 #define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */
lzzcd001 0:febabd1da7f4 282 #define PHY_REG_RECR 0x15 /* Receive Error Counter */
lzzcd001 0:febabd1da7f4 283 #define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */
lzzcd001 0:febabd1da7f4 284 #define PHY_REG_RBR 0x17 /* RMII and Bypass Register */
lzzcd001 0:febabd1da7f4 285 #define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */
lzzcd001 0:febabd1da7f4 286 #define PHY_REG_PHYCR 0x19 /* PHY Control Register */
lzzcd001 0:febabd1da7f4 287 #define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */
lzzcd001 0:febabd1da7f4 288 #define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */
lzzcd001 0:febabd1da7f4 289 #define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */
lzzcd001 0:febabd1da7f4 290
lzzcd001 0:febabd1da7f4 291 #define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */
lzzcd001 0:febabd1da7f4 292 #define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */
lzzcd001 0:febabd1da7f4 293 #define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */
lzzcd001 0:febabd1da7f4 294 #define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */
lzzcd001 0:febabd1da7f4 295 #define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */
lzzcd001 0:febabd1da7f4 296
lzzcd001 0:febabd1da7f4 297 #define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */
lzzcd001 0:febabd1da7f4 298 #define DP83848C_ID 0x20005C90 /* PHY Identifier */
lzzcd001 0:febabd1da7f4 299 #endif