Zhen Liu / Mbed 2 deprecated HW1_extraD

Extra problem 4 for HW 1

Dependencies:   mbed

PowerControl/EthernetPowerControl.cpp@0:febabd1da7f4, 2015-02-18 (annotated)

Committer:
lzzcd001
Date:
Wed Feb 18 14:49:06 2015 +0000
Revision:
0:febabd1da7f4
Extra problem 4 for HW 1

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lzzcd001 0:febabd1da7f4 1 #include "EthernetPowerControl.h"
lzzcd001 0:febabd1da7f4 2
lzzcd001 0:febabd1da7f4 3 static void write_PHY (unsigned int PhyReg, unsigned short Value) {
lzzcd001 0:febabd1da7f4 4 /* Write a data 'Value' to PHY register 'PhyReg'. */
lzzcd001 0:febabd1da7f4 5 unsigned int tout;
lzzcd001 0:febabd1da7f4 6 /* Hardware MII Management for LPC176x devices. */
lzzcd001 0:febabd1da7f4 7 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
lzzcd001 0:febabd1da7f4 8 LPC_EMAC->MWTD = Value;
lzzcd001 0:febabd1da7f4 9
lzzcd001 0:febabd1da7f4 10 /* Wait utill operation completed */
lzzcd001 0:febabd1da7f4 11 for (tout = 0; tout < MII_WR_TOUT; tout++) {
lzzcd001 0:febabd1da7f4 12 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
lzzcd001 0:febabd1da7f4 13 break;
lzzcd001 0:febabd1da7f4 14 }
lzzcd001 0:febabd1da7f4 15 }
lzzcd001 0:febabd1da7f4 16 }
lzzcd001 0:febabd1da7f4 17
lzzcd001 0:febabd1da7f4 18 static unsigned short read_PHY (unsigned int PhyReg) {
lzzcd001 0:febabd1da7f4 19 /* Read a PHY register 'PhyReg'. */
lzzcd001 0:febabd1da7f4 20 unsigned int tout, val;
lzzcd001 0:febabd1da7f4 21
lzzcd001 0:febabd1da7f4 22 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
lzzcd001 0:febabd1da7f4 23 LPC_EMAC->MCMD = MCMD_READ;
lzzcd001 0:febabd1da7f4 24
lzzcd001 0:febabd1da7f4 25 /* Wait until operation completed */
lzzcd001 0:febabd1da7f4 26 for (tout = 0; tout < MII_RD_TOUT; tout++) {
lzzcd001 0:febabd1da7f4 27 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
lzzcd001 0:febabd1da7f4 28 break;
lzzcd001 0:febabd1da7f4 29 }
lzzcd001 0:febabd1da7f4 30 }
lzzcd001 0:febabd1da7f4 31 LPC_EMAC->MCMD = 0;
lzzcd001 0:febabd1da7f4 32 val = LPC_EMAC->MRDD;
lzzcd001 0:febabd1da7f4 33
lzzcd001 0:febabd1da7f4 34 return (val);
lzzcd001 0:febabd1da7f4 35 }
lzzcd001 0:febabd1da7f4 36
lzzcd001 0:febabd1da7f4 37 void EMAC_Init()
lzzcd001 0:febabd1da7f4 38 {
lzzcd001 0:febabd1da7f4 39 unsigned int tout,regv;
lzzcd001 0:febabd1da7f4 40 /* Power Up the EMAC controller. */
lzzcd001 0:febabd1da7f4 41 Peripheral_PowerUp(LPC1768_PCONP_PCENET);
lzzcd001 0:febabd1da7f4 42
lzzcd001 0:febabd1da7f4 43 LPC_PINCON->PINSEL2 = 0x50150105;
lzzcd001 0:febabd1da7f4 44 LPC_PINCON->PINSEL3 &= ~0x0000000F;
lzzcd001 0:febabd1da7f4 45 LPC_PINCON->PINSEL3 |= 0x00000005;
lzzcd001 0:febabd1da7f4 46
lzzcd001 0:febabd1da7f4 47 /* Reset all EMAC internal modules. */
lzzcd001 0:febabd1da7f4 48 LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
lzzcd001 0:febabd1da7f4 49 MAC1_SIM_RES | MAC1_SOFT_RES;
lzzcd001 0:febabd1da7f4 50 LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
lzzcd001 0:febabd1da7f4 51
lzzcd001 0:febabd1da7f4 52 /* A short delay after reset. */
lzzcd001 0:febabd1da7f4 53 for (tout = 100; tout; tout--);
lzzcd001 0:febabd1da7f4 54
lzzcd001 0:febabd1da7f4 55 /* Initialize MAC control registers. */
lzzcd001 0:febabd1da7f4 56 LPC_EMAC->MAC1 = MAC1_PASS_ALL;
lzzcd001 0:febabd1da7f4 57 LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
lzzcd001 0:febabd1da7f4 58 LPC_EMAC->MAXF = ETH_MAX_FLEN;
lzzcd001 0:febabd1da7f4 59 LPC_EMAC->CLRT = CLRT_DEF;
lzzcd001 0:febabd1da7f4 60 LPC_EMAC->IPGR = IPGR_DEF;
lzzcd001 0:febabd1da7f4 61
lzzcd001 0:febabd1da7f4 62 /* Enable Reduced MII interface. */
lzzcd001 0:febabd1da7f4 63 LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;
lzzcd001 0:febabd1da7f4 64
lzzcd001 0:febabd1da7f4 65 /* Reset Reduced MII Logic. */
lzzcd001 0:febabd1da7f4 66 LPC_EMAC->SUPP = SUPP_RES_RMII;
lzzcd001 0:febabd1da7f4 67 for (tout = 100; tout; tout--);
lzzcd001 0:febabd1da7f4 68 LPC_EMAC->SUPP = 0;
lzzcd001 0:febabd1da7f4 69
lzzcd001 0:febabd1da7f4 70 /* Put the DP83848C in reset mode */
lzzcd001 0:febabd1da7f4 71 write_PHY (PHY_REG_BMCR, 0x8000);
lzzcd001 0:febabd1da7f4 72
lzzcd001 0:febabd1da7f4 73 /* Wait for hardware reset to end. */
lzzcd001 0:febabd1da7f4 74 for (tout = 0; tout < 0x100000; tout++) {
lzzcd001 0:febabd1da7f4 75 regv = read_PHY (PHY_REG_BMCR);
lzzcd001 0:febabd1da7f4 76 if (!(regv & 0x8000)) {
lzzcd001 0:febabd1da7f4 77 /* Reset complete */
lzzcd001 0:febabd1da7f4 78 break;
lzzcd001 0:febabd1da7f4 79 }
lzzcd001 0:febabd1da7f4 80 }
lzzcd001 0:febabd1da7f4 81 }
lzzcd001 0:febabd1da7f4 82
lzzcd001 0:febabd1da7f4 83
lzzcd001 0:febabd1da7f4 84 void PHY_PowerDown()
lzzcd001 0:febabd1da7f4 85 {
lzzcd001 0:febabd1da7f4 86 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
lzzcd001 0:febabd1da7f4 87 EMAC_Init(); //init EMAC if it is not already init'd
lzzcd001 0:febabd1da7f4 88
lzzcd001 0:febabd1da7f4 89 unsigned int regv;
lzzcd001 0:febabd1da7f4 90 regv = read_PHY(PHY_REG_BMCR);
lzzcd001 0:febabd1da7f4 91 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_BMCR_POWERDOWN));
lzzcd001 0:febabd1da7f4 92 regv = read_PHY(PHY_REG_BMCR);
lzzcd001 0:febabd1da7f4 93
lzzcd001 0:febabd1da7f4 94 //shouldn't need the EMAC now.
lzzcd001 0:febabd1da7f4 95 Peripheral_PowerDown(LPC1768_PCONP_PCENET);
lzzcd001 0:febabd1da7f4 96
lzzcd001 0:febabd1da7f4 97 //and turn off the PHY OSC
lzzcd001 0:febabd1da7f4 98 LPC_GPIO1->FIODIR |= 0x8000000;
lzzcd001 0:febabd1da7f4 99 LPC_GPIO1->FIOCLR = 0x8000000;
lzzcd001 0:febabd1da7f4 100 }
lzzcd001 0:febabd1da7f4 101
lzzcd001 0:febabd1da7f4 102 void PHY_PowerUp()
lzzcd001 0:febabd1da7f4 103 {
lzzcd001 0:febabd1da7f4 104 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
lzzcd001 0:febabd1da7f4 105 EMAC_Init(); //init EMAC if it is not already init'd
lzzcd001 0:febabd1da7f4 106
lzzcd001 0:febabd1da7f4 107 LPC_GPIO1->FIODIR |= 0x8000000;
lzzcd001 0:febabd1da7f4 108 LPC_GPIO1->FIOSET = 0x8000000;
lzzcd001 0:febabd1da7f4 109
lzzcd001 0:febabd1da7f4 110 //wait for osc to be stable
lzzcd001 0:febabd1da7f4 111 wait_ms(200);
lzzcd001 0:febabd1da7f4 112
lzzcd001 0:febabd1da7f4 113 unsigned int regv;
lzzcd001 0:febabd1da7f4 114 regv = read_PHY(PHY_REG_BMCR);
lzzcd001 0:febabd1da7f4 115 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_BMCR_POWERDOWN));
lzzcd001 0:febabd1da7f4 116 regv = read_PHY(PHY_REG_BMCR);
lzzcd001 0:febabd1da7f4 117 }
lzzcd001 0:febabd1da7f4 118
lzzcd001 0:febabd1da7f4 119 void PHY_EnergyDetect_Enable()
lzzcd001 0:febabd1da7f4 120 {
lzzcd001 0:febabd1da7f4 121 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
lzzcd001 0:febabd1da7f4 122 EMAC_Init(); //init EMAC if it is not already init'd
lzzcd001 0:febabd1da7f4 123
lzzcd001 0:febabd1da7f4 124 unsigned int regv;
lzzcd001 0:febabd1da7f4 125 regv = read_PHY(PHY_REG_EDCR);
lzzcd001 0:febabd1da7f4 126 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_EDCR_ENABLE));
lzzcd001 0:febabd1da7f4 127 regv = read_PHY(PHY_REG_EDCR);
lzzcd001 0:febabd1da7f4 128 }
lzzcd001 0:febabd1da7f4 129
lzzcd001 0:febabd1da7f4 130 void PHY_EnergyDetect_Disable()
lzzcd001 0:febabd1da7f4 131 {
lzzcd001 0:febabd1da7f4 132 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
lzzcd001 0:febabd1da7f4 133 EMAC_Init(); //init EMAC if it is not already init'd
lzzcd001 0:febabd1da7f4 134 unsigned int regv;
lzzcd001 0:febabd1da7f4 135 regv = read_PHY(PHY_REG_EDCR);
lzzcd001 0:febabd1da7f4 136 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_EDCR_ENABLE));
lzzcd001 0:febabd1da7f4 137 regv = read_PHY(PHY_REG_EDCR);
lzzcd001 0:febabd1da7f4 138 }