lzbp li / mbed-stm32l0l1-src-1

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Fork of mbed-stm32l0/l1-src by lzbp li

vendor/NXP/LPC4088/cmsis/core_cm4.h@10:3bc89ef62ce7, 2013-06-14 (annotated)

Committer:
emilmont
Date:
Fri Jun 14 17:49:17 2013 +0100
Revision:
10:3bc89ef62ce7
Unify mbed library sources

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 10:3bc89ef62ce7 1 /**************************************************************************//**
emilmont 10:3bc89ef62ce7 2 * @file core_cm4.h
emilmont 10:3bc89ef62ce7 3 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
emilmont 10:3bc89ef62ce7 4 * @version V3.02
emilmont 10:3bc89ef62ce7 5 * @date 16. July 2012
emilmont 10:3bc89ef62ce7 6 *
emilmont 10:3bc89ef62ce7 7 * @note
emilmont 10:3bc89ef62ce7 8 * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
emilmont 10:3bc89ef62ce7 9 *
emilmont 10:3bc89ef62ce7 10 * @par
emilmont 10:3bc89ef62ce7 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
emilmont 10:3bc89ef62ce7 12 * processor based microcontrollers. This file can be freely distributed
emilmont 10:3bc89ef62ce7 13 * within development tools that are supporting such ARM based processors.
emilmont 10:3bc89ef62ce7 14 *
emilmont 10:3bc89ef62ce7 15 * @par
emilmont 10:3bc89ef62ce7 16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
emilmont 10:3bc89ef62ce7 17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
emilmont 10:3bc89ef62ce7 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
emilmont 10:3bc89ef62ce7 19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
emilmont 10:3bc89ef62ce7 20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
emilmont 10:3bc89ef62ce7 21 *
emilmont 10:3bc89ef62ce7 22 ******************************************************************************/
emilmont 10:3bc89ef62ce7 23 #if defined ( __ICCARM__ )
emilmont 10:3bc89ef62ce7 24 #pragma system_include /* treat file as system include file for MISRA check */
emilmont 10:3bc89ef62ce7 25 #endif
emilmont 10:3bc89ef62ce7 26
emilmont 10:3bc89ef62ce7 27 #ifdef __cplusplus
emilmont 10:3bc89ef62ce7 28 extern "C" {
emilmont 10:3bc89ef62ce7 29 #endif
emilmont 10:3bc89ef62ce7 30
emilmont 10:3bc89ef62ce7 31 #ifndef __CORE_CM4_H_GENERIC
emilmont 10:3bc89ef62ce7 32 #define __CORE_CM4_H_GENERIC
emilmont 10:3bc89ef62ce7 33
emilmont 10:3bc89ef62ce7 34 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
emilmont 10:3bc89ef62ce7 35 CMSIS violates the following MISRA-C:2004 rules:
emilmont 10:3bc89ef62ce7 36
emilmont 10:3bc89ef62ce7 37 \li Required Rule 8.5, object/function definition in header file.<br>
emilmont 10:3bc89ef62ce7 38 Function definitions in header files are used to allow 'inlining'.
emilmont 10:3bc89ef62ce7 39
emilmont 10:3bc89ef62ce7 40 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
emilmont 10:3bc89ef62ce7 41 Unions are used for effective representation of core registers.
emilmont 10:3bc89ef62ce7 42
emilmont 10:3bc89ef62ce7 43 \li Advisory Rule 19.7, Function-like macro defined.<br>
emilmont 10:3bc89ef62ce7 44 Function-like macros are used to allow more efficient code.
emilmont 10:3bc89ef62ce7 45 */
emilmont 10:3bc89ef62ce7 46
emilmont 10:3bc89ef62ce7 47
emilmont 10:3bc89ef62ce7 48 /*******************************************************************************
emilmont 10:3bc89ef62ce7 49 * CMSIS definitions
emilmont 10:3bc89ef62ce7 50 ******************************************************************************/
emilmont 10:3bc89ef62ce7 51 /** \ingroup Cortex_M4
emilmont 10:3bc89ef62ce7 52 @{
emilmont 10:3bc89ef62ce7 53 */
emilmont 10:3bc89ef62ce7 54
emilmont 10:3bc89ef62ce7 55 /* CMSIS CM4 definitions */
emilmont 10:3bc89ef62ce7 56 #define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
emilmont 10:3bc89ef62ce7 57 #define __CM4_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
emilmont 10:3bc89ef62ce7 58 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
emilmont 10:3bc89ef62ce7 59 __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
emilmont 10:3bc89ef62ce7 60
emilmont 10:3bc89ef62ce7 61 #define __CORTEX_M (0x04) /*!< Cortex-M Core */
emilmont 10:3bc89ef62ce7 62
emilmont 10:3bc89ef62ce7 63
emilmont 10:3bc89ef62ce7 64 #if defined ( __CC_ARM )
emilmont 10:3bc89ef62ce7 65 #define __ASM __asm /*!< asm keyword for ARM Compiler */
emilmont 10:3bc89ef62ce7 66 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
emilmont 10:3bc89ef62ce7 67 #define __STATIC_INLINE static __inline
emilmont 10:3bc89ef62ce7 68
emilmont 10:3bc89ef62ce7 69 #elif defined ( __ICCARM__ )
emilmont 10:3bc89ef62ce7 70 #define __ASM __asm /*!< asm keyword for IAR Compiler */
emilmont 10:3bc89ef62ce7 71 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
emilmont 10:3bc89ef62ce7 72 #define __STATIC_INLINE static inline
emilmont 10:3bc89ef62ce7 73
emilmont 10:3bc89ef62ce7 74 #elif defined ( __TMS470__ )
emilmont 10:3bc89ef62ce7 75 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
emilmont 10:3bc89ef62ce7 76 #define __STATIC_INLINE static inline
emilmont 10:3bc89ef62ce7 77
emilmont 10:3bc89ef62ce7 78 #elif defined ( __GNUC__ )
emilmont 10:3bc89ef62ce7 79 #define __ASM __asm /*!< asm keyword for GNU Compiler */
emilmont 10:3bc89ef62ce7 80 #define __INLINE inline /*!< inline keyword for GNU Compiler */
emilmont 10:3bc89ef62ce7 81 #define __STATIC_INLINE static inline
emilmont 10:3bc89ef62ce7 82
emilmont 10:3bc89ef62ce7 83 #elif defined ( __TASKING__ )
emilmont 10:3bc89ef62ce7 84 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
emilmont 10:3bc89ef62ce7 85 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
emilmont 10:3bc89ef62ce7 86 #define __STATIC_INLINE static inline
emilmont 10:3bc89ef62ce7 87
emilmont 10:3bc89ef62ce7 88 #endif
emilmont 10:3bc89ef62ce7 89
emilmont 10:3bc89ef62ce7 90 /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
emilmont 10:3bc89ef62ce7 91 */
emilmont 10:3bc89ef62ce7 92 #if defined ( __CC_ARM )
emilmont 10:3bc89ef62ce7 93 #if defined __TARGET_FPU_VFP
emilmont 10:3bc89ef62ce7 94 #if (__FPU_PRESENT == 1)
emilmont 10:3bc89ef62ce7 95 #define __FPU_USED 1
emilmont 10:3bc89ef62ce7 96 #else
emilmont 10:3bc89ef62ce7 97 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 10:3bc89ef62ce7 98 #define __FPU_USED 0
emilmont 10:3bc89ef62ce7 99 #endif
emilmont 10:3bc89ef62ce7 100 #else
emilmont 10:3bc89ef62ce7 101 #define __FPU_USED 0
emilmont 10:3bc89ef62ce7 102 #endif
emilmont 10:3bc89ef62ce7 103
emilmont 10:3bc89ef62ce7 104 #elif defined ( __ICCARM__ )
emilmont 10:3bc89ef62ce7 105 #if defined __ARMVFP__
emilmont 10:3bc89ef62ce7 106 #if (__FPU_PRESENT == 1)
emilmont 10:3bc89ef62ce7 107 #define __FPU_USED 1
emilmont 10:3bc89ef62ce7 108 #else
emilmont 10:3bc89ef62ce7 109 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 10:3bc89ef62ce7 110 #define __FPU_USED 0
emilmont 10:3bc89ef62ce7 111 #endif
emilmont 10:3bc89ef62ce7 112 #else
emilmont 10:3bc89ef62ce7 113 #define __FPU_USED 0
emilmont 10:3bc89ef62ce7 114 #endif
emilmont 10:3bc89ef62ce7 115
emilmont 10:3bc89ef62ce7 116 #elif defined ( __TMS470__ )
emilmont 10:3bc89ef62ce7 117 #if defined __TI_VFP_SUPPORT__
emilmont 10:3bc89ef62ce7 118 #if (__FPU_PRESENT == 1)
emilmont 10:3bc89ef62ce7 119 #define __FPU_USED 1
emilmont 10:3bc89ef62ce7 120 #else
emilmont 10:3bc89ef62ce7 121 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 10:3bc89ef62ce7 122 #define __FPU_USED 0
emilmont 10:3bc89ef62ce7 123 #endif
emilmont 10:3bc89ef62ce7 124 #else
emilmont 10:3bc89ef62ce7 125 #define __FPU_USED 0
emilmont 10:3bc89ef62ce7 126 #endif
emilmont 10:3bc89ef62ce7 127
emilmont 10:3bc89ef62ce7 128 #elif defined ( __GNUC__ )
emilmont 10:3bc89ef62ce7 129 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
emilmont 10:3bc89ef62ce7 130 #if (__FPU_PRESENT == 1)
emilmont 10:3bc89ef62ce7 131 #define __FPU_USED 1
emilmont 10:3bc89ef62ce7 132 #else
emilmont 10:3bc89ef62ce7 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 10:3bc89ef62ce7 134 #define __FPU_USED 0
emilmont 10:3bc89ef62ce7 135 #endif
emilmont 10:3bc89ef62ce7 136 #else
emilmont 10:3bc89ef62ce7 137 #define __FPU_USED 0
emilmont 10:3bc89ef62ce7 138 #endif
emilmont 10:3bc89ef62ce7 139
emilmont 10:3bc89ef62ce7 140 #elif defined ( __TASKING__ )
emilmont 10:3bc89ef62ce7 141 #if defined __FPU_VFP__
emilmont 10:3bc89ef62ce7 142 #if (__FPU_PRESENT == 1)
emilmont 10:3bc89ef62ce7 143 #define __FPU_USED 1
emilmont 10:3bc89ef62ce7 144 #else
emilmont 10:3bc89ef62ce7 145 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 10:3bc89ef62ce7 146 #define __FPU_USED 0
emilmont 10:3bc89ef62ce7 147 #endif
emilmont 10:3bc89ef62ce7 148 #else
emilmont 10:3bc89ef62ce7 149 #define __FPU_USED 0
emilmont 10:3bc89ef62ce7 150 #endif
emilmont 10:3bc89ef62ce7 151 #endif
emilmont 10:3bc89ef62ce7 152
emilmont 10:3bc89ef62ce7 153 #include <stdint.h> /* standard types definitions */
emilmont 10:3bc89ef62ce7 154 #include <core_cmInstr.h> /* Core Instruction Access */
emilmont 10:3bc89ef62ce7 155 #include <core_cmFunc.h> /* Core Function Access */
emilmont 10:3bc89ef62ce7 156 #include <core_cm4_simd.h> /* Compiler specific SIMD Intrinsics */
emilmont 10:3bc89ef62ce7 157
emilmont 10:3bc89ef62ce7 158 #endif /* __CORE_CM4_H_GENERIC */
emilmont 10:3bc89ef62ce7 159
emilmont 10:3bc89ef62ce7 160 #ifndef __CMSIS_GENERIC
emilmont 10:3bc89ef62ce7 161
emilmont 10:3bc89ef62ce7 162 #ifndef __CORE_CM4_H_DEPENDANT
emilmont 10:3bc89ef62ce7 163 #define __CORE_CM4_H_DEPENDANT
emilmont 10:3bc89ef62ce7 164
emilmont 10:3bc89ef62ce7 165 /* check device defines and use defaults */
emilmont 10:3bc89ef62ce7 166 #if defined __CHECK_DEVICE_DEFINES
emilmont 10:3bc89ef62ce7 167 #ifndef __CM4_REV
emilmont 10:3bc89ef62ce7 168 #define __CM4_REV 0x0000
emilmont 10:3bc89ef62ce7 169 #warning "__CM4_REV not defined in device header file; using default!"
emilmont 10:3bc89ef62ce7 170 #endif
emilmont 10:3bc89ef62ce7 171
emilmont 10:3bc89ef62ce7 172 #ifndef __FPU_PRESENT
emilmont 10:3bc89ef62ce7 173 #define __FPU_PRESENT 0
emilmont 10:3bc89ef62ce7 174 #warning "__FPU_PRESENT not defined in device header file; using default!"
emilmont 10:3bc89ef62ce7 175 #endif
emilmont 10:3bc89ef62ce7 176
emilmont 10:3bc89ef62ce7 177 #ifndef __MPU_PRESENT
emilmont 10:3bc89ef62ce7 178 #define __MPU_PRESENT 0
emilmont 10:3bc89ef62ce7 179 #warning "__MPU_PRESENT not defined in device header file; using default!"
emilmont 10:3bc89ef62ce7 180 #endif
emilmont 10:3bc89ef62ce7 181
emilmont 10:3bc89ef62ce7 182 #ifndef __NVIC_PRIO_BITS
emilmont 10:3bc89ef62ce7 183 #define __NVIC_PRIO_BITS 4
emilmont 10:3bc89ef62ce7 184 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
emilmont 10:3bc89ef62ce7 185 #endif
emilmont 10:3bc89ef62ce7 186
emilmont 10:3bc89ef62ce7 187 #ifndef __Vendor_SysTickConfig
emilmont 10:3bc89ef62ce7 188 #define __Vendor_SysTickConfig 0
emilmont 10:3bc89ef62ce7 189 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
emilmont 10:3bc89ef62ce7 190 #endif
emilmont 10:3bc89ef62ce7 191 #endif
emilmont 10:3bc89ef62ce7 192
emilmont 10:3bc89ef62ce7 193 /* IO definitions (access restrictions to peripheral registers) */
emilmont 10:3bc89ef62ce7 194 /**
emilmont 10:3bc89ef62ce7 195 \defgroup CMSIS_glob_defs CMSIS Global Defines
emilmont 10:3bc89ef62ce7 196
emilmont 10:3bc89ef62ce7 197 <strong>IO Type Qualifiers</strong> are used
emilmont 10:3bc89ef62ce7 198 \li to specify the access to peripheral variables.
emilmont 10:3bc89ef62ce7 199 \li for automatic generation of peripheral register debug information.
emilmont 10:3bc89ef62ce7 200 */
emilmont 10:3bc89ef62ce7 201 #ifdef __cplusplus
emilmont 10:3bc89ef62ce7 202 #define __I volatile /*!< Defines 'read only' permissions */
emilmont 10:3bc89ef62ce7 203 #else
emilmont 10:3bc89ef62ce7 204 #define __I volatile const /*!< Defines 'read only' permissions */
emilmont 10:3bc89ef62ce7 205 #endif
emilmont 10:3bc89ef62ce7 206 #define __O volatile /*!< Defines 'write only' permissions */
emilmont 10:3bc89ef62ce7 207 #define __IO volatile /*!< Defines 'read / write' permissions */
emilmont 10:3bc89ef62ce7 208
emilmont 10:3bc89ef62ce7 209 /*@} end of group Cortex_M4 */
emilmont 10:3bc89ef62ce7 210
emilmont 10:3bc89ef62ce7 211
emilmont 10:3bc89ef62ce7 212
emilmont 10:3bc89ef62ce7 213 /*******************************************************************************
emilmont 10:3bc89ef62ce7 214 * Register Abstraction
emilmont 10:3bc89ef62ce7 215 Core Register contain:
emilmont 10:3bc89ef62ce7 216 - Core Register
emilmont 10:3bc89ef62ce7 217 - Core NVIC Register
emilmont 10:3bc89ef62ce7 218 - Core SCB Register
emilmont 10:3bc89ef62ce7 219 - Core SysTick Register
emilmont 10:3bc89ef62ce7 220 - Core Debug Register
emilmont 10:3bc89ef62ce7 221 - Core MPU Register
emilmont 10:3bc89ef62ce7 222 - Core FPU Register
emilmont 10:3bc89ef62ce7 223 ******************************************************************************/
emilmont 10:3bc89ef62ce7 224 /** \defgroup CMSIS_core_register Defines and Type Definitions
emilmont 10:3bc89ef62ce7 225 \brief Type definitions and defines for Cortex-M processor based devices.
emilmont 10:3bc89ef62ce7 226 */
emilmont 10:3bc89ef62ce7 227
emilmont 10:3bc89ef62ce7 228 /** \ingroup CMSIS_core_register
emilmont 10:3bc89ef62ce7 229 \defgroup CMSIS_CORE Status and Control Registers
emilmont 10:3bc89ef62ce7 230 \brief Core Register type definitions.
emilmont 10:3bc89ef62ce7 231 @{
emilmont 10:3bc89ef62ce7 232 */
emilmont 10:3bc89ef62ce7 233
emilmont 10:3bc89ef62ce7 234 /** \brief Union type to access the Application Program Status Register (APSR).
emilmont 10:3bc89ef62ce7 235 */
emilmont 10:3bc89ef62ce7 236 typedef union
emilmont 10:3bc89ef62ce7 237 {
emilmont 10:3bc89ef62ce7 238 struct
emilmont 10:3bc89ef62ce7 239 {
emilmont 10:3bc89ef62ce7 240 #if (__CORTEX_M != 0x04)
emilmont 10:3bc89ef62ce7 241 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
emilmont 10:3bc89ef62ce7 242 #else
emilmont 10:3bc89ef62ce7 243 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
emilmont 10:3bc89ef62ce7 244 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
emilmont 10:3bc89ef62ce7 245 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
emilmont 10:3bc89ef62ce7 246 #endif
emilmont 10:3bc89ef62ce7 247 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
emilmont 10:3bc89ef62ce7 248 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
emilmont 10:3bc89ef62ce7 249 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
emilmont 10:3bc89ef62ce7 250 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
emilmont 10:3bc89ef62ce7 251 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
emilmont 10:3bc89ef62ce7 252 } b; /*!< Structure used for bit access */
emilmont 10:3bc89ef62ce7 253 uint32_t w; /*!< Type used for word access */
emilmont 10:3bc89ef62ce7 254 } APSR_Type;
emilmont 10:3bc89ef62ce7 255
emilmont 10:3bc89ef62ce7 256
emilmont 10:3bc89ef62ce7 257 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
emilmont 10:3bc89ef62ce7 258 */
emilmont 10:3bc89ef62ce7 259 typedef union
emilmont 10:3bc89ef62ce7 260 {
emilmont 10:3bc89ef62ce7 261 struct
emilmont 10:3bc89ef62ce7 262 {
emilmont 10:3bc89ef62ce7 263 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
emilmont 10:3bc89ef62ce7 264 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
emilmont 10:3bc89ef62ce7 265 } b; /*!< Structure used for bit access */
emilmont 10:3bc89ef62ce7 266 uint32_t w; /*!< Type used for word access */
emilmont 10:3bc89ef62ce7 267 } IPSR_Type;
emilmont 10:3bc89ef62ce7 268
emilmont 10:3bc89ef62ce7 269
emilmont 10:3bc89ef62ce7 270 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
emilmont 10:3bc89ef62ce7 271 */
emilmont 10:3bc89ef62ce7 272 typedef union
emilmont 10:3bc89ef62ce7 273 {
emilmont 10:3bc89ef62ce7 274 struct
emilmont 10:3bc89ef62ce7 275 {
emilmont 10:3bc89ef62ce7 276 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
emilmont 10:3bc89ef62ce7 277 #if (__CORTEX_M != 0x04)
emilmont 10:3bc89ef62ce7 278 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
emilmont 10:3bc89ef62ce7 279 #else
emilmont 10:3bc89ef62ce7 280 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
emilmont 10:3bc89ef62ce7 281 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
emilmont 10:3bc89ef62ce7 282 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
emilmont 10:3bc89ef62ce7 283 #endif
emilmont 10:3bc89ef62ce7 284 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
emilmont 10:3bc89ef62ce7 285 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
emilmont 10:3bc89ef62ce7 286 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
emilmont 10:3bc89ef62ce7 287 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
emilmont 10:3bc89ef62ce7 288 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
emilmont 10:3bc89ef62ce7 289 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
emilmont 10:3bc89ef62ce7 290 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
emilmont 10:3bc89ef62ce7 291 } b; /*!< Structure used for bit access */
emilmont 10:3bc89ef62ce7 292 uint32_t w; /*!< Type used for word access */
emilmont 10:3bc89ef62ce7 293 } xPSR_Type;
emilmont 10:3bc89ef62ce7 294
emilmont 10:3bc89ef62ce7 295
emilmont 10:3bc89ef62ce7 296 /** \brief Union type to access the Control Registers (CONTROL).
emilmont 10:3bc89ef62ce7 297 */
emilmont 10:3bc89ef62ce7 298 typedef union
emilmont 10:3bc89ef62ce7 299 {
emilmont 10:3bc89ef62ce7 300 struct
emilmont 10:3bc89ef62ce7 301 {
emilmont 10:3bc89ef62ce7 302 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
emilmont 10:3bc89ef62ce7 303 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
emilmont 10:3bc89ef62ce7 304 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
emilmont 10:3bc89ef62ce7 305 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
emilmont 10:3bc89ef62ce7 306 } b; /*!< Structure used for bit access */
emilmont 10:3bc89ef62ce7 307 uint32_t w; /*!< Type used for word access */
emilmont 10:3bc89ef62ce7 308 } CONTROL_Type;
emilmont 10:3bc89ef62ce7 309
emilmont 10:3bc89ef62ce7 310 /*@} end of group CMSIS_CORE */
emilmont 10:3bc89ef62ce7 311
emilmont 10:3bc89ef62ce7 312
emilmont 10:3bc89ef62ce7 313 /** \ingroup CMSIS_core_register
emilmont 10:3bc89ef62ce7 314 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
emilmont 10:3bc89ef62ce7 315 \brief Type definitions for the NVIC Registers
emilmont 10:3bc89ef62ce7 316 @{
emilmont 10:3bc89ef62ce7 317 */
emilmont 10:3bc89ef62ce7 318
emilmont 10:3bc89ef62ce7 319 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
emilmont 10:3bc89ef62ce7 320 */
emilmont 10:3bc89ef62ce7 321 typedef struct
emilmont 10:3bc89ef62ce7 322 {
emilmont 10:3bc89ef62ce7 323 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
emilmont 10:3bc89ef62ce7 324 uint32_t RESERVED0[24];
emilmont 10:3bc89ef62ce7 325 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
emilmont 10:3bc89ef62ce7 326 uint32_t RSERVED1[24];
emilmont 10:3bc89ef62ce7 327 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
emilmont 10:3bc89ef62ce7 328 uint32_t RESERVED2[24];
emilmont 10:3bc89ef62ce7 329 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
emilmont 10:3bc89ef62ce7 330 uint32_t RESERVED3[24];
emilmont 10:3bc89ef62ce7 331 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
emilmont 10:3bc89ef62ce7 332 uint32_t RESERVED4[56];
emilmont 10:3bc89ef62ce7 333 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
emilmont 10:3bc89ef62ce7 334 uint32_t RESERVED5[644];
emilmont 10:3bc89ef62ce7 335 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
emilmont 10:3bc89ef62ce7 336 } NVIC_Type;
emilmont 10:3bc89ef62ce7 337
emilmont 10:3bc89ef62ce7 338 /* Software Triggered Interrupt Register Definitions */
emilmont 10:3bc89ef62ce7 339 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
emilmont 10:3bc89ef62ce7 340 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
emilmont 10:3bc89ef62ce7 341
emilmont 10:3bc89ef62ce7 342 /*@} end of group CMSIS_NVIC */
emilmont 10:3bc89ef62ce7 343
emilmont 10:3bc89ef62ce7 344
emilmont 10:3bc89ef62ce7 345 /** \ingroup CMSIS_core_register
emilmont 10:3bc89ef62ce7 346 \defgroup CMSIS_SCB System Control Block (SCB)
emilmont 10:3bc89ef62ce7 347 \brief Type definitions for the System Control Block Registers
emilmont 10:3bc89ef62ce7 348 @{
emilmont 10:3bc89ef62ce7 349 */
emilmont 10:3bc89ef62ce7 350
emilmont 10:3bc89ef62ce7 351 /** \brief Structure type to access the System Control Block (SCB).
emilmont 10:3bc89ef62ce7 352 */
emilmont 10:3bc89ef62ce7 353 typedef struct
emilmont 10:3bc89ef62ce7 354 {
emilmont 10:3bc89ef62ce7 355 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
emilmont 10:3bc89ef62ce7 356 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
emilmont 10:3bc89ef62ce7 357 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
emilmont 10:3bc89ef62ce7 358 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
emilmont 10:3bc89ef62ce7 359 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
emilmont 10:3bc89ef62ce7 360 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
emilmont 10:3bc89ef62ce7 361 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
emilmont 10:3bc89ef62ce7 362 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
emilmont 10:3bc89ef62ce7 363 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
emilmont 10:3bc89ef62ce7 364 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
emilmont 10:3bc89ef62ce7 365 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
emilmont 10:3bc89ef62ce7 366 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
emilmont 10:3bc89ef62ce7 367 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
emilmont 10:3bc89ef62ce7 368 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
emilmont 10:3bc89ef62ce7 369 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
emilmont 10:3bc89ef62ce7 370 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
emilmont 10:3bc89ef62ce7 371 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
emilmont 10:3bc89ef62ce7 372 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
emilmont 10:3bc89ef62ce7 373 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
emilmont 10:3bc89ef62ce7 374 uint32_t RESERVED0[5];
emilmont 10:3bc89ef62ce7 375 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
emilmont 10:3bc89ef62ce7 376 } SCB_Type;
emilmont 10:3bc89ef62ce7 377
emilmont 10:3bc89ef62ce7 378 /* SCB CPUID Register Definitions */
emilmont 10:3bc89ef62ce7 379 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
emilmont 10:3bc89ef62ce7 380 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
emilmont 10:3bc89ef62ce7 381
emilmont 10:3bc89ef62ce7 382 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
emilmont 10:3bc89ef62ce7 383 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
emilmont 10:3bc89ef62ce7 384
emilmont 10:3bc89ef62ce7 385 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
emilmont 10:3bc89ef62ce7 386 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
emilmont 10:3bc89ef62ce7 387
emilmont 10:3bc89ef62ce7 388 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
emilmont 10:3bc89ef62ce7 389 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
emilmont 10:3bc89ef62ce7 390
emilmont 10:3bc89ef62ce7 391 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
emilmont 10:3bc89ef62ce7 392 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
emilmont 10:3bc89ef62ce7 393
emilmont 10:3bc89ef62ce7 394 /* SCB Interrupt Control State Register Definitions */
emilmont 10:3bc89ef62ce7 395 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
emilmont 10:3bc89ef62ce7 396 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
emilmont 10:3bc89ef62ce7 397
emilmont 10:3bc89ef62ce7 398 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
emilmont 10:3bc89ef62ce7 399 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
emilmont 10:3bc89ef62ce7 400
emilmont 10:3bc89ef62ce7 401 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
emilmont 10:3bc89ef62ce7 402 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
emilmont 10:3bc89ef62ce7 403
emilmont 10:3bc89ef62ce7 404 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
emilmont 10:3bc89ef62ce7 405 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
emilmont 10:3bc89ef62ce7 406
emilmont 10:3bc89ef62ce7 407 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
emilmont 10:3bc89ef62ce7 408 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
emilmont 10:3bc89ef62ce7 409
emilmont 10:3bc89ef62ce7 410 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
emilmont 10:3bc89ef62ce7 411 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
emilmont 10:3bc89ef62ce7 412
emilmont 10:3bc89ef62ce7 413 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
emilmont 10:3bc89ef62ce7 414 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
emilmont 10:3bc89ef62ce7 415
emilmont 10:3bc89ef62ce7 416 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
emilmont 10:3bc89ef62ce7 417 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
emilmont 10:3bc89ef62ce7 418
emilmont 10:3bc89ef62ce7 419 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
emilmont 10:3bc89ef62ce7 420 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
emilmont 10:3bc89ef62ce7 421
emilmont 10:3bc89ef62ce7 422 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
emilmont 10:3bc89ef62ce7 423 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
emilmont 10:3bc89ef62ce7 424
emilmont 10:3bc89ef62ce7 425 /* SCB Vector Table Offset Register Definitions */
emilmont 10:3bc89ef62ce7 426 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
emilmont 10:3bc89ef62ce7 427 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
emilmont 10:3bc89ef62ce7 428
emilmont 10:3bc89ef62ce7 429 /* SCB Application Interrupt and Reset Control Register Definitions */
emilmont 10:3bc89ef62ce7 430 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
emilmont 10:3bc89ef62ce7 431 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
emilmont 10:3bc89ef62ce7 432
emilmont 10:3bc89ef62ce7 433 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
emilmont 10:3bc89ef62ce7 434 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
emilmont 10:3bc89ef62ce7 435
emilmont 10:3bc89ef62ce7 436 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
emilmont 10:3bc89ef62ce7 437 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
emilmont 10:3bc89ef62ce7 438
emilmont 10:3bc89ef62ce7 439 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
emilmont 10:3bc89ef62ce7 440 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
emilmont 10:3bc89ef62ce7 441
emilmont 10:3bc89ef62ce7 442 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
emilmont 10:3bc89ef62ce7 443 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
emilmont 10:3bc89ef62ce7 444
emilmont 10:3bc89ef62ce7 445 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
emilmont 10:3bc89ef62ce7 446 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
emilmont 10:3bc89ef62ce7 447
emilmont 10:3bc89ef62ce7 448 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
emilmont 10:3bc89ef62ce7 449 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
emilmont 10:3bc89ef62ce7 450
emilmont 10:3bc89ef62ce7 451 /* SCB System Control Register Definitions */
emilmont 10:3bc89ef62ce7 452 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
emilmont 10:3bc89ef62ce7 453 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
emilmont 10:3bc89ef62ce7 454
emilmont 10:3bc89ef62ce7 455 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
emilmont 10:3bc89ef62ce7 456 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
emilmont 10:3bc89ef62ce7 457
emilmont 10:3bc89ef62ce7 458 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
emilmont 10:3bc89ef62ce7 459 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
emilmont 10:3bc89ef62ce7 460
emilmont 10:3bc89ef62ce7 461 /* SCB Configuration Control Register Definitions */
emilmont 10:3bc89ef62ce7 462 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
emilmont 10:3bc89ef62ce7 463 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
emilmont 10:3bc89ef62ce7 464
emilmont 10:3bc89ef62ce7 465 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
emilmont 10:3bc89ef62ce7 466 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
emilmont 10:3bc89ef62ce7 467
emilmont 10:3bc89ef62ce7 468 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
emilmont 10:3bc89ef62ce7 469 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
emilmont 10:3bc89ef62ce7 470
emilmont 10:3bc89ef62ce7 471 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
emilmont 10:3bc89ef62ce7 472 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
emilmont 10:3bc89ef62ce7 473
emilmont 10:3bc89ef62ce7 474 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
emilmont 10:3bc89ef62ce7 475 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
emilmont 10:3bc89ef62ce7 476
emilmont 10:3bc89ef62ce7 477 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
emilmont 10:3bc89ef62ce7 478 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
emilmont 10:3bc89ef62ce7 479
emilmont 10:3bc89ef62ce7 480 /* SCB System Handler Control and State Register Definitions */
emilmont 10:3bc89ef62ce7 481 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
emilmont 10:3bc89ef62ce7 482 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
emilmont 10:3bc89ef62ce7 483
emilmont 10:3bc89ef62ce7 484 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
emilmont 10:3bc89ef62ce7 485 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
emilmont 10:3bc89ef62ce7 486
emilmont 10:3bc89ef62ce7 487 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
emilmont 10:3bc89ef62ce7 488 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
emilmont 10:3bc89ef62ce7 489
emilmont 10:3bc89ef62ce7 490 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
emilmont 10:3bc89ef62ce7 491 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
emilmont 10:3bc89ef62ce7 492
emilmont 10:3bc89ef62ce7 493 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
emilmont 10:3bc89ef62ce7 494 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
emilmont 10:3bc89ef62ce7 495
emilmont 10:3bc89ef62ce7 496 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
emilmont 10:3bc89ef62ce7 497 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
emilmont 10:3bc89ef62ce7 498
emilmont 10:3bc89ef62ce7 499 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
emilmont 10:3bc89ef62ce7 500 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
emilmont 10:3bc89ef62ce7 501
emilmont 10:3bc89ef62ce7 502 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
emilmont 10:3bc89ef62ce7 503 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
emilmont 10:3bc89ef62ce7 504
emilmont 10:3bc89ef62ce7 505 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
emilmont 10:3bc89ef62ce7 506 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
emilmont 10:3bc89ef62ce7 507
emilmont 10:3bc89ef62ce7 508 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
emilmont 10:3bc89ef62ce7 509 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
emilmont 10:3bc89ef62ce7 510
emilmont 10:3bc89ef62ce7 511 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
emilmont 10:3bc89ef62ce7 512 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
emilmont 10:3bc89ef62ce7 513
emilmont 10:3bc89ef62ce7 514 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
emilmont 10:3bc89ef62ce7 515 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
emilmont 10:3bc89ef62ce7 516
emilmont 10:3bc89ef62ce7 517 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
emilmont 10:3bc89ef62ce7 518 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
emilmont 10:3bc89ef62ce7 519
emilmont 10:3bc89ef62ce7 520 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
emilmont 10:3bc89ef62ce7 521 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
emilmont 10:3bc89ef62ce7 522
emilmont 10:3bc89ef62ce7 523 /* SCB Configurable Fault Status Registers Definitions */
emilmont 10:3bc89ef62ce7 524 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
emilmont 10:3bc89ef62ce7 525 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
emilmont 10:3bc89ef62ce7 526
emilmont 10:3bc89ef62ce7 527 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
emilmont 10:3bc89ef62ce7 528 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
emilmont 10:3bc89ef62ce7 529
emilmont 10:3bc89ef62ce7 530 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
emilmont 10:3bc89ef62ce7 531 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
emilmont 10:3bc89ef62ce7 532
emilmont 10:3bc89ef62ce7 533 /* SCB Hard Fault Status Registers Definitions */
emilmont 10:3bc89ef62ce7 534 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
emilmont 10:3bc89ef62ce7 535 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
emilmont 10:3bc89ef62ce7 536
emilmont 10:3bc89ef62ce7 537 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
emilmont 10:3bc89ef62ce7 538 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
emilmont 10:3bc89ef62ce7 539
emilmont 10:3bc89ef62ce7 540 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
emilmont 10:3bc89ef62ce7 541 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
emilmont 10:3bc89ef62ce7 542
emilmont 10:3bc89ef62ce7 543 /* SCB Debug Fault Status Register Definitions */
emilmont 10:3bc89ef62ce7 544 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
emilmont 10:3bc89ef62ce7 545 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
emilmont 10:3bc89ef62ce7 546
emilmont 10:3bc89ef62ce7 547 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
emilmont 10:3bc89ef62ce7 548 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
emilmont 10:3bc89ef62ce7 549
emilmont 10:3bc89ef62ce7 550 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
emilmont 10:3bc89ef62ce7 551 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
emilmont 10:3bc89ef62ce7 552
emilmont 10:3bc89ef62ce7 553 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
emilmont 10:3bc89ef62ce7 554 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
emilmont 10:3bc89ef62ce7 555
emilmont 10:3bc89ef62ce7 556 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
emilmont 10:3bc89ef62ce7 557 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
emilmont 10:3bc89ef62ce7 558
emilmont 10:3bc89ef62ce7 559 /*@} end of group CMSIS_SCB */
emilmont 10:3bc89ef62ce7 560
emilmont 10:3bc89ef62ce7 561
emilmont 10:3bc89ef62ce7 562 /** \ingroup CMSIS_core_register
emilmont 10:3bc89ef62ce7 563 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
emilmont 10:3bc89ef62ce7 564 \brief Type definitions for the System Control and ID Register not in the SCB
emilmont 10:3bc89ef62ce7 565 @{
emilmont 10:3bc89ef62ce7 566 */
emilmont 10:3bc89ef62ce7 567
emilmont 10:3bc89ef62ce7 568 /** \brief Structure type to access the System Control and ID Register not in the SCB.
emilmont 10:3bc89ef62ce7 569 */
emilmont 10:3bc89ef62ce7 570 typedef struct
emilmont 10:3bc89ef62ce7 571 {
emilmont 10:3bc89ef62ce7 572 uint32_t RESERVED0[1];
emilmont 10:3bc89ef62ce7 573 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
emilmont 10:3bc89ef62ce7 574 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
emilmont 10:3bc89ef62ce7 575 } SCnSCB_Type;
emilmont 10:3bc89ef62ce7 576
emilmont 10:3bc89ef62ce7 577 /* Interrupt Controller Type Register Definitions */
emilmont 10:3bc89ef62ce7 578 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
emilmont 10:3bc89ef62ce7 579 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
emilmont 10:3bc89ef62ce7 580
emilmont 10:3bc89ef62ce7 581 /* Auxiliary Control Register Definitions */
emilmont 10:3bc89ef62ce7 582 #define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
emilmont 10:3bc89ef62ce7 583 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
emilmont 10:3bc89ef62ce7 584
emilmont 10:3bc89ef62ce7 585 #define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
emilmont 10:3bc89ef62ce7 586 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
emilmont 10:3bc89ef62ce7 587
emilmont 10:3bc89ef62ce7 588 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
emilmont 10:3bc89ef62ce7 589 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
emilmont 10:3bc89ef62ce7 590
emilmont 10:3bc89ef62ce7 591 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
emilmont 10:3bc89ef62ce7 592 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
emilmont 10:3bc89ef62ce7 593
emilmont 10:3bc89ef62ce7 594 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
emilmont 10:3bc89ef62ce7 595 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
emilmont 10:3bc89ef62ce7 596
emilmont 10:3bc89ef62ce7 597 /*@} end of group CMSIS_SCnotSCB */
emilmont 10:3bc89ef62ce7 598
emilmont 10:3bc89ef62ce7 599
emilmont 10:3bc89ef62ce7 600 /** \ingroup CMSIS_core_register
emilmont 10:3bc89ef62ce7 601 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
emilmont 10:3bc89ef62ce7 602 \brief Type definitions for the System Timer Registers.
emilmont 10:3bc89ef62ce7 603 @{
emilmont 10:3bc89ef62ce7 604 */
emilmont 10:3bc89ef62ce7 605
emilmont 10:3bc89ef62ce7 606 /** \brief Structure type to access the System Timer (SysTick).
emilmont 10:3bc89ef62ce7 607 */
emilmont 10:3bc89ef62ce7 608 typedef struct
emilmont 10:3bc89ef62ce7 609 {
emilmont 10:3bc89ef62ce7 610 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
emilmont 10:3bc89ef62ce7 611 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
emilmont 10:3bc89ef62ce7 612 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
emilmont 10:3bc89ef62ce7 613 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
emilmont 10:3bc89ef62ce7 614 } SysTick_Type;
emilmont 10:3bc89ef62ce7 615
emilmont 10:3bc89ef62ce7 616 /* SysTick Control / Status Register Definitions */
emilmont 10:3bc89ef62ce7 617 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
emilmont 10:3bc89ef62ce7 618 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
emilmont 10:3bc89ef62ce7 619
emilmont 10:3bc89ef62ce7 620 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
emilmont 10:3bc89ef62ce7 621 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
emilmont 10:3bc89ef62ce7 622
emilmont 10:3bc89ef62ce7 623 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
emilmont 10:3bc89ef62ce7 624 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
emilmont 10:3bc89ef62ce7 625
emilmont 10:3bc89ef62ce7 626 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
emilmont 10:3bc89ef62ce7 627 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
emilmont 10:3bc89ef62ce7 628
emilmont 10:3bc89ef62ce7 629 /* SysTick Reload Register Definitions */
emilmont 10:3bc89ef62ce7 630 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
emilmont 10:3bc89ef62ce7 631 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
emilmont 10:3bc89ef62ce7 632
emilmont 10:3bc89ef62ce7 633 /* SysTick Current Register Definitions */
emilmont 10:3bc89ef62ce7 634 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
emilmont 10:3bc89ef62ce7 635 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
emilmont 10:3bc89ef62ce7 636
emilmont 10:3bc89ef62ce7 637 /* SysTick Calibration Register Definitions */
emilmont 10:3bc89ef62ce7 638 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
emilmont 10:3bc89ef62ce7 639 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
emilmont 10:3bc89ef62ce7 640
emilmont 10:3bc89ef62ce7 641 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
emilmont 10:3bc89ef62ce7 642 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
emilmont 10:3bc89ef62ce7 643
emilmont 10:3bc89ef62ce7 644 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
emilmont 10:3bc89ef62ce7 645 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
emilmont 10:3bc89ef62ce7 646
emilmont 10:3bc89ef62ce7 647 /*@} end of group CMSIS_SysTick */
emilmont 10:3bc89ef62ce7 648
emilmont 10:3bc89ef62ce7 649
emilmont 10:3bc89ef62ce7 650 /** \ingroup CMSIS_core_register
emilmont 10:3bc89ef62ce7 651 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
emilmont 10:3bc89ef62ce7 652 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
emilmont 10:3bc89ef62ce7 653 @{
emilmont 10:3bc89ef62ce7 654 */
emilmont 10:3bc89ef62ce7 655
emilmont 10:3bc89ef62ce7 656 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
emilmont 10:3bc89ef62ce7 657 */
emilmont 10:3bc89ef62ce7 658 typedef struct
emilmont 10:3bc89ef62ce7 659 {
emilmont 10:3bc89ef62ce7 660 __O union
emilmont 10:3bc89ef62ce7 661 {
emilmont 10:3bc89ef62ce7 662 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
emilmont 10:3bc89ef62ce7 663 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
emilmont 10:3bc89ef62ce7 664 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
emilmont 10:3bc89ef62ce7 665 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
emilmont 10:3bc89ef62ce7 666 uint32_t RESERVED0[864];
emilmont 10:3bc89ef62ce7 667 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
emilmont 10:3bc89ef62ce7 668 uint32_t RESERVED1[15];
emilmont 10:3bc89ef62ce7 669 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
emilmont 10:3bc89ef62ce7 670 uint32_t RESERVED2[15];
emilmont 10:3bc89ef62ce7 671 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
emilmont 10:3bc89ef62ce7 672 uint32_t RESERVED3[29];
emilmont 10:3bc89ef62ce7 673 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
emilmont 10:3bc89ef62ce7 674 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
emilmont 10:3bc89ef62ce7 675 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
emilmont 10:3bc89ef62ce7 676 uint32_t RESERVED4[43];
emilmont 10:3bc89ef62ce7 677 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
emilmont 10:3bc89ef62ce7 678 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
emilmont 10:3bc89ef62ce7 679 uint32_t RESERVED5[6];
emilmont 10:3bc89ef62ce7 680 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
emilmont 10:3bc89ef62ce7 681 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
emilmont 10:3bc89ef62ce7 682 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
emilmont 10:3bc89ef62ce7 683 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
emilmont 10:3bc89ef62ce7 684 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
emilmont 10:3bc89ef62ce7 685 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
emilmont 10:3bc89ef62ce7 686 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
emilmont 10:3bc89ef62ce7 687 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
emilmont 10:3bc89ef62ce7 688 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
emilmont 10:3bc89ef62ce7 689 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
emilmont 10:3bc89ef62ce7 690 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
emilmont 10:3bc89ef62ce7 691 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
emilmont 10:3bc89ef62ce7 692 } ITM_Type;
emilmont 10:3bc89ef62ce7 693
emilmont 10:3bc89ef62ce7 694 /* ITM Trace Privilege Register Definitions */
emilmont 10:3bc89ef62ce7 695 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
emilmont 10:3bc89ef62ce7 696 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
emilmont 10:3bc89ef62ce7 697
emilmont 10:3bc89ef62ce7 698 /* ITM Trace Control Register Definitions */
emilmont 10:3bc89ef62ce7 699 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
emilmont 10:3bc89ef62ce7 700 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
emilmont 10:3bc89ef62ce7 701
emilmont 10:3bc89ef62ce7 702 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
emilmont 10:3bc89ef62ce7 703 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
emilmont 10:3bc89ef62ce7 704
emilmont 10:3bc89ef62ce7 705 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
emilmont 10:3bc89ef62ce7 706 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
emilmont 10:3bc89ef62ce7 707
emilmont 10:3bc89ef62ce7 708 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
emilmont 10:3bc89ef62ce7 709 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
emilmont 10:3bc89ef62ce7 710
emilmont 10:3bc89ef62ce7 711 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
emilmont 10:3bc89ef62ce7 712 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
emilmont 10:3bc89ef62ce7 713
emilmont 10:3bc89ef62ce7 714 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
emilmont 10:3bc89ef62ce7 715 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
emilmont 10:3bc89ef62ce7 716
emilmont 10:3bc89ef62ce7 717 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
emilmont 10:3bc89ef62ce7 718 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
emilmont 10:3bc89ef62ce7 719
emilmont 10:3bc89ef62ce7 720 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
emilmont 10:3bc89ef62ce7 721 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
emilmont 10:3bc89ef62ce7 722
emilmont 10:3bc89ef62ce7 723 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
emilmont 10:3bc89ef62ce7 724 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
emilmont 10:3bc89ef62ce7 725
emilmont 10:3bc89ef62ce7 726 /* ITM Integration Write Register Definitions */
emilmont 10:3bc89ef62ce7 727 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
emilmont 10:3bc89ef62ce7 728 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
emilmont 10:3bc89ef62ce7 729
emilmont 10:3bc89ef62ce7 730 /* ITM Integration Read Register Definitions */
emilmont 10:3bc89ef62ce7 731 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
emilmont 10:3bc89ef62ce7 732 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
emilmont 10:3bc89ef62ce7 733
emilmont 10:3bc89ef62ce7 734 /* ITM Integration Mode Control Register Definitions */
emilmont 10:3bc89ef62ce7 735 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
emilmont 10:3bc89ef62ce7 736 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
emilmont 10:3bc89ef62ce7 737
emilmont 10:3bc89ef62ce7 738 /* ITM Lock Status Register Definitions */
emilmont 10:3bc89ef62ce7 739 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
emilmont 10:3bc89ef62ce7 740 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
emilmont 10:3bc89ef62ce7 741
emilmont 10:3bc89ef62ce7 742 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
emilmont 10:3bc89ef62ce7 743 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
emilmont 10:3bc89ef62ce7 744
emilmont 10:3bc89ef62ce7 745 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
emilmont 10:3bc89ef62ce7 746 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
emilmont 10:3bc89ef62ce7 747
emilmont 10:3bc89ef62ce7 748 /*@}*/ /* end of group CMSIS_ITM */
emilmont 10:3bc89ef62ce7 749
emilmont 10:3bc89ef62ce7 750
emilmont 10:3bc89ef62ce7 751 /** \ingroup CMSIS_core_register
emilmont 10:3bc89ef62ce7 752 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
emilmont 10:3bc89ef62ce7 753 \brief Type definitions for the Data Watchpoint and Trace (DWT)
emilmont 10:3bc89ef62ce7 754 @{
emilmont 10:3bc89ef62ce7 755 */
emilmont 10:3bc89ef62ce7 756
emilmont 10:3bc89ef62ce7 757 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
emilmont 10:3bc89ef62ce7 758 */
emilmont 10:3bc89ef62ce7 759 typedef struct
emilmont 10:3bc89ef62ce7 760 {
emilmont 10:3bc89ef62ce7 761 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
emilmont 10:3bc89ef62ce7 762 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
emilmont 10:3bc89ef62ce7 763 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
emilmont 10:3bc89ef62ce7 764 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
emilmont 10:3bc89ef62ce7 765 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
emilmont 10:3bc89ef62ce7 766 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
emilmont 10:3bc89ef62ce7 767 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
emilmont 10:3bc89ef62ce7 768 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
emilmont 10:3bc89ef62ce7 769 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
emilmont 10:3bc89ef62ce7 770 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
emilmont 10:3bc89ef62ce7 771 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
emilmont 10:3bc89ef62ce7 772 uint32_t RESERVED0[1];
emilmont 10:3bc89ef62ce7 773 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
emilmont 10:3bc89ef62ce7 774 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
emilmont 10:3bc89ef62ce7 775 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
emilmont 10:3bc89ef62ce7 776 uint32_t RESERVED1[1];
emilmont 10:3bc89ef62ce7 777 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
emilmont 10:3bc89ef62ce7 778 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
emilmont 10:3bc89ef62ce7 779 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
emilmont 10:3bc89ef62ce7 780 uint32_t RESERVED2[1];
emilmont 10:3bc89ef62ce7 781 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
emilmont 10:3bc89ef62ce7 782 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
emilmont 10:3bc89ef62ce7 783 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
emilmont 10:3bc89ef62ce7 784 } DWT_Type;
emilmont 10:3bc89ef62ce7 785
emilmont 10:3bc89ef62ce7 786 /* DWT Control Register Definitions */
emilmont 10:3bc89ef62ce7 787 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
emilmont 10:3bc89ef62ce7 788 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
emilmont 10:3bc89ef62ce7 789
emilmont 10:3bc89ef62ce7 790 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
emilmont 10:3bc89ef62ce7 791 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
emilmont 10:3bc89ef62ce7 792
emilmont 10:3bc89ef62ce7 793 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
emilmont 10:3bc89ef62ce7 794 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
emilmont 10:3bc89ef62ce7 795
emilmont 10:3bc89ef62ce7 796 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
emilmont 10:3bc89ef62ce7 797 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
emilmont 10:3bc89ef62ce7 798
emilmont 10:3bc89ef62ce7 799 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
emilmont 10:3bc89ef62ce7 800 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
emilmont 10:3bc89ef62ce7 801
emilmont 10:3bc89ef62ce7 802 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
emilmont 10:3bc89ef62ce7 803 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
emilmont 10:3bc89ef62ce7 804
emilmont 10:3bc89ef62ce7 805 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
emilmont 10:3bc89ef62ce7 806 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
emilmont 10:3bc89ef62ce7 807
emilmont 10:3bc89ef62ce7 808 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
emilmont 10:3bc89ef62ce7 809 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
emilmont 10:3bc89ef62ce7 810
emilmont 10:3bc89ef62ce7 811 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
emilmont 10:3bc89ef62ce7 812 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
emilmont 10:3bc89ef62ce7 813
emilmont 10:3bc89ef62ce7 814 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
emilmont 10:3bc89ef62ce7 815 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
emilmont 10:3bc89ef62ce7 816
emilmont 10:3bc89ef62ce7 817 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
emilmont 10:3bc89ef62ce7 818 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
emilmont 10:3bc89ef62ce7 819
emilmont 10:3bc89ef62ce7 820 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
emilmont 10:3bc89ef62ce7 821 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
emilmont 10:3bc89ef62ce7 822
emilmont 10:3bc89ef62ce7 823 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
emilmont 10:3bc89ef62ce7 824 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
emilmont 10:3bc89ef62ce7 825
emilmont 10:3bc89ef62ce7 826 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
emilmont 10:3bc89ef62ce7 827 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
emilmont 10:3bc89ef62ce7 828
emilmont 10:3bc89ef62ce7 829 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
emilmont 10:3bc89ef62ce7 830 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
emilmont 10:3bc89ef62ce7 831
emilmont 10:3bc89ef62ce7 832 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
emilmont 10:3bc89ef62ce7 833 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
emilmont 10:3bc89ef62ce7 834
emilmont 10:3bc89ef62ce7 835 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
emilmont 10:3bc89ef62ce7 836 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
emilmont 10:3bc89ef62ce7 837
emilmont 10:3bc89ef62ce7 838 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
emilmont 10:3bc89ef62ce7 839 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
emilmont 10:3bc89ef62ce7 840
emilmont 10:3bc89ef62ce7 841 /* DWT CPI Count Register Definitions */
emilmont 10:3bc89ef62ce7 842 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
emilmont 10:3bc89ef62ce7 843 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
emilmont 10:3bc89ef62ce7 844
emilmont 10:3bc89ef62ce7 845 /* DWT Exception Overhead Count Register Definitions */
emilmont 10:3bc89ef62ce7 846 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
emilmont 10:3bc89ef62ce7 847 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
emilmont 10:3bc89ef62ce7 848
emilmont 10:3bc89ef62ce7 849 /* DWT Sleep Count Register Definitions */
emilmont 10:3bc89ef62ce7 850 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
emilmont 10:3bc89ef62ce7 851 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
emilmont 10:3bc89ef62ce7 852
emilmont 10:3bc89ef62ce7 853 /* DWT LSU Count Register Definitions */
emilmont 10:3bc89ef62ce7 854 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
emilmont 10:3bc89ef62ce7 855 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
emilmont 10:3bc89ef62ce7 856
emilmont 10:3bc89ef62ce7 857 /* DWT Folded-instruction Count Register Definitions */
emilmont 10:3bc89ef62ce7 858 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
emilmont 10:3bc89ef62ce7 859 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
emilmont 10:3bc89ef62ce7 860
emilmont 10:3bc89ef62ce7 861 /* DWT Comparator Mask Register Definitions */
emilmont 10:3bc89ef62ce7 862 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
emilmont 10:3bc89ef62ce7 863 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
emilmont 10:3bc89ef62ce7 864
emilmont 10:3bc89ef62ce7 865 /* DWT Comparator Function Register Definitions */
emilmont 10:3bc89ef62ce7 866 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
emilmont 10:3bc89ef62ce7 867 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
emilmont 10:3bc89ef62ce7 868
emilmont 10:3bc89ef62ce7 869 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
emilmont 10:3bc89ef62ce7 870 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
emilmont 10:3bc89ef62ce7 871
emilmont 10:3bc89ef62ce7 872 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
emilmont 10:3bc89ef62ce7 873 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
emilmont 10:3bc89ef62ce7 874
emilmont 10:3bc89ef62ce7 875 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
emilmont 10:3bc89ef62ce7 876 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
emilmont 10:3bc89ef62ce7 877
emilmont 10:3bc89ef62ce7 878 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
emilmont 10:3bc89ef62ce7 879 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
emilmont 10:3bc89ef62ce7 880
emilmont 10:3bc89ef62ce7 881 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
emilmont 10:3bc89ef62ce7 882 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
emilmont 10:3bc89ef62ce7 883
emilmont 10:3bc89ef62ce7 884 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
emilmont 10:3bc89ef62ce7 885 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
emilmont 10:3bc89ef62ce7 886
emilmont 10:3bc89ef62ce7 887 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
emilmont 10:3bc89ef62ce7 888 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
emilmont 10:3bc89ef62ce7 889
emilmont 10:3bc89ef62ce7 890 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
emilmont 10:3bc89ef62ce7 891 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
emilmont 10:3bc89ef62ce7 892
emilmont 10:3bc89ef62ce7 893 /*@}*/ /* end of group CMSIS_DWT */
emilmont 10:3bc89ef62ce7 894
emilmont 10:3bc89ef62ce7 895
emilmont 10:3bc89ef62ce7 896 /** \ingroup CMSIS_core_register
emilmont 10:3bc89ef62ce7 897 \defgroup CMSIS_TPI Trace Port Interface (TPI)
emilmont 10:3bc89ef62ce7 898 \brief Type definitions for the Trace Port Interface (TPI)
emilmont 10:3bc89ef62ce7 899 @{
emilmont 10:3bc89ef62ce7 900 */
emilmont 10:3bc89ef62ce7 901
emilmont 10:3bc89ef62ce7 902 /** \brief Structure type to access the Trace Port Interface Register (TPI).
emilmont 10:3bc89ef62ce7 903 */
emilmont 10:3bc89ef62ce7 904 typedef struct
emilmont 10:3bc89ef62ce7 905 {
emilmont 10:3bc89ef62ce7 906 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
emilmont 10:3bc89ef62ce7 907 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
emilmont 10:3bc89ef62ce7 908 uint32_t RESERVED0[2];
emilmont 10:3bc89ef62ce7 909 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
emilmont 10:3bc89ef62ce7 910 uint32_t RESERVED1[55];
emilmont 10:3bc89ef62ce7 911 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
emilmont 10:3bc89ef62ce7 912 uint32_t RESERVED2[131];
emilmont 10:3bc89ef62ce7 913 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
emilmont 10:3bc89ef62ce7 914 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
emilmont 10:3bc89ef62ce7 915 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
emilmont 10:3bc89ef62ce7 916 uint32_t RESERVED3[759];
emilmont 10:3bc89ef62ce7 917 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
emilmont 10:3bc89ef62ce7 918 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
emilmont 10:3bc89ef62ce7 919 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
emilmont 10:3bc89ef62ce7 920 uint32_t RESERVED4[1];
emilmont 10:3bc89ef62ce7 921 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
emilmont 10:3bc89ef62ce7 922 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
emilmont 10:3bc89ef62ce7 923 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
emilmont 10:3bc89ef62ce7 924 uint32_t RESERVED5[39];
emilmont 10:3bc89ef62ce7 925 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
emilmont 10:3bc89ef62ce7 926 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
emilmont 10:3bc89ef62ce7 927 uint32_t RESERVED7[8];
emilmont 10:3bc89ef62ce7 928 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
emilmont 10:3bc89ef62ce7 929 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
emilmont 10:3bc89ef62ce7 930 } TPI_Type;
emilmont 10:3bc89ef62ce7 931
emilmont 10:3bc89ef62ce7 932 /* TPI Asynchronous Clock Prescaler Register Definitions */
emilmont 10:3bc89ef62ce7 933 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
emilmont 10:3bc89ef62ce7 934 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
emilmont 10:3bc89ef62ce7 935
emilmont 10:3bc89ef62ce7 936 /* TPI Selected Pin Protocol Register Definitions */
emilmont 10:3bc89ef62ce7 937 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
emilmont 10:3bc89ef62ce7 938 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
emilmont 10:3bc89ef62ce7 939
emilmont 10:3bc89ef62ce7 940 /* TPI Formatter and Flush Status Register Definitions */
emilmont 10:3bc89ef62ce7 941 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
emilmont 10:3bc89ef62ce7 942 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
emilmont 10:3bc89ef62ce7 943
emilmont 10:3bc89ef62ce7 944 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
emilmont 10:3bc89ef62ce7 945 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
emilmont 10:3bc89ef62ce7 946
emilmont 10:3bc89ef62ce7 947 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
emilmont 10:3bc89ef62ce7 948 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
emilmont 10:3bc89ef62ce7 949
emilmont 10:3bc89ef62ce7 950 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
emilmont 10:3bc89ef62ce7 951 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
emilmont 10:3bc89ef62ce7 952
emilmont 10:3bc89ef62ce7 953 /* TPI Formatter and Flush Control Register Definitions */
emilmont 10:3bc89ef62ce7 954 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
emilmont 10:3bc89ef62ce7 955 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
emilmont 10:3bc89ef62ce7 956
emilmont 10:3bc89ef62ce7 957 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
emilmont 10:3bc89ef62ce7 958 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
emilmont 10:3bc89ef62ce7 959
emilmont 10:3bc89ef62ce7 960 /* TPI TRIGGER Register Definitions */
emilmont 10:3bc89ef62ce7 961 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
emilmont 10:3bc89ef62ce7 962 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
emilmont 10:3bc89ef62ce7 963
emilmont 10:3bc89ef62ce7 964 /* TPI Integration ETM Data Register Definitions (FIFO0) */
emilmont 10:3bc89ef62ce7 965 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
emilmont 10:3bc89ef62ce7 966 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
emilmont 10:3bc89ef62ce7 967
emilmont 10:3bc89ef62ce7 968 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
emilmont 10:3bc89ef62ce7 969 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
emilmont 10:3bc89ef62ce7 970
emilmont 10:3bc89ef62ce7 971 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
emilmont 10:3bc89ef62ce7 972 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
emilmont 10:3bc89ef62ce7 973
emilmont 10:3bc89ef62ce7 974 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
emilmont 10:3bc89ef62ce7 975 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
emilmont 10:3bc89ef62ce7 976
emilmont 10:3bc89ef62ce7 977 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
emilmont 10:3bc89ef62ce7 978 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
emilmont 10:3bc89ef62ce7 979
emilmont 10:3bc89ef62ce7 980 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
emilmont 10:3bc89ef62ce7 981 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
emilmont 10:3bc89ef62ce7 982
emilmont 10:3bc89ef62ce7 983 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
emilmont 10:3bc89ef62ce7 984 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
emilmont 10:3bc89ef62ce7 985
emilmont 10:3bc89ef62ce7 986 /* TPI ITATBCTR2 Register Definitions */
emilmont 10:3bc89ef62ce7 987 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
emilmont 10:3bc89ef62ce7 988 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
emilmont 10:3bc89ef62ce7 989
emilmont 10:3bc89ef62ce7 990 /* TPI Integration ITM Data Register Definitions (FIFO1) */
emilmont 10:3bc89ef62ce7 991 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
emilmont 10:3bc89ef62ce7 992 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
emilmont 10:3bc89ef62ce7 993
emilmont 10:3bc89ef62ce7 994 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
emilmont 10:3bc89ef62ce7 995 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
emilmont 10:3bc89ef62ce7 996
emilmont 10:3bc89ef62ce7 997 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
emilmont 10:3bc89ef62ce7 998 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
emilmont 10:3bc89ef62ce7 999
emilmont 10:3bc89ef62ce7 1000 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
emilmont 10:3bc89ef62ce7 1001 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
emilmont 10:3bc89ef62ce7 1002
emilmont 10:3bc89ef62ce7 1003 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
emilmont 10:3bc89ef62ce7 1004 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
emilmont 10:3bc89ef62ce7 1005
emilmont 10:3bc89ef62ce7 1006 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
emilmont 10:3bc89ef62ce7 1007 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
emilmont 10:3bc89ef62ce7 1008
emilmont 10:3bc89ef62ce7 1009 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
emilmont 10:3bc89ef62ce7 1010 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
emilmont 10:3bc89ef62ce7 1011
emilmont 10:3bc89ef62ce7 1012 /* TPI ITATBCTR0 Register Definitions */
emilmont 10:3bc89ef62ce7 1013 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
emilmont 10:3bc89ef62ce7 1014 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
emilmont 10:3bc89ef62ce7 1015
emilmont 10:3bc89ef62ce7 1016 /* TPI Integration Mode Control Register Definitions */
emilmont 10:3bc89ef62ce7 1017 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
emilmont 10:3bc89ef62ce7 1018 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
emilmont 10:3bc89ef62ce7 1019
emilmont 10:3bc89ef62ce7 1020 /* TPI DEVID Register Definitions */
emilmont 10:3bc89ef62ce7 1021 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
emilmont 10:3bc89ef62ce7 1022 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
emilmont 10:3bc89ef62ce7 1023
emilmont 10:3bc89ef62ce7 1024 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
emilmont 10:3bc89ef62ce7 1025 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
emilmont 10:3bc89ef62ce7 1026
emilmont 10:3bc89ef62ce7 1027 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
emilmont 10:3bc89ef62ce7 1028 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
emilmont 10:3bc89ef62ce7 1029
emilmont 10:3bc89ef62ce7 1030 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
emilmont 10:3bc89ef62ce7 1031 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
emilmont 10:3bc89ef62ce7 1032
emilmont 10:3bc89ef62ce7 1033 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
emilmont 10:3bc89ef62ce7 1034 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
emilmont 10:3bc89ef62ce7 1035
emilmont 10:3bc89ef62ce7 1036 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
emilmont 10:3bc89ef62ce7 1037 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
emilmont 10:3bc89ef62ce7 1038
emilmont 10:3bc89ef62ce7 1039 /* TPI DEVTYPE Register Definitions */
emilmont 10:3bc89ef62ce7 1040 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
emilmont 10:3bc89ef62ce7 1041 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
emilmont 10:3bc89ef62ce7 1042
emilmont 10:3bc89ef62ce7 1043 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
emilmont 10:3bc89ef62ce7 1044 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
emilmont 10:3bc89ef62ce7 1045
emilmont 10:3bc89ef62ce7 1046 /*@}*/ /* end of group CMSIS_TPI */
emilmont 10:3bc89ef62ce7 1047
emilmont 10:3bc89ef62ce7 1048
emilmont 10:3bc89ef62ce7 1049 #if (__MPU_PRESENT == 1)
emilmont 10:3bc89ef62ce7 1050 /** \ingroup CMSIS_core_register
emilmont 10:3bc89ef62ce7 1051 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
emilmont 10:3bc89ef62ce7 1052 \brief Type definitions for the Memory Protection Unit (MPU)
emilmont 10:3bc89ef62ce7 1053 @{
emilmont 10:3bc89ef62ce7 1054 */
emilmont 10:3bc89ef62ce7 1055
emilmont 10:3bc89ef62ce7 1056 /** \brief Structure type to access the Memory Protection Unit (MPU).
emilmont 10:3bc89ef62ce7 1057 */
emilmont 10:3bc89ef62ce7 1058 typedef struct
emilmont 10:3bc89ef62ce7 1059 {
emilmont 10:3bc89ef62ce7 1060 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
emilmont 10:3bc89ef62ce7 1061 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
emilmont 10:3bc89ef62ce7 1062 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
emilmont 10:3bc89ef62ce7 1063 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
emilmont 10:3bc89ef62ce7 1064 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
emilmont 10:3bc89ef62ce7 1065 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
emilmont 10:3bc89ef62ce7 1066 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
emilmont 10:3bc89ef62ce7 1067 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
emilmont 10:3bc89ef62ce7 1068 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
emilmont 10:3bc89ef62ce7 1069 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
emilmont 10:3bc89ef62ce7 1070 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
emilmont 10:3bc89ef62ce7 1071 } MPU_Type;
emilmont 10:3bc89ef62ce7 1072
emilmont 10:3bc89ef62ce7 1073 /* MPU Type Register */
emilmont 10:3bc89ef62ce7 1074 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
emilmont 10:3bc89ef62ce7 1075 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
emilmont 10:3bc89ef62ce7 1076
emilmont 10:3bc89ef62ce7 1077 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
emilmont 10:3bc89ef62ce7 1078 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
emilmont 10:3bc89ef62ce7 1079
emilmont 10:3bc89ef62ce7 1080 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
emilmont 10:3bc89ef62ce7 1081 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
emilmont 10:3bc89ef62ce7 1082
emilmont 10:3bc89ef62ce7 1083 /* MPU Control Register */
emilmont 10:3bc89ef62ce7 1084 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
emilmont 10:3bc89ef62ce7 1085 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
emilmont 10:3bc89ef62ce7 1086
emilmont 10:3bc89ef62ce7 1087 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
emilmont 10:3bc89ef62ce7 1088 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
emilmont 10:3bc89ef62ce7 1089
emilmont 10:3bc89ef62ce7 1090 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
emilmont 10:3bc89ef62ce7 1091 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
emilmont 10:3bc89ef62ce7 1092
emilmont 10:3bc89ef62ce7 1093 /* MPU Region Number Register */
emilmont 10:3bc89ef62ce7 1094 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
emilmont 10:3bc89ef62ce7 1095 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
emilmont 10:3bc89ef62ce7 1096
emilmont 10:3bc89ef62ce7 1097 /* MPU Region Base Address Register */
emilmont 10:3bc89ef62ce7 1098 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
emilmont 10:3bc89ef62ce7 1099 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
emilmont 10:3bc89ef62ce7 1100
emilmont 10:3bc89ef62ce7 1101 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
emilmont 10:3bc89ef62ce7 1102 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
emilmont 10:3bc89ef62ce7 1103
emilmont 10:3bc89ef62ce7 1104 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
emilmont 10:3bc89ef62ce7 1105 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
emilmont 10:3bc89ef62ce7 1106
emilmont 10:3bc89ef62ce7 1107 /* MPU Region Attribute and Size Register */
emilmont 10:3bc89ef62ce7 1108 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
emilmont 10:3bc89ef62ce7 1109 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
emilmont 10:3bc89ef62ce7 1110
emilmont 10:3bc89ef62ce7 1111 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
emilmont 10:3bc89ef62ce7 1112 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
emilmont 10:3bc89ef62ce7 1113
emilmont 10:3bc89ef62ce7 1114 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
emilmont 10:3bc89ef62ce7 1115 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
emilmont 10:3bc89ef62ce7 1116
emilmont 10:3bc89ef62ce7 1117 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
emilmont 10:3bc89ef62ce7 1118 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
emilmont 10:3bc89ef62ce7 1119
emilmont 10:3bc89ef62ce7 1120 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
emilmont 10:3bc89ef62ce7 1121 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
emilmont 10:3bc89ef62ce7 1122
emilmont 10:3bc89ef62ce7 1123 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
emilmont 10:3bc89ef62ce7 1124 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
emilmont 10:3bc89ef62ce7 1125
emilmont 10:3bc89ef62ce7 1126 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
emilmont 10:3bc89ef62ce7 1127 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
emilmont 10:3bc89ef62ce7 1128
emilmont 10:3bc89ef62ce7 1129 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
emilmont 10:3bc89ef62ce7 1130 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
emilmont 10:3bc89ef62ce7 1131
emilmont 10:3bc89ef62ce7 1132 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
emilmont 10:3bc89ef62ce7 1133 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
emilmont 10:3bc89ef62ce7 1134
emilmont 10:3bc89ef62ce7 1135 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
emilmont 10:3bc89ef62ce7 1136 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
emilmont 10:3bc89ef62ce7 1137
emilmont 10:3bc89ef62ce7 1138 /*@} end of group CMSIS_MPU */
emilmont 10:3bc89ef62ce7 1139 #endif
emilmont 10:3bc89ef62ce7 1140
emilmont 10:3bc89ef62ce7 1141
emilmont 10:3bc89ef62ce7 1142 #if (__FPU_PRESENT == 1)
emilmont 10:3bc89ef62ce7 1143 /** \ingroup CMSIS_core_register
emilmont 10:3bc89ef62ce7 1144 \defgroup CMSIS_FPU Floating Point Unit (FPU)
emilmont 10:3bc89ef62ce7 1145 \brief Type definitions for the Floating Point Unit (FPU)
emilmont 10:3bc89ef62ce7 1146 @{
emilmont 10:3bc89ef62ce7 1147 */
emilmont 10:3bc89ef62ce7 1148
emilmont 10:3bc89ef62ce7 1149 /** \brief Structure type to access the Floating Point Unit (FPU).
emilmont 10:3bc89ef62ce7 1150 */
emilmont 10:3bc89ef62ce7 1151 typedef struct
emilmont 10:3bc89ef62ce7 1152 {
emilmont 10:3bc89ef62ce7 1153 uint32_t RESERVED0[1];
emilmont 10:3bc89ef62ce7 1154 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
emilmont 10:3bc89ef62ce7 1155 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
emilmont 10:3bc89ef62ce7 1156 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
emilmont 10:3bc89ef62ce7 1157 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
emilmont 10:3bc89ef62ce7 1158 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
emilmont 10:3bc89ef62ce7 1159 } FPU_Type;
emilmont 10:3bc89ef62ce7 1160
emilmont 10:3bc89ef62ce7 1161 /* Floating-Point Context Control Register */
emilmont 10:3bc89ef62ce7 1162 #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
emilmont 10:3bc89ef62ce7 1163 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
emilmont 10:3bc89ef62ce7 1164
emilmont 10:3bc89ef62ce7 1165 #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
emilmont 10:3bc89ef62ce7 1166 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
emilmont 10:3bc89ef62ce7 1167
emilmont 10:3bc89ef62ce7 1168 #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
emilmont 10:3bc89ef62ce7 1169 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
emilmont 10:3bc89ef62ce7 1170
emilmont 10:3bc89ef62ce7 1171 #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
emilmont 10:3bc89ef62ce7 1172 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
emilmont 10:3bc89ef62ce7 1173
emilmont 10:3bc89ef62ce7 1174 #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
emilmont 10:3bc89ef62ce7 1175 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
emilmont 10:3bc89ef62ce7 1176
emilmont 10:3bc89ef62ce7 1177 #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
emilmont 10:3bc89ef62ce7 1178 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
emilmont 10:3bc89ef62ce7 1179
emilmont 10:3bc89ef62ce7 1180 #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
emilmont 10:3bc89ef62ce7 1181 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
emilmont 10:3bc89ef62ce7 1182
emilmont 10:3bc89ef62ce7 1183 #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
emilmont 10:3bc89ef62ce7 1184 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
emilmont 10:3bc89ef62ce7 1185
emilmont 10:3bc89ef62ce7 1186 #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
emilmont 10:3bc89ef62ce7 1187 #define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */
emilmont 10:3bc89ef62ce7 1188
emilmont 10:3bc89ef62ce7 1189 /* Floating-Point Context Address Register */
emilmont 10:3bc89ef62ce7 1190 #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
emilmont 10:3bc89ef62ce7 1191 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
emilmont 10:3bc89ef62ce7 1192
emilmont 10:3bc89ef62ce7 1193 /* Floating-Point Default Status Control Register */
emilmont 10:3bc89ef62ce7 1194 #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
emilmont 10:3bc89ef62ce7 1195 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
emilmont 10:3bc89ef62ce7 1196
emilmont 10:3bc89ef62ce7 1197 #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
emilmont 10:3bc89ef62ce7 1198 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
emilmont 10:3bc89ef62ce7 1199
emilmont 10:3bc89ef62ce7 1200 #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
emilmont 10:3bc89ef62ce7 1201 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
emilmont 10:3bc89ef62ce7 1202
emilmont 10:3bc89ef62ce7 1203 #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
emilmont 10:3bc89ef62ce7 1204 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
emilmont 10:3bc89ef62ce7 1205
emilmont 10:3bc89ef62ce7 1206 /* Media and FP Feature Register 0 */
emilmont 10:3bc89ef62ce7 1207 #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
emilmont 10:3bc89ef62ce7 1208 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
emilmont 10:3bc89ef62ce7 1209
emilmont 10:3bc89ef62ce7 1210 #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
emilmont 10:3bc89ef62ce7 1211 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
emilmont 10:3bc89ef62ce7 1212
emilmont 10:3bc89ef62ce7 1213 #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
emilmont 10:3bc89ef62ce7 1214 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
emilmont 10:3bc89ef62ce7 1215
emilmont 10:3bc89ef62ce7 1216 #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
emilmont 10:3bc89ef62ce7 1217 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
emilmont 10:3bc89ef62ce7 1218
emilmont 10:3bc89ef62ce7 1219 #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
emilmont 10:3bc89ef62ce7 1220 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
emilmont 10:3bc89ef62ce7 1221
emilmont 10:3bc89ef62ce7 1222 #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
emilmont 10:3bc89ef62ce7 1223 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
emilmont 10:3bc89ef62ce7 1224
emilmont 10:3bc89ef62ce7 1225 #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
emilmont 10:3bc89ef62ce7 1226 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
emilmont 10:3bc89ef62ce7 1227
emilmont 10:3bc89ef62ce7 1228 #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
emilmont 10:3bc89ef62ce7 1229 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */
emilmont 10:3bc89ef62ce7 1230
emilmont 10:3bc89ef62ce7 1231 /* Media and FP Feature Register 1 */
emilmont 10:3bc89ef62ce7 1232 #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
emilmont 10:3bc89ef62ce7 1233 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
emilmont 10:3bc89ef62ce7 1234
emilmont 10:3bc89ef62ce7 1235 #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
emilmont 10:3bc89ef62ce7 1236 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
emilmont 10:3bc89ef62ce7 1237
emilmont 10:3bc89ef62ce7 1238 #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
emilmont 10:3bc89ef62ce7 1239 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
emilmont 10:3bc89ef62ce7 1240
emilmont 10:3bc89ef62ce7 1241 #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
emilmont 10:3bc89ef62ce7 1242 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */
emilmont 10:3bc89ef62ce7 1243
emilmont 10:3bc89ef62ce7 1244 /*@} end of group CMSIS_FPU */
emilmont 10:3bc89ef62ce7 1245 #endif
emilmont 10:3bc89ef62ce7 1246
emilmont 10:3bc89ef62ce7 1247
emilmont 10:3bc89ef62ce7 1248 /** \ingroup CMSIS_core_register
emilmont 10:3bc89ef62ce7 1249 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
emilmont 10:3bc89ef62ce7 1250 \brief Type definitions for the Core Debug Registers
emilmont 10:3bc89ef62ce7 1251 @{
emilmont 10:3bc89ef62ce7 1252 */
emilmont 10:3bc89ef62ce7 1253
emilmont 10:3bc89ef62ce7 1254 /** \brief Structure type to access the Core Debug Register (CoreDebug).
emilmont 10:3bc89ef62ce7 1255 */
emilmont 10:3bc89ef62ce7 1256 typedef struct
emilmont 10:3bc89ef62ce7 1257 {
emilmont 10:3bc89ef62ce7 1258 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
emilmont 10:3bc89ef62ce7 1259 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
emilmont 10:3bc89ef62ce7 1260 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
emilmont 10:3bc89ef62ce7 1261 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
emilmont 10:3bc89ef62ce7 1262 } CoreDebug_Type;
emilmont 10:3bc89ef62ce7 1263
emilmont 10:3bc89ef62ce7 1264 /* Debug Halting Control and Status Register */
emilmont 10:3bc89ef62ce7 1265 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
emilmont 10:3bc89ef62ce7 1266 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
emilmont 10:3bc89ef62ce7 1267
emilmont 10:3bc89ef62ce7 1268 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
emilmont 10:3bc89ef62ce7 1269 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
emilmont 10:3bc89ef62ce7 1270
emilmont 10:3bc89ef62ce7 1271 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
emilmont 10:3bc89ef62ce7 1272 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
emilmont 10:3bc89ef62ce7 1273
emilmont 10:3bc89ef62ce7 1274 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
emilmont 10:3bc89ef62ce7 1275 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
emilmont 10:3bc89ef62ce7 1276
emilmont 10:3bc89ef62ce7 1277 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
emilmont 10:3bc89ef62ce7 1278 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
emilmont 10:3bc89ef62ce7 1279
emilmont 10:3bc89ef62ce7 1280 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
emilmont 10:3bc89ef62ce7 1281 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
emilmont 10:3bc89ef62ce7 1282
emilmont 10:3bc89ef62ce7 1283 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
emilmont 10:3bc89ef62ce7 1284 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
emilmont 10:3bc89ef62ce7 1285
emilmont 10:3bc89ef62ce7 1286 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
emilmont 10:3bc89ef62ce7 1287 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
emilmont 10:3bc89ef62ce7 1288
emilmont 10:3bc89ef62ce7 1289 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
emilmont 10:3bc89ef62ce7 1290 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
emilmont 10:3bc89ef62ce7 1291
emilmont 10:3bc89ef62ce7 1292 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
emilmont 10:3bc89ef62ce7 1293 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
emilmont 10:3bc89ef62ce7 1294
emilmont 10:3bc89ef62ce7 1295 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
emilmont 10:3bc89ef62ce7 1296 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
emilmont 10:3bc89ef62ce7 1297
emilmont 10:3bc89ef62ce7 1298 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
emilmont 10:3bc89ef62ce7 1299 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
emilmont 10:3bc89ef62ce7 1300
emilmont 10:3bc89ef62ce7 1301 /* Debug Core Register Selector Register */
emilmont 10:3bc89ef62ce7 1302 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
emilmont 10:3bc89ef62ce7 1303 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
emilmont 10:3bc89ef62ce7 1304
emilmont 10:3bc89ef62ce7 1305 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
emilmont 10:3bc89ef62ce7 1306 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
emilmont 10:3bc89ef62ce7 1307
emilmont 10:3bc89ef62ce7 1308 /* Debug Exception and Monitor Control Register */
emilmont 10:3bc89ef62ce7 1309 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
emilmont 10:3bc89ef62ce7 1310 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
emilmont 10:3bc89ef62ce7 1311
emilmont 10:3bc89ef62ce7 1312 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
emilmont 10:3bc89ef62ce7 1313 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
emilmont 10:3bc89ef62ce7 1314
emilmont 10:3bc89ef62ce7 1315 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
emilmont 10:3bc89ef62ce7 1316 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
emilmont 10:3bc89ef62ce7 1317
emilmont 10:3bc89ef62ce7 1318 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
emilmont 10:3bc89ef62ce7 1319 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
emilmont 10:3bc89ef62ce7 1320
emilmont 10:3bc89ef62ce7 1321 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
emilmont 10:3bc89ef62ce7 1322 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
emilmont 10:3bc89ef62ce7 1323
emilmont 10:3bc89ef62ce7 1324 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
emilmont 10:3bc89ef62ce7 1325 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
emilmont 10:3bc89ef62ce7 1326
emilmont 10:3bc89ef62ce7 1327 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
emilmont 10:3bc89ef62ce7 1328 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
emilmont 10:3bc89ef62ce7 1329
emilmont 10:3bc89ef62ce7 1330 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
emilmont 10:3bc89ef62ce7 1331 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
emilmont 10:3bc89ef62ce7 1332
emilmont 10:3bc89ef62ce7 1333 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
emilmont 10:3bc89ef62ce7 1334 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
emilmont 10:3bc89ef62ce7 1335
emilmont 10:3bc89ef62ce7 1336 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
emilmont 10:3bc89ef62ce7 1337 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
emilmont 10:3bc89ef62ce7 1338
emilmont 10:3bc89ef62ce7 1339 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
emilmont 10:3bc89ef62ce7 1340 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
emilmont 10:3bc89ef62ce7 1341
emilmont 10:3bc89ef62ce7 1342 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
emilmont 10:3bc89ef62ce7 1343 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
emilmont 10:3bc89ef62ce7 1344
emilmont 10:3bc89ef62ce7 1345 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
emilmont 10:3bc89ef62ce7 1346 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
emilmont 10:3bc89ef62ce7 1347
emilmont 10:3bc89ef62ce7 1348 /*@} end of group CMSIS_CoreDebug */
emilmont 10:3bc89ef62ce7 1349
emilmont 10:3bc89ef62ce7 1350
emilmont 10:3bc89ef62ce7 1351 /** \ingroup CMSIS_core_register
emilmont 10:3bc89ef62ce7 1352 \defgroup CMSIS_core_base Core Definitions
emilmont 10:3bc89ef62ce7 1353 \brief Definitions for base addresses, unions, and structures.
emilmont 10:3bc89ef62ce7 1354 @{
emilmont 10:3bc89ef62ce7 1355 */
emilmont 10:3bc89ef62ce7 1356
emilmont 10:3bc89ef62ce7 1357 /* Memory mapping of Cortex-M4 Hardware */
emilmont 10:3bc89ef62ce7 1358 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
emilmont 10:3bc89ef62ce7 1359 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
emilmont 10:3bc89ef62ce7 1360 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
emilmont 10:3bc89ef62ce7 1361 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
emilmont 10:3bc89ef62ce7 1362 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
emilmont 10:3bc89ef62ce7 1363 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
emilmont 10:3bc89ef62ce7 1364 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
emilmont 10:3bc89ef62ce7 1365 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
emilmont 10:3bc89ef62ce7 1366
emilmont 10:3bc89ef62ce7 1367 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
emilmont 10:3bc89ef62ce7 1368 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
emilmont 10:3bc89ef62ce7 1369 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
emilmont 10:3bc89ef62ce7 1370 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
emilmont 10:3bc89ef62ce7 1371 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
emilmont 10:3bc89ef62ce7 1372 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
emilmont 10:3bc89ef62ce7 1373 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
emilmont 10:3bc89ef62ce7 1374 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
emilmont 10:3bc89ef62ce7 1375
emilmont 10:3bc89ef62ce7 1376 #if (__MPU_PRESENT == 1)
emilmont 10:3bc89ef62ce7 1377 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
emilmont 10:3bc89ef62ce7 1378 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
emilmont 10:3bc89ef62ce7 1379 #endif
emilmont 10:3bc89ef62ce7 1380
emilmont 10:3bc89ef62ce7 1381 #if (__FPU_PRESENT == 1)
emilmont 10:3bc89ef62ce7 1382 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
emilmont 10:3bc89ef62ce7 1383 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
emilmont 10:3bc89ef62ce7 1384 #endif
emilmont 10:3bc89ef62ce7 1385
emilmont 10:3bc89ef62ce7 1386 /*@} */
emilmont 10:3bc89ef62ce7 1387
emilmont 10:3bc89ef62ce7 1388
emilmont 10:3bc89ef62ce7 1389
emilmont 10:3bc89ef62ce7 1390 /*******************************************************************************
emilmont 10:3bc89ef62ce7 1391 * Hardware Abstraction Layer
emilmont 10:3bc89ef62ce7 1392 Core Function Interface contains:
emilmont 10:3bc89ef62ce7 1393 - Core NVIC Functions
emilmont 10:3bc89ef62ce7 1394 - Core SysTick Functions
emilmont 10:3bc89ef62ce7 1395 - Core Debug Functions
emilmont 10:3bc89ef62ce7 1396 - Core Register Access Functions
emilmont 10:3bc89ef62ce7 1397 ******************************************************************************/
emilmont 10:3bc89ef62ce7 1398 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
emilmont 10:3bc89ef62ce7 1399 */
emilmont 10:3bc89ef62ce7 1400
emilmont 10:3bc89ef62ce7 1401
emilmont 10:3bc89ef62ce7 1402
emilmont 10:3bc89ef62ce7 1403 /* ########################## NVIC functions #################################### */
emilmont 10:3bc89ef62ce7 1404 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 10:3bc89ef62ce7 1405 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
emilmont 10:3bc89ef62ce7 1406 \brief Functions that manage interrupts and exceptions via the NVIC.
emilmont 10:3bc89ef62ce7 1407 @{
emilmont 10:3bc89ef62ce7 1408 */
emilmont 10:3bc89ef62ce7 1409
emilmont 10:3bc89ef62ce7 1410 /** \brief Set Priority Grouping
emilmont 10:3bc89ef62ce7 1411
emilmont 10:3bc89ef62ce7 1412 The function sets the priority grouping field using the required unlock sequence.
emilmont 10:3bc89ef62ce7 1413 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
emilmont 10:3bc89ef62ce7 1414 Only values from 0..7 are used.
emilmont 10:3bc89ef62ce7 1415 In case of a conflict between priority grouping and available
emilmont 10:3bc89ef62ce7 1416 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
emilmont 10:3bc89ef62ce7 1417
emilmont 10:3bc89ef62ce7 1418 \param [in] PriorityGroup Priority grouping field.
emilmont 10:3bc89ef62ce7 1419 */
emilmont 10:3bc89ef62ce7 1420 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
emilmont 10:3bc89ef62ce7 1421 {
emilmont 10:3bc89ef62ce7 1422 uint32_t reg_value;
emilmont 10:3bc89ef62ce7 1423 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
emilmont 10:3bc89ef62ce7 1424
emilmont 10:3bc89ef62ce7 1425 reg_value = SCB->AIRCR; /* read old register configuration */
emilmont 10:3bc89ef62ce7 1426 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
emilmont 10:3bc89ef62ce7 1427 reg_value = (reg_value |
emilmont 10:3bc89ef62ce7 1428 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
emilmont 10:3bc89ef62ce7 1429 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
emilmont 10:3bc89ef62ce7 1430 SCB->AIRCR = reg_value;
emilmont 10:3bc89ef62ce7 1431 }
emilmont 10:3bc89ef62ce7 1432
emilmont 10:3bc89ef62ce7 1433
emilmont 10:3bc89ef62ce7 1434 /** \brief Get Priority Grouping
emilmont 10:3bc89ef62ce7 1435
emilmont 10:3bc89ef62ce7 1436 The function reads the priority grouping field from the NVIC Interrupt Controller.
emilmont 10:3bc89ef62ce7 1437
emilmont 10:3bc89ef62ce7 1438 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
emilmont 10:3bc89ef62ce7 1439 */
emilmont 10:3bc89ef62ce7 1440 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
emilmont 10:3bc89ef62ce7 1441 {
emilmont 10:3bc89ef62ce7 1442 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
emilmont 10:3bc89ef62ce7 1443 }
emilmont 10:3bc89ef62ce7 1444
emilmont 10:3bc89ef62ce7 1445
emilmont 10:3bc89ef62ce7 1446 /** \brief Enable External Interrupt
emilmont 10:3bc89ef62ce7 1447
emilmont 10:3bc89ef62ce7 1448 The function enables a device-specific interrupt in the NVIC interrupt controller.
emilmont 10:3bc89ef62ce7 1449
emilmont 10:3bc89ef62ce7 1450 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 10:3bc89ef62ce7 1451 */
emilmont 10:3bc89ef62ce7 1452 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
emilmont 10:3bc89ef62ce7 1453 {
emilmont 10:3bc89ef62ce7 1454 /* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
emilmont 10:3bc89ef62ce7 1455 NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
emilmont 10:3bc89ef62ce7 1456 }
emilmont 10:3bc89ef62ce7 1457
emilmont 10:3bc89ef62ce7 1458
emilmont 10:3bc89ef62ce7 1459 /** \brief Disable External Interrupt
emilmont 10:3bc89ef62ce7 1460
emilmont 10:3bc89ef62ce7 1461 The function disables a device-specific interrupt in the NVIC interrupt controller.
emilmont 10:3bc89ef62ce7 1462
emilmont 10:3bc89ef62ce7 1463 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 10:3bc89ef62ce7 1464 */
emilmont 10:3bc89ef62ce7 1465 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
emilmont 10:3bc89ef62ce7 1466 {
emilmont 10:3bc89ef62ce7 1467 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
emilmont 10:3bc89ef62ce7 1468 }
emilmont 10:3bc89ef62ce7 1469
emilmont 10:3bc89ef62ce7 1470
emilmont 10:3bc89ef62ce7 1471 /** \brief Get Pending Interrupt
emilmont 10:3bc89ef62ce7 1472
emilmont 10:3bc89ef62ce7 1473 The function reads the pending register in the NVIC and returns the pending bit
emilmont 10:3bc89ef62ce7 1474 for the specified interrupt.
emilmont 10:3bc89ef62ce7 1475
emilmont 10:3bc89ef62ce7 1476 \param [in] IRQn Interrupt number.
emilmont 10:3bc89ef62ce7 1477
emilmont 10:3bc89ef62ce7 1478 \return 0 Interrupt status is not pending.
emilmont 10:3bc89ef62ce7 1479 \return 1 Interrupt status is pending.
emilmont 10:3bc89ef62ce7 1480 */
emilmont 10:3bc89ef62ce7 1481 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
emilmont 10:3bc89ef62ce7 1482 {
emilmont 10:3bc89ef62ce7 1483 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
emilmont 10:3bc89ef62ce7 1484 }
emilmont 10:3bc89ef62ce7 1485
emilmont 10:3bc89ef62ce7 1486
emilmont 10:3bc89ef62ce7 1487 /** \brief Set Pending Interrupt
emilmont 10:3bc89ef62ce7 1488
emilmont 10:3bc89ef62ce7 1489 The function sets the pending bit of an external interrupt.
emilmont 10:3bc89ef62ce7 1490
emilmont 10:3bc89ef62ce7 1491 \param [in] IRQn Interrupt number. Value cannot be negative.
emilmont 10:3bc89ef62ce7 1492 */
emilmont 10:3bc89ef62ce7 1493 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
emilmont 10:3bc89ef62ce7 1494 {
emilmont 10:3bc89ef62ce7 1495 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
emilmont 10:3bc89ef62ce7 1496 }
emilmont 10:3bc89ef62ce7 1497
emilmont 10:3bc89ef62ce7 1498
emilmont 10:3bc89ef62ce7 1499 /** \brief Clear Pending Interrupt
emilmont 10:3bc89ef62ce7 1500
emilmont 10:3bc89ef62ce7 1501 The function clears the pending bit of an external interrupt.
emilmont 10:3bc89ef62ce7 1502
emilmont 10:3bc89ef62ce7 1503 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 10:3bc89ef62ce7 1504 */
emilmont 10:3bc89ef62ce7 1505 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
emilmont 10:3bc89ef62ce7 1506 {
emilmont 10:3bc89ef62ce7 1507 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
emilmont 10:3bc89ef62ce7 1508 }
emilmont 10:3bc89ef62ce7 1509
emilmont 10:3bc89ef62ce7 1510
emilmont 10:3bc89ef62ce7 1511 /** \brief Get Active Interrupt
emilmont 10:3bc89ef62ce7 1512
emilmont 10:3bc89ef62ce7 1513 The function reads the active register in NVIC and returns the active bit.
emilmont 10:3bc89ef62ce7 1514
emilmont 10:3bc89ef62ce7 1515 \param [in] IRQn Interrupt number.
emilmont 10:3bc89ef62ce7 1516
emilmont 10:3bc89ef62ce7 1517 \return 0 Interrupt status is not active.
emilmont 10:3bc89ef62ce7 1518 \return 1 Interrupt status is active.
emilmont 10:3bc89ef62ce7 1519 */
emilmont 10:3bc89ef62ce7 1520 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
emilmont 10:3bc89ef62ce7 1521 {
emilmont 10:3bc89ef62ce7 1522 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
emilmont 10:3bc89ef62ce7 1523 }
emilmont 10:3bc89ef62ce7 1524
emilmont 10:3bc89ef62ce7 1525
emilmont 10:3bc89ef62ce7 1526 /** \brief Set Interrupt Priority
emilmont 10:3bc89ef62ce7 1527
emilmont 10:3bc89ef62ce7 1528 The function sets the priority of an interrupt.
emilmont 10:3bc89ef62ce7 1529
emilmont 10:3bc89ef62ce7 1530 \note The priority cannot be set for every core interrupt.
emilmont 10:3bc89ef62ce7 1531
emilmont 10:3bc89ef62ce7 1532 \param [in] IRQn Interrupt number.
emilmont 10:3bc89ef62ce7 1533 \param [in] priority Priority to set.
emilmont 10:3bc89ef62ce7 1534 */
emilmont 10:3bc89ef62ce7 1535 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
emilmont 10:3bc89ef62ce7 1536 {
emilmont 10:3bc89ef62ce7 1537 if(IRQn < 0) {
emilmont 10:3bc89ef62ce7 1538 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
emilmont 10:3bc89ef62ce7 1539 else {
emilmont 10:3bc89ef62ce7 1540 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
emilmont 10:3bc89ef62ce7 1541 }
emilmont 10:3bc89ef62ce7 1542
emilmont 10:3bc89ef62ce7 1543
emilmont 10:3bc89ef62ce7 1544 /** \brief Get Interrupt Priority
emilmont 10:3bc89ef62ce7 1545
emilmont 10:3bc89ef62ce7 1546 The function reads the priority of an interrupt. The interrupt
emilmont 10:3bc89ef62ce7 1547 number can be positive to specify an external (device specific)
emilmont 10:3bc89ef62ce7 1548 interrupt, or negative to specify an internal (core) interrupt.
emilmont 10:3bc89ef62ce7 1549
emilmont 10:3bc89ef62ce7 1550
emilmont 10:3bc89ef62ce7 1551 \param [in] IRQn Interrupt number.
emilmont 10:3bc89ef62ce7 1552 \return Interrupt Priority. Value is aligned automatically to the implemented
emilmont 10:3bc89ef62ce7 1553 priority bits of the microcontroller.
emilmont 10:3bc89ef62ce7 1554 */
emilmont 10:3bc89ef62ce7 1555 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
emilmont 10:3bc89ef62ce7 1556 {
emilmont 10:3bc89ef62ce7 1557
emilmont 10:3bc89ef62ce7 1558 if(IRQn < 0) {
emilmont 10:3bc89ef62ce7 1559 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
emilmont 10:3bc89ef62ce7 1560 else {
emilmont 10:3bc89ef62ce7 1561 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
emilmont 10:3bc89ef62ce7 1562 }
emilmont 10:3bc89ef62ce7 1563
emilmont 10:3bc89ef62ce7 1564
emilmont 10:3bc89ef62ce7 1565 /** \brief Encode Priority
emilmont 10:3bc89ef62ce7 1566
emilmont 10:3bc89ef62ce7 1567 The function encodes the priority for an interrupt with the given priority group,
emilmont 10:3bc89ef62ce7 1568 preemptive priority value, and subpriority value.
emilmont 10:3bc89ef62ce7 1569 In case of a conflict between priority grouping and available
emilmont 10:3bc89ef62ce7 1570 priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
emilmont 10:3bc89ef62ce7 1571
emilmont 10:3bc89ef62ce7 1572 \param [in] PriorityGroup Used priority group.
emilmont 10:3bc89ef62ce7 1573 \param [in] PreemptPriority Preemptive priority value (starting from 0).
emilmont 10:3bc89ef62ce7 1574 \param [in] SubPriority Subpriority value (starting from 0).
emilmont 10:3bc89ef62ce7 1575 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
emilmont 10:3bc89ef62ce7 1576 */
emilmont 10:3bc89ef62ce7 1577 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
emilmont 10:3bc89ef62ce7 1578 {
emilmont 10:3bc89ef62ce7 1579 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
emilmont 10:3bc89ef62ce7 1580 uint32_t PreemptPriorityBits;
emilmont 10:3bc89ef62ce7 1581 uint32_t SubPriorityBits;
emilmont 10:3bc89ef62ce7 1582
emilmont 10:3bc89ef62ce7 1583 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
emilmont 10:3bc89ef62ce7 1584 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
emilmont 10:3bc89ef62ce7 1585
emilmont 10:3bc89ef62ce7 1586 return (
emilmont 10:3bc89ef62ce7 1587 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
emilmont 10:3bc89ef62ce7 1588 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
emilmont 10:3bc89ef62ce7 1589 );
emilmont 10:3bc89ef62ce7 1590 }
emilmont 10:3bc89ef62ce7 1591
emilmont 10:3bc89ef62ce7 1592
emilmont 10:3bc89ef62ce7 1593 /** \brief Decode Priority
emilmont 10:3bc89ef62ce7 1594
emilmont 10:3bc89ef62ce7 1595 The function decodes an interrupt priority value with a given priority group to
emilmont 10:3bc89ef62ce7 1596 preemptive priority value and subpriority value.
emilmont 10:3bc89ef62ce7 1597 In case of a conflict between priority grouping and available
emilmont 10:3bc89ef62ce7 1598 priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
emilmont 10:3bc89ef62ce7 1599
emilmont 10:3bc89ef62ce7 1600 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
emilmont 10:3bc89ef62ce7 1601 \param [in] PriorityGroup Used priority group.
emilmont 10:3bc89ef62ce7 1602 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
emilmont 10:3bc89ef62ce7 1603 \param [out] pSubPriority Subpriority value (starting from 0).
emilmont 10:3bc89ef62ce7 1604 */
emilmont 10:3bc89ef62ce7 1605 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
emilmont 10:3bc89ef62ce7 1606 {
emilmont 10:3bc89ef62ce7 1607 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
emilmont 10:3bc89ef62ce7 1608 uint32_t PreemptPriorityBits;
emilmont 10:3bc89ef62ce7 1609 uint32_t SubPriorityBits;
emilmont 10:3bc89ef62ce7 1610
emilmont 10:3bc89ef62ce7 1611 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
emilmont 10:3bc89ef62ce7 1612 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
emilmont 10:3bc89ef62ce7 1613
emilmont 10:3bc89ef62ce7 1614 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
emilmont 10:3bc89ef62ce7 1615 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
emilmont 10:3bc89ef62ce7 1616 }
emilmont 10:3bc89ef62ce7 1617
emilmont 10:3bc89ef62ce7 1618
emilmont 10:3bc89ef62ce7 1619 /** \brief System Reset
emilmont 10:3bc89ef62ce7 1620
emilmont 10:3bc89ef62ce7 1621 The function initiates a system reset request to reset the MCU.
emilmont 10:3bc89ef62ce7 1622 */
emilmont 10:3bc89ef62ce7 1623 __STATIC_INLINE void NVIC_SystemReset(void)
emilmont 10:3bc89ef62ce7 1624 {
emilmont 10:3bc89ef62ce7 1625 __DSB(); /* Ensure all outstanding memory accesses included
emilmont 10:3bc89ef62ce7 1626 buffered write are completed before reset */
emilmont 10:3bc89ef62ce7 1627 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
emilmont 10:3bc89ef62ce7 1628 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
emilmont 10:3bc89ef62ce7 1629 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
emilmont 10:3bc89ef62ce7 1630 __DSB(); /* Ensure completion of memory access */
emilmont 10:3bc89ef62ce7 1631 while(1); /* wait until reset */
emilmont 10:3bc89ef62ce7 1632 }
emilmont 10:3bc89ef62ce7 1633
emilmont 10:3bc89ef62ce7 1634 /*@} end of CMSIS_Core_NVICFunctions */
emilmont 10:3bc89ef62ce7 1635
emilmont 10:3bc89ef62ce7 1636
emilmont 10:3bc89ef62ce7 1637
emilmont 10:3bc89ef62ce7 1638 /* ################################## SysTick function ############################################ */
emilmont 10:3bc89ef62ce7 1639 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 10:3bc89ef62ce7 1640 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
emilmont 10:3bc89ef62ce7 1641 \brief Functions that configure the System.
emilmont 10:3bc89ef62ce7 1642 @{
emilmont 10:3bc89ef62ce7 1643 */
emilmont 10:3bc89ef62ce7 1644
emilmont 10:3bc89ef62ce7 1645 #if (__Vendor_SysTickConfig == 0)
emilmont 10:3bc89ef62ce7 1646
emilmont 10:3bc89ef62ce7 1647 /** \brief System Tick Configuration
emilmont 10:3bc89ef62ce7 1648
emilmont 10:3bc89ef62ce7 1649 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
emilmont 10:3bc89ef62ce7 1650 Counter is in free running mode to generate periodic interrupts.
emilmont 10:3bc89ef62ce7 1651
emilmont 10:3bc89ef62ce7 1652 \param [in] ticks Number of ticks between two interrupts.
emilmont 10:3bc89ef62ce7 1653
emilmont 10:3bc89ef62ce7 1654 \return 0 Function succeeded.
emilmont 10:3bc89ef62ce7 1655 \return 1 Function failed.
emilmont 10:3bc89ef62ce7 1656
emilmont 10:3bc89ef62ce7 1657 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
emilmont 10:3bc89ef62ce7 1658 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
emilmont 10:3bc89ef62ce7 1659 must contain a vendor-specific implementation of this function.
emilmont 10:3bc89ef62ce7 1660
emilmont 10:3bc89ef62ce7 1661 */
emilmont 10:3bc89ef62ce7 1662 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
emilmont 10:3bc89ef62ce7 1663 {
emilmont 10:3bc89ef62ce7 1664 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
emilmont 10:3bc89ef62ce7 1665
emilmont 10:3bc89ef62ce7 1666 SysTick->LOAD = ticks - 1; /* set reload register */
emilmont 10:3bc89ef62ce7 1667 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
emilmont 10:3bc89ef62ce7 1668 SysTick->VAL = 0; /* Load the SysTick Counter Value */
emilmont 10:3bc89ef62ce7 1669 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
emilmont 10:3bc89ef62ce7 1670 SysTick_CTRL_TICKINT_Msk |
emilmont 10:3bc89ef62ce7 1671 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
emilmont 10:3bc89ef62ce7 1672 return (0); /* Function successful */
emilmont 10:3bc89ef62ce7 1673 }
emilmont 10:3bc89ef62ce7 1674
emilmont 10:3bc89ef62ce7 1675 #endif
emilmont 10:3bc89ef62ce7 1676
emilmont 10:3bc89ef62ce7 1677 /*@} end of CMSIS_Core_SysTickFunctions */
emilmont 10:3bc89ef62ce7 1678
emilmont 10:3bc89ef62ce7 1679
emilmont 10:3bc89ef62ce7 1680
emilmont 10:3bc89ef62ce7 1681 /* ##################################### Debug In/Output function ########################################### */
emilmont 10:3bc89ef62ce7 1682 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 10:3bc89ef62ce7 1683 \defgroup CMSIS_core_DebugFunctions ITM Functions
emilmont 10:3bc89ef62ce7 1684 \brief Functions that access the ITM debug interface.
emilmont 10:3bc89ef62ce7 1685 @{
emilmont 10:3bc89ef62ce7 1686 */
emilmont 10:3bc89ef62ce7 1687
emilmont 10:3bc89ef62ce7 1688 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
emilmont 10:3bc89ef62ce7 1689 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
emilmont 10:3bc89ef62ce7 1690
emilmont 10:3bc89ef62ce7 1691
emilmont 10:3bc89ef62ce7 1692 /** \brief ITM Send Character
emilmont 10:3bc89ef62ce7 1693
emilmont 10:3bc89ef62ce7 1694 The function transmits a character via the ITM channel 0, and
emilmont 10:3bc89ef62ce7 1695 \li Just returns when no debugger is connected that has booked the output.
emilmont 10:3bc89ef62ce7 1696 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
emilmont 10:3bc89ef62ce7 1697
emilmont 10:3bc89ef62ce7 1698 \param [in] ch Character to transmit.
emilmont 10:3bc89ef62ce7 1699
emilmont 10:3bc89ef62ce7 1700 \returns Character to transmit.
emilmont 10:3bc89ef62ce7 1701 */
emilmont 10:3bc89ef62ce7 1702 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
emilmont 10:3bc89ef62ce7 1703 {
emilmont 10:3bc89ef62ce7 1704 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
emilmont 10:3bc89ef62ce7 1705 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
emilmont 10:3bc89ef62ce7 1706 {
emilmont 10:3bc89ef62ce7 1707 while (ITM->PORT[0].u32 == 0);
emilmont 10:3bc89ef62ce7 1708 ITM->PORT[0].u8 = (uint8_t) ch;
emilmont 10:3bc89ef62ce7 1709 }
emilmont 10:3bc89ef62ce7 1710 return (ch);
emilmont 10:3bc89ef62ce7 1711 }
emilmont 10:3bc89ef62ce7 1712
emilmont 10:3bc89ef62ce7 1713
emilmont 10:3bc89ef62ce7 1714 /** \brief ITM Receive Character
emilmont 10:3bc89ef62ce7 1715
emilmont 10:3bc89ef62ce7 1716 The function inputs a character via the external variable \ref ITM_RxBuffer.
emilmont 10:3bc89ef62ce7 1717
emilmont 10:3bc89ef62ce7 1718 \return Received character.
emilmont 10:3bc89ef62ce7 1719 \return -1 No character pending.
emilmont 10:3bc89ef62ce7 1720 */
emilmont 10:3bc89ef62ce7 1721 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
emilmont 10:3bc89ef62ce7 1722 int32_t ch = -1; /* no character available */
emilmont 10:3bc89ef62ce7 1723
emilmont 10:3bc89ef62ce7 1724 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
emilmont 10:3bc89ef62ce7 1725 ch = ITM_RxBuffer;
emilmont 10:3bc89ef62ce7 1726 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
emilmont 10:3bc89ef62ce7 1727 }
emilmont 10:3bc89ef62ce7 1728
emilmont 10:3bc89ef62ce7 1729 return (ch);
emilmont 10:3bc89ef62ce7 1730 }
emilmont 10:3bc89ef62ce7 1731
emilmont 10:3bc89ef62ce7 1732
emilmont 10:3bc89ef62ce7 1733 /** \brief ITM Check Character
emilmont 10:3bc89ef62ce7 1734
emilmont 10:3bc89ef62ce7 1735 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
emilmont 10:3bc89ef62ce7 1736
emilmont 10:3bc89ef62ce7 1737 \return 0 No character available.
emilmont 10:3bc89ef62ce7 1738 \return 1 Character available.
emilmont 10:3bc89ef62ce7 1739 */
emilmont 10:3bc89ef62ce7 1740 __STATIC_INLINE int32_t ITM_CheckChar (void) {
emilmont 10:3bc89ef62ce7 1741
emilmont 10:3bc89ef62ce7 1742 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
emilmont 10:3bc89ef62ce7 1743 return (0); /* no character available */
emilmont 10:3bc89ef62ce7 1744 } else {
emilmont 10:3bc89ef62ce7 1745 return (1); /* character available */
emilmont 10:3bc89ef62ce7 1746 }
emilmont 10:3bc89ef62ce7 1747 }
emilmont 10:3bc89ef62ce7 1748
emilmont 10:3bc89ef62ce7 1749 /*@} end of CMSIS_core_DebugFunctions */
emilmont 10:3bc89ef62ce7 1750
emilmont 10:3bc89ef62ce7 1751 #endif /* __CORE_CM4_H_DEPENDANT */
emilmont 10:3bc89ef62ce7 1752
emilmont 10:3bc89ef62ce7 1753 #endif /* __CMSIS_GENERIC */
emilmont 10:3bc89ef62ce7 1754
emilmont 10:3bc89ef62ce7 1755 #ifdef __cplusplus
emilmont 10:3bc89ef62ce7 1756 }
emilmont 10:3bc89ef62ce7 1757 #endif