Initial commit
mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dma.c@0:bb348c97df44, 2020-09-16 (annotated)
- Committer:
- lypinator
- Date:
- Wed Sep 16 01:11:49 2020 +0000
- Revision:
- 0:bb348c97df44
Added PWM
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
lypinator | 0:bb348c97df44 | 1 | /** |
lypinator | 0:bb348c97df44 | 2 | ****************************************************************************** |
lypinator | 0:bb348c97df44 | 3 | * @file stm32f4xx_ll_dma.c |
lypinator | 0:bb348c97df44 | 4 | * @author MCD Application Team |
lypinator | 0:bb348c97df44 | 5 | * @brief DMA LL module driver. |
lypinator | 0:bb348c97df44 | 6 | ****************************************************************************** |
lypinator | 0:bb348c97df44 | 7 | * @attention |
lypinator | 0:bb348c97df44 | 8 | * |
lypinator | 0:bb348c97df44 | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
lypinator | 0:bb348c97df44 | 10 | * |
lypinator | 0:bb348c97df44 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
lypinator | 0:bb348c97df44 | 12 | * are permitted provided that the following conditions are met: |
lypinator | 0:bb348c97df44 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
lypinator | 0:bb348c97df44 | 14 | * this list of conditions and the following disclaimer. |
lypinator | 0:bb348c97df44 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
lypinator | 0:bb348c97df44 | 16 | * this list of conditions and the following disclaimer in the documentation |
lypinator | 0:bb348c97df44 | 17 | * and/or other materials provided with the distribution. |
lypinator | 0:bb348c97df44 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
lypinator | 0:bb348c97df44 | 19 | * may be used to endorse or promote products derived from this software |
lypinator | 0:bb348c97df44 | 20 | * without specific prior written permission. |
lypinator | 0:bb348c97df44 | 21 | * |
lypinator | 0:bb348c97df44 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
lypinator | 0:bb348c97df44 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
lypinator | 0:bb348c97df44 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
lypinator | 0:bb348c97df44 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
lypinator | 0:bb348c97df44 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
lypinator | 0:bb348c97df44 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
lypinator | 0:bb348c97df44 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
lypinator | 0:bb348c97df44 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
lypinator | 0:bb348c97df44 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
lypinator | 0:bb348c97df44 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
lypinator | 0:bb348c97df44 | 32 | * |
lypinator | 0:bb348c97df44 | 33 | ****************************************************************************** |
lypinator | 0:bb348c97df44 | 34 | */ |
lypinator | 0:bb348c97df44 | 35 | #if defined(USE_FULL_LL_DRIVER) |
lypinator | 0:bb348c97df44 | 36 | |
lypinator | 0:bb348c97df44 | 37 | /* Includes ------------------------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 38 | #include "stm32f4xx_ll_dma.h" |
lypinator | 0:bb348c97df44 | 39 | #include "stm32f4xx_ll_bus.h" |
lypinator | 0:bb348c97df44 | 40 | #ifdef USE_FULL_ASSERT |
lypinator | 0:bb348c97df44 | 41 | #include "stm32_assert.h" |
lypinator | 0:bb348c97df44 | 42 | #else |
lypinator | 0:bb348c97df44 | 43 | #define assert_param(expr) ((void)0U) |
lypinator | 0:bb348c97df44 | 44 | #endif |
lypinator | 0:bb348c97df44 | 45 | |
lypinator | 0:bb348c97df44 | 46 | /** @addtogroup STM32F4xx_LL_Driver |
lypinator | 0:bb348c97df44 | 47 | * @{ |
lypinator | 0:bb348c97df44 | 48 | */ |
lypinator | 0:bb348c97df44 | 49 | |
lypinator | 0:bb348c97df44 | 50 | #if defined (DMA1) || defined (DMA2) |
lypinator | 0:bb348c97df44 | 51 | |
lypinator | 0:bb348c97df44 | 52 | /** @defgroup DMA_LL DMA |
lypinator | 0:bb348c97df44 | 53 | * @{ |
lypinator | 0:bb348c97df44 | 54 | */ |
lypinator | 0:bb348c97df44 | 55 | |
lypinator | 0:bb348c97df44 | 56 | /* Private types -------------------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 57 | /* Private variables ---------------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 58 | /* Private constants ---------------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 59 | /* Private macros ------------------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 60 | /** @addtogroup DMA_LL_Private_Macros |
lypinator | 0:bb348c97df44 | 61 | * @{ |
lypinator | 0:bb348c97df44 | 62 | */ |
lypinator | 0:bb348c97df44 | 63 | #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \ |
lypinator | 0:bb348c97df44 | 64 | ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \ |
lypinator | 0:bb348c97df44 | 65 | ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY)) |
lypinator | 0:bb348c97df44 | 66 | |
lypinator | 0:bb348c97df44 | 67 | #define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \ |
lypinator | 0:bb348c97df44 | 68 | ((__VALUE__) == LL_DMA_MODE_CIRCULAR) || \ |
lypinator | 0:bb348c97df44 | 69 | ((__VALUE__) == LL_DMA_MODE_PFCTRL)) |
lypinator | 0:bb348c97df44 | 70 | |
lypinator | 0:bb348c97df44 | 71 | #define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \ |
lypinator | 0:bb348c97df44 | 72 | ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT)) |
lypinator | 0:bb348c97df44 | 73 | |
lypinator | 0:bb348c97df44 | 74 | #define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \ |
lypinator | 0:bb348c97df44 | 75 | ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT)) |
lypinator | 0:bb348c97df44 | 76 | |
lypinator | 0:bb348c97df44 | 77 | #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \ |
lypinator | 0:bb348c97df44 | 78 | ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \ |
lypinator | 0:bb348c97df44 | 79 | ((__VALUE__) == LL_DMA_PDATAALIGN_WORD)) |
lypinator | 0:bb348c97df44 | 80 | |
lypinator | 0:bb348c97df44 | 81 | #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \ |
lypinator | 0:bb348c97df44 | 82 | ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \ |
lypinator | 0:bb348c97df44 | 83 | ((__VALUE__) == LL_DMA_MDATAALIGN_WORD)) |
lypinator | 0:bb348c97df44 | 84 | |
lypinator | 0:bb348c97df44 | 85 | #define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) |
lypinator | 0:bb348c97df44 | 86 | |
lypinator | 0:bb348c97df44 | 87 | #define IS_LL_DMA_CHANNEL(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_0) || \ |
lypinator | 0:bb348c97df44 | 88 | ((__VALUE__) == LL_DMA_CHANNEL_1) || \ |
lypinator | 0:bb348c97df44 | 89 | ((__VALUE__) == LL_DMA_CHANNEL_2) || \ |
lypinator | 0:bb348c97df44 | 90 | ((__VALUE__) == LL_DMA_CHANNEL_3) || \ |
lypinator | 0:bb348c97df44 | 91 | ((__VALUE__) == LL_DMA_CHANNEL_4) || \ |
lypinator | 0:bb348c97df44 | 92 | ((__VALUE__) == LL_DMA_CHANNEL_5) || \ |
lypinator | 0:bb348c97df44 | 93 | ((__VALUE__) == LL_DMA_CHANNEL_6) || \ |
lypinator | 0:bb348c97df44 | 94 | ((__VALUE__) == LL_DMA_CHANNEL_7)) |
lypinator | 0:bb348c97df44 | 95 | |
lypinator | 0:bb348c97df44 | 96 | #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \ |
lypinator | 0:bb348c97df44 | 97 | ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \ |
lypinator | 0:bb348c97df44 | 98 | ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \ |
lypinator | 0:bb348c97df44 | 99 | ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH)) |
lypinator | 0:bb348c97df44 | 100 | |
lypinator | 0:bb348c97df44 | 101 | #define IS_LL_DMA_ALL_STREAM_INSTANCE(INSTANCE, STREAM) ((((INSTANCE) == DMA1) && \ |
lypinator | 0:bb348c97df44 | 102 | (((STREAM) == LL_DMA_STREAM_0) || \ |
lypinator | 0:bb348c97df44 | 103 | ((STREAM) == LL_DMA_STREAM_1) || \ |
lypinator | 0:bb348c97df44 | 104 | ((STREAM) == LL_DMA_STREAM_2) || \ |
lypinator | 0:bb348c97df44 | 105 | ((STREAM) == LL_DMA_STREAM_3) || \ |
lypinator | 0:bb348c97df44 | 106 | ((STREAM) == LL_DMA_STREAM_4) || \ |
lypinator | 0:bb348c97df44 | 107 | ((STREAM) == LL_DMA_STREAM_5) || \ |
lypinator | 0:bb348c97df44 | 108 | ((STREAM) == LL_DMA_STREAM_6) || \ |
lypinator | 0:bb348c97df44 | 109 | ((STREAM) == LL_DMA_STREAM_7) || \ |
lypinator | 0:bb348c97df44 | 110 | ((STREAM) == LL_DMA_STREAM_ALL))) ||\ |
lypinator | 0:bb348c97df44 | 111 | (((INSTANCE) == DMA2) && \ |
lypinator | 0:bb348c97df44 | 112 | (((STREAM) == LL_DMA_STREAM_0) || \ |
lypinator | 0:bb348c97df44 | 113 | ((STREAM) == LL_DMA_STREAM_1) || \ |
lypinator | 0:bb348c97df44 | 114 | ((STREAM) == LL_DMA_STREAM_2) || \ |
lypinator | 0:bb348c97df44 | 115 | ((STREAM) == LL_DMA_STREAM_3) || \ |
lypinator | 0:bb348c97df44 | 116 | ((STREAM) == LL_DMA_STREAM_4) || \ |
lypinator | 0:bb348c97df44 | 117 | ((STREAM) == LL_DMA_STREAM_5) || \ |
lypinator | 0:bb348c97df44 | 118 | ((STREAM) == LL_DMA_STREAM_6) || \ |
lypinator | 0:bb348c97df44 | 119 | ((STREAM) == LL_DMA_STREAM_7) || \ |
lypinator | 0:bb348c97df44 | 120 | ((STREAM) == LL_DMA_STREAM_ALL)))) |
lypinator | 0:bb348c97df44 | 121 | |
lypinator | 0:bb348c97df44 | 122 | #define IS_LL_DMA_FIFO_MODE_STATE(STATE) (((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \ |
lypinator | 0:bb348c97df44 | 123 | ((STATE) == LL_DMA_FIFOMODE_ENABLE)) |
lypinator | 0:bb348c97df44 | 124 | |
lypinator | 0:bb348c97df44 | 125 | #define IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_4) || \ |
lypinator | 0:bb348c97df44 | 126 | ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_2) || \ |
lypinator | 0:bb348c97df44 | 127 | ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_3_4) || \ |
lypinator | 0:bb348c97df44 | 128 | ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_FULL)) |
lypinator | 0:bb348c97df44 | 129 | |
lypinator | 0:bb348c97df44 | 130 | #define IS_LL_DMA_MEMORY_BURST(BURST) (((BURST) == LL_DMA_MBURST_SINGLE) || \ |
lypinator | 0:bb348c97df44 | 131 | ((BURST) == LL_DMA_MBURST_INC4) || \ |
lypinator | 0:bb348c97df44 | 132 | ((BURST) == LL_DMA_MBURST_INC8) || \ |
lypinator | 0:bb348c97df44 | 133 | ((BURST) == LL_DMA_MBURST_INC16)) |
lypinator | 0:bb348c97df44 | 134 | |
lypinator | 0:bb348c97df44 | 135 | #define IS_LL_DMA_PERIPHERAL_BURST(BURST) (((BURST) == LL_DMA_PBURST_SINGLE) || \ |
lypinator | 0:bb348c97df44 | 136 | ((BURST) == LL_DMA_PBURST_INC4) || \ |
lypinator | 0:bb348c97df44 | 137 | ((BURST) == LL_DMA_PBURST_INC8) || \ |
lypinator | 0:bb348c97df44 | 138 | ((BURST) == LL_DMA_PBURST_INC16)) |
lypinator | 0:bb348c97df44 | 139 | |
lypinator | 0:bb348c97df44 | 140 | /** |
lypinator | 0:bb348c97df44 | 141 | * @} |
lypinator | 0:bb348c97df44 | 142 | */ |
lypinator | 0:bb348c97df44 | 143 | |
lypinator | 0:bb348c97df44 | 144 | /* Private function prototypes -----------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 145 | |
lypinator | 0:bb348c97df44 | 146 | /* Exported functions --------------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 147 | /** @addtogroup DMA_LL_Exported_Functions |
lypinator | 0:bb348c97df44 | 148 | * @{ |
lypinator | 0:bb348c97df44 | 149 | */ |
lypinator | 0:bb348c97df44 | 150 | |
lypinator | 0:bb348c97df44 | 151 | /** @addtogroup DMA_LL_EF_Init |
lypinator | 0:bb348c97df44 | 152 | * @{ |
lypinator | 0:bb348c97df44 | 153 | */ |
lypinator | 0:bb348c97df44 | 154 | |
lypinator | 0:bb348c97df44 | 155 | /** |
lypinator | 0:bb348c97df44 | 156 | * @brief De-initialize the DMA registers to their default reset values. |
lypinator | 0:bb348c97df44 | 157 | * @param DMAx DMAx Instance |
lypinator | 0:bb348c97df44 | 158 | * @param Stream This parameter can be one of the following values: |
lypinator | 0:bb348c97df44 | 159 | * @arg @ref LL_DMA_STREAM_0 |
lypinator | 0:bb348c97df44 | 160 | * @arg @ref LL_DMA_STREAM_1 |
lypinator | 0:bb348c97df44 | 161 | * @arg @ref LL_DMA_STREAM_2 |
lypinator | 0:bb348c97df44 | 162 | * @arg @ref LL_DMA_STREAM_3 |
lypinator | 0:bb348c97df44 | 163 | * @arg @ref LL_DMA_STREAM_4 |
lypinator | 0:bb348c97df44 | 164 | * @arg @ref LL_DMA_STREAM_5 |
lypinator | 0:bb348c97df44 | 165 | * @arg @ref LL_DMA_STREAM_6 |
lypinator | 0:bb348c97df44 | 166 | * @arg @ref LL_DMA_STREAM_7 |
lypinator | 0:bb348c97df44 | 167 | * @arg @ref LL_DMA_STREAM_ALL |
lypinator | 0:bb348c97df44 | 168 | * @retval An ErrorStatus enumeration value: |
lypinator | 0:bb348c97df44 | 169 | * - SUCCESS: DMA registers are de-initialized |
lypinator | 0:bb348c97df44 | 170 | * - ERROR: DMA registers are not de-initialized |
lypinator | 0:bb348c97df44 | 171 | */ |
lypinator | 0:bb348c97df44 | 172 | uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream) |
lypinator | 0:bb348c97df44 | 173 | { |
lypinator | 0:bb348c97df44 | 174 | DMA_Stream_TypeDef *tmp = (DMA_Stream_TypeDef *)DMA1_Stream0; |
lypinator | 0:bb348c97df44 | 175 | ErrorStatus status = SUCCESS; |
lypinator | 0:bb348c97df44 | 176 | |
lypinator | 0:bb348c97df44 | 177 | /* Check the DMA Instance DMAx and Stream parameters*/ |
lypinator | 0:bb348c97df44 | 178 | assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream)); |
lypinator | 0:bb348c97df44 | 179 | |
lypinator | 0:bb348c97df44 | 180 | if (Stream == LL_DMA_STREAM_ALL) |
lypinator | 0:bb348c97df44 | 181 | { |
lypinator | 0:bb348c97df44 | 182 | if (DMAx == DMA1) |
lypinator | 0:bb348c97df44 | 183 | { |
lypinator | 0:bb348c97df44 | 184 | /* Force reset of DMA clock */ |
lypinator | 0:bb348c97df44 | 185 | LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1); |
lypinator | 0:bb348c97df44 | 186 | |
lypinator | 0:bb348c97df44 | 187 | /* Release reset of DMA clock */ |
lypinator | 0:bb348c97df44 | 188 | LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1); |
lypinator | 0:bb348c97df44 | 189 | } |
lypinator | 0:bb348c97df44 | 190 | else if (DMAx == DMA2) |
lypinator | 0:bb348c97df44 | 191 | { |
lypinator | 0:bb348c97df44 | 192 | /* Force reset of DMA clock */ |
lypinator | 0:bb348c97df44 | 193 | LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2); |
lypinator | 0:bb348c97df44 | 194 | |
lypinator | 0:bb348c97df44 | 195 | /* Release reset of DMA clock */ |
lypinator | 0:bb348c97df44 | 196 | LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2); |
lypinator | 0:bb348c97df44 | 197 | } |
lypinator | 0:bb348c97df44 | 198 | else |
lypinator | 0:bb348c97df44 | 199 | { |
lypinator | 0:bb348c97df44 | 200 | status = ERROR; |
lypinator | 0:bb348c97df44 | 201 | } |
lypinator | 0:bb348c97df44 | 202 | } |
lypinator | 0:bb348c97df44 | 203 | else |
lypinator | 0:bb348c97df44 | 204 | { |
lypinator | 0:bb348c97df44 | 205 | /* Disable the selected Stream */ |
lypinator | 0:bb348c97df44 | 206 | LL_DMA_DisableStream(DMAx,Stream); |
lypinator | 0:bb348c97df44 | 207 | |
lypinator | 0:bb348c97df44 | 208 | /* Get the DMA Stream Instance */ |
lypinator | 0:bb348c97df44 | 209 | tmp = (DMA_Stream_TypeDef *)(__LL_DMA_GET_STREAM_INSTANCE(DMAx, Stream)); |
lypinator | 0:bb348c97df44 | 210 | |
lypinator | 0:bb348c97df44 | 211 | /* Reset DMAx_Streamy configuration register */ |
lypinator | 0:bb348c97df44 | 212 | LL_DMA_WriteReg(tmp, CR, 0U); |
lypinator | 0:bb348c97df44 | 213 | |
lypinator | 0:bb348c97df44 | 214 | /* Reset DMAx_Streamy remaining bytes register */ |
lypinator | 0:bb348c97df44 | 215 | LL_DMA_WriteReg(tmp, NDTR, 0U); |
lypinator | 0:bb348c97df44 | 216 | |
lypinator | 0:bb348c97df44 | 217 | /* Reset DMAx_Streamy peripheral address register */ |
lypinator | 0:bb348c97df44 | 218 | LL_DMA_WriteReg(tmp, PAR, 0U); |
lypinator | 0:bb348c97df44 | 219 | |
lypinator | 0:bb348c97df44 | 220 | /* Reset DMAx_Streamy memory address register */ |
lypinator | 0:bb348c97df44 | 221 | LL_DMA_WriteReg(tmp, M0AR, 0U); |
lypinator | 0:bb348c97df44 | 222 | |
lypinator | 0:bb348c97df44 | 223 | /* Reset DMAx_Streamy memory address register */ |
lypinator | 0:bb348c97df44 | 224 | LL_DMA_WriteReg(tmp, M1AR, 0U); |
lypinator | 0:bb348c97df44 | 225 | |
lypinator | 0:bb348c97df44 | 226 | /* Reset DMAx_Streamy FIFO control register */ |
lypinator | 0:bb348c97df44 | 227 | LL_DMA_WriteReg(tmp, FCR, 0x00000021U); |
lypinator | 0:bb348c97df44 | 228 | |
lypinator | 0:bb348c97df44 | 229 | /* Reset Channel register field for DMAx Stream*/ |
lypinator | 0:bb348c97df44 | 230 | LL_DMA_SetChannelSelection(DMAx, Stream, LL_DMA_CHANNEL_0); |
lypinator | 0:bb348c97df44 | 231 | |
lypinator | 0:bb348c97df44 | 232 | if(Stream == LL_DMA_STREAM_0) |
lypinator | 0:bb348c97df44 | 233 | { |
lypinator | 0:bb348c97df44 | 234 | /* Reset the Stream0 pending flags */ |
lypinator | 0:bb348c97df44 | 235 | DMAx->LIFCR = 0x0000003FU; |
lypinator | 0:bb348c97df44 | 236 | } |
lypinator | 0:bb348c97df44 | 237 | else if(Stream == LL_DMA_STREAM_1) |
lypinator | 0:bb348c97df44 | 238 | { |
lypinator | 0:bb348c97df44 | 239 | /* Reset the Stream1 pending flags */ |
lypinator | 0:bb348c97df44 | 240 | DMAx->LIFCR = 0x00000F40U; |
lypinator | 0:bb348c97df44 | 241 | } |
lypinator | 0:bb348c97df44 | 242 | else if(Stream == LL_DMA_STREAM_2) |
lypinator | 0:bb348c97df44 | 243 | { |
lypinator | 0:bb348c97df44 | 244 | /* Reset the Stream2 pending flags */ |
lypinator | 0:bb348c97df44 | 245 | DMAx->LIFCR = 0x003F0000U; |
lypinator | 0:bb348c97df44 | 246 | } |
lypinator | 0:bb348c97df44 | 247 | else if(Stream == LL_DMA_STREAM_3) |
lypinator | 0:bb348c97df44 | 248 | { |
lypinator | 0:bb348c97df44 | 249 | /* Reset the Stream3 pending flags */ |
lypinator | 0:bb348c97df44 | 250 | DMAx->LIFCR = 0x0F400000U; |
lypinator | 0:bb348c97df44 | 251 | } |
lypinator | 0:bb348c97df44 | 252 | else if(Stream == LL_DMA_STREAM_4) |
lypinator | 0:bb348c97df44 | 253 | { |
lypinator | 0:bb348c97df44 | 254 | /* Reset the Stream4 pending flags */ |
lypinator | 0:bb348c97df44 | 255 | DMAx->HIFCR = 0x0000003FU; |
lypinator | 0:bb348c97df44 | 256 | } |
lypinator | 0:bb348c97df44 | 257 | else if(Stream == LL_DMA_STREAM_5) |
lypinator | 0:bb348c97df44 | 258 | { |
lypinator | 0:bb348c97df44 | 259 | /* Reset the Stream5 pending flags */ |
lypinator | 0:bb348c97df44 | 260 | DMAx->HIFCR = 0x00000F40U; |
lypinator | 0:bb348c97df44 | 261 | } |
lypinator | 0:bb348c97df44 | 262 | else if(Stream == LL_DMA_STREAM_6) |
lypinator | 0:bb348c97df44 | 263 | { |
lypinator | 0:bb348c97df44 | 264 | /* Reset the Stream6 pending flags */ |
lypinator | 0:bb348c97df44 | 265 | DMAx->HIFCR = 0x003F0000U; |
lypinator | 0:bb348c97df44 | 266 | } |
lypinator | 0:bb348c97df44 | 267 | else if(Stream == LL_DMA_STREAM_7) |
lypinator | 0:bb348c97df44 | 268 | { |
lypinator | 0:bb348c97df44 | 269 | /* Reset the Stream7 pending flags */ |
lypinator | 0:bb348c97df44 | 270 | DMAx->HIFCR = 0x0F400000U; |
lypinator | 0:bb348c97df44 | 271 | } |
lypinator | 0:bb348c97df44 | 272 | else |
lypinator | 0:bb348c97df44 | 273 | { |
lypinator | 0:bb348c97df44 | 274 | status = ERROR; |
lypinator | 0:bb348c97df44 | 275 | } |
lypinator | 0:bb348c97df44 | 276 | } |
lypinator | 0:bb348c97df44 | 277 | |
lypinator | 0:bb348c97df44 | 278 | return status; |
lypinator | 0:bb348c97df44 | 279 | } |
lypinator | 0:bb348c97df44 | 280 | |
lypinator | 0:bb348c97df44 | 281 | /** |
lypinator | 0:bb348c97df44 | 282 | * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct. |
lypinator | 0:bb348c97df44 | 283 | * @note To convert DMAx_Streamy Instance to DMAx Instance and Streamy, use helper macros : |
lypinator | 0:bb348c97df44 | 284 | * @arg @ref __LL_DMA_GET_INSTANCE |
lypinator | 0:bb348c97df44 | 285 | * @arg @ref __LL_DMA_GET_STREAM |
lypinator | 0:bb348c97df44 | 286 | * @param DMAx DMAx Instance |
lypinator | 0:bb348c97df44 | 287 | * @param Stream This parameter can be one of the following values: |
lypinator | 0:bb348c97df44 | 288 | * @arg @ref LL_DMA_STREAM_0 |
lypinator | 0:bb348c97df44 | 289 | * @arg @ref LL_DMA_STREAM_1 |
lypinator | 0:bb348c97df44 | 290 | * @arg @ref LL_DMA_STREAM_2 |
lypinator | 0:bb348c97df44 | 291 | * @arg @ref LL_DMA_STREAM_3 |
lypinator | 0:bb348c97df44 | 292 | * @arg @ref LL_DMA_STREAM_4 |
lypinator | 0:bb348c97df44 | 293 | * @arg @ref LL_DMA_STREAM_5 |
lypinator | 0:bb348c97df44 | 294 | * @arg @ref LL_DMA_STREAM_6 |
lypinator | 0:bb348c97df44 | 295 | * @arg @ref LL_DMA_STREAM_7 |
lypinator | 0:bb348c97df44 | 296 | * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure. |
lypinator | 0:bb348c97df44 | 297 | * @retval An ErrorStatus enumeration value: |
lypinator | 0:bb348c97df44 | 298 | * - SUCCESS: DMA registers are initialized |
lypinator | 0:bb348c97df44 | 299 | * - ERROR: Not applicable |
lypinator | 0:bb348c97df44 | 300 | */ |
lypinator | 0:bb348c97df44 | 301 | uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct) |
lypinator | 0:bb348c97df44 | 302 | { |
lypinator | 0:bb348c97df44 | 303 | /* Check the DMA Instance DMAx and Stream parameters*/ |
lypinator | 0:bb348c97df44 | 304 | assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream)); |
lypinator | 0:bb348c97df44 | 305 | |
lypinator | 0:bb348c97df44 | 306 | /* Check the DMA parameters from DMA_InitStruct */ |
lypinator | 0:bb348c97df44 | 307 | assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction)); |
lypinator | 0:bb348c97df44 | 308 | assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode)); |
lypinator | 0:bb348c97df44 | 309 | assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode)); |
lypinator | 0:bb348c97df44 | 310 | assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode)); |
lypinator | 0:bb348c97df44 | 311 | assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize)); |
lypinator | 0:bb348c97df44 | 312 | assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize)); |
lypinator | 0:bb348c97df44 | 313 | assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData)); |
lypinator | 0:bb348c97df44 | 314 | assert_param(IS_LL_DMA_CHANNEL(DMA_InitStruct->Channel)); |
lypinator | 0:bb348c97df44 | 315 | assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority)); |
lypinator | 0:bb348c97df44 | 316 | assert_param(IS_LL_DMA_FIFO_MODE_STATE(DMA_InitStruct->FIFOMode)); |
lypinator | 0:bb348c97df44 | 317 | /* Check the memory burst, peripheral burst and FIFO threshold parameters only |
lypinator | 0:bb348c97df44 | 318 | when FIFO mode is enabled */ |
lypinator | 0:bb348c97df44 | 319 | if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE) |
lypinator | 0:bb348c97df44 | 320 | { |
lypinator | 0:bb348c97df44 | 321 | assert_param(IS_LL_DMA_FIFO_THRESHOLD(DMA_InitStruct->FIFOThreshold)); |
lypinator | 0:bb348c97df44 | 322 | assert_param(IS_LL_DMA_MEMORY_BURST(DMA_InitStruct->MemBurst)); |
lypinator | 0:bb348c97df44 | 323 | assert_param(IS_LL_DMA_PERIPHERAL_BURST(DMA_InitStruct->PeriphBurst)); |
lypinator | 0:bb348c97df44 | 324 | } |
lypinator | 0:bb348c97df44 | 325 | |
lypinator | 0:bb348c97df44 | 326 | /*---------------------------- DMAx SxCR Configuration ------------------------ |
lypinator | 0:bb348c97df44 | 327 | * Configure DMAx_Streamy: data transfer direction, data transfer mode, |
lypinator | 0:bb348c97df44 | 328 | * peripheral and memory increment mode, |
lypinator | 0:bb348c97df44 | 329 | * data size alignment and priority level with parameters : |
lypinator | 0:bb348c97df44 | 330 | * - Direction: DMA_SxCR_DIR[1:0] bits |
lypinator | 0:bb348c97df44 | 331 | * - Mode: DMA_SxCR_CIRC bit |
lypinator | 0:bb348c97df44 | 332 | * - PeriphOrM2MSrcIncMode: DMA_SxCR_PINC bit |
lypinator | 0:bb348c97df44 | 333 | * - MemoryOrM2MDstIncMode: DMA_SxCR_MINC bit |
lypinator | 0:bb348c97df44 | 334 | * - PeriphOrM2MSrcDataSize: DMA_SxCR_PSIZE[1:0] bits |
lypinator | 0:bb348c97df44 | 335 | * - MemoryOrM2MDstDataSize: DMA_SxCR_MSIZE[1:0] bits |
lypinator | 0:bb348c97df44 | 336 | * - Priority: DMA_SxCR_PL[1:0] bits |
lypinator | 0:bb348c97df44 | 337 | */ |
lypinator | 0:bb348c97df44 | 338 | LL_DMA_ConfigTransfer(DMAx, Stream, DMA_InitStruct->Direction | \ |
lypinator | 0:bb348c97df44 | 339 | DMA_InitStruct->Mode | \ |
lypinator | 0:bb348c97df44 | 340 | DMA_InitStruct->PeriphOrM2MSrcIncMode | \ |
lypinator | 0:bb348c97df44 | 341 | DMA_InitStruct->MemoryOrM2MDstIncMode | \ |
lypinator | 0:bb348c97df44 | 342 | DMA_InitStruct->PeriphOrM2MSrcDataSize | \ |
lypinator | 0:bb348c97df44 | 343 | DMA_InitStruct->MemoryOrM2MDstDataSize | \ |
lypinator | 0:bb348c97df44 | 344 | DMA_InitStruct->Priority |
lypinator | 0:bb348c97df44 | 345 | ); |
lypinator | 0:bb348c97df44 | 346 | |
lypinator | 0:bb348c97df44 | 347 | if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE) |
lypinator | 0:bb348c97df44 | 348 | { |
lypinator | 0:bb348c97df44 | 349 | /*---------------------------- DMAx SxFCR Configuration ------------------------ |
lypinator | 0:bb348c97df44 | 350 | * Configure DMAx_Streamy: fifo mode and fifo threshold with parameters : |
lypinator | 0:bb348c97df44 | 351 | * - FIFOMode: DMA_SxFCR_DMDIS bit |
lypinator | 0:bb348c97df44 | 352 | * - FIFOThreshold: DMA_SxFCR_FTH[1:0] bits |
lypinator | 0:bb348c97df44 | 353 | */ |
lypinator | 0:bb348c97df44 | 354 | LL_DMA_ConfigFifo(DMAx, Stream, DMA_InitStruct->FIFOMode, DMA_InitStruct->FIFOThreshold); |
lypinator | 0:bb348c97df44 | 355 | |
lypinator | 0:bb348c97df44 | 356 | /*---------------------------- DMAx SxCR Configuration -------------------------- |
lypinator | 0:bb348c97df44 | 357 | * Configure DMAx_Streamy: memory burst transfer with parameters : |
lypinator | 0:bb348c97df44 | 358 | * - MemBurst: DMA_SxCR_MBURST[1:0] bits |
lypinator | 0:bb348c97df44 | 359 | */ |
lypinator | 0:bb348c97df44 | 360 | LL_DMA_SetMemoryBurstxfer(DMAx,Stream,DMA_InitStruct->MemBurst); |
lypinator | 0:bb348c97df44 | 361 | |
lypinator | 0:bb348c97df44 | 362 | /*---------------------------- DMAx SxCR Configuration -------------------------- |
lypinator | 0:bb348c97df44 | 363 | * Configure DMAx_Streamy: peripheral burst transfer with parameters : |
lypinator | 0:bb348c97df44 | 364 | * - PeriphBurst: DMA_SxCR_PBURST[1:0] bits |
lypinator | 0:bb348c97df44 | 365 | */ |
lypinator | 0:bb348c97df44 | 366 | LL_DMA_SetPeriphBurstxfer(DMAx,Stream,DMA_InitStruct->PeriphBurst); |
lypinator | 0:bb348c97df44 | 367 | } |
lypinator | 0:bb348c97df44 | 368 | |
lypinator | 0:bb348c97df44 | 369 | /*-------------------------- DMAx SxM0AR Configuration -------------------------- |
lypinator | 0:bb348c97df44 | 370 | * Configure the memory or destination base address with parameter : |
lypinator | 0:bb348c97df44 | 371 | * - MemoryOrM2MDstAddress: DMA_SxM0AR_M0A[31:0] bits |
lypinator | 0:bb348c97df44 | 372 | */ |
lypinator | 0:bb348c97df44 | 373 | LL_DMA_SetMemoryAddress(DMAx, Stream, DMA_InitStruct->MemoryOrM2MDstAddress); |
lypinator | 0:bb348c97df44 | 374 | |
lypinator | 0:bb348c97df44 | 375 | /*-------------------------- DMAx SxPAR Configuration --------------------------- |
lypinator | 0:bb348c97df44 | 376 | * Configure the peripheral or source base address with parameter : |
lypinator | 0:bb348c97df44 | 377 | * - PeriphOrM2MSrcAddress: DMA_SxPAR_PA[31:0] bits |
lypinator | 0:bb348c97df44 | 378 | */ |
lypinator | 0:bb348c97df44 | 379 | LL_DMA_SetPeriphAddress(DMAx, Stream, DMA_InitStruct->PeriphOrM2MSrcAddress); |
lypinator | 0:bb348c97df44 | 380 | |
lypinator | 0:bb348c97df44 | 381 | /*--------------------------- DMAx SxNDTR Configuration ------------------------- |
lypinator | 0:bb348c97df44 | 382 | * Configure the peripheral base address with parameter : |
lypinator | 0:bb348c97df44 | 383 | * - NbData: DMA_SxNDT[15:0] bits |
lypinator | 0:bb348c97df44 | 384 | */ |
lypinator | 0:bb348c97df44 | 385 | LL_DMA_SetDataLength(DMAx, Stream, DMA_InitStruct->NbData); |
lypinator | 0:bb348c97df44 | 386 | |
lypinator | 0:bb348c97df44 | 387 | /*--------------------------- DMA SxCR_CHSEL Configuration ---------------------- |
lypinator | 0:bb348c97df44 | 388 | * Configure the peripheral base address with parameter : |
lypinator | 0:bb348c97df44 | 389 | * - PeriphRequest: DMA_SxCR_CHSEL[2:0] bits |
lypinator | 0:bb348c97df44 | 390 | */ |
lypinator | 0:bb348c97df44 | 391 | LL_DMA_SetChannelSelection(DMAx, Stream, DMA_InitStruct->Channel); |
lypinator | 0:bb348c97df44 | 392 | |
lypinator | 0:bb348c97df44 | 393 | return SUCCESS; |
lypinator | 0:bb348c97df44 | 394 | } |
lypinator | 0:bb348c97df44 | 395 | |
lypinator | 0:bb348c97df44 | 396 | /** |
lypinator | 0:bb348c97df44 | 397 | * @brief Set each @ref LL_DMA_InitTypeDef field to default value. |
lypinator | 0:bb348c97df44 | 398 | * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure. |
lypinator | 0:bb348c97df44 | 399 | * @retval None |
lypinator | 0:bb348c97df44 | 400 | */ |
lypinator | 0:bb348c97df44 | 401 | void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct) |
lypinator | 0:bb348c97df44 | 402 | { |
lypinator | 0:bb348c97df44 | 403 | /* Set DMA_InitStruct fields to default values */ |
lypinator | 0:bb348c97df44 | 404 | DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U; |
lypinator | 0:bb348c97df44 | 405 | DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U; |
lypinator | 0:bb348c97df44 | 406 | DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY; |
lypinator | 0:bb348c97df44 | 407 | DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL; |
lypinator | 0:bb348c97df44 | 408 | DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; |
lypinator | 0:bb348c97df44 | 409 | DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT; |
lypinator | 0:bb348c97df44 | 410 | DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE; |
lypinator | 0:bb348c97df44 | 411 | DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE; |
lypinator | 0:bb348c97df44 | 412 | DMA_InitStruct->NbData = 0x00000000U; |
lypinator | 0:bb348c97df44 | 413 | DMA_InitStruct->Channel = LL_DMA_CHANNEL_0; |
lypinator | 0:bb348c97df44 | 414 | DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW; |
lypinator | 0:bb348c97df44 | 415 | DMA_InitStruct->FIFOMode = LL_DMA_FIFOMODE_DISABLE; |
lypinator | 0:bb348c97df44 | 416 | DMA_InitStruct->FIFOThreshold = LL_DMA_FIFOTHRESHOLD_1_4; |
lypinator | 0:bb348c97df44 | 417 | DMA_InitStruct->MemBurst = LL_DMA_MBURST_SINGLE; |
lypinator | 0:bb348c97df44 | 418 | DMA_InitStruct->PeriphBurst = LL_DMA_PBURST_SINGLE; |
lypinator | 0:bb348c97df44 | 419 | } |
lypinator | 0:bb348c97df44 | 420 | |
lypinator | 0:bb348c97df44 | 421 | /** |
lypinator | 0:bb348c97df44 | 422 | * @} |
lypinator | 0:bb348c97df44 | 423 | */ |
lypinator | 0:bb348c97df44 | 424 | |
lypinator | 0:bb348c97df44 | 425 | /** |
lypinator | 0:bb348c97df44 | 426 | * @} |
lypinator | 0:bb348c97df44 | 427 | */ |
lypinator | 0:bb348c97df44 | 428 | |
lypinator | 0:bb348c97df44 | 429 | /** |
lypinator | 0:bb348c97df44 | 430 | * @} |
lypinator | 0:bb348c97df44 | 431 | */ |
lypinator | 0:bb348c97df44 | 432 | |
lypinator | 0:bb348c97df44 | 433 | #endif /* DMA1 || DMA2 */ |
lypinator | 0:bb348c97df44 | 434 | |
lypinator | 0:bb348c97df44 | 435 | /** |
lypinator | 0:bb348c97df44 | 436 | * @} |
lypinator | 0:bb348c97df44 | 437 | */ |
lypinator | 0:bb348c97df44 | 438 | |
lypinator | 0:bb348c97df44 | 439 | #endif /* USE_FULL_LL_DRIVER */ |
lypinator | 0:bb348c97df44 | 440 | |
lypinator | 0:bb348c97df44 | 441 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |