Initial commit
mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc.c@0:bb348c97df44, 2020-09-16 (annotated)
- Committer:
- lypinator
- Date:
- Wed Sep 16 01:11:49 2020 +0000
- Revision:
- 0:bb348c97df44
Added PWM
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
lypinator | 0:bb348c97df44 | 1 | /** |
lypinator | 0:bb348c97df44 | 2 | ****************************************************************************** |
lypinator | 0:bb348c97df44 | 3 | * @file stm32f4xx_hal_rcc.c |
lypinator | 0:bb348c97df44 | 4 | * @author MCD Application Team |
lypinator | 0:bb348c97df44 | 5 | * @brief RCC HAL module driver. |
lypinator | 0:bb348c97df44 | 6 | * This file provides firmware functions to manage the following |
lypinator | 0:bb348c97df44 | 7 | * functionalities of the Reset and Clock Control (RCC) peripheral: |
lypinator | 0:bb348c97df44 | 8 | * + Initialization and de-initialization functions |
lypinator | 0:bb348c97df44 | 9 | * + Peripheral Control functions |
lypinator | 0:bb348c97df44 | 10 | * |
lypinator | 0:bb348c97df44 | 11 | @verbatim |
lypinator | 0:bb348c97df44 | 12 | ============================================================================== |
lypinator | 0:bb348c97df44 | 13 | ##### RCC specific features ##### |
lypinator | 0:bb348c97df44 | 14 | ============================================================================== |
lypinator | 0:bb348c97df44 | 15 | [..] |
lypinator | 0:bb348c97df44 | 16 | After reset the device is running from Internal High Speed oscillator |
lypinator | 0:bb348c97df44 | 17 | (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache |
lypinator | 0:bb348c97df44 | 18 | and I-Cache are disabled, and all peripherals are off except internal |
lypinator | 0:bb348c97df44 | 19 | SRAM, Flash and JTAG. |
lypinator | 0:bb348c97df44 | 20 | (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses; |
lypinator | 0:bb348c97df44 | 21 | all peripherals mapped on these busses are running at HSI speed. |
lypinator | 0:bb348c97df44 | 22 | (+) The clock for all peripherals is switched off, except the SRAM and FLASH. |
lypinator | 0:bb348c97df44 | 23 | (+) All GPIOs are in input floating state, except the JTAG pins which |
lypinator | 0:bb348c97df44 | 24 | are assigned to be used for debug purpose. |
lypinator | 0:bb348c97df44 | 25 | |
lypinator | 0:bb348c97df44 | 26 | [..] |
lypinator | 0:bb348c97df44 | 27 | Once the device started from reset, the user application has to: |
lypinator | 0:bb348c97df44 | 28 | (+) Configure the clock source to be used to drive the System clock |
lypinator | 0:bb348c97df44 | 29 | (if the application needs higher frequency/performance) |
lypinator | 0:bb348c97df44 | 30 | (+) Configure the System clock frequency and Flash settings |
lypinator | 0:bb348c97df44 | 31 | (+) Configure the AHB and APB busses prescalers |
lypinator | 0:bb348c97df44 | 32 | (+) Enable the clock for the peripheral(s) to be used |
lypinator | 0:bb348c97df44 | 33 | (+) Configure the clock source(s) for peripherals which clocks are not |
lypinator | 0:bb348c97df44 | 34 | derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) |
lypinator | 0:bb348c97df44 | 35 | |
lypinator | 0:bb348c97df44 | 36 | ##### RCC Limitations ##### |
lypinator | 0:bb348c97df44 | 37 | ============================================================================== |
lypinator | 0:bb348c97df44 | 38 | [..] |
lypinator | 0:bb348c97df44 | 39 | A delay between an RCC peripheral clock enable and the effective peripheral |
lypinator | 0:bb348c97df44 | 40 | enabling should be taken into account in order to manage the peripheral read/write |
lypinator | 0:bb348c97df44 | 41 | from/to registers. |
lypinator | 0:bb348c97df44 | 42 | (+) This delay depends on the peripheral mapping. |
lypinator | 0:bb348c97df44 | 43 | (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle |
lypinator | 0:bb348c97df44 | 44 | after the clock enable bit is set on the hardware register |
lypinator | 0:bb348c97df44 | 45 | (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle |
lypinator | 0:bb348c97df44 | 46 | after the clock enable bit is set on the hardware register |
lypinator | 0:bb348c97df44 | 47 | |
lypinator | 0:bb348c97df44 | 48 | [..] |
lypinator | 0:bb348c97df44 | 49 | Implemented Workaround: |
lypinator | 0:bb348c97df44 | 50 | (+) For AHB & APB peripherals, a dummy read to the peripheral register has been |
lypinator | 0:bb348c97df44 | 51 | inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. |
lypinator | 0:bb348c97df44 | 52 | |
lypinator | 0:bb348c97df44 | 53 | @endverbatim |
lypinator | 0:bb348c97df44 | 54 | ****************************************************************************** |
lypinator | 0:bb348c97df44 | 55 | * @attention |
lypinator | 0:bb348c97df44 | 56 | * |
lypinator | 0:bb348c97df44 | 57 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
lypinator | 0:bb348c97df44 | 58 | * |
lypinator | 0:bb348c97df44 | 59 | * Redistribution and use in source and binary forms, with or without modification, |
lypinator | 0:bb348c97df44 | 60 | * are permitted provided that the following conditions are met: |
lypinator | 0:bb348c97df44 | 61 | * 1. Redistributions of source code must retain the above copyright notice, |
lypinator | 0:bb348c97df44 | 62 | * this list of conditions and the following disclaimer. |
lypinator | 0:bb348c97df44 | 63 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
lypinator | 0:bb348c97df44 | 64 | * this list of conditions and the following disclaimer in the documentation |
lypinator | 0:bb348c97df44 | 65 | * and/or other materials provided with the distribution. |
lypinator | 0:bb348c97df44 | 66 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
lypinator | 0:bb348c97df44 | 67 | * may be used to endorse or promote products derived from this software |
lypinator | 0:bb348c97df44 | 68 | * without specific prior written permission. |
lypinator | 0:bb348c97df44 | 69 | * |
lypinator | 0:bb348c97df44 | 70 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
lypinator | 0:bb348c97df44 | 71 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
lypinator | 0:bb348c97df44 | 72 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
lypinator | 0:bb348c97df44 | 73 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
lypinator | 0:bb348c97df44 | 74 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
lypinator | 0:bb348c97df44 | 75 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
lypinator | 0:bb348c97df44 | 76 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
lypinator | 0:bb348c97df44 | 77 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
lypinator | 0:bb348c97df44 | 78 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
lypinator | 0:bb348c97df44 | 79 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
lypinator | 0:bb348c97df44 | 80 | * |
lypinator | 0:bb348c97df44 | 81 | ****************************************************************************** |
lypinator | 0:bb348c97df44 | 82 | */ |
lypinator | 0:bb348c97df44 | 83 | |
lypinator | 0:bb348c97df44 | 84 | /* Includes ------------------------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 85 | #include "stm32f4xx_hal.h" |
lypinator | 0:bb348c97df44 | 86 | |
lypinator | 0:bb348c97df44 | 87 | /** @addtogroup STM32F4xx_HAL_Driver |
lypinator | 0:bb348c97df44 | 88 | * @{ |
lypinator | 0:bb348c97df44 | 89 | */ |
lypinator | 0:bb348c97df44 | 90 | |
lypinator | 0:bb348c97df44 | 91 | /** @defgroup RCC RCC |
lypinator | 0:bb348c97df44 | 92 | * @brief RCC HAL module driver |
lypinator | 0:bb348c97df44 | 93 | * @{ |
lypinator | 0:bb348c97df44 | 94 | */ |
lypinator | 0:bb348c97df44 | 95 | |
lypinator | 0:bb348c97df44 | 96 | #ifdef HAL_RCC_MODULE_ENABLED |
lypinator | 0:bb348c97df44 | 97 | |
lypinator | 0:bb348c97df44 | 98 | /* Private typedef -----------------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 99 | /* Private define ------------------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 100 | /** @addtogroup RCC_Private_Constants |
lypinator | 0:bb348c97df44 | 101 | * @{ |
lypinator | 0:bb348c97df44 | 102 | */ |
lypinator | 0:bb348c97df44 | 103 | |
lypinator | 0:bb348c97df44 | 104 | /* Private macro -------------------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 105 | #define __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() |
lypinator | 0:bb348c97df44 | 106 | #define MCO1_GPIO_PORT GPIOA |
lypinator | 0:bb348c97df44 | 107 | #define MCO1_PIN GPIO_PIN_8 |
lypinator | 0:bb348c97df44 | 108 | |
lypinator | 0:bb348c97df44 | 109 | #define __MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() |
lypinator | 0:bb348c97df44 | 110 | #define MCO2_GPIO_PORT GPIOC |
lypinator | 0:bb348c97df44 | 111 | #define MCO2_PIN GPIO_PIN_9 |
lypinator | 0:bb348c97df44 | 112 | /** |
lypinator | 0:bb348c97df44 | 113 | * @} |
lypinator | 0:bb348c97df44 | 114 | */ |
lypinator | 0:bb348c97df44 | 115 | |
lypinator | 0:bb348c97df44 | 116 | /* Private variables ---------------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 117 | /** @defgroup RCC_Private_Variables RCC Private Variables |
lypinator | 0:bb348c97df44 | 118 | * @{ |
lypinator | 0:bb348c97df44 | 119 | */ |
lypinator | 0:bb348c97df44 | 120 | /** |
lypinator | 0:bb348c97df44 | 121 | * @} |
lypinator | 0:bb348c97df44 | 122 | */ |
lypinator | 0:bb348c97df44 | 123 | /* Private function prototypes -----------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 124 | /* Private functions ---------------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 125 | |
lypinator | 0:bb348c97df44 | 126 | /** @defgroup RCC_Exported_Functions RCC Exported Functions |
lypinator | 0:bb348c97df44 | 127 | * @{ |
lypinator | 0:bb348c97df44 | 128 | */ |
lypinator | 0:bb348c97df44 | 129 | |
lypinator | 0:bb348c97df44 | 130 | /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions |
lypinator | 0:bb348c97df44 | 131 | * @brief Initialization and Configuration functions |
lypinator | 0:bb348c97df44 | 132 | * |
lypinator | 0:bb348c97df44 | 133 | @verbatim |
lypinator | 0:bb348c97df44 | 134 | =============================================================================== |
lypinator | 0:bb348c97df44 | 135 | ##### Initialization and de-initialization functions ##### |
lypinator | 0:bb348c97df44 | 136 | =============================================================================== |
lypinator | 0:bb348c97df44 | 137 | [..] |
lypinator | 0:bb348c97df44 | 138 | This section provides functions allowing to configure the internal/external oscillators |
lypinator | 0:bb348c97df44 | 139 | (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1 |
lypinator | 0:bb348c97df44 | 140 | and APB2). |
lypinator | 0:bb348c97df44 | 141 | |
lypinator | 0:bb348c97df44 | 142 | [..] Internal/external clock and PLL configuration |
lypinator | 0:bb348c97df44 | 143 | (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through |
lypinator | 0:bb348c97df44 | 144 | the PLL as System clock source. |
lypinator | 0:bb348c97df44 | 145 | |
lypinator | 0:bb348c97df44 | 146 | (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC |
lypinator | 0:bb348c97df44 | 147 | clock source. |
lypinator | 0:bb348c97df44 | 148 | |
lypinator | 0:bb348c97df44 | 149 | (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or |
lypinator | 0:bb348c97df44 | 150 | through the PLL as System clock source. Can be used also as RTC clock source. |
lypinator | 0:bb348c97df44 | 151 | |
lypinator | 0:bb348c97df44 | 152 | (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. |
lypinator | 0:bb348c97df44 | 153 | |
lypinator | 0:bb348c97df44 | 154 | (#) PLL (clocked by HSI or HSE), featuring two different output clocks: |
lypinator | 0:bb348c97df44 | 155 | (++) The first output is used to generate the high speed system clock (up to 168 MHz) |
lypinator | 0:bb348c97df44 | 156 | (++) The second output is used to generate the clock for the USB OTG FS (48 MHz), |
lypinator | 0:bb348c97df44 | 157 | the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz). |
lypinator | 0:bb348c97df44 | 158 | |
lypinator | 0:bb348c97df44 | 159 | (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE() |
lypinator | 0:bb348c97df44 | 160 | and if a HSE clock failure occurs(HSE used directly or through PLL as System |
lypinator | 0:bb348c97df44 | 161 | clock source), the System clocks automatically switched to HSI and an interrupt |
lypinator | 0:bb348c97df44 | 162 | is generated if enabled. The interrupt is linked to the Cortex-M4 NMI |
lypinator | 0:bb348c97df44 | 163 | (Non-Maskable Interrupt) exception vector. |
lypinator | 0:bb348c97df44 | 164 | |
lypinator | 0:bb348c97df44 | 165 | (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL |
lypinator | 0:bb348c97df44 | 166 | clock (through a configurable prescaler) on PA8 pin. |
lypinator | 0:bb348c97df44 | 167 | |
lypinator | 0:bb348c97df44 | 168 | (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S |
lypinator | 0:bb348c97df44 | 169 | clock (through a configurable prescaler) on PC9 pin. |
lypinator | 0:bb348c97df44 | 170 | |
lypinator | 0:bb348c97df44 | 171 | [..] System, AHB and APB busses clocks configuration |
lypinator | 0:bb348c97df44 | 172 | (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, |
lypinator | 0:bb348c97df44 | 173 | HSE and PLL. |
lypinator | 0:bb348c97df44 | 174 | The AHB clock (HCLK) is derived from System clock through configurable |
lypinator | 0:bb348c97df44 | 175 | prescaler and used to clock the CPU, memory and peripherals mapped |
lypinator | 0:bb348c97df44 | 176 | on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived |
lypinator | 0:bb348c97df44 | 177 | from AHB clock through configurable prescalers and used to clock |
lypinator | 0:bb348c97df44 | 178 | the peripherals mapped on these busses. You can use |
lypinator | 0:bb348c97df44 | 179 | "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. |
lypinator | 0:bb348c97df44 | 180 | |
lypinator | 0:bb348c97df44 | 181 | (#) For the STM32F405xx/07xx and STM32F415xx/17xx devices, the maximum |
lypinator | 0:bb348c97df44 | 182 | frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz. |
lypinator | 0:bb348c97df44 | 183 | Depending on the device voltage range, the maximum frequency should |
lypinator | 0:bb348c97df44 | 184 | be adapted accordingly (refer to the product datasheets for more details). |
lypinator | 0:bb348c97df44 | 185 | |
lypinator | 0:bb348c97df44 | 186 | (#) For the STM32F42xxx, STM32F43xxx, STM32F446xx, STM32F469xx and STM32F479xx devices, |
lypinator | 0:bb348c97df44 | 187 | the maximum frequency of the SYSCLK and HCLK is 180 MHz, PCLK2 90 MHz and PCLK1 45 MHz. |
lypinator | 0:bb348c97df44 | 188 | Depending on the device voltage range, the maximum frequency should |
lypinator | 0:bb348c97df44 | 189 | be adapted accordingly (refer to the product datasheets for more details). |
lypinator | 0:bb348c97df44 | 190 | |
lypinator | 0:bb348c97df44 | 191 | (#) For the STM32F401xx, the maximum frequency of the SYSCLK and HCLK is 84 MHz, |
lypinator | 0:bb348c97df44 | 192 | PCLK2 84 MHz and PCLK1 42 MHz. |
lypinator | 0:bb348c97df44 | 193 | Depending on the device voltage range, the maximum frequency should |
lypinator | 0:bb348c97df44 | 194 | be adapted accordingly (refer to the product datasheets for more details). |
lypinator | 0:bb348c97df44 | 195 | |
lypinator | 0:bb348c97df44 | 196 | (#) For the STM32F41xxx, the maximum frequency of the SYSCLK and HCLK is 100 MHz, |
lypinator | 0:bb348c97df44 | 197 | PCLK2 100 MHz and PCLK1 50 MHz. |
lypinator | 0:bb348c97df44 | 198 | Depending on the device voltage range, the maximum frequency should |
lypinator | 0:bb348c97df44 | 199 | be adapted accordingly (refer to the product datasheets for more details). |
lypinator | 0:bb348c97df44 | 200 | |
lypinator | 0:bb348c97df44 | 201 | @endverbatim |
lypinator | 0:bb348c97df44 | 202 | * @{ |
lypinator | 0:bb348c97df44 | 203 | */ |
lypinator | 0:bb348c97df44 | 204 | |
lypinator | 0:bb348c97df44 | 205 | /** |
lypinator | 0:bb348c97df44 | 206 | * @brief Resets the RCC clock configuration to the default reset state. |
lypinator | 0:bb348c97df44 | 207 | * @note The default reset state of the clock configuration is given below: |
lypinator | 0:bb348c97df44 | 208 | * - HSI ON and used as system clock source |
lypinator | 0:bb348c97df44 | 209 | * - HSE and PLL OFF |
lypinator | 0:bb348c97df44 | 210 | * - AHB, APB1 and APB2 prescaler set to 1. |
lypinator | 0:bb348c97df44 | 211 | * - CSS, MCO1 and MCO2 OFF |
lypinator | 0:bb348c97df44 | 212 | * - All interrupts disabled |
lypinator | 0:bb348c97df44 | 213 | * @note This function doesn't modify the configuration of the |
lypinator | 0:bb348c97df44 | 214 | * - Peripheral clocks |
lypinator | 0:bb348c97df44 | 215 | * - LSI, LSE and RTC clocks |
lypinator | 0:bb348c97df44 | 216 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 217 | */ |
lypinator | 0:bb348c97df44 | 218 | __weak HAL_StatusTypeDef HAL_RCC_DeInit(void) |
lypinator | 0:bb348c97df44 | 219 | { |
lypinator | 0:bb348c97df44 | 220 | return HAL_OK; |
lypinator | 0:bb348c97df44 | 221 | } |
lypinator | 0:bb348c97df44 | 222 | |
lypinator | 0:bb348c97df44 | 223 | /** |
lypinator | 0:bb348c97df44 | 224 | * @brief Initializes the RCC Oscillators according to the specified parameters in the |
lypinator | 0:bb348c97df44 | 225 | * RCC_OscInitTypeDef. |
lypinator | 0:bb348c97df44 | 226 | * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that |
lypinator | 0:bb348c97df44 | 227 | * contains the configuration information for the RCC Oscillators. |
lypinator | 0:bb348c97df44 | 228 | * @note The PLL is not disabled when used as system clock. |
lypinator | 0:bb348c97df44 | 229 | * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not |
lypinator | 0:bb348c97df44 | 230 | * supported by this API. User should request a transition to LSE Off |
lypinator | 0:bb348c97df44 | 231 | * first and then LSE On or LSE Bypass. |
lypinator | 0:bb348c97df44 | 232 | * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not |
lypinator | 0:bb348c97df44 | 233 | * supported by this API. User should request a transition to HSE Off |
lypinator | 0:bb348c97df44 | 234 | * first and then HSE On or HSE Bypass. |
lypinator | 0:bb348c97df44 | 235 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 236 | */ |
lypinator | 0:bb348c97df44 | 237 | __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) |
lypinator | 0:bb348c97df44 | 238 | { |
lypinator | 0:bb348c97df44 | 239 | uint32_t tickstart; |
lypinator | 0:bb348c97df44 | 240 | |
lypinator | 0:bb348c97df44 | 241 | /* Check Null pointer */ |
lypinator | 0:bb348c97df44 | 242 | if(RCC_OscInitStruct == NULL) |
lypinator | 0:bb348c97df44 | 243 | { |
lypinator | 0:bb348c97df44 | 244 | return HAL_ERROR; |
lypinator | 0:bb348c97df44 | 245 | } |
lypinator | 0:bb348c97df44 | 246 | |
lypinator | 0:bb348c97df44 | 247 | /* Check the parameters */ |
lypinator | 0:bb348c97df44 | 248 | assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); |
lypinator | 0:bb348c97df44 | 249 | /*------------------------------- HSE Configuration ------------------------*/ |
lypinator | 0:bb348c97df44 | 250 | if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) |
lypinator | 0:bb348c97df44 | 251 | { |
lypinator | 0:bb348c97df44 | 252 | /* Check the parameters */ |
lypinator | 0:bb348c97df44 | 253 | assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); |
lypinator | 0:bb348c97df44 | 254 | /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ |
lypinator | 0:bb348c97df44 | 255 | if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\ |
lypinator | 0:bb348c97df44 | 256 | ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) |
lypinator | 0:bb348c97df44 | 257 | { |
lypinator | 0:bb348c97df44 | 258 | if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) |
lypinator | 0:bb348c97df44 | 259 | { |
lypinator | 0:bb348c97df44 | 260 | return HAL_ERROR; |
lypinator | 0:bb348c97df44 | 261 | } |
lypinator | 0:bb348c97df44 | 262 | } |
lypinator | 0:bb348c97df44 | 263 | else |
lypinator | 0:bb348c97df44 | 264 | { |
lypinator | 0:bb348c97df44 | 265 | /* Set the new HSE configuration ---------------------------------------*/ |
lypinator | 0:bb348c97df44 | 266 | __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); |
lypinator | 0:bb348c97df44 | 267 | |
lypinator | 0:bb348c97df44 | 268 | /* Check the HSE State */ |
lypinator | 0:bb348c97df44 | 269 | if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF) |
lypinator | 0:bb348c97df44 | 270 | { |
lypinator | 0:bb348c97df44 | 271 | /* Get Start Tick */ |
lypinator | 0:bb348c97df44 | 272 | tickstart = HAL_GetTick(); |
lypinator | 0:bb348c97df44 | 273 | |
lypinator | 0:bb348c97df44 | 274 | /* Wait till HSE is ready */ |
lypinator | 0:bb348c97df44 | 275 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) |
lypinator | 0:bb348c97df44 | 276 | { |
lypinator | 0:bb348c97df44 | 277 | if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) |
lypinator | 0:bb348c97df44 | 278 | { |
lypinator | 0:bb348c97df44 | 279 | return HAL_TIMEOUT; |
lypinator | 0:bb348c97df44 | 280 | } |
lypinator | 0:bb348c97df44 | 281 | } |
lypinator | 0:bb348c97df44 | 282 | } |
lypinator | 0:bb348c97df44 | 283 | else |
lypinator | 0:bb348c97df44 | 284 | { |
lypinator | 0:bb348c97df44 | 285 | /* Get Start Tick */ |
lypinator | 0:bb348c97df44 | 286 | tickstart = HAL_GetTick(); |
lypinator | 0:bb348c97df44 | 287 | |
lypinator | 0:bb348c97df44 | 288 | /* Wait till HSE is bypassed or disabled */ |
lypinator | 0:bb348c97df44 | 289 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) |
lypinator | 0:bb348c97df44 | 290 | { |
lypinator | 0:bb348c97df44 | 291 | if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) |
lypinator | 0:bb348c97df44 | 292 | { |
lypinator | 0:bb348c97df44 | 293 | return HAL_TIMEOUT; |
lypinator | 0:bb348c97df44 | 294 | } |
lypinator | 0:bb348c97df44 | 295 | } |
lypinator | 0:bb348c97df44 | 296 | } |
lypinator | 0:bb348c97df44 | 297 | } |
lypinator | 0:bb348c97df44 | 298 | } |
lypinator | 0:bb348c97df44 | 299 | /*----------------------------- HSI Configuration --------------------------*/ |
lypinator | 0:bb348c97df44 | 300 | if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) |
lypinator | 0:bb348c97df44 | 301 | { |
lypinator | 0:bb348c97df44 | 302 | /* Check the parameters */ |
lypinator | 0:bb348c97df44 | 303 | assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); |
lypinator | 0:bb348c97df44 | 304 | assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); |
lypinator | 0:bb348c97df44 | 305 | |
lypinator | 0:bb348c97df44 | 306 | /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ |
lypinator | 0:bb348c97df44 | 307 | if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\ |
lypinator | 0:bb348c97df44 | 308 | ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) |
lypinator | 0:bb348c97df44 | 309 | { |
lypinator | 0:bb348c97df44 | 310 | /* When HSI is used as system clock it will not disabled */ |
lypinator | 0:bb348c97df44 | 311 | if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) |
lypinator | 0:bb348c97df44 | 312 | { |
lypinator | 0:bb348c97df44 | 313 | return HAL_ERROR; |
lypinator | 0:bb348c97df44 | 314 | } |
lypinator | 0:bb348c97df44 | 315 | /* Otherwise, just the calibration is allowed */ |
lypinator | 0:bb348c97df44 | 316 | else |
lypinator | 0:bb348c97df44 | 317 | { |
lypinator | 0:bb348c97df44 | 318 | /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ |
lypinator | 0:bb348c97df44 | 319 | __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); |
lypinator | 0:bb348c97df44 | 320 | } |
lypinator | 0:bb348c97df44 | 321 | } |
lypinator | 0:bb348c97df44 | 322 | else |
lypinator | 0:bb348c97df44 | 323 | { |
lypinator | 0:bb348c97df44 | 324 | /* Check the HSI State */ |
lypinator | 0:bb348c97df44 | 325 | if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF) |
lypinator | 0:bb348c97df44 | 326 | { |
lypinator | 0:bb348c97df44 | 327 | /* Enable the Internal High Speed oscillator (HSI). */ |
lypinator | 0:bb348c97df44 | 328 | __HAL_RCC_HSI_ENABLE(); |
lypinator | 0:bb348c97df44 | 329 | |
lypinator | 0:bb348c97df44 | 330 | /* Get Start Tick*/ |
lypinator | 0:bb348c97df44 | 331 | tickstart = HAL_GetTick(); |
lypinator | 0:bb348c97df44 | 332 | |
lypinator | 0:bb348c97df44 | 333 | /* Wait till HSI is ready */ |
lypinator | 0:bb348c97df44 | 334 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) |
lypinator | 0:bb348c97df44 | 335 | { |
lypinator | 0:bb348c97df44 | 336 | if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) |
lypinator | 0:bb348c97df44 | 337 | { |
lypinator | 0:bb348c97df44 | 338 | return HAL_TIMEOUT; |
lypinator | 0:bb348c97df44 | 339 | } |
lypinator | 0:bb348c97df44 | 340 | } |
lypinator | 0:bb348c97df44 | 341 | |
lypinator | 0:bb348c97df44 | 342 | /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */ |
lypinator | 0:bb348c97df44 | 343 | __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); |
lypinator | 0:bb348c97df44 | 344 | } |
lypinator | 0:bb348c97df44 | 345 | else |
lypinator | 0:bb348c97df44 | 346 | { |
lypinator | 0:bb348c97df44 | 347 | /* Disable the Internal High Speed oscillator (HSI). */ |
lypinator | 0:bb348c97df44 | 348 | __HAL_RCC_HSI_DISABLE(); |
lypinator | 0:bb348c97df44 | 349 | |
lypinator | 0:bb348c97df44 | 350 | /* Get Start Tick*/ |
lypinator | 0:bb348c97df44 | 351 | tickstart = HAL_GetTick(); |
lypinator | 0:bb348c97df44 | 352 | |
lypinator | 0:bb348c97df44 | 353 | /* Wait till HSI is ready */ |
lypinator | 0:bb348c97df44 | 354 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) |
lypinator | 0:bb348c97df44 | 355 | { |
lypinator | 0:bb348c97df44 | 356 | if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) |
lypinator | 0:bb348c97df44 | 357 | { |
lypinator | 0:bb348c97df44 | 358 | return HAL_TIMEOUT; |
lypinator | 0:bb348c97df44 | 359 | } |
lypinator | 0:bb348c97df44 | 360 | } |
lypinator | 0:bb348c97df44 | 361 | } |
lypinator | 0:bb348c97df44 | 362 | } |
lypinator | 0:bb348c97df44 | 363 | } |
lypinator | 0:bb348c97df44 | 364 | /*------------------------------ LSI Configuration -------------------------*/ |
lypinator | 0:bb348c97df44 | 365 | if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) |
lypinator | 0:bb348c97df44 | 366 | { |
lypinator | 0:bb348c97df44 | 367 | /* Check the parameters */ |
lypinator | 0:bb348c97df44 | 368 | assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); |
lypinator | 0:bb348c97df44 | 369 | |
lypinator | 0:bb348c97df44 | 370 | /* Check the LSI State */ |
lypinator | 0:bb348c97df44 | 371 | if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF) |
lypinator | 0:bb348c97df44 | 372 | { |
lypinator | 0:bb348c97df44 | 373 | /* Enable the Internal Low Speed oscillator (LSI). */ |
lypinator | 0:bb348c97df44 | 374 | __HAL_RCC_LSI_ENABLE(); |
lypinator | 0:bb348c97df44 | 375 | |
lypinator | 0:bb348c97df44 | 376 | /* Get Start Tick*/ |
lypinator | 0:bb348c97df44 | 377 | tickstart = HAL_GetTick(); |
lypinator | 0:bb348c97df44 | 378 | |
lypinator | 0:bb348c97df44 | 379 | /* Wait till LSI is ready */ |
lypinator | 0:bb348c97df44 | 380 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) |
lypinator | 0:bb348c97df44 | 381 | { |
lypinator | 0:bb348c97df44 | 382 | if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) |
lypinator | 0:bb348c97df44 | 383 | { |
lypinator | 0:bb348c97df44 | 384 | return HAL_TIMEOUT; |
lypinator | 0:bb348c97df44 | 385 | } |
lypinator | 0:bb348c97df44 | 386 | } |
lypinator | 0:bb348c97df44 | 387 | } |
lypinator | 0:bb348c97df44 | 388 | else |
lypinator | 0:bb348c97df44 | 389 | { |
lypinator | 0:bb348c97df44 | 390 | /* Disable the Internal Low Speed oscillator (LSI). */ |
lypinator | 0:bb348c97df44 | 391 | __HAL_RCC_LSI_DISABLE(); |
lypinator | 0:bb348c97df44 | 392 | |
lypinator | 0:bb348c97df44 | 393 | /* Get Start Tick */ |
lypinator | 0:bb348c97df44 | 394 | tickstart = HAL_GetTick(); |
lypinator | 0:bb348c97df44 | 395 | |
lypinator | 0:bb348c97df44 | 396 | /* Wait till LSI is ready */ |
lypinator | 0:bb348c97df44 | 397 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) |
lypinator | 0:bb348c97df44 | 398 | { |
lypinator | 0:bb348c97df44 | 399 | if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) |
lypinator | 0:bb348c97df44 | 400 | { |
lypinator | 0:bb348c97df44 | 401 | return HAL_TIMEOUT; |
lypinator | 0:bb348c97df44 | 402 | } |
lypinator | 0:bb348c97df44 | 403 | } |
lypinator | 0:bb348c97df44 | 404 | } |
lypinator | 0:bb348c97df44 | 405 | } |
lypinator | 0:bb348c97df44 | 406 | /*------------------------------ LSE Configuration -------------------------*/ |
lypinator | 0:bb348c97df44 | 407 | if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) |
lypinator | 0:bb348c97df44 | 408 | { |
lypinator | 0:bb348c97df44 | 409 | FlagStatus pwrclkchanged = RESET; |
lypinator | 0:bb348c97df44 | 410 | |
lypinator | 0:bb348c97df44 | 411 | /* Check the parameters */ |
lypinator | 0:bb348c97df44 | 412 | assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); |
lypinator | 0:bb348c97df44 | 413 | |
lypinator | 0:bb348c97df44 | 414 | /* Update LSE configuration in Backup Domain control register */ |
lypinator | 0:bb348c97df44 | 415 | /* Requires to enable write access to Backup Domain of necessary */ |
lypinator | 0:bb348c97df44 | 416 | if(__HAL_RCC_PWR_IS_CLK_DISABLED()) |
lypinator | 0:bb348c97df44 | 417 | { |
lypinator | 0:bb348c97df44 | 418 | __HAL_RCC_PWR_CLK_ENABLE(); |
lypinator | 0:bb348c97df44 | 419 | pwrclkchanged = SET; |
lypinator | 0:bb348c97df44 | 420 | } |
lypinator | 0:bb348c97df44 | 421 | |
lypinator | 0:bb348c97df44 | 422 | if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) |
lypinator | 0:bb348c97df44 | 423 | { |
lypinator | 0:bb348c97df44 | 424 | /* Enable write access to Backup domain */ |
lypinator | 0:bb348c97df44 | 425 | SET_BIT(PWR->CR, PWR_CR_DBP); |
lypinator | 0:bb348c97df44 | 426 | |
lypinator | 0:bb348c97df44 | 427 | /* Wait for Backup domain Write protection disable */ |
lypinator | 0:bb348c97df44 | 428 | tickstart = HAL_GetTick(); |
lypinator | 0:bb348c97df44 | 429 | |
lypinator | 0:bb348c97df44 | 430 | while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) |
lypinator | 0:bb348c97df44 | 431 | { |
lypinator | 0:bb348c97df44 | 432 | if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) |
lypinator | 0:bb348c97df44 | 433 | { |
lypinator | 0:bb348c97df44 | 434 | return HAL_TIMEOUT; |
lypinator | 0:bb348c97df44 | 435 | } |
lypinator | 0:bb348c97df44 | 436 | } |
lypinator | 0:bb348c97df44 | 437 | } |
lypinator | 0:bb348c97df44 | 438 | |
lypinator | 0:bb348c97df44 | 439 | /* Set the new LSE configuration -----------------------------------------*/ |
lypinator | 0:bb348c97df44 | 440 | __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); |
lypinator | 0:bb348c97df44 | 441 | /* Check the LSE State */ |
lypinator | 0:bb348c97df44 | 442 | if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) |
lypinator | 0:bb348c97df44 | 443 | { |
lypinator | 0:bb348c97df44 | 444 | /* Get Start Tick*/ |
lypinator | 0:bb348c97df44 | 445 | tickstart = HAL_GetTick(); |
lypinator | 0:bb348c97df44 | 446 | |
lypinator | 0:bb348c97df44 | 447 | /* Wait till LSE is ready */ |
lypinator | 0:bb348c97df44 | 448 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) |
lypinator | 0:bb348c97df44 | 449 | { |
lypinator | 0:bb348c97df44 | 450 | if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) |
lypinator | 0:bb348c97df44 | 451 | { |
lypinator | 0:bb348c97df44 | 452 | return HAL_TIMEOUT; |
lypinator | 0:bb348c97df44 | 453 | } |
lypinator | 0:bb348c97df44 | 454 | } |
lypinator | 0:bb348c97df44 | 455 | } |
lypinator | 0:bb348c97df44 | 456 | else |
lypinator | 0:bb348c97df44 | 457 | { |
lypinator | 0:bb348c97df44 | 458 | /* Get Start Tick */ |
lypinator | 0:bb348c97df44 | 459 | tickstart = HAL_GetTick(); |
lypinator | 0:bb348c97df44 | 460 | |
lypinator | 0:bb348c97df44 | 461 | /* Wait till LSE is ready */ |
lypinator | 0:bb348c97df44 | 462 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) |
lypinator | 0:bb348c97df44 | 463 | { |
lypinator | 0:bb348c97df44 | 464 | if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) |
lypinator | 0:bb348c97df44 | 465 | { |
lypinator | 0:bb348c97df44 | 466 | return HAL_TIMEOUT; |
lypinator | 0:bb348c97df44 | 467 | } |
lypinator | 0:bb348c97df44 | 468 | } |
lypinator | 0:bb348c97df44 | 469 | } |
lypinator | 0:bb348c97df44 | 470 | |
lypinator | 0:bb348c97df44 | 471 | /* Restore clock configuration if changed */ |
lypinator | 0:bb348c97df44 | 472 | if(pwrclkchanged == SET) |
lypinator | 0:bb348c97df44 | 473 | { |
lypinator | 0:bb348c97df44 | 474 | __HAL_RCC_PWR_CLK_DISABLE(); |
lypinator | 0:bb348c97df44 | 475 | } |
lypinator | 0:bb348c97df44 | 476 | } |
lypinator | 0:bb348c97df44 | 477 | /*-------------------------------- PLL Configuration -----------------------*/ |
lypinator | 0:bb348c97df44 | 478 | /* Check the parameters */ |
lypinator | 0:bb348c97df44 | 479 | assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); |
lypinator | 0:bb348c97df44 | 480 | if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) |
lypinator | 0:bb348c97df44 | 481 | { |
lypinator | 0:bb348c97df44 | 482 | /* Check if the PLL is used as system clock or not */ |
lypinator | 0:bb348c97df44 | 483 | if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) |
lypinator | 0:bb348c97df44 | 484 | { |
lypinator | 0:bb348c97df44 | 485 | if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) |
lypinator | 0:bb348c97df44 | 486 | { |
lypinator | 0:bb348c97df44 | 487 | /* Check the parameters */ |
lypinator | 0:bb348c97df44 | 488 | assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); |
lypinator | 0:bb348c97df44 | 489 | assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); |
lypinator | 0:bb348c97df44 | 490 | assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); |
lypinator | 0:bb348c97df44 | 491 | assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); |
lypinator | 0:bb348c97df44 | 492 | assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); |
lypinator | 0:bb348c97df44 | 493 | |
lypinator | 0:bb348c97df44 | 494 | /* Disable the main PLL. */ |
lypinator | 0:bb348c97df44 | 495 | __HAL_RCC_PLL_DISABLE(); |
lypinator | 0:bb348c97df44 | 496 | |
lypinator | 0:bb348c97df44 | 497 | /* Get Start Tick */ |
lypinator | 0:bb348c97df44 | 498 | tickstart = HAL_GetTick(); |
lypinator | 0:bb348c97df44 | 499 | |
lypinator | 0:bb348c97df44 | 500 | /* Wait till PLL is ready */ |
lypinator | 0:bb348c97df44 | 501 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) |
lypinator | 0:bb348c97df44 | 502 | { |
lypinator | 0:bb348c97df44 | 503 | if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) |
lypinator | 0:bb348c97df44 | 504 | { |
lypinator | 0:bb348c97df44 | 505 | return HAL_TIMEOUT; |
lypinator | 0:bb348c97df44 | 506 | } |
lypinator | 0:bb348c97df44 | 507 | } |
lypinator | 0:bb348c97df44 | 508 | |
lypinator | 0:bb348c97df44 | 509 | /* Configure the main PLL clock source, multiplication and division factors. */ |
lypinator | 0:bb348c97df44 | 510 | WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \ |
lypinator | 0:bb348c97df44 | 511 | RCC_OscInitStruct->PLL.PLLM | \ |
lypinator | 0:bb348c97df44 | 512 | (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \ |
lypinator | 0:bb348c97df44 | 513 | (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \ |
lypinator | 0:bb348c97df44 | 514 | (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))); |
lypinator | 0:bb348c97df44 | 515 | /* Enable the main PLL. */ |
lypinator | 0:bb348c97df44 | 516 | __HAL_RCC_PLL_ENABLE(); |
lypinator | 0:bb348c97df44 | 517 | |
lypinator | 0:bb348c97df44 | 518 | /* Get Start Tick */ |
lypinator | 0:bb348c97df44 | 519 | tickstart = HAL_GetTick(); |
lypinator | 0:bb348c97df44 | 520 | |
lypinator | 0:bb348c97df44 | 521 | /* Wait till PLL is ready */ |
lypinator | 0:bb348c97df44 | 522 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) |
lypinator | 0:bb348c97df44 | 523 | { |
lypinator | 0:bb348c97df44 | 524 | if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) |
lypinator | 0:bb348c97df44 | 525 | { |
lypinator | 0:bb348c97df44 | 526 | return HAL_TIMEOUT; |
lypinator | 0:bb348c97df44 | 527 | } |
lypinator | 0:bb348c97df44 | 528 | } |
lypinator | 0:bb348c97df44 | 529 | } |
lypinator | 0:bb348c97df44 | 530 | else |
lypinator | 0:bb348c97df44 | 531 | { |
lypinator | 0:bb348c97df44 | 532 | /* Disable the main PLL. */ |
lypinator | 0:bb348c97df44 | 533 | __HAL_RCC_PLL_DISABLE(); |
lypinator | 0:bb348c97df44 | 534 | |
lypinator | 0:bb348c97df44 | 535 | /* Get Start Tick */ |
lypinator | 0:bb348c97df44 | 536 | tickstart = HAL_GetTick(); |
lypinator | 0:bb348c97df44 | 537 | |
lypinator | 0:bb348c97df44 | 538 | /* Wait till PLL is ready */ |
lypinator | 0:bb348c97df44 | 539 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) |
lypinator | 0:bb348c97df44 | 540 | { |
lypinator | 0:bb348c97df44 | 541 | if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) |
lypinator | 0:bb348c97df44 | 542 | { |
lypinator | 0:bb348c97df44 | 543 | return HAL_TIMEOUT; |
lypinator | 0:bb348c97df44 | 544 | } |
lypinator | 0:bb348c97df44 | 545 | } |
lypinator | 0:bb348c97df44 | 546 | } |
lypinator | 0:bb348c97df44 | 547 | } |
lypinator | 0:bb348c97df44 | 548 | else |
lypinator | 0:bb348c97df44 | 549 | { |
lypinator | 0:bb348c97df44 | 550 | return HAL_ERROR; |
lypinator | 0:bb348c97df44 | 551 | } |
lypinator | 0:bb348c97df44 | 552 | } |
lypinator | 0:bb348c97df44 | 553 | return HAL_OK; |
lypinator | 0:bb348c97df44 | 554 | } |
lypinator | 0:bb348c97df44 | 555 | |
lypinator | 0:bb348c97df44 | 556 | /** |
lypinator | 0:bb348c97df44 | 557 | * @brief Initializes the CPU, AHB and APB busses clocks according to the specified |
lypinator | 0:bb348c97df44 | 558 | * parameters in the RCC_ClkInitStruct. |
lypinator | 0:bb348c97df44 | 559 | * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that |
lypinator | 0:bb348c97df44 | 560 | * contains the configuration information for the RCC peripheral. |
lypinator | 0:bb348c97df44 | 561 | * @param FLatency FLASH Latency, this parameter depend on device selected |
lypinator | 0:bb348c97df44 | 562 | * |
lypinator | 0:bb348c97df44 | 563 | * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency |
lypinator | 0:bb348c97df44 | 564 | * and updated by HAL_RCC_GetHCLKFreq() function called within this function |
lypinator | 0:bb348c97df44 | 565 | * |
lypinator | 0:bb348c97df44 | 566 | * @note The HSI is used (enabled by hardware) as system clock source after |
lypinator | 0:bb348c97df44 | 567 | * startup from Reset, wake-up from STOP and STANDBY mode, or in case |
lypinator | 0:bb348c97df44 | 568 | * of failure of the HSE used directly or indirectly as system clock |
lypinator | 0:bb348c97df44 | 569 | * (if the Clock Security System CSS is enabled). |
lypinator | 0:bb348c97df44 | 570 | * |
lypinator | 0:bb348c97df44 | 571 | * @note A switch from one clock source to another occurs only if the target |
lypinator | 0:bb348c97df44 | 572 | * clock source is ready (clock stable after startup delay or PLL locked). |
lypinator | 0:bb348c97df44 | 573 | * If a clock source which is not yet ready is selected, the switch will |
lypinator | 0:bb348c97df44 | 574 | * occur when the clock source will be ready. |
lypinator | 0:bb348c97df44 | 575 | * |
lypinator | 0:bb348c97df44 | 576 | * @note Depending on the device voltage range, the software has to set correctly |
lypinator | 0:bb348c97df44 | 577 | * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency |
lypinator | 0:bb348c97df44 | 578 | * (for more details refer to section above "Initialization/de-initialization functions") |
lypinator | 0:bb348c97df44 | 579 | * @retval None |
lypinator | 0:bb348c97df44 | 580 | */ |
lypinator | 0:bb348c97df44 | 581 | HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) |
lypinator | 0:bb348c97df44 | 582 | { |
lypinator | 0:bb348c97df44 | 583 | uint32_t tickstart; |
lypinator | 0:bb348c97df44 | 584 | |
lypinator | 0:bb348c97df44 | 585 | /* Check Null pointer */ |
lypinator | 0:bb348c97df44 | 586 | if(RCC_ClkInitStruct == NULL) |
lypinator | 0:bb348c97df44 | 587 | { |
lypinator | 0:bb348c97df44 | 588 | return HAL_ERROR; |
lypinator | 0:bb348c97df44 | 589 | } |
lypinator | 0:bb348c97df44 | 590 | |
lypinator | 0:bb348c97df44 | 591 | /* Check the parameters */ |
lypinator | 0:bb348c97df44 | 592 | assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); |
lypinator | 0:bb348c97df44 | 593 | assert_param(IS_FLASH_LATENCY(FLatency)); |
lypinator | 0:bb348c97df44 | 594 | |
lypinator | 0:bb348c97df44 | 595 | /* To correctly read data from FLASH memory, the number of wait states (LATENCY) |
lypinator | 0:bb348c97df44 | 596 | must be correctly programmed according to the frequency of the CPU clock |
lypinator | 0:bb348c97df44 | 597 | (HCLK) and the supply voltage of the device. */ |
lypinator | 0:bb348c97df44 | 598 | |
lypinator | 0:bb348c97df44 | 599 | /* Increasing the number of wait states because of higher CPU frequency */ |
lypinator | 0:bb348c97df44 | 600 | if(FLatency > __HAL_FLASH_GET_LATENCY()) |
lypinator | 0:bb348c97df44 | 601 | { |
lypinator | 0:bb348c97df44 | 602 | /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ |
lypinator | 0:bb348c97df44 | 603 | __HAL_FLASH_SET_LATENCY(FLatency); |
lypinator | 0:bb348c97df44 | 604 | |
lypinator | 0:bb348c97df44 | 605 | /* Check that the new number of wait states is taken into account to access the Flash |
lypinator | 0:bb348c97df44 | 606 | memory by reading the FLASH_ACR register */ |
lypinator | 0:bb348c97df44 | 607 | if(__HAL_FLASH_GET_LATENCY() != FLatency) |
lypinator | 0:bb348c97df44 | 608 | { |
lypinator | 0:bb348c97df44 | 609 | return HAL_ERROR; |
lypinator | 0:bb348c97df44 | 610 | } |
lypinator | 0:bb348c97df44 | 611 | } |
lypinator | 0:bb348c97df44 | 612 | |
lypinator | 0:bb348c97df44 | 613 | /*-------------------------- HCLK Configuration --------------------------*/ |
lypinator | 0:bb348c97df44 | 614 | if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) |
lypinator | 0:bb348c97df44 | 615 | { |
lypinator | 0:bb348c97df44 | 616 | /* Set the highest APBx dividers in order to ensure that we do not go through |
lypinator | 0:bb348c97df44 | 617 | a non-spec phase whatever we decrease or increase HCLK. */ |
lypinator | 0:bb348c97df44 | 618 | if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) |
lypinator | 0:bb348c97df44 | 619 | { |
lypinator | 0:bb348c97df44 | 620 | MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); |
lypinator | 0:bb348c97df44 | 621 | } |
lypinator | 0:bb348c97df44 | 622 | |
lypinator | 0:bb348c97df44 | 623 | if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) |
lypinator | 0:bb348c97df44 | 624 | { |
lypinator | 0:bb348c97df44 | 625 | MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); |
lypinator | 0:bb348c97df44 | 626 | } |
lypinator | 0:bb348c97df44 | 627 | |
lypinator | 0:bb348c97df44 | 628 | assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); |
lypinator | 0:bb348c97df44 | 629 | MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); |
lypinator | 0:bb348c97df44 | 630 | } |
lypinator | 0:bb348c97df44 | 631 | |
lypinator | 0:bb348c97df44 | 632 | /*------------------------- SYSCLK Configuration ---------------------------*/ |
lypinator | 0:bb348c97df44 | 633 | if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) |
lypinator | 0:bb348c97df44 | 634 | { |
lypinator | 0:bb348c97df44 | 635 | assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); |
lypinator | 0:bb348c97df44 | 636 | |
lypinator | 0:bb348c97df44 | 637 | /* HSE is selected as System Clock Source */ |
lypinator | 0:bb348c97df44 | 638 | if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) |
lypinator | 0:bb348c97df44 | 639 | { |
lypinator | 0:bb348c97df44 | 640 | /* Check the HSE ready flag */ |
lypinator | 0:bb348c97df44 | 641 | if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) |
lypinator | 0:bb348c97df44 | 642 | { |
lypinator | 0:bb348c97df44 | 643 | return HAL_ERROR; |
lypinator | 0:bb348c97df44 | 644 | } |
lypinator | 0:bb348c97df44 | 645 | } |
lypinator | 0:bb348c97df44 | 646 | /* PLL is selected as System Clock Source */ |
lypinator | 0:bb348c97df44 | 647 | else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || |
lypinator | 0:bb348c97df44 | 648 | (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)) |
lypinator | 0:bb348c97df44 | 649 | { |
lypinator | 0:bb348c97df44 | 650 | /* Check the PLL ready flag */ |
lypinator | 0:bb348c97df44 | 651 | if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) |
lypinator | 0:bb348c97df44 | 652 | { |
lypinator | 0:bb348c97df44 | 653 | return HAL_ERROR; |
lypinator | 0:bb348c97df44 | 654 | } |
lypinator | 0:bb348c97df44 | 655 | } |
lypinator | 0:bb348c97df44 | 656 | /* HSI is selected as System Clock Source */ |
lypinator | 0:bb348c97df44 | 657 | else |
lypinator | 0:bb348c97df44 | 658 | { |
lypinator | 0:bb348c97df44 | 659 | /* Check the HSI ready flag */ |
lypinator | 0:bb348c97df44 | 660 | if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) |
lypinator | 0:bb348c97df44 | 661 | { |
lypinator | 0:bb348c97df44 | 662 | return HAL_ERROR; |
lypinator | 0:bb348c97df44 | 663 | } |
lypinator | 0:bb348c97df44 | 664 | } |
lypinator | 0:bb348c97df44 | 665 | |
lypinator | 0:bb348c97df44 | 666 | __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); |
lypinator | 0:bb348c97df44 | 667 | |
lypinator | 0:bb348c97df44 | 668 | /* Get Start Tick */ |
lypinator | 0:bb348c97df44 | 669 | tickstart = HAL_GetTick(); |
lypinator | 0:bb348c97df44 | 670 | |
lypinator | 0:bb348c97df44 | 671 | while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) |
lypinator | 0:bb348c97df44 | 672 | { |
lypinator | 0:bb348c97df44 | 673 | if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) |
lypinator | 0:bb348c97df44 | 674 | { |
lypinator | 0:bb348c97df44 | 675 | return HAL_TIMEOUT; |
lypinator | 0:bb348c97df44 | 676 | } |
lypinator | 0:bb348c97df44 | 677 | } |
lypinator | 0:bb348c97df44 | 678 | } |
lypinator | 0:bb348c97df44 | 679 | |
lypinator | 0:bb348c97df44 | 680 | /* Decreasing the number of wait states because of lower CPU frequency */ |
lypinator | 0:bb348c97df44 | 681 | if(FLatency < __HAL_FLASH_GET_LATENCY()) |
lypinator | 0:bb348c97df44 | 682 | { |
lypinator | 0:bb348c97df44 | 683 | /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ |
lypinator | 0:bb348c97df44 | 684 | __HAL_FLASH_SET_LATENCY(FLatency); |
lypinator | 0:bb348c97df44 | 685 | |
lypinator | 0:bb348c97df44 | 686 | /* Check that the new number of wait states is taken into account to access the Flash |
lypinator | 0:bb348c97df44 | 687 | memory by reading the FLASH_ACR register */ |
lypinator | 0:bb348c97df44 | 688 | if(__HAL_FLASH_GET_LATENCY() != FLatency) |
lypinator | 0:bb348c97df44 | 689 | { |
lypinator | 0:bb348c97df44 | 690 | return HAL_ERROR; |
lypinator | 0:bb348c97df44 | 691 | } |
lypinator | 0:bb348c97df44 | 692 | } |
lypinator | 0:bb348c97df44 | 693 | |
lypinator | 0:bb348c97df44 | 694 | /*-------------------------- PCLK1 Configuration ---------------------------*/ |
lypinator | 0:bb348c97df44 | 695 | if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) |
lypinator | 0:bb348c97df44 | 696 | { |
lypinator | 0:bb348c97df44 | 697 | assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); |
lypinator | 0:bb348c97df44 | 698 | MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); |
lypinator | 0:bb348c97df44 | 699 | } |
lypinator | 0:bb348c97df44 | 700 | |
lypinator | 0:bb348c97df44 | 701 | /*-------------------------- PCLK2 Configuration ---------------------------*/ |
lypinator | 0:bb348c97df44 | 702 | if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) |
lypinator | 0:bb348c97df44 | 703 | { |
lypinator | 0:bb348c97df44 | 704 | assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); |
lypinator | 0:bb348c97df44 | 705 | MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); |
lypinator | 0:bb348c97df44 | 706 | } |
lypinator | 0:bb348c97df44 | 707 | |
lypinator | 0:bb348c97df44 | 708 | /* Update the SystemCoreClock global variable */ |
lypinator | 0:bb348c97df44 | 709 | SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; |
lypinator | 0:bb348c97df44 | 710 | |
lypinator | 0:bb348c97df44 | 711 | /* Configure the source of time base considering new system clocks settings */ |
lypinator | 0:bb348c97df44 | 712 | HAL_InitTick (TICK_INT_PRIORITY); |
lypinator | 0:bb348c97df44 | 713 | |
lypinator | 0:bb348c97df44 | 714 | return HAL_OK; |
lypinator | 0:bb348c97df44 | 715 | } |
lypinator | 0:bb348c97df44 | 716 | |
lypinator | 0:bb348c97df44 | 717 | /** |
lypinator | 0:bb348c97df44 | 718 | * @} |
lypinator | 0:bb348c97df44 | 719 | */ |
lypinator | 0:bb348c97df44 | 720 | |
lypinator | 0:bb348c97df44 | 721 | /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions |
lypinator | 0:bb348c97df44 | 722 | * @brief RCC clocks control functions |
lypinator | 0:bb348c97df44 | 723 | * |
lypinator | 0:bb348c97df44 | 724 | @verbatim |
lypinator | 0:bb348c97df44 | 725 | =============================================================================== |
lypinator | 0:bb348c97df44 | 726 | ##### Peripheral Control functions ##### |
lypinator | 0:bb348c97df44 | 727 | =============================================================================== |
lypinator | 0:bb348c97df44 | 728 | [..] |
lypinator | 0:bb348c97df44 | 729 | This subsection provides a set of functions allowing to control the RCC Clocks |
lypinator | 0:bb348c97df44 | 730 | frequencies. |
lypinator | 0:bb348c97df44 | 731 | |
lypinator | 0:bb348c97df44 | 732 | @endverbatim |
lypinator | 0:bb348c97df44 | 733 | * @{ |
lypinator | 0:bb348c97df44 | 734 | */ |
lypinator | 0:bb348c97df44 | 735 | |
lypinator | 0:bb348c97df44 | 736 | /** |
lypinator | 0:bb348c97df44 | 737 | * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9). |
lypinator | 0:bb348c97df44 | 738 | * @note PA8/PC9 should be configured in alternate function mode. |
lypinator | 0:bb348c97df44 | 739 | * @param RCC_MCOx specifies the output direction for the clock source. |
lypinator | 0:bb348c97df44 | 740 | * This parameter can be one of the following values: |
lypinator | 0:bb348c97df44 | 741 | * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8). |
lypinator | 0:bb348c97df44 | 742 | * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9). |
lypinator | 0:bb348c97df44 | 743 | * @param RCC_MCOSource specifies the clock source to output. |
lypinator | 0:bb348c97df44 | 744 | * This parameter can be one of the following values: |
lypinator | 0:bb348c97df44 | 745 | * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source |
lypinator | 0:bb348c97df44 | 746 | * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source |
lypinator | 0:bb348c97df44 | 747 | * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source |
lypinator | 0:bb348c97df44 | 748 | * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source |
lypinator | 0:bb348c97df44 | 749 | * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source |
lypinator | 0:bb348c97df44 | 750 | * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx |
lypinator | 0:bb348c97df44 | 751 | * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices |
lypinator | 0:bb348c97df44 | 752 | * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source |
lypinator | 0:bb348c97df44 | 753 | * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source |
lypinator | 0:bb348c97df44 | 754 | * @param RCC_MCODiv specifies the MCOx prescaler. |
lypinator | 0:bb348c97df44 | 755 | * This parameter can be one of the following values: |
lypinator | 0:bb348c97df44 | 756 | * @arg RCC_MCODIV_1: no division applied to MCOx clock |
lypinator | 0:bb348c97df44 | 757 | * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock |
lypinator | 0:bb348c97df44 | 758 | * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock |
lypinator | 0:bb348c97df44 | 759 | * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock |
lypinator | 0:bb348c97df44 | 760 | * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock |
lypinator | 0:bb348c97df44 | 761 | * @note For STM32F410Rx devices to output I2SCLK clock on MCO2 you should have |
lypinator | 0:bb348c97df44 | 762 | * at last one of the SPI clocks enabled (SPI1, SPI2 or SPI5). |
lypinator | 0:bb348c97df44 | 763 | * @retval None |
lypinator | 0:bb348c97df44 | 764 | */ |
lypinator | 0:bb348c97df44 | 765 | void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) |
lypinator | 0:bb348c97df44 | 766 | { |
lypinator | 0:bb348c97df44 | 767 | GPIO_InitTypeDef GPIO_InitStruct; |
lypinator | 0:bb348c97df44 | 768 | /* Check the parameters */ |
lypinator | 0:bb348c97df44 | 769 | assert_param(IS_RCC_MCO(RCC_MCOx)); |
lypinator | 0:bb348c97df44 | 770 | assert_param(IS_RCC_MCODIV(RCC_MCODiv)); |
lypinator | 0:bb348c97df44 | 771 | /* RCC_MCO1 */ |
lypinator | 0:bb348c97df44 | 772 | if(RCC_MCOx == RCC_MCO1) |
lypinator | 0:bb348c97df44 | 773 | { |
lypinator | 0:bb348c97df44 | 774 | assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); |
lypinator | 0:bb348c97df44 | 775 | |
lypinator | 0:bb348c97df44 | 776 | /* MCO1 Clock Enable */ |
lypinator | 0:bb348c97df44 | 777 | __MCO1_CLK_ENABLE(); |
lypinator | 0:bb348c97df44 | 778 | |
lypinator | 0:bb348c97df44 | 779 | /* Configure the MCO1 pin in alternate function mode */ |
lypinator | 0:bb348c97df44 | 780 | GPIO_InitStruct.Pin = MCO1_PIN; |
lypinator | 0:bb348c97df44 | 781 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; |
lypinator | 0:bb348c97df44 | 782 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; |
lypinator | 0:bb348c97df44 | 783 | GPIO_InitStruct.Pull = GPIO_NOPULL; |
lypinator | 0:bb348c97df44 | 784 | GPIO_InitStruct.Alternate = GPIO_AF0_MCO; |
lypinator | 0:bb348c97df44 | 785 | HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct); |
lypinator | 0:bb348c97df44 | 786 | |
lypinator | 0:bb348c97df44 | 787 | /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */ |
lypinator | 0:bb348c97df44 | 788 | MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv)); |
lypinator | 0:bb348c97df44 | 789 | |
lypinator | 0:bb348c97df44 | 790 | /* This RCC MCO1 enable feature is available only on STM32F410xx devices */ |
lypinator | 0:bb348c97df44 | 791 | #if defined(RCC_CFGR_MCO1EN) |
lypinator | 0:bb348c97df44 | 792 | __HAL_RCC_MCO1_ENABLE(); |
lypinator | 0:bb348c97df44 | 793 | #endif /* RCC_CFGR_MCO1EN */ |
lypinator | 0:bb348c97df44 | 794 | } |
lypinator | 0:bb348c97df44 | 795 | #if defined(RCC_CFGR_MCO2) |
lypinator | 0:bb348c97df44 | 796 | else |
lypinator | 0:bb348c97df44 | 797 | { |
lypinator | 0:bb348c97df44 | 798 | assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource)); |
lypinator | 0:bb348c97df44 | 799 | |
lypinator | 0:bb348c97df44 | 800 | /* MCO2 Clock Enable */ |
lypinator | 0:bb348c97df44 | 801 | __MCO2_CLK_ENABLE(); |
lypinator | 0:bb348c97df44 | 802 | |
lypinator | 0:bb348c97df44 | 803 | /* Configure the MCO2 pin in alternate function mode */ |
lypinator | 0:bb348c97df44 | 804 | GPIO_InitStruct.Pin = MCO2_PIN; |
lypinator | 0:bb348c97df44 | 805 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; |
lypinator | 0:bb348c97df44 | 806 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; |
lypinator | 0:bb348c97df44 | 807 | GPIO_InitStruct.Pull = GPIO_NOPULL; |
lypinator | 0:bb348c97df44 | 808 | GPIO_InitStruct.Alternate = GPIO_AF0_MCO; |
lypinator | 0:bb348c97df44 | 809 | HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct); |
lypinator | 0:bb348c97df44 | 810 | |
lypinator | 0:bb348c97df44 | 811 | /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */ |
lypinator | 0:bb348c97df44 | 812 | MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3U))); |
lypinator | 0:bb348c97df44 | 813 | |
lypinator | 0:bb348c97df44 | 814 | /* This RCC MCO2 enable feature is available only on STM32F410Rx devices */ |
lypinator | 0:bb348c97df44 | 815 | #if defined(RCC_CFGR_MCO2EN) |
lypinator | 0:bb348c97df44 | 816 | __HAL_RCC_MCO2_ENABLE(); |
lypinator | 0:bb348c97df44 | 817 | #endif /* RCC_CFGR_MCO2EN */ |
lypinator | 0:bb348c97df44 | 818 | } |
lypinator | 0:bb348c97df44 | 819 | #endif /* RCC_CFGR_MCO2 */ |
lypinator | 0:bb348c97df44 | 820 | } |
lypinator | 0:bb348c97df44 | 821 | |
lypinator | 0:bb348c97df44 | 822 | /** |
lypinator | 0:bb348c97df44 | 823 | * @brief Enables the Clock Security System. |
lypinator | 0:bb348c97df44 | 824 | * @note If a failure is detected on the HSE oscillator clock, this oscillator |
lypinator | 0:bb348c97df44 | 825 | * is automatically disabled and an interrupt is generated to inform the |
lypinator | 0:bb348c97df44 | 826 | * software about the failure (Clock Security System Interrupt, CSSI), |
lypinator | 0:bb348c97df44 | 827 | * allowing the MCU to perform rescue operations. The CSSI is linked to |
lypinator | 0:bb348c97df44 | 828 | * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. |
lypinator | 0:bb348c97df44 | 829 | * @retval None |
lypinator | 0:bb348c97df44 | 830 | */ |
lypinator | 0:bb348c97df44 | 831 | void HAL_RCC_EnableCSS(void) |
lypinator | 0:bb348c97df44 | 832 | { |
lypinator | 0:bb348c97df44 | 833 | *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE; |
lypinator | 0:bb348c97df44 | 834 | } |
lypinator | 0:bb348c97df44 | 835 | |
lypinator | 0:bb348c97df44 | 836 | /** |
lypinator | 0:bb348c97df44 | 837 | * @brief Disables the Clock Security System. |
lypinator | 0:bb348c97df44 | 838 | * @retval None |
lypinator | 0:bb348c97df44 | 839 | */ |
lypinator | 0:bb348c97df44 | 840 | void HAL_RCC_DisableCSS(void) |
lypinator | 0:bb348c97df44 | 841 | { |
lypinator | 0:bb348c97df44 | 842 | *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE; |
lypinator | 0:bb348c97df44 | 843 | } |
lypinator | 0:bb348c97df44 | 844 | |
lypinator | 0:bb348c97df44 | 845 | /** |
lypinator | 0:bb348c97df44 | 846 | * @brief Returns the SYSCLK frequency |
lypinator | 0:bb348c97df44 | 847 | * |
lypinator | 0:bb348c97df44 | 848 | * @note The system frequency computed by this function is not the real |
lypinator | 0:bb348c97df44 | 849 | * frequency in the chip. It is calculated based on the predefined |
lypinator | 0:bb348c97df44 | 850 | * constant and the selected clock source: |
lypinator | 0:bb348c97df44 | 851 | * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) |
lypinator | 0:bb348c97df44 | 852 | * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) |
lypinator | 0:bb348c97df44 | 853 | * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) |
lypinator | 0:bb348c97df44 | 854 | * or HSI_VALUE(*) multiplied/divided by the PLL factors. |
lypinator | 0:bb348c97df44 | 855 | * @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value |
lypinator | 0:bb348c97df44 | 856 | * 16 MHz) but the real value may vary depending on the variations |
lypinator | 0:bb348c97df44 | 857 | * in voltage and temperature. |
lypinator | 0:bb348c97df44 | 858 | * @note (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value |
lypinator | 0:bb348c97df44 | 859 | * 25 MHz), user has to ensure that HSE_VALUE is same as the real |
lypinator | 0:bb348c97df44 | 860 | * frequency of the crystal used. Otherwise, this function may |
lypinator | 0:bb348c97df44 | 861 | * have wrong result. |
lypinator | 0:bb348c97df44 | 862 | * |
lypinator | 0:bb348c97df44 | 863 | * @note The result of this function could be not correct when using fractional |
lypinator | 0:bb348c97df44 | 864 | * value for HSE crystal. |
lypinator | 0:bb348c97df44 | 865 | * |
lypinator | 0:bb348c97df44 | 866 | * @note This function can be used by the user application to compute the |
lypinator | 0:bb348c97df44 | 867 | * baudrate for the communication peripherals or configure other parameters. |
lypinator | 0:bb348c97df44 | 868 | * |
lypinator | 0:bb348c97df44 | 869 | * @note Each time SYSCLK changes, this function must be called to update the |
lypinator | 0:bb348c97df44 | 870 | * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. |
lypinator | 0:bb348c97df44 | 871 | * |
lypinator | 0:bb348c97df44 | 872 | * |
lypinator | 0:bb348c97df44 | 873 | * @retval SYSCLK frequency |
lypinator | 0:bb348c97df44 | 874 | */ |
lypinator | 0:bb348c97df44 | 875 | __weak uint32_t HAL_RCC_GetSysClockFreq(void) |
lypinator | 0:bb348c97df44 | 876 | { |
lypinator | 0:bb348c97df44 | 877 | uint32_t pllm = 0U, pllvco = 0U, pllp = 0U; |
lypinator | 0:bb348c97df44 | 878 | uint32_t sysclockfreq = 0U; |
lypinator | 0:bb348c97df44 | 879 | |
lypinator | 0:bb348c97df44 | 880 | /* Get SYSCLK source -------------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 881 | switch (RCC->CFGR & RCC_CFGR_SWS) |
lypinator | 0:bb348c97df44 | 882 | { |
lypinator | 0:bb348c97df44 | 883 | case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ |
lypinator | 0:bb348c97df44 | 884 | { |
lypinator | 0:bb348c97df44 | 885 | sysclockfreq = HSI_VALUE; |
lypinator | 0:bb348c97df44 | 886 | break; |
lypinator | 0:bb348c97df44 | 887 | } |
lypinator | 0:bb348c97df44 | 888 | case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ |
lypinator | 0:bb348c97df44 | 889 | { |
lypinator | 0:bb348c97df44 | 890 | sysclockfreq = HSE_VALUE; |
lypinator | 0:bb348c97df44 | 891 | break; |
lypinator | 0:bb348c97df44 | 892 | } |
lypinator | 0:bb348c97df44 | 893 | case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */ |
lypinator | 0:bb348c97df44 | 894 | { |
lypinator | 0:bb348c97df44 | 895 | /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN |
lypinator | 0:bb348c97df44 | 896 | SYSCLK = PLL_VCO / PLLP */ |
lypinator | 0:bb348c97df44 | 897 | pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; |
lypinator | 0:bb348c97df44 | 898 | if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) |
lypinator | 0:bb348c97df44 | 899 | { |
lypinator | 0:bb348c97df44 | 900 | /* HSE used as PLL clock source */ |
lypinator | 0:bb348c97df44 | 901 | pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); |
lypinator | 0:bb348c97df44 | 902 | } |
lypinator | 0:bb348c97df44 | 903 | else |
lypinator | 0:bb348c97df44 | 904 | { |
lypinator | 0:bb348c97df44 | 905 | /* HSI used as PLL clock source */ |
lypinator | 0:bb348c97df44 | 906 | pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); |
lypinator | 0:bb348c97df44 | 907 | } |
lypinator | 0:bb348c97df44 | 908 | pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U); |
lypinator | 0:bb348c97df44 | 909 | |
lypinator | 0:bb348c97df44 | 910 | sysclockfreq = pllvco/pllp; |
lypinator | 0:bb348c97df44 | 911 | break; |
lypinator | 0:bb348c97df44 | 912 | } |
lypinator | 0:bb348c97df44 | 913 | default: |
lypinator | 0:bb348c97df44 | 914 | { |
lypinator | 0:bb348c97df44 | 915 | sysclockfreq = HSI_VALUE; |
lypinator | 0:bb348c97df44 | 916 | break; |
lypinator | 0:bb348c97df44 | 917 | } |
lypinator | 0:bb348c97df44 | 918 | } |
lypinator | 0:bb348c97df44 | 919 | return sysclockfreq; |
lypinator | 0:bb348c97df44 | 920 | } |
lypinator | 0:bb348c97df44 | 921 | |
lypinator | 0:bb348c97df44 | 922 | /** |
lypinator | 0:bb348c97df44 | 923 | * @brief Returns the HCLK frequency |
lypinator | 0:bb348c97df44 | 924 | * @note Each time HCLK changes, this function must be called to update the |
lypinator | 0:bb348c97df44 | 925 | * right HCLK value. Otherwise, any configuration based on this function will be incorrect. |
lypinator | 0:bb348c97df44 | 926 | * |
lypinator | 0:bb348c97df44 | 927 | * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency |
lypinator | 0:bb348c97df44 | 928 | * and updated within this function |
lypinator | 0:bb348c97df44 | 929 | * @retval HCLK frequency |
lypinator | 0:bb348c97df44 | 930 | */ |
lypinator | 0:bb348c97df44 | 931 | uint32_t HAL_RCC_GetHCLKFreq(void) |
lypinator | 0:bb348c97df44 | 932 | { |
lypinator | 0:bb348c97df44 | 933 | return SystemCoreClock; |
lypinator | 0:bb348c97df44 | 934 | } |
lypinator | 0:bb348c97df44 | 935 | |
lypinator | 0:bb348c97df44 | 936 | /** |
lypinator | 0:bb348c97df44 | 937 | * @brief Returns the PCLK1 frequency |
lypinator | 0:bb348c97df44 | 938 | * @note Each time PCLK1 changes, this function must be called to update the |
lypinator | 0:bb348c97df44 | 939 | * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. |
lypinator | 0:bb348c97df44 | 940 | * @retval PCLK1 frequency |
lypinator | 0:bb348c97df44 | 941 | */ |
lypinator | 0:bb348c97df44 | 942 | uint32_t HAL_RCC_GetPCLK1Freq(void) |
lypinator | 0:bb348c97df44 | 943 | { |
lypinator | 0:bb348c97df44 | 944 | /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ |
lypinator | 0:bb348c97df44 | 945 | return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]); |
lypinator | 0:bb348c97df44 | 946 | } |
lypinator | 0:bb348c97df44 | 947 | |
lypinator | 0:bb348c97df44 | 948 | /** |
lypinator | 0:bb348c97df44 | 949 | * @brief Returns the PCLK2 frequency |
lypinator | 0:bb348c97df44 | 950 | * @note Each time PCLK2 changes, this function must be called to update the |
lypinator | 0:bb348c97df44 | 951 | * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. |
lypinator | 0:bb348c97df44 | 952 | * @retval PCLK2 frequency |
lypinator | 0:bb348c97df44 | 953 | */ |
lypinator | 0:bb348c97df44 | 954 | uint32_t HAL_RCC_GetPCLK2Freq(void) |
lypinator | 0:bb348c97df44 | 955 | { |
lypinator | 0:bb348c97df44 | 956 | /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ |
lypinator | 0:bb348c97df44 | 957 | return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]); |
lypinator | 0:bb348c97df44 | 958 | } |
lypinator | 0:bb348c97df44 | 959 | |
lypinator | 0:bb348c97df44 | 960 | /** |
lypinator | 0:bb348c97df44 | 961 | * @brief Configures the RCC_OscInitStruct according to the internal |
lypinator | 0:bb348c97df44 | 962 | * RCC configuration registers. |
lypinator | 0:bb348c97df44 | 963 | * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that |
lypinator | 0:bb348c97df44 | 964 | * will be configured. |
lypinator | 0:bb348c97df44 | 965 | * @retval None |
lypinator | 0:bb348c97df44 | 966 | */ |
lypinator | 0:bb348c97df44 | 967 | __weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) |
lypinator | 0:bb348c97df44 | 968 | { |
lypinator | 0:bb348c97df44 | 969 | /* Set all possible values for the Oscillator type parameter ---------------*/ |
lypinator | 0:bb348c97df44 | 970 | RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; |
lypinator | 0:bb348c97df44 | 971 | |
lypinator | 0:bb348c97df44 | 972 | /* Get the HSE configuration -----------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 973 | if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP) |
lypinator | 0:bb348c97df44 | 974 | { |
lypinator | 0:bb348c97df44 | 975 | RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; |
lypinator | 0:bb348c97df44 | 976 | } |
lypinator | 0:bb348c97df44 | 977 | else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON) |
lypinator | 0:bb348c97df44 | 978 | { |
lypinator | 0:bb348c97df44 | 979 | RCC_OscInitStruct->HSEState = RCC_HSE_ON; |
lypinator | 0:bb348c97df44 | 980 | } |
lypinator | 0:bb348c97df44 | 981 | else |
lypinator | 0:bb348c97df44 | 982 | { |
lypinator | 0:bb348c97df44 | 983 | RCC_OscInitStruct->HSEState = RCC_HSE_OFF; |
lypinator | 0:bb348c97df44 | 984 | } |
lypinator | 0:bb348c97df44 | 985 | |
lypinator | 0:bb348c97df44 | 986 | /* Get the HSI configuration -----------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 987 | if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION) |
lypinator | 0:bb348c97df44 | 988 | { |
lypinator | 0:bb348c97df44 | 989 | RCC_OscInitStruct->HSIState = RCC_HSI_ON; |
lypinator | 0:bb348c97df44 | 990 | } |
lypinator | 0:bb348c97df44 | 991 | else |
lypinator | 0:bb348c97df44 | 992 | { |
lypinator | 0:bb348c97df44 | 993 | RCC_OscInitStruct->HSIState = RCC_HSI_OFF; |
lypinator | 0:bb348c97df44 | 994 | } |
lypinator | 0:bb348c97df44 | 995 | |
lypinator | 0:bb348c97df44 | 996 | RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); |
lypinator | 0:bb348c97df44 | 997 | |
lypinator | 0:bb348c97df44 | 998 | /* Get the LSE configuration -----------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 999 | if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) |
lypinator | 0:bb348c97df44 | 1000 | { |
lypinator | 0:bb348c97df44 | 1001 | RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; |
lypinator | 0:bb348c97df44 | 1002 | } |
lypinator | 0:bb348c97df44 | 1003 | else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON) |
lypinator | 0:bb348c97df44 | 1004 | { |
lypinator | 0:bb348c97df44 | 1005 | RCC_OscInitStruct->LSEState = RCC_LSE_ON; |
lypinator | 0:bb348c97df44 | 1006 | } |
lypinator | 0:bb348c97df44 | 1007 | else |
lypinator | 0:bb348c97df44 | 1008 | { |
lypinator | 0:bb348c97df44 | 1009 | RCC_OscInitStruct->LSEState = RCC_LSE_OFF; |
lypinator | 0:bb348c97df44 | 1010 | } |
lypinator | 0:bb348c97df44 | 1011 | |
lypinator | 0:bb348c97df44 | 1012 | /* Get the LSI configuration -----------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 1013 | if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION) |
lypinator | 0:bb348c97df44 | 1014 | { |
lypinator | 0:bb348c97df44 | 1015 | RCC_OscInitStruct->LSIState = RCC_LSI_ON; |
lypinator | 0:bb348c97df44 | 1016 | } |
lypinator | 0:bb348c97df44 | 1017 | else |
lypinator | 0:bb348c97df44 | 1018 | { |
lypinator | 0:bb348c97df44 | 1019 | RCC_OscInitStruct->LSIState = RCC_LSI_OFF; |
lypinator | 0:bb348c97df44 | 1020 | } |
lypinator | 0:bb348c97df44 | 1021 | |
lypinator | 0:bb348c97df44 | 1022 | /* Get the PLL configuration -----------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 1023 | if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON) |
lypinator | 0:bb348c97df44 | 1024 | { |
lypinator | 0:bb348c97df44 | 1025 | RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; |
lypinator | 0:bb348c97df44 | 1026 | } |
lypinator | 0:bb348c97df44 | 1027 | else |
lypinator | 0:bb348c97df44 | 1028 | { |
lypinator | 0:bb348c97df44 | 1029 | RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; |
lypinator | 0:bb348c97df44 | 1030 | } |
lypinator | 0:bb348c97df44 | 1031 | RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); |
lypinator | 0:bb348c97df44 | 1032 | RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM); |
lypinator | 0:bb348c97df44 | 1033 | RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); |
lypinator | 0:bb348c97df44 | 1034 | RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> RCC_PLLCFGR_PLLP_Pos); |
lypinator | 0:bb348c97df44 | 1035 | RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos); |
lypinator | 0:bb348c97df44 | 1036 | } |
lypinator | 0:bb348c97df44 | 1037 | |
lypinator | 0:bb348c97df44 | 1038 | /** |
lypinator | 0:bb348c97df44 | 1039 | * @brief Configures the RCC_ClkInitStruct according to the internal |
lypinator | 0:bb348c97df44 | 1040 | * RCC configuration registers. |
lypinator | 0:bb348c97df44 | 1041 | * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that |
lypinator | 0:bb348c97df44 | 1042 | * will be configured. |
lypinator | 0:bb348c97df44 | 1043 | * @param pFLatency Pointer on the Flash Latency. |
lypinator | 0:bb348c97df44 | 1044 | * @retval None |
lypinator | 0:bb348c97df44 | 1045 | */ |
lypinator | 0:bb348c97df44 | 1046 | void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) |
lypinator | 0:bb348c97df44 | 1047 | { |
lypinator | 0:bb348c97df44 | 1048 | /* Set all possible values for the Clock type parameter --------------------*/ |
lypinator | 0:bb348c97df44 | 1049 | RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; |
lypinator | 0:bb348c97df44 | 1050 | |
lypinator | 0:bb348c97df44 | 1051 | /* Get the SYSCLK configuration --------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 1052 | RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); |
lypinator | 0:bb348c97df44 | 1053 | |
lypinator | 0:bb348c97df44 | 1054 | /* Get the HCLK configuration ----------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 1055 | RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); |
lypinator | 0:bb348c97df44 | 1056 | |
lypinator | 0:bb348c97df44 | 1057 | /* Get the APB1 configuration ----------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 1058 | RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); |
lypinator | 0:bb348c97df44 | 1059 | |
lypinator | 0:bb348c97df44 | 1060 | /* Get the APB2 configuration ----------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 1061 | RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U); |
lypinator | 0:bb348c97df44 | 1062 | |
lypinator | 0:bb348c97df44 | 1063 | /* Get the Flash Wait State (Latency) configuration ------------------------*/ |
lypinator | 0:bb348c97df44 | 1064 | *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); |
lypinator | 0:bb348c97df44 | 1065 | } |
lypinator | 0:bb348c97df44 | 1066 | |
lypinator | 0:bb348c97df44 | 1067 | /** |
lypinator | 0:bb348c97df44 | 1068 | * @brief This function handles the RCC CSS interrupt request. |
lypinator | 0:bb348c97df44 | 1069 | * @note This API should be called under the NMI_Handler(). |
lypinator | 0:bb348c97df44 | 1070 | * @retval None |
lypinator | 0:bb348c97df44 | 1071 | */ |
lypinator | 0:bb348c97df44 | 1072 | void HAL_RCC_NMI_IRQHandler(void) |
lypinator | 0:bb348c97df44 | 1073 | { |
lypinator | 0:bb348c97df44 | 1074 | /* Check RCC CSSF flag */ |
lypinator | 0:bb348c97df44 | 1075 | if(__HAL_RCC_GET_IT(RCC_IT_CSS)) |
lypinator | 0:bb348c97df44 | 1076 | { |
lypinator | 0:bb348c97df44 | 1077 | /* RCC Clock Security System interrupt user callback */ |
lypinator | 0:bb348c97df44 | 1078 | HAL_RCC_CSSCallback(); |
lypinator | 0:bb348c97df44 | 1079 | |
lypinator | 0:bb348c97df44 | 1080 | /* Clear RCC CSS pending bit */ |
lypinator | 0:bb348c97df44 | 1081 | __HAL_RCC_CLEAR_IT(RCC_IT_CSS); |
lypinator | 0:bb348c97df44 | 1082 | } |
lypinator | 0:bb348c97df44 | 1083 | } |
lypinator | 0:bb348c97df44 | 1084 | |
lypinator | 0:bb348c97df44 | 1085 | /** |
lypinator | 0:bb348c97df44 | 1086 | * @brief RCC Clock Security System interrupt callback |
lypinator | 0:bb348c97df44 | 1087 | * @retval None |
lypinator | 0:bb348c97df44 | 1088 | */ |
lypinator | 0:bb348c97df44 | 1089 | __weak void HAL_RCC_CSSCallback(void) |
lypinator | 0:bb348c97df44 | 1090 | { |
lypinator | 0:bb348c97df44 | 1091 | /* NOTE : This function Should not be modified, when the callback is needed, |
lypinator | 0:bb348c97df44 | 1092 | the HAL_RCC_CSSCallback could be implemented in the user file |
lypinator | 0:bb348c97df44 | 1093 | */ |
lypinator | 0:bb348c97df44 | 1094 | } |
lypinator | 0:bb348c97df44 | 1095 | |
lypinator | 0:bb348c97df44 | 1096 | /** |
lypinator | 0:bb348c97df44 | 1097 | * @} |
lypinator | 0:bb348c97df44 | 1098 | */ |
lypinator | 0:bb348c97df44 | 1099 | |
lypinator | 0:bb348c97df44 | 1100 | /** |
lypinator | 0:bb348c97df44 | 1101 | * @} |
lypinator | 0:bb348c97df44 | 1102 | */ |
lypinator | 0:bb348c97df44 | 1103 | |
lypinator | 0:bb348c97df44 | 1104 | #endif /* HAL_RCC_MODULE_ENABLED */ |
lypinator | 0:bb348c97df44 | 1105 | /** |
lypinator | 0:bb348c97df44 | 1106 | * @} |
lypinator | 0:bb348c97df44 | 1107 | */ |
lypinator | 0:bb348c97df44 | 1108 | |
lypinator | 0:bb348c97df44 | 1109 | /** |
lypinator | 0:bb348c97df44 | 1110 | * @} |
lypinator | 0:bb348c97df44 | 1111 | */ |
lypinator | 0:bb348c97df44 | 1112 | |
lypinator | 0:bb348c97df44 | 1113 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |