Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/system_clock.c@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lypinator 0:bb348c97df44 1 /* mbed Microcontroller Library
lypinator 0:bb348c97df44 2 * Copyright (c) 2006-2017 ARM Limited
lypinator 0:bb348c97df44 3 *
lypinator 0:bb348c97df44 4 * Licensed under the Apache License, Version 2.0 (the "License");
lypinator 0:bb348c97df44 5 * you may not use this file except in compliance with the License.
lypinator 0:bb348c97df44 6 * You may obtain a copy of the License at
lypinator 0:bb348c97df44 7 *
lypinator 0:bb348c97df44 8 * http://www.apache.org/licenses/LICENSE-2.0
lypinator 0:bb348c97df44 9 *
lypinator 0:bb348c97df44 10 * Unless required by applicable law or agreed to in writing, software
lypinator 0:bb348c97df44 11 * distributed under the License is distributed on an "AS IS" BASIS,
lypinator 0:bb348c97df44 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
lypinator 0:bb348c97df44 13 * See the License for the specific language governing permissions and
lypinator 0:bb348c97df44 14 * limitations under the License.
lypinator 0:bb348c97df44 15 */
lypinator 0:bb348c97df44 16
lypinator 0:bb348c97df44 17 /**
lypinator 0:bb348c97df44 18 * This file configures the system clock as follows:
lypinator 0:bb348c97df44 19 *--------------------------------------------------------------------------------------
lypinator 0:bb348c97df44 20 * System clock source | PLL_HSE_XTAL | PLL_HSE_XTAL
lypinator 0:bb348c97df44 21 * | (external 8 MHz clock) | (external 8 MHz clock)
lypinator 0:bb348c97df44 22 *--------------------------------------------------------------------------------------
lypinator 0:bb348c97df44 23 * SYSCLK(MHz) | 168 | 180
lypinator 0:bb348c97df44 24 *--------------------------------------------------------------------------------------
lypinator 0:bb348c97df44 25 * AHBCLK (MHz) | 168 | 180
lypinator 0:bb348c97df44 26 *--------------------------------------------------------------------------------------
lypinator 0:bb348c97df44 27 * APB1CLK (MHz) | 42 | 45
lypinator 0:bb348c97df44 28 *--------------------------------------------------------------------------------------
lypinator 0:bb348c97df44 29 * APB2CLK (MHz) | 84 | 90
lypinator 0:bb348c97df44 30 *--------------------------------------------------------------------------------------
lypinator 0:bb348c97df44 31 * USB capable (48 MHz precise clock) | YES | NO
lypinator 0:bb348c97df44 32 *--------------------------------------------------------------------------------------
lypinator 0:bb348c97df44 33 **/
lypinator 0:bb348c97df44 34
lypinator 0:bb348c97df44 35 #include "stm32f4xx.h"
lypinator 0:bb348c97df44 36 #include "nvic_addr.h"
lypinator 0:bb348c97df44 37
lypinator 0:bb348c97df44 38
lypinator 0:bb348c97df44 39 /* Select the SYSCLOCK to start with (0=OFF, 1=ON) */
lypinator 0:bb348c97df44 40 #define USE_SYSCLOCK_168 (1) /* Use external 8MHz xtal and sets SYSCLK to 168MHz */
lypinator 0:bb348c97df44 41 #define USE_SYSCLOCK_180 (0) /* Use external 8MHz xtal and sets SYSCLK to 180MHz */
lypinator 0:bb348c97df44 42
lypinator 0:bb348c97df44 43
lypinator 0:bb348c97df44 44 void SetSysClock(void);
lypinator 0:bb348c97df44 45
lypinator 0:bb348c97df44 46 /**
lypinator 0:bb348c97df44 47 * @brief Setup the microcontroller system
lypinator 0:bb348c97df44 48 * Initialize the FPU setting, vector table location and External memory
lypinator 0:bb348c97df44 49 * configuration.
lypinator 0:bb348c97df44 50 * @param None
lypinator 0:bb348c97df44 51 * @retval None
lypinator 0:bb348c97df44 52 */
lypinator 0:bb348c97df44 53 void SystemInit(void)
lypinator 0:bb348c97df44 54 {
lypinator 0:bb348c97df44 55 /* FPU settings ------------------------------------------------------------*/
lypinator 0:bb348c97df44 56 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
lypinator 0:bb348c97df44 57 SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
lypinator 0:bb348c97df44 58 #endif
lypinator 0:bb348c97df44 59 /* Reset the RCC clock configuration to the default reset state ------------*/
lypinator 0:bb348c97df44 60 /* Set HSION bit */
lypinator 0:bb348c97df44 61 RCC->CR |= (uint32_t)0x00000001;
lypinator 0:bb348c97df44 62
lypinator 0:bb348c97df44 63 /* Reset CFGR register */
lypinator 0:bb348c97df44 64 RCC->CFGR = 0x00000000;
lypinator 0:bb348c97df44 65
lypinator 0:bb348c97df44 66 /* Reset HSEON, CSSON and PLLON bits */
lypinator 0:bb348c97df44 67 RCC->CR &= (uint32_t)0xFEF6FFFF;
lypinator 0:bb348c97df44 68
lypinator 0:bb348c97df44 69 /* Reset PLLCFGR register */
lypinator 0:bb348c97df44 70 RCC->PLLCFGR = 0x24003010;
lypinator 0:bb348c97df44 71
lypinator 0:bb348c97df44 72 /* Reset HSEBYP bit */
lypinator 0:bb348c97df44 73 RCC->CR &= (uint32_t)0xFFFBFFFF;
lypinator 0:bb348c97df44 74
lypinator 0:bb348c97df44 75 /* Disable all interrupts */
lypinator 0:bb348c97df44 76 RCC->CIR = 0x00000000;
lypinator 0:bb348c97df44 77
lypinator 0:bb348c97df44 78 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
lypinator 0:bb348c97df44 79 SystemInit_ExtMemCtl();
lypinator 0:bb348c97df44 80 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
lypinator 0:bb348c97df44 81
lypinator 0:bb348c97df44 82 /* Configure the Vector Table location add offset address ------------------*/
lypinator 0:bb348c97df44 83 #ifdef VECT_TAB_SRAM
lypinator 0:bb348c97df44 84 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
lypinator 0:bb348c97df44 85 #else
lypinator 0:bb348c97df44 86 SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
lypinator 0:bb348c97df44 87 #endif
lypinator 0:bb348c97df44 88
lypinator 0:bb348c97df44 89 }
lypinator 0:bb348c97df44 90
lypinator 0:bb348c97df44 91
lypinator 0:bb348c97df44 92 /** System Clock Configuration
lypinator 0:bb348c97df44 93 */
lypinator 0:bb348c97df44 94 #if USE_SYSCLOCK_168 != 0
lypinator 0:bb348c97df44 95 /*
lypinator 0:bb348c97df44 96 * generated code by STM32CubeMX 4.4.0 for board 32F429Discovery
lypinator 0:bb348c97df44 97 * and SYSCLK=168MHZ
lypinator 0:bb348c97df44 98 */
lypinator 0:bb348c97df44 99 void SetSysClock(void)
lypinator 0:bb348c97df44 100 {
lypinator 0:bb348c97df44 101
lypinator 0:bb348c97df44 102 RCC_OscInitTypeDef RCC_OscInitStruct;
lypinator 0:bb348c97df44 103 RCC_ClkInitTypeDef RCC_ClkInitStruct;
lypinator 0:bb348c97df44 104
lypinator 0:bb348c97df44 105 __HAL_RCC_PWR_CLK_ENABLE();
lypinator 0:bb348c97df44 106
lypinator 0:bb348c97df44 107 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
lypinator 0:bb348c97df44 108
lypinator 0:bb348c97df44 109 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
lypinator 0:bb348c97df44 110 RCC_OscInitStruct.HSEState = RCC_HSE_ON;
lypinator 0:bb348c97df44 111 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
lypinator 0:bb348c97df44 112 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
lypinator 0:bb348c97df44 113 RCC_OscInitStruct.PLL.PLLM = 24;
lypinator 0:bb348c97df44 114 RCC_OscInitStruct.PLL.PLLN = 336;
lypinator 0:bb348c97df44 115 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
lypinator 0:bb348c97df44 116 RCC_OscInitStruct.PLL.PLLQ = 7;
lypinator 0:bb348c97df44 117 HAL_RCC_OscConfig(&RCC_OscInitStruct);
lypinator 0:bb348c97df44 118
lypinator 0:bb348c97df44 119 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1
lypinator 0:bb348c97df44 120 | RCC_CLOCKTYPE_PCLK2;
lypinator 0:bb348c97df44 121 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
lypinator 0:bb348c97df44 122 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
lypinator 0:bb348c97df44 123 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
lypinator 0:bb348c97df44 124 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
lypinator 0:bb348c97df44 125 HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
lypinator 0:bb348c97df44 126
lypinator 0:bb348c97df44 127 // HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_3);
lypinator 0:bb348c97df44 128
lypinator 0:bb348c97df44 129
lypinator 0:bb348c97df44 130 }
lypinator 0:bb348c97df44 131
lypinator 0:bb348c97df44 132 #elif USE_SYSCLOCK_180 != 0
lypinator 0:bb348c97df44 133 /*
lypinator 0:bb348c97df44 134 * generated code by STM32CubeMX 4.4.0 for board 32F429Discovery
lypinator 0:bb348c97df44 135 * and SYSCLK=180MHZ
lypinator 0:bb348c97df44 136 */
lypinator 0:bb348c97df44 137 void SetSysClock(void)
lypinator 0:bb348c97df44 138 {
lypinator 0:bb348c97df44 139
lypinator 0:bb348c97df44 140 RCC_OscInitTypeDef RCC_OscInitStruct;
lypinator 0:bb348c97df44 141 RCC_ClkInitTypeDef RCC_ClkInitStruct;
lypinator 0:bb348c97df44 142
lypinator 0:bb348c97df44 143 __HAL_RCC_PWR_CLK_ENABLE();
lypinator 0:bb348c97df44 144
lypinator 0:bb348c97df44 145 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
lypinator 0:bb348c97df44 146
lypinator 0:bb348c97df44 147 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
lypinator 0:bb348c97df44 148 RCC_OscInitStruct.HSEState = RCC_HSE_ON;
lypinator 0:bb348c97df44 149 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
lypinator 0:bb348c97df44 150 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
lypinator 0:bb348c97df44 151 RCC_OscInitStruct.PLL.PLLM = 8;
lypinator 0:bb348c97df44 152 RCC_OscInitStruct.PLL.PLLN = 360;
lypinator 0:bb348c97df44 153 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
lypinator 0:bb348c97df44 154 RCC_OscInitStruct.PLL.PLLQ = 7;
lypinator 0:bb348c97df44 155 HAL_RCC_OscConfig(&RCC_OscInitStruct);
lypinator 0:bb348c97df44 156
lypinator 0:bb348c97df44 157 HAL_PWREx_EnableOverDrive();
lypinator 0:bb348c97df44 158
lypinator 0:bb348c97df44 159 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1
lypinator 0:bb348c97df44 160 | RCC_CLOCKTYPE_PCLK2;
lypinator 0:bb348c97df44 161 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
lypinator 0:bb348c97df44 162 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
lypinator 0:bb348c97df44 163 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
lypinator 0:bb348c97df44 164 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
lypinator 0:bb348c97df44 165 HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
lypinator 0:bb348c97df44 166
lypinator 0:bb348c97df44 167 // HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_3);
lypinator 0:bb348c97df44 168
lypinator 0:bb348c97df44 169 }
lypinator 0:bb348c97df44 170 #endif