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lpc17xx_clkpwr.h
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00001 /***********************************************************************//** 00002 * @file lpc17xx_clkpwr.h 00003 * @brief Contains all macro definitions and function prototypes 00004 * support for Clock and Power Control firmware library on LPC17xx 00005 * @version 2.0 00006 * @date 21. May. 2010 00007 * @author NXP MCU SW Application Team 00008 ************************************************************************** 00009 * Software that is described herein is for illustrative purposes only 00010 * which provides customers with programming information regarding the 00011 * products. This software is supplied "AS IS" without any warranties. 00012 * NXP Semiconductors assumes no responsibility or liability for the 00013 * use of the software, conveys no license or title under any patent, 00014 * copyright, or mask work right to the product. NXP Semiconductors 00015 * reserves the right to make changes in the software without 00016 * notification. NXP Semiconductors also make no representation or 00017 * warranty that such application will be suitable for the specified 00018 * use without further testing or modification. 00019 **************************************************************************/ 00020 00021 /* Peripheral group ----------------------------------------------------------- */ 00022 /** @defgroup CLKPWR CLKPWR 00023 * @ingroup LPC1700CMSIS_FwLib_Drivers 00024 * @{ 00025 */ 00026 00027 #ifndef LPC17XX_CLKPWR_H_ 00028 #define LPC17XX_CLKPWR_H_ 00029 00030 /* Includes ------------------------------------------------------------------- */ 00031 #include "LPC17xx.h" 00032 #include "lpc_types.h" 00033 00034 #ifdef __cplusplus 00035 extern "C" 00036 { 00037 #endif 00038 00039 /* Public Macros -------------------------------------------------------------- */ 00040 /** @defgroup CLKPWR_Public_Macros CLKPWR Public Macros 00041 * @{ 00042 */ 00043 00044 /********************************************************************** 00045 * Peripheral Clock Selection Definitions 00046 **********************************************************************/ 00047 /** Peripheral clock divider bit position for WDT */ 00048 #define CLKPWR_PCLKSEL_WDT ((uint32_t)(0)) 00049 /** Peripheral clock divider bit position for TIMER0 */ 00050 #define CLKPWR_PCLKSEL_TIMER0 ((uint32_t)(2)) 00051 /** Peripheral clock divider bit position for TIMER1 */ 00052 #define CLKPWR_PCLKSEL_TIMER1 ((uint32_t)(4)) 00053 /** Peripheral clock divider bit position for UART0 */ 00054 #define CLKPWR_PCLKSEL_UART0 ((uint32_t)(6)) 00055 /** Peripheral clock divider bit position for UART1 */ 00056 #define CLKPWR_PCLKSEL_UART1 ((uint32_t)(8)) 00057 /** Peripheral clock divider bit position for PWM1 */ 00058 #define CLKPWR_PCLKSEL_PWM1 ((uint32_t)(12)) 00059 /** Peripheral clock divider bit position for I2C0 */ 00060 #define CLKPWR_PCLKSEL_I2C0 ((uint32_t)(14)) 00061 /** Peripheral clock divider bit position for SPI */ 00062 #define CLKPWR_PCLKSEL_SPI ((uint32_t)(16)) 00063 /** Peripheral clock divider bit position for SSP1 */ 00064 #define CLKPWR_PCLKSEL_SSP1 ((uint32_t)(20)) 00065 /** Peripheral clock divider bit position for DAC */ 00066 #define CLKPWR_PCLKSEL_DAC ((uint32_t)(22)) 00067 /** Peripheral clock divider bit position for ADC */ 00068 #define CLKPWR_PCLKSEL_ADC ((uint32_t)(24)) 00069 /** Peripheral clock divider bit position for CAN1 */ 00070 #define CLKPWR_PCLKSEL_CAN1 ((uint32_t)(26)) 00071 /** Peripheral clock divider bit position for CAN2 */ 00072 #define CLKPWR_PCLKSEL_CAN2 ((uint32_t)(28)) 00073 /** Peripheral clock divider bit position for ACF */ 00074 #define CLKPWR_PCLKSEL_ACF ((uint32_t)(30)) 00075 /** Peripheral clock divider bit position for QEI */ 00076 #define CLKPWR_PCLKSEL_QEI ((uint32_t)(32)) 00077 /** Peripheral clock divider bit position for PCB */ 00078 #define CLKPWR_PCLKSEL_PCB ((uint32_t)(36)) 00079 /** Peripheral clock divider bit position for I2C1 */ 00080 #define CLKPWR_PCLKSEL_I2C1 ((uint32_t)(38)) 00081 /** Peripheral clock divider bit position for SSP0 */ 00082 #define CLKPWR_PCLKSEL_SSP0 ((uint32_t)(42)) 00083 /** Peripheral clock divider bit position for TIMER2 */ 00084 #define CLKPWR_PCLKSEL_TIMER2 ((uint32_t)(44)) 00085 /** Peripheral clock divider bit position for TIMER3 */ 00086 #define CLKPWR_PCLKSEL_TIMER3 ((uint32_t)(46)) 00087 /** Peripheral clock divider bit position for UART2 */ 00088 #define CLKPWR_PCLKSEL_UART2 ((uint32_t)(48)) 00089 /** Peripheral clock divider bit position for UART3 */ 00090 #define CLKPWR_PCLKSEL_UART3 ((uint32_t)(50)) 00091 /** Peripheral clock divider bit position for I2C2 */ 00092 #define CLKPWR_PCLKSEL_I2C2 ((uint32_t)(52)) 00093 /** Peripheral clock divider bit position for I2S */ 00094 #define CLKPWR_PCLKSEL_I2S ((uint32_t)(54)) 00095 /** Peripheral clock divider bit position for RIT */ 00096 #define CLKPWR_PCLKSEL_RIT ((uint32_t)(58)) 00097 /** Peripheral clock divider bit position for SYSCON */ 00098 #define CLKPWR_PCLKSEL_SYSCON ((uint32_t)(60)) 00099 /** Peripheral clock divider bit position for MC */ 00100 #define CLKPWR_PCLKSEL_MC ((uint32_t)(62)) 00101 00102 /** Macro for Peripheral Clock Selection register bit values 00103 * Note: When CCLK_DIV_8, Peripheral�s clock is selected to 00104 * PCLK_xyz = CCLK/8 except for CAN1, CAN2, and CAN filtering 00105 * when �11�selects PCLK_xyz = CCLK/6 */ 00106 /* Peripheral clock divider is set to 4 from CCLK */ 00107 #define CLKPWR_PCLKSEL_CCLK_DIV_4 ((uint32_t)(0)) 00108 /** Peripheral clock divider is the same with CCLK */ 00109 #define CLKPWR_PCLKSEL_CCLK_DIV_1 ((uint32_t)(1)) 00110 /** Peripheral clock divider is set to 2 from CCLK */ 00111 #define CLKPWR_PCLKSEL_CCLK_DIV_2 ((uint32_t)(2)) 00112 00113 00114 /******************************************************************** 00115 * Power Control for Peripherals Definitions 00116 **********************************************************************/ 00117 /** Timer/Counter 0 power/clock control bit */ 00118 #define CLKPWR_PCONP_PCTIM0 ((uint32_t)(1<<1)) 00119 /* Timer/Counter 1 power/clock control bit */ 00120 #define CLKPWR_PCONP_PCTIM1 ((uint32_t)(1<<2)) 00121 /** UART0 power/clock control bit */ 00122 #define CLKPWR_PCONP_PCUART0 ((uint32_t)(1<<3)) 00123 /** UART1 power/clock control bit */ 00124 #define CLKPWR_PCONP_PCUART1 ((uint32_t)(1<<4)) 00125 /** PWM1 power/clock control bit */ 00126 #define CLKPWR_PCONP_PCPWM1 ((uint32_t)(1<<6)) 00127 /** The I2C0 interface power/clock control bit */ 00128 #define CLKPWR_PCONP_PCI2C0 ((uint32_t)(1<<7)) 00129 /** The SPI interface power/clock control bit */ 00130 #define CLKPWR_PCONP_PCSPI ((uint32_t)(1<<8)) 00131 /** The RTC power/clock control bit */ 00132 #define CLKPWR_PCONP_PCRTC ((uint32_t)(1<<9)) 00133 /** The SSP1 interface power/clock control bit */ 00134 #define CLKPWR_PCONP_PCSSP1 ((uint32_t)(1<<10)) 00135 /** A/D converter 0 (ADC0) power/clock control bit */ 00136 #define CLKPWR_PCONP_PCAD ((uint32_t)(1<<12)) 00137 /** CAN Controller 1 power/clock control bit */ 00138 #define CLKPWR_PCONP_PCAN1 ((uint32_t)(1<<13)) 00139 /** CAN Controller 2 power/clock control bit */ 00140 #define CLKPWR_PCONP_PCAN2 ((uint32_t)(1<<14)) 00141 /** GPIO power/clock control bit */ 00142 #define CLKPWR_PCONP_PCGPIO ((uint32_t)(1<<15)) 00143 /** Repetitive Interrupt Timer power/clock control bit */ 00144 #define CLKPWR_PCONP_PCRIT ((uint32_t)(1<<16)) 00145 /** Motor Control PWM */ 00146 #define CLKPWR_PCONP_PCMC ((uint32_t)(1<<17)) 00147 /** Quadrature Encoder Interface power/clock control bit */ 00148 #define CLKPWR_PCONP_PCQEI ((uint32_t)(1<<18)) 00149 /** The I2C1 interface power/clock control bit */ 00150 #define CLKPWR_PCONP_PCI2C1 ((uint32_t)(1<<19)) 00151 /** The SSP0 interface power/clock control bit */ 00152 #define CLKPWR_PCONP_PCSSP0 ((uint32_t)(1<<21)) 00153 /** Timer 2 power/clock control bit */ 00154 #define CLKPWR_PCONP_PCTIM2 ((uint32_t)(1<<22)) 00155 /** Timer 3 power/clock control bit */ 00156 #define CLKPWR_PCONP_PCTIM3 ((uint32_t)(1<<23)) 00157 /** UART 2 power/clock control bit */ 00158 #define CLKPWR_PCONP_PCUART2 ((uint32_t)(1<<24)) 00159 /** UART 3 power/clock control bit */ 00160 #define CLKPWR_PCONP_PCUART3 ((uint32_t)(1<<25)) 00161 /** I2C interface 2 power/clock control bit */ 00162 #define CLKPWR_PCONP_PCI2C2 ((uint32_t)(1<<26)) 00163 /** I2S interface power/clock control bit*/ 00164 #define CLKPWR_PCONP_PCI2S ((uint32_t)(1<<27)) 00165 /** GP DMA function power/clock control bit*/ 00166 #define CLKPWR_PCONP_PCGPDMA ((uint32_t)(1<<29)) 00167 /** Ethernet block power/clock control bit*/ 00168 #define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30)) 00169 /** USB interface power/clock control bit*/ 00170 #define CLKPWR_PCONP_PCUSB ((uint32_t)(1<<31)) 00171 00172 00173 /** 00174 * @} 00175 */ 00176 /* Private Macros ------------------------------------------------------------- */ 00177 /** @defgroup CLKPWR_Private_Macros CLKPWR Private Macros 00178 * @{ 00179 */ 00180 00181 /* --------------------- BIT DEFINITIONS -------------------------------------- */ 00182 /*********************************************************************//** 00183 * Macro defines for Clock Source Select Register 00184 **********************************************************************/ 00185 /** Internal RC oscillator */ 00186 #define CLKPWR_CLKSRCSEL_CLKSRC_IRC ((uint32_t)(0x00)) 00187 /** Main oscillator */ 00188 #define CLKPWR_CLKSRCSEL_CLKSRC_MAINOSC ((uint32_t)(0x01)) 00189 /** RTC oscillator */ 00190 #define CLKPWR_CLKSRCSEL_CLKSRC_RTC ((uint32_t)(0x02)) 00191 /** Clock source selection bit mask */ 00192 #define CLKPWR_CLKSRCSEL_BITMASK ((uint32_t)(0x03)) 00193 00194 /*********************************************************************//** 00195 * Macro defines for Clock Output Configuration Register 00196 **********************************************************************/ 00197 /* Clock Output Configuration register definition */ 00198 /** Selects the CPU clock as the CLKOUT source */ 00199 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_CPU ((uint32_t)(0x00)) 00200 /** Selects the main oscillator as the CLKOUT source */ 00201 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_MAINOSC ((uint32_t)(0x01)) 00202 /** Selects the Internal RC oscillator as the CLKOUT source */ 00203 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_RC ((uint32_t)(0x02)) 00204 /** Selects the USB clock as the CLKOUT source */ 00205 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_USB ((uint32_t)(0x03)) 00206 /** Selects the RTC oscillator as the CLKOUT source */ 00207 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_RTC ((uint32_t)(0x04)) 00208 /** Integer value to divide the output clock by, minus one */ 00209 #define CLKPWR_CLKOUTCFG_CLKOUTDIV(n) ((uint32_t)((n&0x0F)<<4)) 00210 /** CLKOUT enable control */ 00211 #define CLKPWR_CLKOUTCFG_CLKOUT_EN ((uint32_t)(1<<8)) 00212 /** CLKOUT activity indication */ 00213 #define CLKPWR_CLKOUTCFG_CLKOUT_ACT ((uint32_t)(1<<9)) 00214 /** Clock source selection bit mask */ 00215 #define CLKPWR_CLKOUTCFG_BITMASK ((uint32_t)(0x3FF)) 00216 00217 /*********************************************************************//** 00218 * Macro defines for PPL0 Control Register 00219 **********************************************************************/ 00220 /** PLL 0 control enable */ 00221 #define CLKPWR_PLL0CON_ENABLE ((uint32_t)(0x01)) 00222 /** PLL 0 control connect */ 00223 #define CLKPWR_PLL0CON_CONNECT ((uint32_t)(0x02)) 00224 /** PLL 0 control bit mask */ 00225 #define CLKPWR_PLL0CON_BITMASK ((uint32_t)(0x03)) 00226 00227 /*********************************************************************//** 00228 * Macro defines for PPL0 Configuration Register 00229 **********************************************************************/ 00230 /** PLL 0 Configuration MSEL field */ 00231 #define CLKPWR_PLL0CFG_MSEL(n) ((uint32_t)(n&0x7FFF)) 00232 /** PLL 0 Configuration NSEL field */ 00233 #define CLKPWR_PLL0CFG_NSEL(n) ((uint32_t)((n<<16)&0xFF0000)) 00234 /** PLL 0 Configuration bit mask */ 00235 #define CLKPWR_PLL0CFG_BITMASK ((uint32_t)(0xFF7FFF)) 00236 00237 00238 /*********************************************************************//** 00239 * Macro defines for PPL0 Status Register 00240 **********************************************************************/ 00241 /** PLL 0 MSEL value */ 00242 #define CLKPWR_PLL0STAT_MSEL(n) ((uint32_t)(n&0x7FFF)) 00243 /** PLL NSEL get value */ 00244 #define CLKPWR_PLL0STAT_NSEL(n) ((uint32_t)((n>>16)&0xFF)) 00245 /** PLL status enable bit */ 00246 #define CLKPWR_PLL0STAT_PLLE ((uint32_t)(1<<24)) 00247 /** PLL status Connect bit */ 00248 #define CLKPWR_PLL0STAT_PLLC ((uint32_t)(1<<25)) 00249 /** PLL status lock */ 00250 #define CLKPWR_PLL0STAT_PLOCK ((uint32_t)(1<<26)) 00251 00252 /*********************************************************************//** 00253 * Macro defines for PPL0 Feed Register 00254 **********************************************************************/ 00255 /** PLL0 Feed bit mask */ 00256 #define CLKPWR_PLL0FEED_BITMASK ((uint32_t)0xFF) 00257 00258 /*********************************************************************//** 00259 * Macro defines for PLL1 Control Register 00260 **********************************************************************/ 00261 /** USB PLL control enable */ 00262 #define CLKPWR_PLL1CON_ENABLE ((uint32_t)(0x01)) 00263 /** USB PLL control connect */ 00264 #define CLKPWR_PLL1CON_CONNECT ((uint32_t)(0x02)) 00265 /** USB PLL control bit mask */ 00266 #define CLKPWR_PLL1CON_BITMASK ((uint32_t)(0x03)) 00267 00268 /*********************************************************************//** 00269 * Macro defines for PLL1 Configuration Register 00270 **********************************************************************/ 00271 /** USB PLL MSEL set value */ 00272 #define CLKPWR_PLL1CFG_MSEL(n) ((uint32_t)(n&0x1F)) 00273 /** USB PLL PSEL set value */ 00274 #define CLKPWR_PLL1CFG_PSEL(n) ((uint32_t)((n&0x03)<<5)) 00275 /** USB PLL configuration bit mask */ 00276 #define CLKPWR_PLL1CFG_BITMASK ((uint32_t)(0x7F)) 00277 00278 /*********************************************************************//** 00279 * Macro defines for PLL1 Status Register 00280 **********************************************************************/ 00281 /** USB PLL MSEL get value */ 00282 #define CLKPWR_PLL1STAT_MSEL(n) ((uint32_t)(n&0x1F)) 00283 /** USB PLL PSEL get value */ 00284 #define CLKPWR_PLL1STAT_PSEL(n) ((uint32_t)((n>>5)&0x03)) 00285 /** USB PLL status enable bit */ 00286 #define CLKPWR_PLL1STAT_PLLE ((uint32_t)(1<<8)) 00287 /** USB PLL status Connect bit */ 00288 #define CLKPWR_PLL1STAT_PLLC ((uint32_t)(1<<9)) 00289 /** USB PLL status lock */ 00290 #define CLKPWR_PLL1STAT_PLOCK ((uint32_t)(1<<10)) 00291 00292 /*********************************************************************//** 00293 * Macro defines for PLL1 Feed Register 00294 **********************************************************************/ 00295 /** PLL1 Feed bit mask */ 00296 #define CLKPWR_PLL1FEED_BITMASK ((uint32_t)0xFF) 00297 00298 /*********************************************************************//** 00299 * Macro defines for CPU Clock Configuration Register 00300 **********************************************************************/ 00301 /** CPU Clock configuration bit mask */ 00302 #define CLKPWR_CCLKCFG_BITMASK ((uint32_t)(0xFF)) 00303 00304 /*********************************************************************//** 00305 * Macro defines for USB Clock Configuration Register 00306 **********************************************************************/ 00307 /** USB Clock Configuration bit mask */ 00308 #define CLKPWR_USBCLKCFG_BITMASK ((uint32_t)(0x0F)) 00309 00310 /*********************************************************************//** 00311 * Macro defines for IRC Trim Register 00312 **********************************************************************/ 00313 /** IRC Trim bit mask */ 00314 #define CLKPWR_IRCTRIM_BITMASK ((uint32_t)(0x0F)) 00315 00316 /*********************************************************************//** 00317 * Macro defines for Peripheral Clock Selection Register 0 and 1 00318 **********************************************************************/ 00319 /** Peripheral Clock Selection 0 mask bit */ 00320 #define CLKPWR_PCLKSEL0_BITMASK ((uint32_t)(0xFFF3F3FF)) 00321 /** Peripheral Clock Selection 1 mask bit */ 00322 #define CLKPWR_PCLKSEL1_BITMASK ((uint32_t)(0xFCF3F0F3)) 00323 /** Macro to set peripheral clock of each type 00324 * p: position of two bits that hold divider of peripheral clock 00325 * n: value of divider of peripheral clock to be set */ 00326 #define CLKPWR_PCLKSEL_SET(p,n) _SBF(p,n) 00327 /** Macro to mask peripheral clock of each type */ 00328 #define CLKPWR_PCLKSEL_BITMASK(p) _SBF(p,0x03) 00329 /** Macro to get peripheral clock of each type */ 00330 #define CLKPWR_PCLKSEL_GET(p, n) ((uint32_t)((n>>p)&0x03)) 00331 00332 /*********************************************************************//** 00333 * Macro defines for Power Mode Control Register 00334 **********************************************************************/ 00335 /** Power mode control bit 0 */ 00336 #define CLKPWR_PCON_PM0 ((uint32_t)(1<<0)) 00337 /** Power mode control bit 1 */ 00338 #define CLKPWR_PCON_PM1 ((uint32_t)(1<<1)) 00339 /** Brown-Out Reduced Power Mode */ 00340 #define CLKPWR_PCON_BODPDM ((uint32_t)(1<<2)) 00341 /** Brown-Out Global Disable */ 00342 #define CLKPWR_PCON_BOGD ((uint32_t)(1<<3)) 00343 /** Brown Out Reset Disable */ 00344 #define CLKPWR_PCON_BORD ((uint32_t)(1<<4)) 00345 /** Sleep Mode entry flag */ 00346 #define CLKPWR_PCON_SMFLAG ((uint32_t)(1<<8)) 00347 /** Deep Sleep entry flag */ 00348 #define CLKPWR_PCON_DSFLAG ((uint32_t)(1<<9)) 00349 /** Power-down entry flag */ 00350 #define CLKPWR_PCON_PDFLAG ((uint32_t)(1<<10)) 00351 /** Deep Power-down entry flag */ 00352 #define CLKPWR_PCON_DPDFLAG ((uint32_t)(1<<11)) 00353 00354 /*********************************************************************//** 00355 * Macro defines for Power Control for Peripheral Register 00356 **********************************************************************/ 00357 /** Power Control for Peripherals bit mask */ 00358 #define CLKPWR_PCONP_BITMASK 0xEFEFF7DE 00359 00360 /** 00361 * @} 00362 */ 00363 00364 00365 /* Public Functions ----------------------------------------------------------- */ 00366 /** @defgroup CLKPWR_Public_Functions CLKPWR Public Functions 00367 * @{ 00368 */ 00369 00370 void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal); 00371 uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType); 00372 uint32_t CLKPWR_GetPCLK (uint32_t ClkType); 00373 void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState); 00374 void CLKPWR_Sleep(void); 00375 void CLKPWR_DeepSleep(void); 00376 void CLKPWR_PowerDown(void); 00377 void CLKPWR_DeepPowerDown(void); 00378 00379 /** 00380 * @} 00381 */ 00382 00383 00384 #ifdef __cplusplus 00385 } 00386 #endif 00387 00388 #endif /* LPC17XX_CLKPWR_H_ */ 00389 00390 /** 00391 * @} 00392 */ 00393 00394 /* --------------------------------- End Of File ------------------------------ */
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