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| lynxeyed_atsu |
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/**************************************************************************//**
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| lynxeyed_atsu |
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* @file system_LPC17xx.c
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* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File
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| lynxeyed_atsu |
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4
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* for the NXP LPC17xx Device Series
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* @version V1.03
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* @date 07. October 2009
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*
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* @note
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* Copyright (C) 2009 ARM Limited. All rights reserved.
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*
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* @par
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12
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* ARM Limited (ARM) is supplying this software for use with Cortex-M
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13
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* processor based microcontrollers. This file can be freely distributed
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14
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* within development tools that are supporting such ARM based processors.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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******************************************************************************/
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#include <stdint.h>
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#include "LPC17xx.h"
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/** @addtogroup LPC17xx_System
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* @{
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*/
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/*
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//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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*/
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/*--------------------- Clock Configuration ----------------------------------
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//
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| lynxeyed_atsu |
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// <e> Clock Configuration
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| lynxeyed_atsu |
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// <h> System Controls and Status Register (SCS)
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| lynxeyed_atsu |
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42
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// <o1.4> OSCRANGE: Main Oscillator Range Select
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43
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// <0=> 1 MHz to 20 MHz
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44
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// <1=> 15 MHz to 24 MHz
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45
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// <e1.5> OSCEN: Main Oscillator Enable
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46
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// </e>
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| lynxeyed_atsu |
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47
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// </h>
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| lynxeyed_atsu |
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48
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//
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| lynxeyed_atsu |
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49
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// <h> Clock Source Select Register (CLKSRCSEL)
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| lynxeyed_atsu |
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50
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// <o2.0..1> CLKSRC: PLL Clock Source Selection
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| lynxeyed_atsu |
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51
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// <0=> Internal RC oscillator
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| lynxeyed_atsu |
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52
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// <1=> Main oscillator
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| lynxeyed_atsu |
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53
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// <2=> RTC oscillator
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| lynxeyed_atsu |
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54
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// </h>
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| lynxeyed_atsu |
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55
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//
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| lynxeyed_atsu |
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56
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// <e3> PLL0 Configuration (Main PLL)
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| lynxeyed_atsu |
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57
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// <h> PLL0 Configuration Register (PLL0CFG)
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| lynxeyed_atsu |
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58
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// <i> F_cco0 = (2 * M * F_in) / N
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| lynxeyed_atsu |
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59
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// <i> F_in must be in the range of 32 kHz to 50 MHz
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| lynxeyed_atsu |
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60
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// <i> F_cco0 must be in the range of 275 MHz to 550 MHz
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| lynxeyed_atsu |
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61
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// <o4.0..14> MSEL: PLL Multiplier Selection
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62
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// <6-32768><#-1>
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| lynxeyed_atsu |
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63
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// <i> M Value
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| lynxeyed_atsu |
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64
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// <o4.16..23> NSEL: PLL Divider Selection
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| lynxeyed_atsu |
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65
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// <1-256><#-1>
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| lynxeyed_atsu |
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66
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// <i> N Value
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| lynxeyed_atsu |
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67
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// </h>
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| lynxeyed_atsu |
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68
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// </e>
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| lynxeyed_atsu |
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69
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//
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| lynxeyed_atsu |
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70
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// <e5> PLL1 Configuration (USB PLL)
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| lynxeyed_atsu |
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71
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// <h> PLL1 Configuration Register (PLL1CFG)
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| lynxeyed_atsu |
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72
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// <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P)
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| lynxeyed_atsu |
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73
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// <i> F_cco1 = F_osc * M * 2 * P
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| lynxeyed_atsu |
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74
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// <i> F_cco1 must be in the range of 156 MHz to 320 MHz
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| lynxeyed_atsu |
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75
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// <o6.0..4> MSEL: PLL Multiplier Selection
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| lynxeyed_atsu |
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76
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// <1-32><#-1>
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| lynxeyed_atsu |
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77
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// <i> M Value (for USB maximum value is 4)
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| lynxeyed_atsu |
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78
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// <o6.5..6> PSEL: PLL Divider Selection
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| lynxeyed_atsu |
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79
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// <0=> 1
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| lynxeyed_atsu |
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80
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// <1=> 2
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81
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// <2=> 4
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82
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// <3=> 8
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83
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// <i> P Value
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| lynxeyed_atsu |
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84
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// </h>
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| lynxeyed_atsu |
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85
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// </e>
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| lynxeyed_atsu |
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86
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//
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| lynxeyed_atsu |
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87
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// <h> CPU Clock Configuration Register (CCLKCFG)
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| lynxeyed_atsu |
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88
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// <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0
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| lynxeyed_atsu |
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89
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// <3-256><#-1>
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| lynxeyed_atsu |
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90
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// </h>
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| lynxeyed_atsu |
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91
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//
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| lynxeyed_atsu |
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92
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// <h> USB Clock Configuration Register (USBCLKCFG)
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| lynxeyed_atsu |
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93
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// <o8.0..3> USBSEL: Divide Value for USB Clock from PLL0
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94
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// <0-15>
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| lynxeyed_atsu |
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95
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// <i> Divide is USBSEL + 1
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| lynxeyed_atsu |
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96
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// </h>
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| lynxeyed_atsu |
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|
97
|
//
|
| lynxeyed_atsu |
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98
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// <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
|
| lynxeyed_atsu |
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|
99
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// <o9.0..1> PCLK_WDT: Peripheral Clock Selection for WDT
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| lynxeyed_atsu |
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100
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// <0=> Pclk = Cclk / 4
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| lynxeyed_atsu |
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101
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// <1=> Pclk = Cclk
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| lynxeyed_atsu |
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|
102
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// <2=> Pclk = Cclk / 2
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| lynxeyed_atsu |
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103
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// <3=> Pclk = Hclk / 8
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| lynxeyed_atsu |
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104
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// <o9.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0
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| lynxeyed_atsu |
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105
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// <0=> Pclk = Cclk / 4
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| lynxeyed_atsu |
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106
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// <1=> Pclk = Cclk
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| lynxeyed_atsu |
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|
107
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// <2=> Pclk = Cclk / 2
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| lynxeyed_atsu |
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|
108
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// <3=> Pclk = Hclk / 8
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| lynxeyed_atsu |
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|
109
|
// <o9.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1
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| lynxeyed_atsu |
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|
110
|
// <0=> Pclk = Cclk / 4
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| lynxeyed_atsu |
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|
111
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// <1=> Pclk = Cclk
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| lynxeyed_atsu |
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|
112
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// <2=> Pclk = Cclk / 2
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| lynxeyed_atsu |
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|
113
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// <3=> Pclk = Hclk / 8
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| lynxeyed_atsu |
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|
114
|
// <o9.6..7> PCLK_UART0: Peripheral Clock Selection for UART0
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| lynxeyed_atsu |
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|
115
|
// <0=> Pclk = Cclk / 4
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| lynxeyed_atsu |
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|
116
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// <1=> Pclk = Cclk
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| lynxeyed_atsu |
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|
117
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// <2=> Pclk = Cclk / 2
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| lynxeyed_atsu |
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|
118
|
// <3=> Pclk = Hclk / 8
|
| lynxeyed_atsu |
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|
119
|
// <o9.8..9> PCLK_UART1: Peripheral Clock Selection for UART1
|
| lynxeyed_atsu |
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|
120
|
// <0=> Pclk = Cclk / 4
|
| lynxeyed_atsu |
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|
121
|
// <1=> Pclk = Cclk
|
| lynxeyed_atsu |
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|
122
|
// <2=> Pclk = Cclk / 2
|
| lynxeyed_atsu |
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|
123
|
// <3=> Pclk = Hclk / 8
|
| lynxeyed_atsu |
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|
124
|
// <o9.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1
|
| lynxeyed_atsu |
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|
125
|
// <0=> Pclk = Cclk / 4
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| lynxeyed_atsu |
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|
126
|
// <1=> Pclk = Cclk
|
| lynxeyed_atsu |
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|
127
|
// <2=> Pclk = Cclk / 2
|
| lynxeyed_atsu |
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|
128
|
// <3=> Pclk = Hclk / 8
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
129
|
// <o9.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
130
|
// <0=> Pclk = Cclk / 4
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
131
|
// <1=> Pclk = Cclk
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
132
|
// <2=> Pclk = Cclk / 2
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
133
|
// <3=> Pclk = Hclk / 8
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
134
|
// <o9.16..17> PCLK_SPI: Peripheral Clock Selection for SPI
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
135
|
// <0=> Pclk = Cclk / 4
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
136
|
// <1=> Pclk = Cclk
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
137
|
// <2=> Pclk = Cclk / 2
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
138
|
// <3=> Pclk = Hclk / 8
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
139
|
// <o9.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
140
|
// <0=> Pclk = Cclk / 4
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
141
|
// <1=> Pclk = Cclk
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
142
|
// <2=> Pclk = Cclk / 2
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
143
|
// <3=> Pclk = Hclk / 8
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
144
|
// <o9.22..23> PCLK_DAC: Peripheral Clock Selection for DAC
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
145
|
// <0=> Pclk = Cclk / 4
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
146
|
// <1=> Pclk = Cclk
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
147
|
// <2=> Pclk = Cclk / 2
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
148
|
// <3=> Pclk = Hclk / 8
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
149
|
// <o9.24..25> PCLK_ADC: Peripheral Clock Selection for ADC
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
150
|
// <0=> Pclk = Cclk / 4
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
151
|
// <1=> Pclk = Cclk
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
152
|
// <2=> Pclk = Cclk / 2
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
153
|
// <3=> Pclk = Hclk / 8
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
154
|
// <o9.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
155
|
// <0=> Pclk = Cclk / 4
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
156
|
// <1=> Pclk = Cclk
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
157
|
// <2=> Pclk = Cclk / 2
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
158
|
// <3=> Pclk = Hclk / 6
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
159
|
// <o9.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
160
|
// <0=> Pclk = Cclk / 4
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
161
|
// <1=> Pclk = Cclk
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
162
|
// <2=> Pclk = Cclk / 2
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
163
|
// <3=> Pclk = Hclk / 6
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
164
|
// <o9.30..31> PCLK_ACF: Peripheral Clock Selection for ACF
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
165
|
// <0=> Pclk = Cclk / 4
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
166
|
// <1=> Pclk = Cclk
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
167
|
// <2=> Pclk = Cclk / 2
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
168
|
// <3=> Pclk = Hclk / 6
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
169
|
// </h>
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
170
|
//
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
171
|
// <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
172
|
// <o10.0..1> PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
173
|
// <0=> Pclk = Cclk / 4
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
174
|
// <1=> Pclk = Cclk
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
175
|
// <2=> Pclk = Cclk / 2
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
176
|
// <3=> Pclk = Hclk / 8
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
177
|
// <o10.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
178
|
// <0=> Pclk = Cclk / 4
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
179
|
// <1=> Pclk = Cclk
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
180
|
// <2=> Pclk = Cclk / 2
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
181
|
// <3=> Pclk = Hclk / 8
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
182
|
// <o10.4..5> PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
183
|
// <0=> Pclk = Cclk / 4
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
184
|
// <1=> Pclk = Cclk
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
185
|
// <2=> Pclk = Cclk / 2
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
186
|
// <3=> Pclk = Hclk / 8
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
187
|
// <o10.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
188
|
// <0=> Pclk = Cclk / 4
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
189
|
// <1=> Pclk = Cclk
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
190
|
// <2=> Pclk = Cclk / 2
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
191
|
// <3=> Pclk = Hclk / 8
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
192
|
// <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
193
|
// <0=> Pclk = Cclk / 4
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
194
|
// <1=> Pclk = Cclk
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
195
|
// <2=> Pclk = Cclk / 2
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
196
|
// <3=> Pclk = Hclk / 8
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
197
|
// <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
198
|
// <0=> Pclk = Cclk / 4
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
199
|
// <1=> Pclk = Cclk
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
200
|
// <2=> Pclk = Cclk / 2
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
201
|
// <3=> Pclk = Hclk / 8
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
202
|
// <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
203
|
// <0=> Pclk = Cclk / 4
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
204
|
// <1=> Pclk = Cclk
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
205
|
// <2=> Pclk = Cclk / 2
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
206
|
// <3=> Pclk = Hclk / 8
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
207
|
// <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
208
|
// <0=> Pclk = Cclk / 4
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
209
|
// <1=> Pclk = Cclk
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
210
|
// <2=> Pclk = Cclk / 2
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
211
|
// <3=> Pclk = Hclk / 8
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
212
|
// <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
213
|
// <0=> Pclk = Cclk / 4
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
214
|
// <1=> Pclk = Cclk
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
215
|
// <2=> Pclk = Cclk / 2
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
216
|
// <3=> Pclk = Hclk / 8
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
217
|
// <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
218
|
// <0=> Pclk = Cclk / 4
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
219
|
// <1=> Pclk = Cclk
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
220
|
// <2=> Pclk = Cclk / 2
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
221
|
// <3=> Pclk = Hclk / 8
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
222
|
// <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
223
|
// <0=> Pclk = Cclk / 4
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
224
|
// <1=> Pclk = Cclk
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
225
|
// <2=> Pclk = Cclk / 2
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
226
|
// <3=> Pclk = Hclk / 8
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
227
|
// <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
228
|
// <0=> Pclk = Cclk / 4
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
229
|
// <1=> Pclk = Cclk
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
230
|
// <2=> Pclk = Cclk / 2
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
231
|
// <3=> Pclk = Hclk / 8
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
232
|
// <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
233
|
// <0=> Pclk = Cclk / 4
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
234
|
// <1=> Pclk = Cclk
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
235
|
// <2=> Pclk = Cclk / 2
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
236
|
// <3=> Pclk = Hclk / 8
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
237
|
// <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
238
|
// <0=> Pclk = Cclk / 4
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
239
|
// <1=> Pclk = Cclk
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
240
|
// <2=> Pclk = Cclk / 2
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
241
|
// <3=> Pclk = Hclk / 8
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
242
|
// </h>
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
243
|
//
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
244
|
// <h> Power Control for Peripherals Register (PCONP)
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
245
|
// <o11.1> PCTIM0: Timer/Counter 0 power/clock enable
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
246
|
// <o11.2> PCTIM1: Timer/Counter 1 power/clock enable
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
247
|
// <o11.3> PCUART0: UART 0 power/clock enable
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
248
|
// <o11.4> PCUART1: UART 1 power/clock enable
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
249
|
// <o11.6> PCPWM1: PWM 1 power/clock enable
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
250
|
// <o11.7> PCI2C0: I2C interface 0 power/clock enable
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
251
|
// <o11.8> PCSPI: SPI interface power/clock enable
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
252
|
// <o11.9> PCRTC: RTC power/clock enable
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
253
|
// <o11.10> PCSSP1: SSP interface 1 power/clock enable
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
254
|
// <o11.12> PCAD: A/D converter power/clock enable
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
255
|
// <o11.13> PCCAN1: CAN controller 1 power/clock enable
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
256
|
// <o11.14> PCCAN2: CAN controller 2 power/clock enable
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
257
|
// <o11.15> PCGPIO: GPIOs power/clock enable
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
258
|
// <o11.16> PCRIT: Repetitive interrupt timer power/clock enable
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
259
|
// <o11.17> PCMC: Motor control PWM power/clock enable
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
260
|
// <o11.18> PCQEI: Quadrature encoder interface power/clock enable
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
261
|
// <o11.19> PCI2C1: I2C interface 1 power/clock enable
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
262
|
// <o11.21> PCSSP0: SSP interface 0 power/clock enable
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
263
|
// <o11.22> PCTIM2: Timer 2 power/clock enable
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
264
|
// <o11.23> PCTIM3: Timer 3 power/clock enable
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
265
|
// <o11.24> PCUART2: UART 2 power/clock enable
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
266
|
// <o11.25> PCUART3: UART 3 power/clock enable
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
267
|
// <o11.26> PCI2C2: I2C interface 2 power/clock enable
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
268
|
// <o11.27> PCI2S: I2S interface power/clock enable
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
269
|
// <o11.29> PCGPDMA: GP DMA function power/clock enable
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
270
|
// <o11.30> PCENET: Ethernet block power/clock enable
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
271
|
// <o11.31> PCUSB: USB interface power/clock enable
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
272
|
// </h>
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
273
|
//
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
274
|
// <h> Clock Output Configuration Register (CLKOUTCFG)
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
275
|
// <o12.0..3> CLKOUTSEL: Selects clock source for CLKOUT
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
276
|
// <0=> CPU clock
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
277
|
// <1=> Main oscillator
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
278
|
// <2=> Internal RC oscillator
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
279
|
// <3=> USB clock
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
280
|
// <4=> RTC oscillator
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
281
|
// <o12.4..7> CLKOUTDIV: Selects clock divider for CLKOUT
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
282
|
// <1-16><#-1>
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
283
|
// <o12.8> CLKOUT_EN: CLKOUT enable control
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
284
|
// </h>
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
285
|
//
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
286
|
// </e>
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
287
|
*/
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
288
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
289
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
290
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
291
|
/** @addtogroup LPC17xx_System_Defines LPC17xx System Defines
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
292
|
@{
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
293
|
*/
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
294
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
295
|
#define CLOCK_SETUP 1
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
296
|
#define SCS_Val 0x00000020
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
297
|
#define CLKSRCSEL_Val 0x00000001
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
298
|
#define PLL0_SETUP 1
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
299
|
#define PLL0CFG_Val 0x00050063
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
300
|
#define PLL1_SETUP 1
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
301
|
#define PLL1CFG_Val 0x00000023
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
302
|
#define CCLKCFG_Val 0x00000003
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
303
|
#define USBCLKCFG_Val 0x00000000
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
304
|
#define PCLKSEL0_Val 0x00000000
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
305
|
#define PCLKSEL1_Val 0x00000000
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
306
|
#define PCONP_Val 0x042887DE
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
307
|
#define CLKOUTCFG_Val 0x00000000
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
308
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
309
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
310
|
/*--------------------- Flash Accelerator Configuration ----------------------
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
311
|
//
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
312
|
// <e> Flash Accelerator Configuration
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
313
|
// <o1.0..11> Reserved
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
314
|
// <o1.12..15> FLASHTIM: Flash Access Time
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
315
|
// <0=> 1 CPU clock (for CPU clock up to 20 MHz)
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
316
|
// <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
317
|
// <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
318
|
// <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
319
|
// <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
320
|
// <5=> 6 CPU clocks (for any CPU clock)
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
321
|
// </e>
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
322
|
*/
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
323
|
#define FLASH_SETUP 1
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
324
|
#define FLASHCFG_Val 0x0000303A
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
325
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
326
|
/*
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
327
|
//-------- <<< end of configuration section >>> ------------------------------
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
328
|
*/
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
329
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
330
|
/*----------------------------------------------------------------------------
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
331
|
Check the register settings
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
332
|
*----------------------------------------------------------------------------*/
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
333
|
#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
334
|
#define CHECK_RSVD(val, mask) (val & mask)
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
335
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
336
|
/* Clock Configuration -------------------------------------------------------*/
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
337
|
#if (CHECK_RSVD((SCS_Val), ~0x00000030))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
338
|
#error "SCS: Invalid values of reserved bits!"
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
339
|
#endif
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
340
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
341
|
#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
342
|
#error "CLKSRCSEL: Value out of range!"
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
343
|
#endif
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
344
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
345
|
#if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
346
|
#error "PLL0CFG: Invalid values of reserved bits!"
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
347
|
#endif
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
348
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
349
|
#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
350
|
#error "PLL1CFG: Invalid values of reserved bits!"
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
351
|
#endif
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
352
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
353
|
#if ((CCLKCFG_Val != 0) && (((CCLKCFG_Val - 1) % 2)))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
354
|
#error "CCLKCFG: CCLKSEL field does not contain only odd values or 0!"
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
355
|
#endif
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
356
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
357
|
#if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
358
|
#error "USBCLKCFG: Invalid values of reserved bits!"
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
359
|
#endif
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
360
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
361
|
#if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
362
|
#error "PCLKSEL0: Invalid values of reserved bits!"
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
363
|
#endif
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
364
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
365
|
#if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
366
|
#error "PCLKSEL1: Invalid values of reserved bits!"
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
367
|
#endif
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
368
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
369
|
#if (CHECK_RSVD((PCONP_Val), 0x10100821))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
370
|
#error "PCONP: Invalid values of reserved bits!"
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
371
|
#endif
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
372
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
373
|
#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
374
|
#error "CLKOUTCFG: Invalid values of reserved bits!"
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
375
|
#endif
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
376
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
377
|
/* Flash Accelerator Configuration -------------------------------------------*/
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
378
|
#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
379
|
#error "FLASHCFG: Invalid values of reserved bits!"
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
380
|
#endif
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
381
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
382
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
383
|
/*----------------------------------------------------------------------------
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
384
|
DEFINES
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
385
|
*----------------------------------------------------------------------------*/
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
386
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
387
|
/*----------------------------------------------------------------------------
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
388
|
Define clocks
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
389
|
*----------------------------------------------------------------------------*/
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
390
|
#define XTAL (12000000UL) /* Oscillator frequency */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
391
|
#define OSC_CLK ( XTAL) /* Main oscillator frequency */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
392
|
#define RTC_CLK ( 32768UL) /* RTC oscillator frequency */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
393
|
#define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
394
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
395
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
396
|
/* F_cco0 = (2 * M * F_in) / N */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
397
|
#define __M (((PLL0CFG_Val ) & 0x7FFF) + 1)
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
398
|
#define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
399
|
#define __FCCO(__F_IN) ((2 * __M * __F_IN) / __N)
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
400
|
#define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1)
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
401
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
402
|
/* Determine core clock frequency according to settings */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
403
|
#if (PLL0_SETUP)
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
404
|
#if ((CLKSRCSEL_Val & 0x03) == 1)
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
405
|
#define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
406
|
#elif ((CLKSRCSEL_Val & 0x03) == 2)
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
407
|
#define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
408
|
#else
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
409
|
#define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
410
|
#endif
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
411
|
#else
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
412
|
#if ((CLKSRCSEL_Val & 0x03) == 1)
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
413
|
#define __CORE_CLK (OSC_CLK / __CCLK_DIV)
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
414
|
#elif ((CLKSRCSEL_Val & 0x03) == 2)
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
415
|
#define __CORE_CLK (RTC_CLK / __CCLK_DIV)
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
416
|
#else
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
417
|
#define __CORE_CLK (IRC_OSC / __CCLK_DIV)
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
418
|
#endif
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
419
|
#endif
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
420
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
421
|
/**
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
422
|
* @}
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
423
|
*/
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
424
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
425
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
426
|
/** @addtogroup LPC17xx_System_Public_Variables LPC17xx System Public Variables
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
427
|
@{
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
428
|
*/
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
429
|
/*----------------------------------------------------------------------------
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
430
|
Clock Variable definitions
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
431
|
*----------------------------------------------------------------------------*/
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
432
|
//uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
433
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
434
|
/**
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
435
|
* @}
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
436
|
*/
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
437
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
438
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
439
|
/** @addtogroup LPC17xx_System_Public_Functions LPC17xx System Public Functions
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
440
|
@{
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
441
|
*/
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
442
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
443
|
/*----------------------------------------------------------------------------
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
444
|
Clock functions
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
445
|
*----------------------------------------------------------------------------*/
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
446
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
447
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
448
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
449
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
450
|
/**
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
451
|
* Initialize the system
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
452
|
*
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
453
|
* @param none
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
454
|
* @return none
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
455
|
*
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
456
|
* @brief Setup the microcontroller system.
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
457
|
* Initialize the System.
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
458
|
*/
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
459
|
/*
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
460
|
void SystemInit (void)
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
461
|
{
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
462
|
#if (CLOCK_SETUP) // Clock Setup
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
463
|
LPC_SC->SCS = SCS_Val;
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
464
|
if (LPC_SC->SCS & (1 << 5)) { // If Main Oscillator is enabled
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
465
|
while ((LPC_SC->SCS & (1<<6)) == 0);// Wait for Oscillator to be ready
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
466
|
}
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
467
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
468
|
LPC_SC->CCLKCFG = CCLKCFG_Val; // Setup Clock Divider
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
469
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
470
|
LPC_SC->PCLKSEL0 = PCLKSEL0_Val; // Peripheral Clock Selection
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
471
|
LPC_SC->PCLKSEL1 = PCLKSEL1_Val;
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
472
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
473
|
#if (PLL0_SETUP)
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
474
|
LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; // Select Clock Source for PLL0
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
475
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
476
|
LPC_SC->PLL0CFG = PLL0CFG_Val; // configure PLL0
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
477
|
LPC_SC->PLL0FEED = 0xAA;
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
478
|
LPC_SC->PLL0FEED = 0x55;
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
479
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
480
|
LPC_SC->PLL0CON = 0x01; // PLL0 Enable
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
481
|
LPC_SC->PLL0FEED = 0xAA;
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
482
|
LPC_SC->PLL0FEED = 0x55;
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
483
|
while (!(LPC_SC->PLL0STAT & (1<<26)));// Wait for PLOCK0
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
484
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
485
|
LPC_SC->PLL0CON = 0x03; // PLL0 Enable & Connect
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
486
|
LPC_SC->PLL0FEED = 0xAA;
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
487
|
LPC_SC->PLL0FEED = 0x55;
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
488
|
while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));//Wait for PLLC0_STAT & PLLE0_STAT
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
489
|
#endif
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
490
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
491
|
#if (PLL1_SETUP)
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
492
|
LPC_SC->PLL1CFG = PLL1CFG_Val;
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
493
|
LPC_SC->PLL1FEED = 0xAA;
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
494
|
LPC_SC->PLL1FEED = 0x55;
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
495
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
496
|
LPC_SC->PLL1CON = 0x01; // PLL1 Enable
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
497
|
LPC_SC->PLL1FEED = 0xAA;
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
498
|
LPC_SC->PLL1FEED = 0x55;
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
499
|
while (!(LPC_SC->PLL1STAT & (1<<10)));// Wait for PLOCK1
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
500
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
501
|
LPC_SC->PLL1CON = 0x03; // PLL1 Enable & Connect
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
502
|
LPC_SC->PLL1FEED = 0xAA;
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
503
|
LPC_SC->PLL1FEED = 0x55;
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
504
|
while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));// Wait for PLLC1_STAT & PLLE1_STAT
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
505
|
#else
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
506
|
LPC_SC->USBCLKCFG = USBCLKCFG_Val; // Setup USB Clock Divider
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
507
|
#endif
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
508
|
LPC_SC->PCONP = PCONP_Val; // Power Control for Peripherals
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
509
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
510
|
LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; // Clock Output Configuration
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
511
|
#endif
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
512
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
513
|
#if (FLASH_SETUP == 1) // Flash Accelerator Setup
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
514
|
LPC_SC->FLASHCFG = FLASHCFG_Val;
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
515
|
#endif
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
516
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
517
|
// Set Vector table offset value
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
518
|
#if (__RAM_MODE__==1)
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
519
|
SCB->VTOR = 0x10000000 & 0x3FFFFF80;
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
520
|
#else
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
521
|
SCB->VTOR = 0x00000000 & 0x3FFFFF80;
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
522
|
#endif
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
523
|
}
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
524
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
525
|
*/
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
526
|
/**
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
527
|
* @}
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
528
|
*/
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
529
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
530
|
/**
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
531
|
* @}
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
532
|
*/
|
xeye_ atsu