xeye_ atsu
/
DMA_LLI_TEST
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Data Structures
Here are the data structures with brief descriptions:
| GPDMA_Channel_CFG_Type | GPDMA Channel configuration structure type definition |
| GPDMA_LLI_Type | GPDMA Linker List Item structure type definition |
| I2S_CFG_Type | I2S configuration structure definition |
| I2S_DMAConf_Type | I2S DMA configuration structure definition |
| I2S_MODEConf_Type | I2S mode configuration structure definition |
| LPC_ADC_TypeDef | Analog-to-Digital Converter (ADC) register structure definition |
| LPC_CAN_TypeDef | Controller Area Network Controller (CAN) register structure definition |
| LPC_CANAF_RAM_TypeDef | Controller Area Network Acceptance Filter RAM (CANAF_RAM)structure definition |
| LPC_CANAF_TypeDef | Controller Area Network Acceptance Filter(CANAF) register structure definition |
| LPC_CANCR_TypeDef | Controller Area Network Central (CANCR) register structure definition |
| LPC_DAC_TypeDef | Digital-to-Analog Converter (DAC) register structure definition |
| LPC_EMAC_TypeDef | Ethernet Media Access Controller (EMAC) register structure definition |
| LPC_GPDMA_TypeDef | General Purpose Direct Memory Access (GPDMA) register structure definition |
| LPC_GPDMACH_TypeDef | General Purpose Direct Memory Access Channel (GPDMACH) register structure definition |
| LPC_GPIO_TypeDef | General Purpose Input/Output (GPIO) register structure definition |
| LPC_GPIOINT_TypeDef | General Purpose Input/Output interrupt (GPIOINT) register structure definition |
| LPC_I2C_TypeDef | Inter-Integrated Circuit (I2C) register structure definition |
| LPC_I2S_TypeDef | Inter IC Sound (I2S) register structure definition |
| LPC_MCPWM_TypeDef | Motor Control Pulse-Width Modulation (MCPWM) register structure definition |
| LPC_PINCON_TypeDef | Pin Connect Block (PINCON) register structure definition |
| LPC_PWM_TypeDef | Pulse-Width Modulation (PWM) register structure definition |
| LPC_QEI_TypeDef | Quadrature Encoder Interface (QEI) register structure definition |
| LPC_RIT_TypeDef | Repetitive Interrupt Timer (RIT) register structure definition |
| LPC_RTC_TypeDef | Real-Time Clock (RTC) register structure definition |
| LPC_SC_TypeDef | System Control (SC) register structure definition |
| LPC_SPI_TypeDef | Serial Peripheral Interface (SPI) register structure definition |
| LPC_SSP_TypeDef | Synchronous Serial Communication (SSP) register structure definition |
| LPC_TIM_TypeDef | Timer (TIM) register structure definition |
| LPC_UART0_TypeDef | Universal Asynchronous Receiver Transmitter 0 (UART0) register structure definition |
| LPC_UART1_TypeDef | Universal Asynchronous Receiver Transmitter 1 (UART1) register structure definition |
| LPC_UART_TypeDef | Universal Asynchronous Receiver Transmitter (UART) register structure definition |
| LPC_USB_TypeDef | Universal Serial Bus (USB) register structure definition |
| LPC_WDT_TypeDef | Watchdog Timer (WDT) register structure definition |
| PINSEL_CFG_Type | Pin configuration structure |
| TextLCD | A TextLCD interface for driving 4-bit HD44780-based LCDs |
| UART1_RS485_CTRLCFG_Type | UART1 Full modem - RS485 Control configuration type |
| UART_AB_CFG_Type | Auto Baudrate mode configuration type definition |
| UART_CFG_Type | UART Configuration Structure definition |
| UART_FIFO_CFG_Type | UART FIFO Configuration Structure definition |
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