Wen-ting Lo
Basic
LPG_Config.h@5:b9d12dfdc674, 2019-04-23 (annotated)
- Committer:
- lwtroach
- Date:
- Tue Apr 23 09:53:11 2019 +0000
- Revision:
- 5:b9d12dfdc674
- Parent:
- 2:e90526c0bcbe
- Child:
- 6:86eea1bcf499
Refined the work before
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| lwtroach | 0:6bdfb6ccd136 | 1 | #ifndef _LPG_CONFIG_ |
| lwtroach | 1:347333bac1fb | 2 | #define _LPG_CONFIG_ |
| lwtroach | 1:347333bac1fb | 3 | #ifdef _WISE_1570_ |
| lwtroach | 1:347333bac1fb | 4 | #define GPIO_0 PB_9 |
| lwtroach | 1:347333bac1fb | 5 | #define GPIO_1 PC_7 |
| lwtroach | 1:347333bac1fb | 6 | #define GPIO_2 PB_15 |
| lwtroach | 1:347333bac1fb | 7 | #define GPIO_3 PB_12 |
| lwtroach | 1:347333bac1fb | 8 | #define GPIO_4 PC_8 |
| lwtroach | 1:347333bac1fb | 9 | #define GPIO_5 PC_13 |
| lwtroach | 1:347333bac1fb | 10 | #define UART_TX PC_10 |
| lwtroach | 1:347333bac1fb | 11 | #define UART_RX PC_11 |
| lwtroach | 1:347333bac1fb | 12 | #define ADC_0 PA_1 |
| lwtroach | 1:347333bac1fb | 13 | #define ADC_1 PC_2 |
| lwtroach | 1:347333bac1fb | 14 | #define ADC_2 PC_4 |
| lwtroach | 1:347333bac1fb | 15 | #define PWM_0 PB_0 |
| lwtroach | 1:347333bac1fb | 16 | #define PWM_1 PB_1 |
| lwtroach | 1:347333bac1fb | 17 | #define I2C1_DATA PB_11 |
| lwtroach | 1:347333bac1fb | 18 | #define I2C1_DCLK PB_10 |
| lwtroach | 1:347333bac1fb | 19 | #define I2C0_DATA PB_7 |
| lwtroach | 1:347333bac1fb | 20 | #define I2C0_DCLK PB_6 |
| lwtroach | 5:b9d12dfdc674 | 21 | #else /*BG96*/ |
| lwtroach | 1:347333bac1fb | 22 | #define LED_1 PC_0 |
| lwtroach | 1:347333bac1fb | 23 | #define LED_2 PC_1 |
| lwtroach | 1:347333bac1fb | 24 | #define LED_3 PC_2 |
| lwtroach | 1:347333bac1fb | 25 | #define UART_TX PC_10 |
| lwtroach | 1:347333bac1fb | 26 | #define UART_RX PC_11 |
| lwtroach | 1:347333bac1fb | 27 | #define D_UART_TX PA_9 |
| lwtroach | 1:347333bac1fb | 28 | #define D_UART_RX PA_10 |
| lwtroach | 2:e90526c0bcbe | 29 | #define BTN PA_0 |
| lwtroach | 2:e90526c0bcbe | 30 | #define PWR_LTE PC_3 |
| lwtroach | 2:e90526c0bcbe | 31 | #define KEY PC_4 |
| lwtroach | 2:e90526c0bcbe | 32 | #define RST PC_5 |
| lwtroach | 5:b9d12dfdc674 | 33 | #define D_UART_BR 115200 |
| lwtroach | 5:b9d12dfdc674 | 34 | #define AT_UART_BR 115200 |
| lwtroach | 2:e90526c0bcbe | 35 | #define MEM_START 0x0800C4F0 |
| lwtroach | 2:e90526c0bcbe | 36 | |
| lwtroach | 2:e90526c0bcbe | 37 | |
| lwtroach | 1:347333bac1fb | 38 | #endif |
| lwtroach | 0:6bdfb6ccd136 | 39 | #endif |