Wen-ting Lo
Basic
LPG_Config.h@9:4731ae675a01, 2019-04-24 (annotated)
- Committer:
- lwtroach
- Date:
- Wed Apr 24 06:13:22 2019 +0000
- Branch:
- Flash_Exam
- Revision:
- 9:4731ae675a01
- Parent:
- 7:e556528beeba
When programming the data into flash, the size to API of IAP must be the correct size of data itself, or the algorithm will save the next data after it.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| lwtroach | 0:6bdfb6ccd136 | 1 | #ifndef _LPG_CONFIG_ |
| lwtroach | 1:347333bac1fb | 2 | #define _LPG_CONFIG_ |
| lwtroach | 7:e556528beeba | 3 | #ifdef _WISE_1570_ |
| lwtroach | 7:e556528beeba | 4 | #define GPIO_0 PB_9 |
| lwtroach | 7:e556528beeba | 5 | #define GPIO_1 PC_7 |
| lwtroach | 7:e556528beeba | 6 | #define GPIO_2 PB_15 |
| lwtroach | 7:e556528beeba | 7 | #define GPIO_3 PB_12 |
| lwtroach | 7:e556528beeba | 8 | #define GPIO_4 PC_8 |
| lwtroach | 7:e556528beeba | 9 | #define GPIO_5 PC_13 |
| lwtroach | 7:e556528beeba | 10 | #define UART_TX PC_10 |
| lwtroach | 7:e556528beeba | 11 | #define UART_RX PC_11 |
| lwtroach | 7:e556528beeba | 12 | #define ADC_0 PA_1 |
| lwtroach | 7:e556528beeba | 13 | #define ADC_1 PC_2 |
| lwtroach | 7:e556528beeba | 14 | #define ADC_2 PC_4 |
| lwtroach | 7:e556528beeba | 15 | #define PWM_0 PB_0 |
| lwtroach | 7:e556528beeba | 16 | #define PWM_1 PB_1 |
| lwtroach | 7:e556528beeba | 17 | #define I2C1_DATA PB_11 |
| lwtroach | 7:e556528beeba | 18 | #define I2C1_DCLK PB_10 |
| lwtroach | 7:e556528beeba | 19 | #define I2C0_DATA PB_7 |
| lwtroach | 7:e556528beeba | 20 | #define I2C0_DCLK PB_6 |
| lwtroach | 7:e556528beeba | 21 | #else /*BG96*/ |
| lwtroach | 7:e556528beeba | 22 | #define LED_1 PC_0 |
| lwtroach | 7:e556528beeba | 23 | #define LED_2 PC_1 |
| lwtroach | 7:e556528beeba | 24 | #define LED_3 PC_2 |
| lwtroach | 7:e556528beeba | 25 | #define UART_TX PC_10 |
| lwtroach | 7:e556528beeba | 26 | #define UART_RX PC_11 |
| lwtroach | 7:e556528beeba | 27 | #define D_UART_TX PA_9 |
| lwtroach | 7:e556528beeba | 28 | #define D_UART_RX PA_10 |
| lwtroach | 7:e556528beeba | 29 | #define BTN PA_0 |
| lwtroach | 7:e556528beeba | 30 | #define PWR_LTE PC_3 |
| lwtroach | 7:e556528beeba | 31 | #define KEY PC_4 |
| lwtroach | 7:e556528beeba | 32 | #define RST PC_5 |
| lwtroach | 7:e556528beeba | 33 | #define D_UART_BR 115200 |
| lwtroach | 7:e556528beeba | 34 | #define AT_UART_BR 115200 |
| lwtroach | 2:e90526c0bcbe | 35 | #define MEM_START 0x0800C4F0 |
| lwtroach | 7:e556528beeba | 36 | |
| lwtroach | 7:e556528beeba | 37 | |
| lwtroach | 1:347333bac1fb | 38 | #endif |
| lwtroach | 0:6bdfb6ccd136 | 39 | #endif |