Lukas Formanek / SX1276Lib_LoRa_Access_Point

use with LoRa Access Point

Fork of SX1276Lib by Semtech

sx1276/sx1276-hal.cpp@30:9b08b16f99e5, 2018-04-18 (annotated)

Committer:
lukas_formanek
Date:
Wed Apr 18 22:04:57 2018 +0000
Revision:
30:9b08b16f99e5
Parent:
29:a0a6f7743cc5 
19.4.2018

Who changed what in which revision?

UserRevisionLine numberNew contents of line
GregCr 0:e6ceb13d2d05 1 /*
GregCr 0:e6ceb13d2d05 2 / _____) _ | |
GregCr 0:e6ceb13d2d05 3 ( (____ _____ ____ _| |_ _____ ____| |__
GregCr 0:e6ceb13d2d05 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
GregCr 0:e6ceb13d2d05 5 _____) ) ____| | | || |_| ____( (___| | | |
GregCr 0:e6ceb13d2d05 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
mluis 22:7f3aab69cca9 7 (C) 2014 Semtech
GregCr 0:e6ceb13d2d05 8
GregCr 0:e6ceb13d2d05 9 Description: -
GregCr 0:e6ceb13d2d05 10
GregCr 0:e6ceb13d2d05 11 License: Revised BSD License, see LICENSE.TXT file include in the project
GregCr 0:e6ceb13d2d05 12
GregCr 0:e6ceb13d2d05 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
GregCr 0:e6ceb13d2d05 14 */
GregCr 0:e6ceb13d2d05 15 #include "sx1276-hal.h"
GregCr 0:e6ceb13d2d05 16
mluis 22:7f3aab69cca9 17 const RadioRegisters_t SX1276MB1xAS::RadioRegsInit[] = RADIO_INIT_REGISTERS_VALUE;
GregCr 0:e6ceb13d2d05 18
mluis 21:2e496deb7858 19 SX1276MB1xAS::SX1276MB1xAS( RadioEvents_t *events,
GregCr 0:e6ceb13d2d05 20 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
GregCr 0:e6ceb13d2d05 21 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5,
GregCr 0:e6ceb13d2d05 22 PinName antSwitch )
mluis 21:2e496deb7858 23 : SX1276( events, mosi, miso, sclk, nss, reset, dio0, dio1, dio2, dio3, dio4, dio5 ),
mluis 27:d09a8ef807e2 24 AntSwitch( antSwitch ),
GregCr 12:aa5b3bf7fdf4 25 #if( defined ( TARGET_NUCLEO_L152RE ) )
mluis 27:d09a8ef807e2 26 Fake( D8 )
GregCr 12:aa5b3bf7fdf4 27 #else
mluis 27:d09a8ef807e2 28 Fake( A3 )
GregCr 0:e6ceb13d2d05 29 #endif
GregCr 0:e6ceb13d2d05 30 {
mluis 21:2e496deb7858 31 this->RadioEvents = events;
mluis 21:2e496deb7858 32
GregCr 0:e6ceb13d2d05 33 Reset( );
mluis 27:d09a8ef807e2 34
GregCr 0:e6ceb13d2d05 35 RxChainCalibration( );
mluis 27:d09a8ef807e2 36
GregCr 0:e6ceb13d2d05 37 IoInit( );
mluis 27:d09a8ef807e2 38
GregCr 0:e6ceb13d2d05 39 SetOpMode( RF_OPMODE_SLEEP );
mluis 27:d09a8ef807e2 40
GregCr 0:e6ceb13d2d05 41 IoIrqInit( dioIrq );
mluis 27:d09a8ef807e2 42
GregCr 0:e6ceb13d2d05 43 RadioRegistersInit( );
GregCr 0:e6ceb13d2d05 44
GregCr 0:e6ceb13d2d05 45 SetModem( MODEM_FSK );
GregCr 0:e6ceb13d2d05 46
mluis 21:2e496deb7858 47 this->settings.State = RF_IDLE ;
GregCr 0:e6ceb13d2d05 48 }
GregCr 0:e6ceb13d2d05 49
mluis 27:d09a8ef807e2 50 SX1276MB1xAS::SX1276MB1xAS( RadioEvents_t *events )
GregCr 12:aa5b3bf7fdf4 51 #if defined ( TARGET_NUCLEO_L152RE )
mluis 21:2e496deb7858 52 : SX1276( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, A3, D9 ), // For NUCLEO L152RE dio4 is on port A3
mluis 27:d09a8ef807e2 53 AntSwitch( A4 ),
mluis 27:d09a8ef807e2 54 Fake( D8 )
mluis 20:e05596ba4166 55 #elif defined( TARGET_LPC11U6X )
mluis 21:2e496deb7858 56 : SX1276( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, D8, D9 ),
mluis 27:d09a8ef807e2 57 AntSwitch( P0_23 ),
mluis 27:d09a8ef807e2 58 Fake( A3 )
GregCr 0:e6ceb13d2d05 59 #else
lukas_formanek 30:9b08b16f99e5 60 : SX1276( events, RFM_MOSI, RFM_MISO, RFM_SCK, RFM_NSS, RFM_RST, RFM_DIO0, RFM_DIO1, RFM_DIO2, RFM_DIO3, RFM_DIO4, RFM_DIO5 ), // My board
lukas_formanek 30:9b08b16f99e5 61 // SX1276( events, D11, D12, D13, D10, A0, D6, D3, D4, D5, D7, D9 ), // My board
lukas_formanek 29:a0a6f7743cc5 62 // SX1276( events, D11, D12, D13, D10, A0, D6, D3, D4, D5, D7, D9 ), // NUCLEO F401
mluis 27:d09a8ef807e2 63 AntSwitch( A4 ),
mluis 27:d09a8ef807e2 64 Fake( A3 )
GregCr 0:e6ceb13d2d05 65 #endif
GregCr 0:e6ceb13d2d05 66 {
mluis 21:2e496deb7858 67 this->RadioEvents = events;
mluis 21:2e496deb7858 68
GregCr 0:e6ceb13d2d05 69 Reset( );
mluis 27:d09a8ef807e2 70
GregCr 5:11ec8a6ba4f0 71 boardConnected = UNKNOWN;
mluis 27:d09a8ef807e2 72
GregCr 1:f979673946c0 73 DetectBoardType( );
mluis 27:d09a8ef807e2 74
GregCr 0:e6ceb13d2d05 75 RxChainCalibration( );
mluis 27:d09a8ef807e2 76
GregCr 0:e6ceb13d2d05 77 IoInit( );
mluis 27:d09a8ef807e2 78
GregCr 0:e6ceb13d2d05 79 SetOpMode( RF_OPMODE_SLEEP );
GregCr 0:e6ceb13d2d05 80 IoIrqInit( dioIrq );
mluis 27:d09a8ef807e2 81
GregCr 0:e6ceb13d2d05 82 RadioRegistersInit( );
GregCr 0:e6ceb13d2d05 83
GregCr 0:e6ceb13d2d05 84 SetModem( MODEM_FSK );
GregCr 0:e6ceb13d2d05 85
mluis 21:2e496deb7858 86 this->settings.State = RF_IDLE ;
GregCr 0:e6ceb13d2d05 87 }
GregCr 0:e6ceb13d2d05 88
GregCr 0:e6ceb13d2d05 89 //-------------------------------------------------------------------------
GregCr 0:e6ceb13d2d05 90 // Board relative functions
GregCr 0:e6ceb13d2d05 91 //-------------------------------------------------------------------------
GregCr 2:5eb3066446dd 92 uint8_t SX1276MB1xAS::DetectBoardType( void )
GregCr 1:f979673946c0 93 {
GregCr 5:11ec8a6ba4f0 94 if( boardConnected == UNKNOWN )
GregCr 1:f979673946c0 95 {
mluis 27:d09a8ef807e2 96 this->AntSwitch.input( );
GregCr 5:11ec8a6ba4f0 97 wait_ms( 1 );
mluis 27:d09a8ef807e2 98 if( this->AntSwitch == 1 )
GregCr 5:11ec8a6ba4f0 99 {
GregCr 5:11ec8a6ba4f0 100 boardConnected = SX1276MB1LAS;
GregCr 5:11ec8a6ba4f0 101 }
GregCr 5:11ec8a6ba4f0 102 else
GregCr 5:11ec8a6ba4f0 103 {
GregCr 5:11ec8a6ba4f0 104 boardConnected = SX1276MB1MAS;
GregCr 5:11ec8a6ba4f0 105 }
mluis 27:d09a8ef807e2 106 this->AntSwitch.output( );
GregCr 5:11ec8a6ba4f0 107 wait_ms( 1 );
GregCr 1:f979673946c0 108 }
GregCr 2:5eb3066446dd 109 return ( boardConnected );
GregCr 1:f979673946c0 110 }
GregCr 0:e6ceb13d2d05 111
GregCr 0:e6ceb13d2d05 112 void SX1276MB1xAS::IoInit( void )
GregCr 0:e6ceb13d2d05 113 {
GregCr 0:e6ceb13d2d05 114 AntSwInit( );
GregCr 0:e6ceb13d2d05 115 SpiInit( );
GregCr 0:e6ceb13d2d05 116 }
GregCr 0:e6ceb13d2d05 117
mluis 22:7f3aab69cca9 118 void SX1276MB1xAS::RadioRegistersInit( )
mluis 22:7f3aab69cca9 119 {
GregCr 0:e6ceb13d2d05 120 uint8_t i = 0;
GregCr 0:e6ceb13d2d05 121 for( i = 0; i < sizeof( RadioRegsInit ) / sizeof( RadioRegisters_t ); i++ )
GregCr 0:e6ceb13d2d05 122 {
GregCr 0:e6ceb13d2d05 123 SetModem( RadioRegsInit[i].Modem );
GregCr 0:e6ceb13d2d05 124 Write( RadioRegsInit[i].Addr, RadioRegsInit[i].Value );
GregCr 0:e6ceb13d2d05 125 }
GregCr 0:e6ceb13d2d05 126 }
GregCr 0:e6ceb13d2d05 127
GregCr 0:e6ceb13d2d05 128 void SX1276MB1xAS::SpiInit( void )
GregCr 0:e6ceb13d2d05 129 {
GregCr 0:e6ceb13d2d05 130 nss = 1;
GregCr 0:e6ceb13d2d05 131 spi.format( 8,0 );
GregCr 0:e6ceb13d2d05 132 uint32_t frequencyToSet = 8000000;
mluis 27:d09a8ef807e2 133 #if( defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_LPC11U6X ) )
GregCr 0:e6ceb13d2d05 134 spi.frequency( frequencyToSet );
GregCr 0:e6ceb13d2d05 135 #elif( defined ( TARGET_KL25Z ) ) //busclock frequency is halved -> double the spi frequency to compensate
GregCr 0:e6ceb13d2d05 136 spi.frequency( frequencyToSet * 2 );
GregCr 0:e6ceb13d2d05 137 #else
GregCr 0:e6ceb13d2d05 138 #warning "Check the board's SPI frequency"
GregCr 0:e6ceb13d2d05 139 #endif
GregCr 0:e6ceb13d2d05 140 wait(0.1);
GregCr 0:e6ceb13d2d05 141 }
GregCr 0:e6ceb13d2d05 142
GregCr 0:e6ceb13d2d05 143 void SX1276MB1xAS::IoIrqInit( DioIrqHandler *irqHandlers )
GregCr 0:e6ceb13d2d05 144 {
mluis 27:d09a8ef807e2 145 #if( defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_LPC11U6X ) )
mluis 27:d09a8ef807e2 146 dio0.mode( PullDown );
mluis 27:d09a8ef807e2 147 dio1.mode( PullDown );
mluis 27:d09a8ef807e2 148 dio2.mode( PullDown );
mluis 27:d09a8ef807e2 149 dio3.mode( PullDown );
mluis 27:d09a8ef807e2 150 dio4.mode( PullDown );
mluis 22:7f3aab69cca9 151 #endif
mluis 27:d09a8ef807e2 152 dio0.rise( mbed::callback( this, static_cast< TriggerMB1xAS > ( irqHandlers[0] ) ) );
mluis 27:d09a8ef807e2 153 dio1.rise( mbed::callback( this, static_cast< TriggerMB1xAS > ( irqHandlers[1] ) ) );
mluis 27:d09a8ef807e2 154 dio2.rise( mbed::callback( this, static_cast< TriggerMB1xAS > ( irqHandlers[2] ) ) );
mluis 27:d09a8ef807e2 155 dio3.rise( mbed::callback( this, static_cast< TriggerMB1xAS > ( irqHandlers[3] ) ) );
mluis 27:d09a8ef807e2 156 dio4.rise( mbed::callback( this, static_cast< TriggerMB1xAS > ( irqHandlers[4] ) ) );
GregCr 0:e6ceb13d2d05 157 }
GregCr 0:e6ceb13d2d05 158
GregCr 0:e6ceb13d2d05 159 void SX1276MB1xAS::IoDeInit( void )
GregCr 0:e6ceb13d2d05 160 {
GregCr 0:e6ceb13d2d05 161 //nothing
GregCr 0:e6ceb13d2d05 162 }
GregCr 0:e6ceb13d2d05 163
mluis 27:d09a8ef807e2 164 void SX1276MB1xAS::SetRfTxPower( int8_t power )
mluis 27:d09a8ef807e2 165 {
mluis 27:d09a8ef807e2 166 uint8_t paConfig = 0;
mluis 27:d09a8ef807e2 167 uint8_t paDac = 0;
mluis 27:d09a8ef807e2 168
mluis 27:d09a8ef807e2 169 paConfig = Read( REG_PACONFIG );
mluis 27:d09a8ef807e2 170 paDac = Read( REG_PADAC );
mluis 27:d09a8ef807e2 171
mluis 27:d09a8ef807e2 172 paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | GetPaSelect( this->settings.Channel );
mluis 27:d09a8ef807e2 173 paConfig = ( paConfig & RF_PACONFIG_MAX_POWER_MASK ) | 0x70;
mluis 27:d09a8ef807e2 174
mluis 27:d09a8ef807e2 175 if( ( paConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
mluis 27:d09a8ef807e2 176 {
mluis 27:d09a8ef807e2 177 if( power > 17 )
mluis 27:d09a8ef807e2 178 {
mluis 27:d09a8ef807e2 179 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_ON;
mluis 27:d09a8ef807e2 180 }
mluis 27:d09a8ef807e2 181 else
mluis 27:d09a8ef807e2 182 {
mluis 27:d09a8ef807e2 183 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_OFF;
mluis 27:d09a8ef807e2 184 }
mluis 27:d09a8ef807e2 185 if( ( paDac & RF_PADAC_20DBM_ON ) == RF_PADAC_20DBM_ON )
mluis 27:d09a8ef807e2 186 {
mluis 27:d09a8ef807e2 187 if( power < 5 )
mluis 27:d09a8ef807e2 188 {
mluis 27:d09a8ef807e2 189 power = 5;
mluis 27:d09a8ef807e2 190 }
mluis 27:d09a8ef807e2 191 if( power > 20 )
mluis 27:d09a8ef807e2 192 {
mluis 27:d09a8ef807e2 193 power = 20;
mluis 27:d09a8ef807e2 194 }
mluis 27:d09a8ef807e2 195 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 5 ) & 0x0F );
mluis 27:d09a8ef807e2 196 }
mluis 27:d09a8ef807e2 197 else
mluis 27:d09a8ef807e2 198 {
mluis 27:d09a8ef807e2 199 if( power < 2 )
mluis 27:d09a8ef807e2 200 {
mluis 27:d09a8ef807e2 201 power = 2;
mluis 27:d09a8ef807e2 202 }
mluis 27:d09a8ef807e2 203 if( power > 17 )
mluis 27:d09a8ef807e2 204 {
mluis 27:d09a8ef807e2 205 power = 17;
mluis 27:d09a8ef807e2 206 }
mluis 27:d09a8ef807e2 207 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 2 ) & 0x0F );
mluis 27:d09a8ef807e2 208 }
mluis 27:d09a8ef807e2 209 }
mluis 27:d09a8ef807e2 210 else
mluis 27:d09a8ef807e2 211 {
mluis 27:d09a8ef807e2 212 if( power < -1 )
mluis 27:d09a8ef807e2 213 {
mluis 27:d09a8ef807e2 214 power = -1;
mluis 27:d09a8ef807e2 215 }
mluis 27:d09a8ef807e2 216 if( power > 14 )
mluis 27:d09a8ef807e2 217 {
mluis 27:d09a8ef807e2 218 power = 14;
mluis 27:d09a8ef807e2 219 }
mluis 27:d09a8ef807e2 220 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power + 1 ) & 0x0F );
mluis 27:d09a8ef807e2 221 }
mluis 27:d09a8ef807e2 222 Write( REG_PACONFIG, paConfig );
mluis 27:d09a8ef807e2 223 Write( REG_PADAC, paDac );
mluis 27:d09a8ef807e2 224 }
mluis 27:d09a8ef807e2 225
GregCr 0:e6ceb13d2d05 226 uint8_t SX1276MB1xAS::GetPaSelect( uint32_t channel )
GregCr 0:e6ceb13d2d05 227 {
GregCr 0:e6ceb13d2d05 228 if( channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 229 {
GregCr 3:ca84be1f3fac 230 if( boardConnected == SX1276MB1LAS )
GregCr 1:f979673946c0 231 {
GregCr 1:f979673946c0 232 return RF_PACONFIG_PASELECT_PABOOST;
GregCr 1:f979673946c0 233 }
GregCr 1:f979673946c0 234 else
GregCr 1:f979673946c0 235 {
GregCr 1:f979673946c0 236 return RF_PACONFIG_PASELECT_RFO;
GregCr 1:f979673946c0 237 }
GregCr 0:e6ceb13d2d05 238 }
GregCr 0:e6ceb13d2d05 239 else
GregCr 0:e6ceb13d2d05 240 {
GregCr 0:e6ceb13d2d05 241 return RF_PACONFIG_PASELECT_RFO;
GregCr 0:e6ceb13d2d05 242 }
GregCr 0:e6ceb13d2d05 243 }
GregCr 0:e6ceb13d2d05 244
GregCr 0:e6ceb13d2d05 245 void SX1276MB1xAS::SetAntSwLowPower( bool status )
GregCr 0:e6ceb13d2d05 246 {
GregCr 0:e6ceb13d2d05 247 if( isRadioActive != status )
GregCr 0:e6ceb13d2d05 248 {
GregCr 0:e6ceb13d2d05 249 isRadioActive = status;
GregCr 0:e6ceb13d2d05 250
GregCr 0:e6ceb13d2d05 251 if( status == false )
GregCr 0:e6ceb13d2d05 252 {
GregCr 0:e6ceb13d2d05 253 AntSwInit( );
GregCr 0:e6ceb13d2d05 254 }
GregCr 0:e6ceb13d2d05 255 else
GregCr 0:e6ceb13d2d05 256 {
GregCr 0:e6ceb13d2d05 257 AntSwDeInit( );
GregCr 0:e6ceb13d2d05 258 }
GregCr 0:e6ceb13d2d05 259 }
GregCr 0:e6ceb13d2d05 260 }
GregCr 0:e6ceb13d2d05 261
GregCr 0:e6ceb13d2d05 262 void SX1276MB1xAS::AntSwInit( void )
GregCr 0:e6ceb13d2d05 263 {
mluis 27:d09a8ef807e2 264 this->AntSwitch = 0;
GregCr 0:e6ceb13d2d05 265 }
GregCr 0:e6ceb13d2d05 266
GregCr 0:e6ceb13d2d05 267 void SX1276MB1xAS::AntSwDeInit( void )
GregCr 0:e6ceb13d2d05 268 {
mluis 27:d09a8ef807e2 269 this->AntSwitch = 0;
GregCr 0:e6ceb13d2d05 270 }
GregCr 0:e6ceb13d2d05 271
mluis 27:d09a8ef807e2 272 void SX1276MB1xAS::SetAntSw( uint8_t opMode )
GregCr 0:e6ceb13d2d05 273 {
mluis 27:d09a8ef807e2 274 switch( opMode )
GregCr 0:e6ceb13d2d05 275 {
mluis 27:d09a8ef807e2 276 case RFLR_OPMODE_TRANSMITTER:
mluis 27:d09a8ef807e2 277 this->AntSwitch = 1;
mluis 27:d09a8ef807e2 278 break;
mluis 27:d09a8ef807e2 279 case RFLR_OPMODE_RECEIVER:
mluis 27:d09a8ef807e2 280 case RFLR_OPMODE_RECEIVER_SINGLE:
mluis 27:d09a8ef807e2 281 case RFLR_OPMODE_CAD:
mluis 27:d09a8ef807e2 282 this->AntSwitch = 0;
mluis 27:d09a8ef807e2 283 break;
mluis 27:d09a8ef807e2 284 default:
mluis 27:d09a8ef807e2 285 this->AntSwitch = 0;
mluis 27:d09a8ef807e2 286 break;
GregCr 0:e6ceb13d2d05 287 }
GregCr 0:e6ceb13d2d05 288 }
GregCr 0:e6ceb13d2d05 289
GregCr 0:e6ceb13d2d05 290 bool SX1276MB1xAS::CheckRfFrequency( uint32_t frequency )
GregCr 0:e6ceb13d2d05 291 {
mluis 27:d09a8ef807e2 292 // Implement check. Currently all frequencies are supported
GregCr 0:e6ceb13d2d05 293 return true;
GregCr 0:e6ceb13d2d05 294 }
GregCr 0:e6ceb13d2d05 295
GregCr 0:e6ceb13d2d05 296 void SX1276MB1xAS::Reset( void )
GregCr 0:e6ceb13d2d05 297 {
mluis 27:d09a8ef807e2 298 reset.output( );
GregCr 0:e6ceb13d2d05 299 reset = 0;
GregCr 0:e6ceb13d2d05 300 wait_ms( 1 );
mluis 27:d09a8ef807e2 301 reset.input( );
GregCr 0:e6ceb13d2d05 302 wait_ms( 6 );
GregCr 0:e6ceb13d2d05 303 }
mluis 27:d09a8ef807e2 304
GregCr 0:e6ceb13d2d05 305 void SX1276MB1xAS::Write( uint8_t addr, uint8_t data )
GregCr 0:e6ceb13d2d05 306 {
GregCr 0:e6ceb13d2d05 307 Write( addr, &data, 1 );
GregCr 0:e6ceb13d2d05 308 }
GregCr 0:e6ceb13d2d05 309
GregCr 0:e6ceb13d2d05 310 uint8_t SX1276MB1xAS::Read( uint8_t addr )
GregCr 0:e6ceb13d2d05 311 {
GregCr 0:e6ceb13d2d05 312 uint8_t data;
GregCr 0:e6ceb13d2d05 313 Read( addr, &data, 1 );
GregCr 0:e6ceb13d2d05 314 return data;
GregCr 0:e6ceb13d2d05 315 }
GregCr 0:e6ceb13d2d05 316
GregCr 0:e6ceb13d2d05 317 void SX1276MB1xAS::Write( uint8_t addr, uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 318 {
GregCr 0:e6ceb13d2d05 319 uint8_t i;
GregCr 0:e6ceb13d2d05 320
GregCr 0:e6ceb13d2d05 321 nss = 0;
GregCr 0:e6ceb13d2d05 322 spi.write( addr | 0x80 );
GregCr 0:e6ceb13d2d05 323 for( i = 0; i < size; i++ )
GregCr 0:e6ceb13d2d05 324 {
GregCr 0:e6ceb13d2d05 325 spi.write( buffer[i] );
GregCr 0:e6ceb13d2d05 326 }
GregCr 0:e6ceb13d2d05 327 nss = 1;
GregCr 0:e6ceb13d2d05 328 }
GregCr 0:e6ceb13d2d05 329
GregCr 0:e6ceb13d2d05 330 void SX1276MB1xAS::Read( uint8_t addr, uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 331 {
GregCr 0:e6ceb13d2d05 332 uint8_t i;
GregCr 0:e6ceb13d2d05 333
GregCr 0:e6ceb13d2d05 334 nss = 0;
GregCr 0:e6ceb13d2d05 335 spi.write( addr & 0x7F );
GregCr 0:e6ceb13d2d05 336 for( i = 0; i < size; i++ )
GregCr 0:e6ceb13d2d05 337 {
GregCr 0:e6ceb13d2d05 338 buffer[i] = spi.write( 0 );
GregCr 0:e6ceb13d2d05 339 }
GregCr 0:e6ceb13d2d05 340 nss = 1;
GregCr 0:e6ceb13d2d05 341 }
GregCr 0:e6ceb13d2d05 342
GregCr 0:e6ceb13d2d05 343 void SX1276MB1xAS::WriteFifo( uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 344 {
GregCr 0:e6ceb13d2d05 345 Write( 0, buffer, size );
GregCr 0:e6ceb13d2d05 346 }
GregCr 0:e6ceb13d2d05 347
GregCr 0:e6ceb13d2d05 348 void SX1276MB1xAS::ReadFifo( uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 349 {
GregCr 0:e6ceb13d2d05 350 Read( 0, buffer, size );
GregCr 0:e6ceb13d2d05 351 }