Lukas Formanek / SX1276Lib_LoRa_Access_Point

use with LoRa Access Point

Fork of SX1276Lib by Semtech

sx1276/sx1276.cpp@14:8552d0b840be, 2015-01-07 (annotated)

Committer:
mluis
Date:
Wed Jan 07 08:51:37 2015 +0000
Revision:
14:8552d0b840be
Parent:
13:618826a997e2
Child:
15:04374b1c33fa
Corrected in SetRxConfig method the FSK modem preamble register name.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
GregCr 0:e6ceb13d2d05 1 /*
GregCr 0:e6ceb13d2d05 2 / _____) _ | |
GregCr 0:e6ceb13d2d05 3 ( (____ _____ ____ _| |_ _____ ____| |__
GregCr 0:e6ceb13d2d05 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
GregCr 0:e6ceb13d2d05 5 _____) ) ____| | | || |_| ____( (___| | | |
GregCr 0:e6ceb13d2d05 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
GregCr 8:0fe3e0e8007b 7 ( C )2014 Semtech
GregCr 0:e6ceb13d2d05 8
GregCr 0:e6ceb13d2d05 9 Description: Actual implementation of a SX1276 radio, inherits Radio
GregCr 0:e6ceb13d2d05 10
GregCr 0:e6ceb13d2d05 11 License: Revised BSD License, see LICENSE.TXT file include in the project
GregCr 0:e6ceb13d2d05 12
GregCr 0:e6ceb13d2d05 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
GregCr 0:e6ceb13d2d05 14 */
GregCr 0:e6ceb13d2d05 15 #include "sx1276.h"
GregCr 0:e6ceb13d2d05 16
GregCr 0:e6ceb13d2d05 17 const FskBandwidth_t SX1276::FskBandwidths[] =
GregCr 0:e6ceb13d2d05 18 {
GregCr 0:e6ceb13d2d05 19 { 2600 , 0x17 },
GregCr 0:e6ceb13d2d05 20 { 3100 , 0x0F },
GregCr 0:e6ceb13d2d05 21 { 3900 , 0x07 },
GregCr 0:e6ceb13d2d05 22 { 5200 , 0x16 },
GregCr 0:e6ceb13d2d05 23 { 6300 , 0x0E },
GregCr 0:e6ceb13d2d05 24 { 7800 , 0x06 },
GregCr 0:e6ceb13d2d05 25 { 10400 , 0x15 },
GregCr 0:e6ceb13d2d05 26 { 12500 , 0x0D },
GregCr 0:e6ceb13d2d05 27 { 15600 , 0x05 },
GregCr 0:e6ceb13d2d05 28 { 20800 , 0x14 },
GregCr 0:e6ceb13d2d05 29 { 25000 , 0x0C },
GregCr 0:e6ceb13d2d05 30 { 31300 , 0x04 },
GregCr 0:e6ceb13d2d05 31 { 41700 , 0x13 },
GregCr 0:e6ceb13d2d05 32 { 50000 , 0x0B },
GregCr 0:e6ceb13d2d05 33 { 62500 , 0x03 },
GregCr 0:e6ceb13d2d05 34 { 83333 , 0x12 },
GregCr 0:e6ceb13d2d05 35 { 100000, 0x0A },
GregCr 0:e6ceb13d2d05 36 { 125000, 0x02 },
GregCr 0:e6ceb13d2d05 37 { 166700, 0x11 },
GregCr 0:e6ceb13d2d05 38 { 200000, 0x09 },
GregCr 0:e6ceb13d2d05 39 { 250000, 0x01 }
GregCr 0:e6ceb13d2d05 40 };
GregCr 0:e6ceb13d2d05 41
GregCr 0:e6ceb13d2d05 42
GregCr 7:2b555111463f 43 SX1276::SX1276( void ( *txDone )( ), void ( *txTimeout ) ( ), void ( *rxDone ) ( uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr ),
mluis 13:618826a997e2 44 void ( *rxTimeout ) ( ), void ( *rxError ) ( ), void ( *fhssChangeChannel ) ( uint8_t channelIndex ), void ( *cadDone ) ( bool channelActivityDetected ),
mluis 13:618826a997e2 45 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
GregCr 0:e6ceb13d2d05 46 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5 )
mluis 13:618826a997e2 47 : Radio( txDone, txTimeout, rxDone, rxTimeout, rxError, fhssChangeChannel, cadDone ),
mluis 13:618826a997e2 48 spi( mosi, miso, sclk ),
mluis 13:618826a997e2 49 nss( nss ),
mluis 13:618826a997e2 50 reset( reset ),
mluis 13:618826a997e2 51 dio0( dio0 ), dio1( dio1 ), dio2( dio2 ), dio3( dio3 ), dio4( dio4 ), dio5( dio5 ),
mluis 13:618826a997e2 52 isRadioActive( false )
GregCr 0:e6ceb13d2d05 53 {
mluis 13:618826a997e2 54 wait_ms( 10 );
mluis 13:618826a997e2 55 this->rxTx = 0;
mluis 13:618826a997e2 56 this->rxBuffer = new uint8_t[RX_BUFFER_SIZE];
mluis 13:618826a997e2 57 previousOpMode = RF_OPMODE_STANDBY;
mluis 13:618826a997e2 58
mluis 13:618826a997e2 59 this->dioIrq = new DioIrqHandler[6];
GregCr 0:e6ceb13d2d05 60
mluis 13:618826a997e2 61 this->dioIrq[0] = &SX1276::OnDio0Irq;
mluis 13:618826a997e2 62 this->dioIrq[1] = &SX1276::OnDio1Irq;
mluis 13:618826a997e2 63 this->dioIrq[2] = &SX1276::OnDio2Irq;
mluis 13:618826a997e2 64 this->dioIrq[3] = &SX1276::OnDio3Irq;
mluis 13:618826a997e2 65 this->dioIrq[4] = &SX1276::OnDio4Irq;
mluis 13:618826a997e2 66 this->dioIrq[5] = NULL;
mluis 13:618826a997e2 67
mluis 13:618826a997e2 68 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 69 }
GregCr 0:e6ceb13d2d05 70
GregCr 0:e6ceb13d2d05 71 SX1276::~SX1276( )
GregCr 0:e6ceb13d2d05 72 {
mluis 13:618826a997e2 73 delete this->rxBuffer;
mluis 13:618826a997e2 74 delete this->dioIrq;
GregCr 0:e6ceb13d2d05 75 }
GregCr 0:e6ceb13d2d05 76
GregCr 0:e6ceb13d2d05 77 void SX1276::RxChainCalibration( void )
GregCr 0:e6ceb13d2d05 78 {
GregCr 0:e6ceb13d2d05 79 uint8_t regPaConfigInitVal;
GregCr 0:e6ceb13d2d05 80 uint32_t initialFreq;
GregCr 0:e6ceb13d2d05 81
GregCr 0:e6ceb13d2d05 82 // Save context
GregCr 0:e6ceb13d2d05 83 regPaConfigInitVal = this->Read( REG_PACONFIG );
GregCr 0:e6ceb13d2d05 84 initialFreq = ( double )( ( ( uint32_t )this->Read( REG_FRFMSB ) << 16 ) |
GregCr 0:e6ceb13d2d05 85 ( ( uint32_t )this->Read( REG_FRFMID ) << 8 ) |
GregCr 0:e6ceb13d2d05 86 ( ( uint32_t )this->Read( REG_FRFLSB ) ) ) * ( double )FREQ_STEP;
GregCr 0:e6ceb13d2d05 87
GregCr 0:e6ceb13d2d05 88 // Cut the PA just in case, RFO output, power = -1 dBm
GregCr 0:e6ceb13d2d05 89 this->Write( REG_PACONFIG, 0x00 );
GregCr 0:e6ceb13d2d05 90
GregCr 0:e6ceb13d2d05 91 // Launch Rx chain calibration for LF band
GregCr 0:e6ceb13d2d05 92 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
GregCr 0:e6ceb13d2d05 93 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
GregCr 0:e6ceb13d2d05 94 {
GregCr 0:e6ceb13d2d05 95 }
GregCr 0:e6ceb13d2d05 96
GregCr 0:e6ceb13d2d05 97 // Sets a Frequency in HF band
GregCr 0:e6ceb13d2d05 98 settings.Channel= 868000000 ;
GregCr 0:e6ceb13d2d05 99
GregCr 0:e6ceb13d2d05 100 // Launch Rx chain calibration for HF band
GregCr 0:e6ceb13d2d05 101 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
GregCr 0:e6ceb13d2d05 102 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
GregCr 0:e6ceb13d2d05 103 {
GregCr 0:e6ceb13d2d05 104 }
GregCr 0:e6ceb13d2d05 105
GregCr 0:e6ceb13d2d05 106 // Restore context
GregCr 0:e6ceb13d2d05 107 this->Write( REG_PACONFIG, regPaConfigInitVal );
GregCr 0:e6ceb13d2d05 108 SetChannel( initialFreq );
GregCr 0:e6ceb13d2d05 109 }
GregCr 0:e6ceb13d2d05 110
GregCr 0:e6ceb13d2d05 111 RadioState SX1276::GetState( void )
GregCr 0:e6ceb13d2d05 112 {
GregCr 0:e6ceb13d2d05 113 return this->settings.State;
GregCr 0:e6ceb13d2d05 114 }
GregCr 0:e6ceb13d2d05 115
GregCr 0:e6ceb13d2d05 116 void SX1276::SetChannel( uint32_t freq )
GregCr 0:e6ceb13d2d05 117 {
GregCr 0:e6ceb13d2d05 118 this->settings.Channel = freq;
GregCr 0:e6ceb13d2d05 119 freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP );
GregCr 0:e6ceb13d2d05 120 Write( REG_FRFMSB, ( uint8_t )( ( freq >> 16 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 121 Write( REG_FRFMID, ( uint8_t )( ( freq >> 8 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 122 Write( REG_FRFLSB, ( uint8_t )( freq & 0xFF ) );
GregCr 0:e6ceb13d2d05 123 }
GregCr 0:e6ceb13d2d05 124
GregCr 0:e6ceb13d2d05 125 bool SX1276::IsChannelFree( ModemType modem, uint32_t freq, int8_t rssiThresh )
GregCr 0:e6ceb13d2d05 126 {
GregCr 7:2b555111463f 127 int16_t rssi = 0;
GregCr 0:e6ceb13d2d05 128
GregCr 0:e6ceb13d2d05 129 SetModem( modem );
GregCr 0:e6ceb13d2d05 130
GregCr 0:e6ceb13d2d05 131 SetChannel( freq );
GregCr 0:e6ceb13d2d05 132
GregCr 0:e6ceb13d2d05 133 SetOpMode( RF_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 134
GregCr 4:f0ce52e94d3f 135 wait_ms( 1 );
GregCr 0:e6ceb13d2d05 136
GregCr 0:e6ceb13d2d05 137 rssi = GetRssi( modem );
GregCr 0:e6ceb13d2d05 138
GregCr 0:e6ceb13d2d05 139 Sleep( );
GregCr 0:e6ceb13d2d05 140
GregCr 7:2b555111463f 141 if( rssi > ( int16_t )rssiThresh )
GregCr 0:e6ceb13d2d05 142 {
GregCr 0:e6ceb13d2d05 143 return false;
GregCr 0:e6ceb13d2d05 144 }
GregCr 0:e6ceb13d2d05 145 return true;
GregCr 0:e6ceb13d2d05 146 }
GregCr 0:e6ceb13d2d05 147
GregCr 0:e6ceb13d2d05 148 uint32_t SX1276::Random( void )
GregCr 0:e6ceb13d2d05 149 {
GregCr 0:e6ceb13d2d05 150 uint8_t i;
GregCr 0:e6ceb13d2d05 151 uint32_t rnd = 0;
GregCr 0:e6ceb13d2d05 152
GregCr 0:e6ceb13d2d05 153 /*
GregCr 0:e6ceb13d2d05 154 * Radio setup for random number generation
GregCr 0:e6ceb13d2d05 155 */
GregCr 0:e6ceb13d2d05 156 // Set LoRa modem ON
GregCr 0:e6ceb13d2d05 157 SetModem( MODEM_LORA );
GregCr 0:e6ceb13d2d05 158
GregCr 0:e6ceb13d2d05 159 // Disable LoRa modem interrupts
GregCr 0:e6ceb13d2d05 160 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 0:e6ceb13d2d05 161 RFLR_IRQFLAGS_RXDONE |
GregCr 0:e6ceb13d2d05 162 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 0:e6ceb13d2d05 163 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 0:e6ceb13d2d05 164 RFLR_IRQFLAGS_TXDONE |
GregCr 0:e6ceb13d2d05 165 RFLR_IRQFLAGS_CADDONE |
GregCr 0:e6ceb13d2d05 166 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 0:e6ceb13d2d05 167 RFLR_IRQFLAGS_CADDETECTED );
GregCr 0:e6ceb13d2d05 168
GregCr 0:e6ceb13d2d05 169 // Set radio in continuous reception
GregCr 0:e6ceb13d2d05 170 SetOpMode( RF_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 171
GregCr 0:e6ceb13d2d05 172 for( i = 0; i < 32; i++ )
GregCr 0:e6ceb13d2d05 173 {
GregCr 4:f0ce52e94d3f 174 wait_ms( 1 );
GregCr 0:e6ceb13d2d05 175 // Unfiltered RSSI value reading. Only takes the LSB value
GregCr 0:e6ceb13d2d05 176 rnd |= ( ( uint32_t )Read( REG_LR_RSSIWIDEBAND ) & 0x01 ) << i;
GregCr 0:e6ceb13d2d05 177 }
GregCr 0:e6ceb13d2d05 178
GregCr 0:e6ceb13d2d05 179 Sleep( );
GregCr 0:e6ceb13d2d05 180
GregCr 0:e6ceb13d2d05 181 return rnd;
GregCr 0:e6ceb13d2d05 182 }
GregCr 0:e6ceb13d2d05 183
GregCr 0:e6ceb13d2d05 184 /*!
GregCr 0:e6ceb13d2d05 185 * Returns the known FSK bandwidth registers value
GregCr 0:e6ceb13d2d05 186 *
GregCr 0:e6ceb13d2d05 187 * \param [IN] bandwidth Bandwidth value in Hz
GregCr 0:e6ceb13d2d05 188 * \retval regValue Bandwidth register value.
GregCr 0:e6ceb13d2d05 189 */
GregCr 0:e6ceb13d2d05 190 uint8_t SX1276::GetFskBandwidthRegValue( uint32_t bandwidth )
GregCr 0:e6ceb13d2d05 191 {
GregCr 0:e6ceb13d2d05 192 uint8_t i;
GregCr 0:e6ceb13d2d05 193
GregCr 0:e6ceb13d2d05 194 for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ) - 1; i++ )
GregCr 0:e6ceb13d2d05 195 {
GregCr 0:e6ceb13d2d05 196 if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandwidth ) )
GregCr 0:e6ceb13d2d05 197 {
GregCr 0:e6ceb13d2d05 198 return FskBandwidths[i].RegValue;
GregCr 0:e6ceb13d2d05 199 }
GregCr 0:e6ceb13d2d05 200 }
GregCr 0:e6ceb13d2d05 201 // ERROR: Value not found
GregCr 0:e6ceb13d2d05 202 while( 1 );
GregCr 0:e6ceb13d2d05 203 }
GregCr 0:e6ceb13d2d05 204
GregCr 0:e6ceb13d2d05 205 void SX1276::SetRxConfig( ModemType modem, uint32_t bandwidth,
GregCr 0:e6ceb13d2d05 206 uint32_t datarate, uint8_t coderate,
GregCr 0:e6ceb13d2d05 207 uint32_t bandwidthAfc, uint16_t preambleLen,
GregCr 0:e6ceb13d2d05 208 uint16_t symbTimeout, bool fixLen,
mluis 13:618826a997e2 209 uint8_t payloadLen,
mluis 13:618826a997e2 210 bool crcOn, bool freqHopOn, uint8_t hopPeriod,
GregCr 6:e7f02929cd3d 211 bool iqInverted, bool rxContinuous )
GregCr 0:e6ceb13d2d05 212 {
GregCr 0:e6ceb13d2d05 213 SetModem( modem );
GregCr 0:e6ceb13d2d05 214
GregCr 0:e6ceb13d2d05 215 switch( modem )
GregCr 0:e6ceb13d2d05 216 {
GregCr 0:e6ceb13d2d05 217 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 218 {
GregCr 0:e6ceb13d2d05 219 this->settings.Fsk.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 220 this->settings.Fsk.Datarate = datarate;
GregCr 0:e6ceb13d2d05 221 this->settings.Fsk.BandwidthAfc = bandwidthAfc;
GregCr 0:e6ceb13d2d05 222 this->settings.Fsk.FixLen = fixLen;
mluis 13:618826a997e2 223 this->settings.Fsk.PayloadLen = payloadLen;
GregCr 0:e6ceb13d2d05 224 this->settings.Fsk.CrcOn = crcOn;
GregCr 0:e6ceb13d2d05 225 this->settings.Fsk.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 226 this->settings.Fsk.RxContinuous = rxContinuous;
GregCr 0:e6ceb13d2d05 227 this->settings.Fsk.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 228
GregCr 0:e6ceb13d2d05 229 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
GregCr 0:e6ceb13d2d05 230 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
GregCr 0:e6ceb13d2d05 231 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
GregCr 0:e6ceb13d2d05 232
GregCr 0:e6ceb13d2d05 233 Write( REG_RXBW, GetFskBandwidthRegValue( bandwidth ) );
GregCr 0:e6ceb13d2d05 234 Write( REG_AFCBW, GetFskBandwidthRegValue( bandwidthAfc ) );
GregCr 0:e6ceb13d2d05 235
mluis 14:8552d0b840be 236 Write( REG_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
mluis 14:8552d0b840be 237 Write( REG_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
GregCr 0:e6ceb13d2d05 238
GregCr 0:e6ceb13d2d05 239 Write( REG_PACKETCONFIG1,
GregCr 0:e6ceb13d2d05 240 ( Read( REG_PACKETCONFIG1 ) &
GregCr 0:e6ceb13d2d05 241 RF_PACKETCONFIG1_CRC_MASK &
GregCr 0:e6ceb13d2d05 242 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
GregCr 0:e6ceb13d2d05 243 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
GregCr 0:e6ceb13d2d05 244 ( crcOn << 4 ) );
mluis 13:618826a997e2 245 if( fixLen == 1 )
mluis 13:618826a997e2 246 {
mluis 13:618826a997e2 247 Write( REG_PAYLOADLENGTH, payloadLen );
mluis 13:618826a997e2 248 }
GregCr 0:e6ceb13d2d05 249 }
GregCr 0:e6ceb13d2d05 250 break;
GregCr 0:e6ceb13d2d05 251 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 252 {
GregCr 0:e6ceb13d2d05 253 if( bandwidth > 2 )
GregCr 0:e6ceb13d2d05 254 {
GregCr 0:e6ceb13d2d05 255 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
GregCr 0:e6ceb13d2d05 256 while( 1 );
GregCr 0:e6ceb13d2d05 257 }
GregCr 0:e6ceb13d2d05 258 bandwidth += 7;
GregCr 0:e6ceb13d2d05 259 this->settings.LoRa.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 260 this->settings.LoRa.Datarate = datarate;
GregCr 0:e6ceb13d2d05 261 this->settings.LoRa.Coderate = coderate;
GregCr 0:e6ceb13d2d05 262 this->settings.LoRa.FixLen = fixLen;
mluis 13:618826a997e2 263 this->settings.LoRa.PayloadLen = payloadLen;
GregCr 0:e6ceb13d2d05 264 this->settings.LoRa.CrcOn = crcOn;
mluis 13:618826a997e2 265 this->settings.LoRa.FreqHopOn = freqHopOn;
mluis 13:618826a997e2 266 this->settings.LoRa.HopPeriod = hopPeriod;
GregCr 0:e6ceb13d2d05 267 this->settings.LoRa.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 268 this->settings.LoRa.RxContinuous = rxContinuous;
mluis 13:618826a997e2 269
GregCr 0:e6ceb13d2d05 270 if( datarate > 12 )
GregCr 0:e6ceb13d2d05 271 {
GregCr 0:e6ceb13d2d05 272 datarate = 12;
GregCr 0:e6ceb13d2d05 273 }
GregCr 0:e6ceb13d2d05 274 else if( datarate < 6 )
GregCr 0:e6ceb13d2d05 275 {
GregCr 0:e6ceb13d2d05 276 datarate = 6;
GregCr 0:e6ceb13d2d05 277 }
GregCr 0:e6ceb13d2d05 278
GregCr 0:e6ceb13d2d05 279 if( ( ( bandwidth == 7 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
GregCr 0:e6ceb13d2d05 280 ( ( bandwidth == 8 ) && ( datarate == 12 ) ) )
GregCr 0:e6ceb13d2d05 281 {
GregCr 0:e6ceb13d2d05 282 this->settings.LoRa.LowDatarateOptimize = 0x01;
GregCr 0:e6ceb13d2d05 283 }
GregCr 0:e6ceb13d2d05 284 else
GregCr 0:e6ceb13d2d05 285 {
GregCr 0:e6ceb13d2d05 286 this->settings.LoRa.LowDatarateOptimize = 0x00;
GregCr 0:e6ceb13d2d05 287 }
GregCr 0:e6ceb13d2d05 288
GregCr 0:e6ceb13d2d05 289 Write( REG_LR_MODEMCONFIG1,
GregCr 0:e6ceb13d2d05 290 ( Read( REG_LR_MODEMCONFIG1 ) &
GregCr 0:e6ceb13d2d05 291 RFLR_MODEMCONFIG1_BW_MASK &
GregCr 0:e6ceb13d2d05 292 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
GregCr 0:e6ceb13d2d05 293 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
GregCr 0:e6ceb13d2d05 294 ( bandwidth << 4 ) | ( coderate << 1 ) |
GregCr 0:e6ceb13d2d05 295 fixLen );
GregCr 0:e6ceb13d2d05 296
GregCr 0:e6ceb13d2d05 297 Write( REG_LR_MODEMCONFIG2,
GregCr 0:e6ceb13d2d05 298 ( Read( REG_LR_MODEMCONFIG2 ) &
GregCr 0:e6ceb13d2d05 299 RFLR_MODEMCONFIG2_SF_MASK &
GregCr 0:e6ceb13d2d05 300 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK &
GregCr 0:e6ceb13d2d05 301 RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) |
GregCr 0:e6ceb13d2d05 302 ( datarate << 4 ) | ( crcOn << 2 ) |
GregCr 0:e6ceb13d2d05 303 ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) );
GregCr 0:e6ceb13d2d05 304
GregCr 0:e6ceb13d2d05 305 Write( REG_LR_MODEMCONFIG3,
GregCr 0:e6ceb13d2d05 306 ( Read( REG_LR_MODEMCONFIG3 ) &
GregCr 0:e6ceb13d2d05 307 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 308 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
GregCr 0:e6ceb13d2d05 309
GregCr 0:e6ceb13d2d05 310 Write( REG_LR_SYMBTIMEOUTLSB, ( uint8_t )( symbTimeout & 0xFF ) );
GregCr 0:e6ceb13d2d05 311
GregCr 0:e6ceb13d2d05 312 Write( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 313 Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
GregCr 0:e6ceb13d2d05 314
mluis 13:618826a997e2 315 if( fixLen == 1 )
mluis 13:618826a997e2 316 {
mluis 13:618826a997e2 317 Write( REG_LR_PAYLOADLENGTH, payloadLen );
mluis 13:618826a997e2 318 }
mluis 13:618826a997e2 319
GregCr 6:e7f02929cd3d 320 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 321 {
GregCr 6:e7f02929cd3d 322 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
GregCr 6:e7f02929cd3d 323 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
GregCr 6:e7f02929cd3d 324 }
GregCr 6:e7f02929cd3d 325
GregCr 0:e6ceb13d2d05 326 if( datarate == 6 )
GregCr 0:e6ceb13d2d05 327 {
GregCr 0:e6ceb13d2d05 328 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 329 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 330 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 331 RFLR_DETECTIONOPTIMIZE_SF6 );
GregCr 0:e6ceb13d2d05 332 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 333 RFLR_DETECTIONTHRESH_SF6 );
GregCr 0:e6ceb13d2d05 334 }
GregCr 0:e6ceb13d2d05 335 else
GregCr 0:e6ceb13d2d05 336 {
GregCr 0:e6ceb13d2d05 337 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 338 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 339 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 340 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 341 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 342 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 343 }
GregCr 0:e6ceb13d2d05 344 }
GregCr 0:e6ceb13d2d05 345 break;
GregCr 0:e6ceb13d2d05 346 }
GregCr 0:e6ceb13d2d05 347 }
GregCr 0:e6ceb13d2d05 348
GregCr 0:e6ceb13d2d05 349 void SX1276::SetTxConfig( ModemType modem, int8_t power, uint32_t fdev,
GregCr 0:e6ceb13d2d05 350 uint32_t bandwidth, uint32_t datarate,
GregCr 0:e6ceb13d2d05 351 uint8_t coderate, uint16_t preambleLen,
mluis 13:618826a997e2 352 bool fixLen, bool crcOn, bool freqHopOn,
mluis 13:618826a997e2 353 uint8_t hopPeriod, bool iqInverted, uint32_t timeout )
GregCr 0:e6ceb13d2d05 354 {
GregCr 0:e6ceb13d2d05 355 uint8_t paConfig = 0;
GregCr 0:e6ceb13d2d05 356 uint8_t paDac = 0;
GregCr 0:e6ceb13d2d05 357
GregCr 0:e6ceb13d2d05 358 SetModem( modem );
GregCr 0:e6ceb13d2d05 359
GregCr 0:e6ceb13d2d05 360 paConfig = Read( REG_PACONFIG );
GregCr 0:e6ceb13d2d05 361 paDac = Read( REG_PADAC );
GregCr 0:e6ceb13d2d05 362
GregCr 0:e6ceb13d2d05 363 paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | GetPaSelect( this->settings.Channel );
GregCr 0:e6ceb13d2d05 364 paConfig = ( paConfig & RF_PACONFIG_MAX_POWER_MASK ) | 0x70;
GregCr 0:e6ceb13d2d05 365
GregCr 0:e6ceb13d2d05 366 if( ( paConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
GregCr 0:e6ceb13d2d05 367 {
GregCr 0:e6ceb13d2d05 368 if( power > 17 )
GregCr 0:e6ceb13d2d05 369 {
GregCr 0:e6ceb13d2d05 370 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_ON;
GregCr 0:e6ceb13d2d05 371 }
GregCr 0:e6ceb13d2d05 372 else
GregCr 0:e6ceb13d2d05 373 {
GregCr 0:e6ceb13d2d05 374 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_OFF;
GregCr 0:e6ceb13d2d05 375 }
GregCr 0:e6ceb13d2d05 376 if( ( paDac & RF_PADAC_20DBM_ON ) == RF_PADAC_20DBM_ON )
GregCr 0:e6ceb13d2d05 377 {
GregCr 0:e6ceb13d2d05 378 if( power < 5 )
GregCr 0:e6ceb13d2d05 379 {
GregCr 0:e6ceb13d2d05 380 power = 5;
GregCr 0:e6ceb13d2d05 381 }
GregCr 0:e6ceb13d2d05 382 if( power > 20 )
GregCr 0:e6ceb13d2d05 383 {
GregCr 0:e6ceb13d2d05 384 power = 20;
GregCr 0:e6ceb13d2d05 385 }
GregCr 0:e6ceb13d2d05 386 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 5 ) & 0x0F );
GregCr 0:e6ceb13d2d05 387 }
GregCr 0:e6ceb13d2d05 388 else
GregCr 0:e6ceb13d2d05 389 {
GregCr 0:e6ceb13d2d05 390 if( power < 2 )
GregCr 0:e6ceb13d2d05 391 {
GregCr 0:e6ceb13d2d05 392 power = 2;
GregCr 0:e6ceb13d2d05 393 }
GregCr 0:e6ceb13d2d05 394 if( power > 17 )
GregCr 0:e6ceb13d2d05 395 {
GregCr 0:e6ceb13d2d05 396 power = 17;
GregCr 0:e6ceb13d2d05 397 }
GregCr 0:e6ceb13d2d05 398 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 2 ) & 0x0F );
GregCr 0:e6ceb13d2d05 399 }
GregCr 0:e6ceb13d2d05 400 }
GregCr 0:e6ceb13d2d05 401 else
GregCr 0:e6ceb13d2d05 402 {
GregCr 0:e6ceb13d2d05 403 if( power < -1 )
GregCr 0:e6ceb13d2d05 404 {
GregCr 0:e6ceb13d2d05 405 power = -1;
GregCr 0:e6ceb13d2d05 406 }
GregCr 0:e6ceb13d2d05 407 if( power > 14 )
GregCr 0:e6ceb13d2d05 408 {
GregCr 0:e6ceb13d2d05 409 power = 14;
GregCr 0:e6ceb13d2d05 410 }
GregCr 0:e6ceb13d2d05 411 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power + 1 ) & 0x0F );
GregCr 0:e6ceb13d2d05 412 }
GregCr 0:e6ceb13d2d05 413 Write( REG_PACONFIG, paConfig );
GregCr 0:e6ceb13d2d05 414 Write( REG_PADAC, paDac );
GregCr 0:e6ceb13d2d05 415
GregCr 0:e6ceb13d2d05 416 switch( modem )
GregCr 0:e6ceb13d2d05 417 {
GregCr 0:e6ceb13d2d05 418 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 419 {
GregCr 0:e6ceb13d2d05 420 this->settings.Fsk.Power = power;
GregCr 0:e6ceb13d2d05 421 this->settings.Fsk.Fdev = fdev;
GregCr 0:e6ceb13d2d05 422 this->settings.Fsk.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 423 this->settings.Fsk.Datarate = datarate;
GregCr 0:e6ceb13d2d05 424 this->settings.Fsk.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 425 this->settings.Fsk.FixLen = fixLen;
GregCr 0:e6ceb13d2d05 426 this->settings.Fsk.CrcOn = crcOn;
GregCr 0:e6ceb13d2d05 427 this->settings.Fsk.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 428 this->settings.Fsk.TxTimeout = timeout;
GregCr 0:e6ceb13d2d05 429
GregCr 0:e6ceb13d2d05 430 fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP );
GregCr 0:e6ceb13d2d05 431 Write( REG_FDEVMSB, ( uint8_t )( fdev >> 8 ) );
GregCr 0:e6ceb13d2d05 432 Write( REG_FDEVLSB, ( uint8_t )( fdev & 0xFF ) );
GregCr 0:e6ceb13d2d05 433
GregCr 0:e6ceb13d2d05 434 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
GregCr 0:e6ceb13d2d05 435 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
GregCr 0:e6ceb13d2d05 436 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
GregCr 0:e6ceb13d2d05 437
GregCr 0:e6ceb13d2d05 438 Write( REG_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
GregCr 0:e6ceb13d2d05 439 Write( REG_PREAMBLELSB, preambleLen & 0xFF );
GregCr 0:e6ceb13d2d05 440
GregCr 0:e6ceb13d2d05 441 Write( REG_PACKETCONFIG1,
GregCr 0:e6ceb13d2d05 442 ( Read( REG_PACKETCONFIG1 ) &
GregCr 0:e6ceb13d2d05 443 RF_PACKETCONFIG1_CRC_MASK &
GregCr 0:e6ceb13d2d05 444 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
GregCr 0:e6ceb13d2d05 445 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
GregCr 0:e6ceb13d2d05 446 ( crcOn << 4 ) );
GregCr 0:e6ceb13d2d05 447 }
GregCr 0:e6ceb13d2d05 448 break;
GregCr 0:e6ceb13d2d05 449 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 450 {
GregCr 0:e6ceb13d2d05 451 this->settings.LoRa.Power = power;
GregCr 0:e6ceb13d2d05 452 if( bandwidth > 2 )
GregCr 0:e6ceb13d2d05 453 {
GregCr 0:e6ceb13d2d05 454 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
GregCr 0:e6ceb13d2d05 455 while( 1 );
GregCr 0:e6ceb13d2d05 456 }
GregCr 0:e6ceb13d2d05 457 bandwidth += 7;
GregCr 0:e6ceb13d2d05 458 this->settings.LoRa.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 459 this->settings.LoRa.Datarate = datarate;
GregCr 0:e6ceb13d2d05 460 this->settings.LoRa.Coderate = coderate;
GregCr 0:e6ceb13d2d05 461 this->settings.LoRa.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 462 this->settings.LoRa.FixLen = fixLen;
GregCr 0:e6ceb13d2d05 463 this->settings.LoRa.CrcOn = crcOn;
mluis 13:618826a997e2 464 this->settings.LoRa.FreqHopOn = freqHopOn;
mluis 13:618826a997e2 465 this->settings.LoRa.HopPeriod = hopPeriod;
GregCr 0:e6ceb13d2d05 466 this->settings.LoRa.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 467 this->settings.LoRa.TxTimeout = timeout;
GregCr 0:e6ceb13d2d05 468
GregCr 0:e6ceb13d2d05 469 if( datarate > 12 )
GregCr 0:e6ceb13d2d05 470 {
GregCr 0:e6ceb13d2d05 471 datarate = 12;
GregCr 0:e6ceb13d2d05 472 }
GregCr 0:e6ceb13d2d05 473 else if( datarate < 6 )
GregCr 0:e6ceb13d2d05 474 {
GregCr 0:e6ceb13d2d05 475 datarate = 6;
GregCr 0:e6ceb13d2d05 476 }
GregCr 0:e6ceb13d2d05 477 if( ( ( bandwidth == 7 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
GregCr 0:e6ceb13d2d05 478 ( ( bandwidth == 8 ) && ( datarate == 12 ) ) )
GregCr 0:e6ceb13d2d05 479 {
GregCr 0:e6ceb13d2d05 480 this->settings.LoRa.LowDatarateOptimize = 0x01;
GregCr 0:e6ceb13d2d05 481 }
GregCr 0:e6ceb13d2d05 482 else
GregCr 0:e6ceb13d2d05 483 {
GregCr 0:e6ceb13d2d05 484 this->settings.LoRa.LowDatarateOptimize = 0x00;
GregCr 0:e6ceb13d2d05 485 }
GregCr 6:e7f02929cd3d 486
GregCr 6:e7f02929cd3d 487 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 488 {
GregCr 6:e7f02929cd3d 489 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
GregCr 6:e7f02929cd3d 490 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
GregCr 6:e7f02929cd3d 491 }
GregCr 6:e7f02929cd3d 492
GregCr 0:e6ceb13d2d05 493 Write( REG_LR_MODEMCONFIG1,
GregCr 0:e6ceb13d2d05 494 ( Read( REG_LR_MODEMCONFIG1 ) &
GregCr 0:e6ceb13d2d05 495 RFLR_MODEMCONFIG1_BW_MASK &
GregCr 0:e6ceb13d2d05 496 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
GregCr 0:e6ceb13d2d05 497 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
GregCr 0:e6ceb13d2d05 498 ( bandwidth << 4 ) | ( coderate << 1 ) |
GregCr 0:e6ceb13d2d05 499 fixLen );
GregCr 0:e6ceb13d2d05 500
GregCr 0:e6ceb13d2d05 501 Write( REG_LR_MODEMCONFIG2,
GregCr 0:e6ceb13d2d05 502 ( Read( REG_LR_MODEMCONFIG2 ) &
GregCr 0:e6ceb13d2d05 503 RFLR_MODEMCONFIG2_SF_MASK &
GregCr 0:e6ceb13d2d05 504 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK ) |
GregCr 0:e6ceb13d2d05 505 ( datarate << 4 ) | ( crcOn << 2 ) );
GregCr 0:e6ceb13d2d05 506
GregCr 0:e6ceb13d2d05 507 Write( REG_LR_MODEMCONFIG3,
GregCr 0:e6ceb13d2d05 508 ( Read( REG_LR_MODEMCONFIG3 ) &
GregCr 0:e6ceb13d2d05 509 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 510 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
GregCr 0:e6ceb13d2d05 511
GregCr 0:e6ceb13d2d05 512 Write( REG_LR_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
GregCr 0:e6ceb13d2d05 513 Write( REG_LR_PREAMBLELSB, preambleLen & 0xFF );
GregCr 0:e6ceb13d2d05 514
GregCr 0:e6ceb13d2d05 515 if( datarate == 6 )
GregCr 0:e6ceb13d2d05 516 {
GregCr 0:e6ceb13d2d05 517 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 518 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 519 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 520 RFLR_DETECTIONOPTIMIZE_SF6 );
GregCr 0:e6ceb13d2d05 521 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 522 RFLR_DETECTIONTHRESH_SF6 );
GregCr 0:e6ceb13d2d05 523 }
GregCr 0:e6ceb13d2d05 524 else
GregCr 0:e6ceb13d2d05 525 {
GregCr 0:e6ceb13d2d05 526 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 527 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 528 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 529 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 530 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 531 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 532 }
GregCr 0:e6ceb13d2d05 533 }
GregCr 0:e6ceb13d2d05 534 break;
GregCr 0:e6ceb13d2d05 535 }
GregCr 0:e6ceb13d2d05 536 }
GregCr 0:e6ceb13d2d05 537
GregCr 0:e6ceb13d2d05 538 double SX1276::TimeOnAir( ModemType modem, uint8_t pktLen )
GregCr 0:e6ceb13d2d05 539 {
GregCr 0:e6ceb13d2d05 540 double airTime = 0.0;
GregCr 0:e6ceb13d2d05 541
GregCr 0:e6ceb13d2d05 542 switch( modem )
GregCr 0:e6ceb13d2d05 543 {
GregCr 0:e6ceb13d2d05 544 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 545 {
GregCr 4:f0ce52e94d3f 546 airTime = ceil( ( 8 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 547 ( ( Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + 1 ) +
GregCr 0:e6ceb13d2d05 548 ( ( this->settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) +
GregCr 0:e6ceb13d2d05 549 ( ( ( Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK ) != 0x00 ) ? 1.0 : 0 ) +
GregCr 0:e6ceb13d2d05 550 pktLen +
GregCr 0:e6ceb13d2d05 551 ( ( this->settings.Fsk.CrcOn == 0x01 ) ? 2.0 : 0 ) ) /
GregCr 0:e6ceb13d2d05 552 this->settings.Fsk.Datarate ) * 1e6 );
GregCr 0:e6ceb13d2d05 553 }
GregCr 0:e6ceb13d2d05 554 break;
GregCr 0:e6ceb13d2d05 555 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 556 {
GregCr 0:e6ceb13d2d05 557 double bw = 0.0;
GregCr 0:e6ceb13d2d05 558 // REMARK: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
GregCr 0:e6ceb13d2d05 559 switch( this->settings.LoRa.Bandwidth )
GregCr 0:e6ceb13d2d05 560 {
GregCr 0:e6ceb13d2d05 561 //case 0: // 7.8 kHz
GregCr 0:e6ceb13d2d05 562 // bw = 78e2;
GregCr 0:e6ceb13d2d05 563 // break;
GregCr 0:e6ceb13d2d05 564 //case 1: // 10.4 kHz
GregCr 0:e6ceb13d2d05 565 // bw = 104e2;
GregCr 0:e6ceb13d2d05 566 // break;
GregCr 0:e6ceb13d2d05 567 //case 2: // 15.6 kHz
GregCr 0:e6ceb13d2d05 568 // bw = 156e2;
GregCr 0:e6ceb13d2d05 569 // break;
GregCr 0:e6ceb13d2d05 570 //case 3: // 20.8 kHz
GregCr 0:e6ceb13d2d05 571 // bw = 208e2;
GregCr 0:e6ceb13d2d05 572 // break;
GregCr 0:e6ceb13d2d05 573 //case 4: // 31.2 kHz
GregCr 0:e6ceb13d2d05 574 // bw = 312e2;
GregCr 0:e6ceb13d2d05 575 // break;
GregCr 0:e6ceb13d2d05 576 //case 5: // 41.4 kHz
GregCr 0:e6ceb13d2d05 577 // bw = 414e2;
GregCr 0:e6ceb13d2d05 578 // break;
GregCr 0:e6ceb13d2d05 579 //case 6: // 62.5 kHz
GregCr 0:e6ceb13d2d05 580 // bw = 625e2;
GregCr 0:e6ceb13d2d05 581 // break;
GregCr 0:e6ceb13d2d05 582 case 7: // 125 kHz
GregCr 0:e6ceb13d2d05 583 bw = 125e3;
GregCr 0:e6ceb13d2d05 584 break;
GregCr 0:e6ceb13d2d05 585 case 8: // 250 kHz
GregCr 0:e6ceb13d2d05 586 bw = 250e3;
GregCr 0:e6ceb13d2d05 587 break;
GregCr 0:e6ceb13d2d05 588 case 9: // 500 kHz
GregCr 0:e6ceb13d2d05 589 bw = 500e3;
GregCr 0:e6ceb13d2d05 590 break;
GregCr 0:e6ceb13d2d05 591 }
GregCr 0:e6ceb13d2d05 592
GregCr 0:e6ceb13d2d05 593 // Symbol rate : time for one symbol (secs)
GregCr 0:e6ceb13d2d05 594 double rs = bw / ( 1 << this->settings.LoRa.Datarate );
GregCr 0:e6ceb13d2d05 595 double ts = 1 / rs;
GregCr 0:e6ceb13d2d05 596 // time of preamble
GregCr 0:e6ceb13d2d05 597 double tPreamble = ( this->settings.LoRa.PreambleLen + 4.25 ) * ts;
GregCr 0:e6ceb13d2d05 598 // Symbol length of payload and time
GregCr 0:e6ceb13d2d05 599 double tmp = ceil( ( 8 * pktLen - 4 * this->settings.LoRa.Datarate +
GregCr 0:e6ceb13d2d05 600 28 + 16 * this->settings.LoRa.CrcOn -
GregCr 0:e6ceb13d2d05 601 ( this->settings.LoRa.FixLen ? 20 : 0 ) ) /
GregCr 0:e6ceb13d2d05 602 ( double )( 4 * this->settings.LoRa.Datarate -
GregCr 0:e6ceb13d2d05 603 ( ( this->settings.LoRa.LowDatarateOptimize > 0 ) ? 8 : 0 ) ) ) *
GregCr 0:e6ceb13d2d05 604 ( this->settings.LoRa.Coderate + 4 );
GregCr 0:e6ceb13d2d05 605 double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 );
GregCr 0:e6ceb13d2d05 606 double tPayload = nPayload * ts;
GregCr 0:e6ceb13d2d05 607 // Time on air
GregCr 0:e6ceb13d2d05 608 double tOnAir = tPreamble + tPayload;
GregCr 0:e6ceb13d2d05 609 // return us secs
GregCr 0:e6ceb13d2d05 610 airTime = floor( tOnAir * 1e6 + 0.999 );
GregCr 0:e6ceb13d2d05 611 }
GregCr 0:e6ceb13d2d05 612 break;
GregCr 0:e6ceb13d2d05 613 }
GregCr 0:e6ceb13d2d05 614 return airTime;
GregCr 0:e6ceb13d2d05 615 }
GregCr 0:e6ceb13d2d05 616
GregCr 0:e6ceb13d2d05 617 void SX1276::Send( uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 618 {
GregCr 0:e6ceb13d2d05 619 uint32_t txTimeout = 0;
GregCr 0:e6ceb13d2d05 620
GregCr 5:11ec8a6ba4f0 621 this->settings.State = IDLE;
GregCr 5:11ec8a6ba4f0 622
GregCr 0:e6ceb13d2d05 623 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 624 {
GregCr 0:e6ceb13d2d05 625 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 626 {
GregCr 0:e6ceb13d2d05 627 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 628 this->settings.FskPacketHandler.Size = size;
GregCr 0:e6ceb13d2d05 629
GregCr 0:e6ceb13d2d05 630 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 631 {
GregCr 0:e6ceb13d2d05 632 WriteFifo( ( uint8_t* )&size, 1 );
GregCr 0:e6ceb13d2d05 633 }
GregCr 0:e6ceb13d2d05 634 else
GregCr 0:e6ceb13d2d05 635 {
GregCr 0:e6ceb13d2d05 636 Write( REG_PAYLOADLENGTH, size );
GregCr 0:e6ceb13d2d05 637 }
GregCr 0:e6ceb13d2d05 638
GregCr 0:e6ceb13d2d05 639 if( ( size > 0 ) && ( size <= 64 ) )
GregCr 0:e6ceb13d2d05 640 {
GregCr 0:e6ceb13d2d05 641 this->settings.FskPacketHandler.ChunkSize = size;
GregCr 0:e6ceb13d2d05 642 }
GregCr 0:e6ceb13d2d05 643 else
GregCr 0:e6ceb13d2d05 644 {
GregCr 0:e6ceb13d2d05 645 this->settings.FskPacketHandler.ChunkSize = 32;
GregCr 0:e6ceb13d2d05 646 }
GregCr 0:e6ceb13d2d05 647
GregCr 0:e6ceb13d2d05 648 // Write payload buffer
GregCr 0:e6ceb13d2d05 649 WriteFifo( buffer, this->settings.FskPacketHandler.ChunkSize );
GregCr 0:e6ceb13d2d05 650 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
GregCr 0:e6ceb13d2d05 651 txTimeout = this->settings.Fsk.TxTimeout;
GregCr 0:e6ceb13d2d05 652 }
GregCr 0:e6ceb13d2d05 653 break;
GregCr 0:e6ceb13d2d05 654 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 655 {
GregCr 0:e6ceb13d2d05 656 if( this->settings.LoRa.IqInverted == true )
GregCr 0:e6ceb13d2d05 657 {
GregCr 0:e6ceb13d2d05 658 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON ) );
GregCr 0:e6ceb13d2d05 659 }
GregCr 0:e6ceb13d2d05 660 else
GregCr 0:e6ceb13d2d05 661 {
GregCr 0:e6ceb13d2d05 662 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
GregCr 0:e6ceb13d2d05 663 }
GregCr 0:e6ceb13d2d05 664
GregCr 0:e6ceb13d2d05 665 this->settings.LoRaPacketHandler.Size = size;
GregCr 0:e6ceb13d2d05 666
GregCr 0:e6ceb13d2d05 667 // Initializes the payload size
GregCr 0:e6ceb13d2d05 668 Write( REG_LR_PAYLOADLENGTH, size );
GregCr 0:e6ceb13d2d05 669
GregCr 0:e6ceb13d2d05 670 // Full buffer used for Tx
GregCr 0:e6ceb13d2d05 671 Write( REG_LR_FIFOTXBASEADDR, 0 );
GregCr 0:e6ceb13d2d05 672 Write( REG_LR_FIFOADDRPTR, 0 );
GregCr 0:e6ceb13d2d05 673
GregCr 0:e6ceb13d2d05 674 // FIFO operations can not take place in Sleep mode
GregCr 0:e6ceb13d2d05 675 if( ( Read( REG_OPMODE ) & ~RF_OPMODE_MASK ) == RF_OPMODE_SLEEP )
GregCr 0:e6ceb13d2d05 676 {
GregCr 0:e6ceb13d2d05 677 Standby( );
GregCr 4:f0ce52e94d3f 678 wait_ms( 1 );
GregCr 0:e6ceb13d2d05 679 }
GregCr 0:e6ceb13d2d05 680 // Write payload buffer
GregCr 0:e6ceb13d2d05 681 WriteFifo( buffer, size );
GregCr 0:e6ceb13d2d05 682 txTimeout = this->settings.LoRa.TxTimeout;
GregCr 0:e6ceb13d2d05 683 }
GregCr 0:e6ceb13d2d05 684 break;
GregCr 0:e6ceb13d2d05 685 }
GregCr 0:e6ceb13d2d05 686
GregCr 0:e6ceb13d2d05 687 Tx( txTimeout );
GregCr 0:e6ceb13d2d05 688 }
GregCr 0:e6ceb13d2d05 689
GregCr 0:e6ceb13d2d05 690 void SX1276::Sleep( void )
GregCr 0:e6ceb13d2d05 691 {
mluis 13:618826a997e2 692 // Initialize driver timeout timers
mluis 13:618826a997e2 693 txTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 694 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 695 SetOpMode( RF_OPMODE_SLEEP );
GregCr 0:e6ceb13d2d05 696 }
GregCr 0:e6ceb13d2d05 697
GregCr 0:e6ceb13d2d05 698 void SX1276::Standby( void )
GregCr 0:e6ceb13d2d05 699 {
GregCr 0:e6ceb13d2d05 700 txTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 701 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 702 SetOpMode( RF_OPMODE_STANDBY );
GregCr 0:e6ceb13d2d05 703 }
GregCr 0:e6ceb13d2d05 704
GregCr 0:e6ceb13d2d05 705 void SX1276::Rx( uint32_t timeout )
GregCr 0:e6ceb13d2d05 706 {
GregCr 0:e6ceb13d2d05 707 bool rxContinuous = false;
GregCr 6:e7f02929cd3d 708
GregCr 0:e6ceb13d2d05 709 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 710 {
GregCr 0:e6ceb13d2d05 711 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 712 {
GregCr 0:e6ceb13d2d05 713 rxContinuous = this->settings.Fsk.RxContinuous;
GregCr 0:e6ceb13d2d05 714
GregCr 0:e6ceb13d2d05 715 // DIO0=PayloadReady
GregCr 0:e6ceb13d2d05 716 // DIO1=FifoLevel
GregCr 0:e6ceb13d2d05 717 // DIO2=SyncAddr
GregCr 0:e6ceb13d2d05 718 // DIO3=FifoEmpty
GregCr 0:e6ceb13d2d05 719 // DIO4=Preamble
GregCr 0:e6ceb13d2d05 720 // DIO5=ModeReady
GregCr 5:11ec8a6ba4f0 721 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK & RF_DIOMAPPING1_DIO1_MASK &
GregCr 0:e6ceb13d2d05 722 RF_DIOMAPPING1_DIO2_MASK ) |
GregCr 0:e6ceb13d2d05 723 RF_DIOMAPPING1_DIO0_00 |
GregCr 0:e6ceb13d2d05 724 RF_DIOMAPPING1_DIO2_11 );
GregCr 0:e6ceb13d2d05 725
GregCr 0:e6ceb13d2d05 726 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
GregCr 0:e6ceb13d2d05 727 RF_DIOMAPPING2_MAP_MASK ) |
GregCr 0:e6ceb13d2d05 728 RF_DIOMAPPING2_DIO4_11 |
GregCr 0:e6ceb13d2d05 729 RF_DIOMAPPING2_MAP_PREAMBLEDETECT );
GregCr 0:e6ceb13d2d05 730
GregCr 0:e6ceb13d2d05 731 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
GregCr 0:e6ceb13d2d05 732
GregCr 0:e6ceb13d2d05 733 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 734 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 735 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 736 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 737 }
GregCr 0:e6ceb13d2d05 738 break;
GregCr 0:e6ceb13d2d05 739 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 740 {
GregCr 0:e6ceb13d2d05 741 if( this->settings.LoRa.IqInverted == true )
GregCr 0:e6ceb13d2d05 742 {
GregCr 0:e6ceb13d2d05 743 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF ) );
GregCr 0:e6ceb13d2d05 744 }
GregCr 0:e6ceb13d2d05 745 else
GregCr 0:e6ceb13d2d05 746 {
GregCr 0:e6ceb13d2d05 747 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
GregCr 0:e6ceb13d2d05 748 }
GregCr 0:e6ceb13d2d05 749
GregCr 0:e6ceb13d2d05 750 rxContinuous = this->settings.LoRa.RxContinuous;
GregCr 0:e6ceb13d2d05 751
GregCr 6:e7f02929cd3d 752 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 753 {
GregCr 6:e7f02929cd3d 754 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 0:e6ceb13d2d05 755 //RFLR_IRQFLAGS_RXDONE |
GregCr 0:e6ceb13d2d05 756 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 4:f0ce52e94d3f 757 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 0:e6ceb13d2d05 758 RFLR_IRQFLAGS_TXDONE |
GregCr 0:e6ceb13d2d05 759 RFLR_IRQFLAGS_CADDONE |
GregCr 6:e7f02929cd3d 760 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 0:e6ceb13d2d05 761 RFLR_IRQFLAGS_CADDETECTED );
GregCr 6:e7f02929cd3d 762
mluis 13:618826a997e2 763 // DIO0=RxDone, DIO2=FhssChangeChannel
mluis 13:618826a997e2 764 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO2_00 );
GregCr 6:e7f02929cd3d 765 }
GregCr 6:e7f02929cd3d 766 else
GregCr 6:e7f02929cd3d 767 {
GregCr 6:e7f02929cd3d 768 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 6:e7f02929cd3d 769 //RFLR_IRQFLAGS_RXDONE |
GregCr 6:e7f02929cd3d 770 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 6:e7f02929cd3d 771 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 6:e7f02929cd3d 772 RFLR_IRQFLAGS_TXDONE |
GregCr 6:e7f02929cd3d 773 RFLR_IRQFLAGS_CADDONE |
GregCr 8:0fe3e0e8007b 774 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 6:e7f02929cd3d 775 RFLR_IRQFLAGS_CADDETECTED );
GregCr 6:e7f02929cd3d 776
GregCr 6:e7f02929cd3d 777 // DIO0=RxDone
GregCr 6:e7f02929cd3d 778 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
GregCr 6:e7f02929cd3d 779 }
GregCr 0:e6ceb13d2d05 780
GregCr 0:e6ceb13d2d05 781 Write( REG_LR_FIFORXBASEADDR, 0 );
GregCr 0:e6ceb13d2d05 782 Write( REG_LR_FIFOADDRPTR, 0 );
GregCr 0:e6ceb13d2d05 783 }
GregCr 0:e6ceb13d2d05 784 break;
GregCr 0:e6ceb13d2d05 785 }
GregCr 0:e6ceb13d2d05 786
GregCr 0:e6ceb13d2d05 787 memset( rxBuffer, 0, ( size_t )RX_BUFFER_SIZE );
GregCr 0:e6ceb13d2d05 788
GregCr 0:e6ceb13d2d05 789 this->settings.State = RX;
GregCr 0:e6ceb13d2d05 790 if( timeout != 0 )
GregCr 0:e6ceb13d2d05 791 {
GregCr 0:e6ceb13d2d05 792 rxTimeoutTimer.attach_us( this, &SX1276::OnTimeoutIrq, timeout );
GregCr 0:e6ceb13d2d05 793 }
GregCr 0:e6ceb13d2d05 794
GregCr 0:e6ceb13d2d05 795 if( this->settings.Modem == MODEM_FSK )
GregCr 0:e6ceb13d2d05 796 {
GregCr 0:e6ceb13d2d05 797 SetOpMode( RF_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 798
GregCr 0:e6ceb13d2d05 799 if( rxContinuous == false )
GregCr 0:e6ceb13d2d05 800 {
GregCr 0:e6ceb13d2d05 801 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 802 ( ( Read( REG_SYNCCONFIG ) &
GregCr 0:e6ceb13d2d05 803 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
GregCr 0:e6ceb13d2d05 804 1.0 ) + 1.0 ) /
GregCr 0:e6ceb13d2d05 805 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
GregCr 0:e6ceb13d2d05 806 }
GregCr 0:e6ceb13d2d05 807 }
GregCr 0:e6ceb13d2d05 808 else
GregCr 0:e6ceb13d2d05 809 {
GregCr 0:e6ceb13d2d05 810 if( rxContinuous == true )
GregCr 0:e6ceb13d2d05 811 {
GregCr 0:e6ceb13d2d05 812 SetOpMode( RFLR_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 813 }
GregCr 0:e6ceb13d2d05 814 else
GregCr 0:e6ceb13d2d05 815 {
GregCr 0:e6ceb13d2d05 816 SetOpMode( RFLR_OPMODE_RECEIVER_SINGLE );
GregCr 0:e6ceb13d2d05 817 }
GregCr 0:e6ceb13d2d05 818 }
GregCr 0:e6ceb13d2d05 819 }
GregCr 0:e6ceb13d2d05 820
GregCr 0:e6ceb13d2d05 821 void SX1276::Tx( uint32_t timeout )
GregCr 0:e6ceb13d2d05 822 {
GregCr 0:e6ceb13d2d05 823 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 824 {
GregCr 0:e6ceb13d2d05 825 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 826 {
GregCr 0:e6ceb13d2d05 827 // DIO0=PacketSent
GregCr 0:e6ceb13d2d05 828 // DIO1=FifoLevel
GregCr 0:e6ceb13d2d05 829 // DIO2=FifoFull
GregCr 0:e6ceb13d2d05 830 // DIO3=FifoEmpty
GregCr 0:e6ceb13d2d05 831 // DIO4=LowBat
GregCr 0:e6ceb13d2d05 832 // DIO5=ModeReady
GregCr 5:11ec8a6ba4f0 833 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK & RF_DIOMAPPING1_DIO1_MASK &
GregCr 0:e6ceb13d2d05 834 RF_DIOMAPPING1_DIO2_MASK ) );
GregCr 0:e6ceb13d2d05 835
GregCr 0:e6ceb13d2d05 836 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
GregCr 0:e6ceb13d2d05 837 RF_DIOMAPPING2_MAP_MASK ) );
GregCr 0:e6ceb13d2d05 838 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
GregCr 0:e6ceb13d2d05 839 }
GregCr 0:e6ceb13d2d05 840 break;
GregCr 0:e6ceb13d2d05 841 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 842 {
GregCr 6:e7f02929cd3d 843
GregCr 6:e7f02929cd3d 844 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 845 {
GregCr 6:e7f02929cd3d 846 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 6:e7f02929cd3d 847 RFLR_IRQFLAGS_RXDONE |
GregCr 6:e7f02929cd3d 848 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 6:e7f02929cd3d 849 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 6:e7f02929cd3d 850 //RFLR_IRQFLAGS_TXDONE |
GregCr 6:e7f02929cd3d 851 RFLR_IRQFLAGS_CADDONE |
GregCr 6:e7f02929cd3d 852 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 6:e7f02929cd3d 853 RFLR_IRQFLAGS_CADDETECTED );
GregCr 6:e7f02929cd3d 854
GregCr 6:e7f02929cd3d 855 // DIO0=TxDone
GregCr 8:0fe3e0e8007b 856 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
GregCr 6:e7f02929cd3d 857 // DIO2=FhssChangeChannel
GregCr 6:e7f02929cd3d 858 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO2_00 );
GregCr 6:e7f02929cd3d 859 }
GregCr 6:e7f02929cd3d 860 else
GregCr 6:e7f02929cd3d 861 {
GregCr 6:e7f02929cd3d 862 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 0:e6ceb13d2d05 863 RFLR_IRQFLAGS_RXDONE |
GregCr 0:e6ceb13d2d05 864 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 0:e6ceb13d2d05 865 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 0:e6ceb13d2d05 866 //RFLR_IRQFLAGS_TXDONE |
GregCr 0:e6ceb13d2d05 867 RFLR_IRQFLAGS_CADDONE |
GregCr 0:e6ceb13d2d05 868 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 0:e6ceb13d2d05 869 RFLR_IRQFLAGS_CADDETECTED );
GregCr 6:e7f02929cd3d 870
GregCr 6:e7f02929cd3d 871 // DIO0=TxDone
GregCr 6:e7f02929cd3d 872 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
GregCr 6:e7f02929cd3d 873 }
GregCr 0:e6ceb13d2d05 874 }
GregCr 0:e6ceb13d2d05 875 break;
GregCr 0:e6ceb13d2d05 876 }
GregCr 0:e6ceb13d2d05 877
GregCr 0:e6ceb13d2d05 878 this->settings.State = TX;
mluis 13:618826a997e2 879 txTimeoutTimer.attach_us( this, &SX1276::OnTimeoutIrq, timeout );
GregCr 0:e6ceb13d2d05 880 SetOpMode( RF_OPMODE_TRANSMITTER );
GregCr 0:e6ceb13d2d05 881 }
GregCr 0:e6ceb13d2d05 882
GregCr 7:2b555111463f 883 void SX1276::StartCad( void )
GregCr 0:e6ceb13d2d05 884 {
GregCr 7:2b555111463f 885 switch( this->settings.Modem )
GregCr 7:2b555111463f 886 {
GregCr 7:2b555111463f 887 case MODEM_FSK:
GregCr 7:2b555111463f 888 {
GregCr 7:2b555111463f 889
GregCr 7:2b555111463f 890 }
GregCr 7:2b555111463f 891 break;
GregCr 7:2b555111463f 892 case MODEM_LORA:
GregCr 7:2b555111463f 893 {
GregCr 7:2b555111463f 894 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 7:2b555111463f 895 RFLR_IRQFLAGS_RXDONE |
GregCr 7:2b555111463f 896 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 7:2b555111463f 897 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 7:2b555111463f 898 RFLR_IRQFLAGS_TXDONE |
GregCr 7:2b555111463f 899 //RFLR_IRQFLAGS_CADDONE |
GregCr 12:aa5b3bf7fdf4 900 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL // |
GregCr 12:aa5b3bf7fdf4 901 //RFLR_IRQFLAGS_CADDETECTED
GregCr 12:aa5b3bf7fdf4 902 );
GregCr 7:2b555111463f 903
GregCr 7:2b555111463f 904 // DIO3=CADDone
GregCr 7:2b555111463f 905 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
GregCr 7:2b555111463f 906
GregCr 7:2b555111463f 907 this->settings.State = CAD;
GregCr 7:2b555111463f 908 SetOpMode( RFLR_OPMODE_CAD );
GregCr 7:2b555111463f 909 }
GregCr 7:2b555111463f 910 break;
GregCr 7:2b555111463f 911 default:
GregCr 7:2b555111463f 912 break;
GregCr 7:2b555111463f 913 }
GregCr 7:2b555111463f 914 }
GregCr 7:2b555111463f 915
GregCr 7:2b555111463f 916 int16_t SX1276::GetRssi( ModemType modem )
GregCr 7:2b555111463f 917 {
GregCr 7:2b555111463f 918 int16_t rssi = 0;
GregCr 0:e6ceb13d2d05 919
GregCr 0:e6ceb13d2d05 920 switch( modem )
GregCr 0:e6ceb13d2d05 921 {
GregCr 0:e6ceb13d2d05 922 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 923 rssi = -( Read( REG_RSSIVALUE ) >> 1 );
GregCr 0:e6ceb13d2d05 924 break;
GregCr 0:e6ceb13d2d05 925 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 926 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 927 {
GregCr 0:e6ceb13d2d05 928 rssi = RSSI_OFFSET_HF + Read( REG_LR_RSSIVALUE );
GregCr 0:e6ceb13d2d05 929 }
GregCr 0:e6ceb13d2d05 930 else
GregCr 0:e6ceb13d2d05 931 {
GregCr 0:e6ceb13d2d05 932 rssi = RSSI_OFFSET_LF + Read( REG_LR_RSSIVALUE );
GregCr 0:e6ceb13d2d05 933 }
GregCr 0:e6ceb13d2d05 934 break;
GregCr 0:e6ceb13d2d05 935 default:
GregCr 0:e6ceb13d2d05 936 rssi = -1;
GregCr 0:e6ceb13d2d05 937 break;
GregCr 0:e6ceb13d2d05 938 }
GregCr 0:e6ceb13d2d05 939 return rssi;
GregCr 0:e6ceb13d2d05 940 }
GregCr 0:e6ceb13d2d05 941
GregCr 0:e6ceb13d2d05 942 void SX1276::SetOpMode( uint8_t opMode )
GregCr 0:e6ceb13d2d05 943 {
GregCr 0:e6ceb13d2d05 944 if( opMode != previousOpMode )
GregCr 0:e6ceb13d2d05 945 {
GregCr 0:e6ceb13d2d05 946 previousOpMode = opMode;
GregCr 0:e6ceb13d2d05 947 if( opMode == RF_OPMODE_SLEEP )
GregCr 0:e6ceb13d2d05 948 {
GregCr 0:e6ceb13d2d05 949 SetAntSwLowPower( true );
GregCr 0:e6ceb13d2d05 950 }
GregCr 0:e6ceb13d2d05 951 else
GregCr 0:e6ceb13d2d05 952 {
GregCr 0:e6ceb13d2d05 953 SetAntSwLowPower( false );
GregCr 0:e6ceb13d2d05 954 if( opMode == RF_OPMODE_TRANSMITTER )
GregCr 0:e6ceb13d2d05 955 {
GregCr 0:e6ceb13d2d05 956 SetAntSw( 1 );
GregCr 0:e6ceb13d2d05 957 }
GregCr 0:e6ceb13d2d05 958 else
GregCr 0:e6ceb13d2d05 959 {
GregCr 0:e6ceb13d2d05 960 SetAntSw( 0 );
GregCr 0:e6ceb13d2d05 961 }
GregCr 0:e6ceb13d2d05 962 }
GregCr 0:e6ceb13d2d05 963 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RF_OPMODE_MASK ) | opMode );
GregCr 0:e6ceb13d2d05 964 }
GregCr 0:e6ceb13d2d05 965 }
GregCr 0:e6ceb13d2d05 966
GregCr 0:e6ceb13d2d05 967 void SX1276::SetModem( ModemType modem )
GregCr 0:e6ceb13d2d05 968 {
GregCr 4:f0ce52e94d3f 969 if( this->settings.Modem != modem )
GregCr 0:e6ceb13d2d05 970 {
mluis 13:618826a997e2 971 this->settings.Modem = modem;
mluis 13:618826a997e2 972 switch( this->settings.Modem )
mluis 13:618826a997e2 973 {
mluis 13:618826a997e2 974 default:
mluis 13:618826a997e2 975 case MODEM_FSK:
mluis 13:618826a997e2 976 SetOpMode( RF_OPMODE_SLEEP );
mluis 13:618826a997e2 977 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF );
mluis 13:618826a997e2 978
mluis 13:618826a997e2 979 Write( REG_DIOMAPPING1, 0x00 );
mluis 13:618826a997e2 980 Write( REG_DIOMAPPING2, 0x30 ); // DIO5=ModeReady
mluis 13:618826a997e2 981 break;
mluis 13:618826a997e2 982 case MODEM_LORA:
mluis 13:618826a997e2 983 SetOpMode( RF_OPMODE_SLEEP );
mluis 13:618826a997e2 984 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON );
mluis 13:618826a997e2 985 Write( 0x30, 0x00 ); // IF = 0
mluis 13:618826a997e2 986 Write( REG_LR_DETECTOPTIMIZE, ( Read( REG_LR_DETECTOPTIMIZE ) & 0x7F ) ); // Manual IF
mluis 13:618826a997e2 987 Write( REG_DIOMAPPING1, 0x00 );
mluis 13:618826a997e2 988 Write( REG_DIOMAPPING2, 0x00 );
mluis 13:618826a997e2 989 break;
mluis 13:618826a997e2 990 }
GregCr 0:e6ceb13d2d05 991 }
GregCr 0:e6ceb13d2d05 992 }
GregCr 0:e6ceb13d2d05 993
GregCr 0:e6ceb13d2d05 994 void SX1276::OnTimeoutIrq( void )
GregCr 0:e6ceb13d2d05 995 {
GregCr 0:e6ceb13d2d05 996 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 997 {
GregCr 0:e6ceb13d2d05 998 case RX:
GregCr 0:e6ceb13d2d05 999 if( this->settings.Modem == MODEM_FSK )
GregCr 0:e6ceb13d2d05 1000 {
GregCr 0:e6ceb13d2d05 1001 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 1002 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 1003 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 1004 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 1005
GregCr 0:e6ceb13d2d05 1006 // Clear Irqs
GregCr 0:e6ceb13d2d05 1007 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
GregCr 0:e6ceb13d2d05 1008 RF_IRQFLAGS1_PREAMBLEDETECT |
GregCr 0:e6ceb13d2d05 1009 RF_IRQFLAGS1_SYNCADDRESSMATCH );
GregCr 0:e6ceb13d2d05 1010 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
GregCr 0:e6ceb13d2d05 1011
GregCr 0:e6ceb13d2d05 1012 if( this->settings.Fsk.RxContinuous == true )
GregCr 0:e6ceb13d2d05 1013 {
GregCr 0:e6ceb13d2d05 1014 // Continuous mode restart Rx chain
GregCr 0:e6ceb13d2d05 1015 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
GregCr 0:e6ceb13d2d05 1016 }
GregCr 0:e6ceb13d2d05 1017 else
GregCr 0:e6ceb13d2d05 1018 {
GregCr 5:11ec8a6ba4f0 1019 this->settings.State = IDLE;
GregCr 5:11ec8a6ba4f0 1020 rxTimeoutSyncWord.detach( );
GregCr 0:e6ceb13d2d05 1021 }
GregCr 0:e6ceb13d2d05 1022 }
GregCr 0:e6ceb13d2d05 1023 if( ( rxTimeout != NULL ) )
GregCr 0:e6ceb13d2d05 1024 {
GregCr 0:e6ceb13d2d05 1025 rxTimeout( );
GregCr 0:e6ceb13d2d05 1026 }
GregCr 0:e6ceb13d2d05 1027 break;
GregCr 0:e6ceb13d2d05 1028 case TX:
mluis 13:618826a997e2 1029 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1030 if( ( txTimeout != NULL ) )
GregCr 0:e6ceb13d2d05 1031 {
GregCr 0:e6ceb13d2d05 1032 txTimeout( );
GregCr 0:e6ceb13d2d05 1033 }
GregCr 0:e6ceb13d2d05 1034 break;
GregCr 0:e6ceb13d2d05 1035 default:
GregCr 0:e6ceb13d2d05 1036 break;
GregCr 0:e6ceb13d2d05 1037 }
GregCr 0:e6ceb13d2d05 1038 }
GregCr 0:e6ceb13d2d05 1039
GregCr 0:e6ceb13d2d05 1040 void SX1276::OnDio0Irq( void )
GregCr 0:e6ceb13d2d05 1041 {
GregCr 0:e6ceb13d2d05 1042 __IO uint8_t irqFlags = 0;
GregCr 0:e6ceb13d2d05 1043
GregCr 0:e6ceb13d2d05 1044 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1045 {
GregCr 0:e6ceb13d2d05 1046 case RX:
GregCr 0:e6ceb13d2d05 1047 //TimerStop( &RxTimeoutTimer );
GregCr 0:e6ceb13d2d05 1048 // RxDone interrupt
GregCr 0:e6ceb13d2d05 1049 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1050 {
GregCr 0:e6ceb13d2d05 1051 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1052 irqFlags = Read( REG_IRQFLAGS2 );
GregCr 0:e6ceb13d2d05 1053 if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK )
GregCr 0:e6ceb13d2d05 1054 {
GregCr 0:e6ceb13d2d05 1055 // Clear Irqs
GregCr 0:e6ceb13d2d05 1056 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
GregCr 0:e6ceb13d2d05 1057 RF_IRQFLAGS1_PREAMBLEDETECT |
GregCr 0:e6ceb13d2d05 1058 RF_IRQFLAGS1_SYNCADDRESSMATCH );
GregCr 0:e6ceb13d2d05 1059 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
GregCr 0:e6ceb13d2d05 1060
GregCr 0:e6ceb13d2d05 1061 if( this->settings.Fsk.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1062 {
GregCr 0:e6ceb13d2d05 1063 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1064 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 1065 ( ( Read( REG_SYNCCONFIG ) &
GregCr 0:e6ceb13d2d05 1066 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
GregCr 0:e6ceb13d2d05 1067 1.0 ) + 1.0 ) /
GregCr 0:e6ceb13d2d05 1068 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
GregCr 0:e6ceb13d2d05 1069 }
GregCr 0:e6ceb13d2d05 1070 else
GregCr 0:e6ceb13d2d05 1071 {
GregCr 0:e6ceb13d2d05 1072 // Continuous mode restart Rx chain
GregCr 0:e6ceb13d2d05 1073 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
GregCr 0:e6ceb13d2d05 1074 }
GregCr 0:e6ceb13d2d05 1075 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1076
GregCr 0:e6ceb13d2d05 1077 if( ( rxError != NULL ) )
GregCr 0:e6ceb13d2d05 1078 {
GregCr 0:e6ceb13d2d05 1079 rxError( );
GregCr 0:e6ceb13d2d05 1080 }
GregCr 0:e6ceb13d2d05 1081 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 1082 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 1083 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 1084 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 1085 break;
GregCr 0:e6ceb13d2d05 1086 }
GregCr 0:e6ceb13d2d05 1087
GregCr 0:e6ceb13d2d05 1088 // Read received packet size
GregCr 0:e6ceb13d2d05 1089 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
GregCr 0:e6ceb13d2d05 1090 {
GregCr 0:e6ceb13d2d05 1091 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 1092 {
GregCr 0:e6ceb13d2d05 1093 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
GregCr 0:e6ceb13d2d05 1094 }
GregCr 0:e6ceb13d2d05 1095 else
GregCr 0:e6ceb13d2d05 1096 {
GregCr 0:e6ceb13d2d05 1097 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
GregCr 0:e6ceb13d2d05 1098 }
GregCr 0:e6ceb13d2d05 1099 ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1100 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1101 }
GregCr 0:e6ceb13d2d05 1102 else
GregCr 0:e6ceb13d2d05 1103 {
GregCr 0:e6ceb13d2d05 1104 ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1105 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1106 }
GregCr 0:e6ceb13d2d05 1107
GregCr 0:e6ceb13d2d05 1108 if( this->settings.Fsk.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1109 {
GregCr 0:e6ceb13d2d05 1110 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1111 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 1112 ( ( Read( REG_SYNCCONFIG ) &
GregCr 0:e6ceb13d2d05 1113 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
GregCr 0:e6ceb13d2d05 1114 1.0 ) + 1.0 ) /
GregCr 0:e6ceb13d2d05 1115 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
GregCr 0:e6ceb13d2d05 1116 }
GregCr 0:e6ceb13d2d05 1117 else
GregCr 0:e6ceb13d2d05 1118 {
GregCr 0:e6ceb13d2d05 1119 // Continuous mode restart Rx chain
GregCr 0:e6ceb13d2d05 1120 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
GregCr 0:e6ceb13d2d05 1121 }
GregCr 0:e6ceb13d2d05 1122 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1123
GregCr 0:e6ceb13d2d05 1124 if( (rxDone != NULL ) )
GregCr 0:e6ceb13d2d05 1125 {
GregCr 0:e6ceb13d2d05 1126 rxDone( rxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0 );
GregCr 0:e6ceb13d2d05 1127 }
GregCr 0:e6ceb13d2d05 1128 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 1129 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 1130 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 1131 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 1132 break;
GregCr 0:e6ceb13d2d05 1133 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1134 {
GregCr 0:e6ceb13d2d05 1135 uint8_t snr = 0;
GregCr 0:e6ceb13d2d05 1136
GregCr 0:e6ceb13d2d05 1137 // Clear Irq
GregCr 0:e6ceb13d2d05 1138 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE );
GregCr 0:e6ceb13d2d05 1139
GregCr 0:e6ceb13d2d05 1140 irqFlags = Read( REG_LR_IRQFLAGS );
GregCr 0:e6ceb13d2d05 1141 if( ( irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK ) == RFLR_IRQFLAGS_PAYLOADCRCERROR )
GregCr 0:e6ceb13d2d05 1142 {
GregCr 0:e6ceb13d2d05 1143 // Clear Irq
GregCr 0:e6ceb13d2d05 1144 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR );
GregCr 0:e6ceb13d2d05 1145
GregCr 0:e6ceb13d2d05 1146 if( this->settings.LoRa.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1147 {
GregCr 0:e6ceb13d2d05 1148 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1149 }
GregCr 0:e6ceb13d2d05 1150 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1151
GregCr 4:f0ce52e94d3f 1152 if( ( rxError != NULL ) )
GregCr 0:e6ceb13d2d05 1153 {
GregCr 0:e6ceb13d2d05 1154 rxError( );
GregCr 0:e6ceb13d2d05 1155 }
GregCr 0:e6ceb13d2d05 1156 break;
GregCr 0:e6ceb13d2d05 1157 }
GregCr 0:e6ceb13d2d05 1158
GregCr 0:e6ceb13d2d05 1159 this->settings.LoRaPacketHandler.SnrValue = Read( REG_LR_PKTSNRVALUE );
GregCr 0:e6ceb13d2d05 1160 if( this->settings.LoRaPacketHandler.SnrValue & 0x80 ) // The SNR sign bit is 1
GregCr 0:e6ceb13d2d05 1161 {
GregCr 0:e6ceb13d2d05 1162 // Invert and divide by 4
GregCr 0:e6ceb13d2d05 1163 snr = ( ( ~this->settings.LoRaPacketHandler.SnrValue + 1 ) & 0xFF ) >> 2;
GregCr 0:e6ceb13d2d05 1164 snr = -snr;
GregCr 0:e6ceb13d2d05 1165 }
GregCr 0:e6ceb13d2d05 1166 else
GregCr 0:e6ceb13d2d05 1167 {
GregCr 0:e6ceb13d2d05 1168 // Divide by 4
GregCr 0:e6ceb13d2d05 1169 snr = ( this->settings.LoRaPacketHandler.SnrValue & 0xFF ) >> 2;
GregCr 0:e6ceb13d2d05 1170 }
GregCr 0:e6ceb13d2d05 1171
GregCr 7:2b555111463f 1172 int16_t rssi = Read( REG_LR_PKTRSSIVALUE );
GregCr 0:e6ceb13d2d05 1173 if( this->settings.LoRaPacketHandler.SnrValue < 0 )
GregCr 0:e6ceb13d2d05 1174 {
GregCr 0:e6ceb13d2d05 1175 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 1176 {
GregCr 0:e6ceb13d2d05 1177 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 ) +
GregCr 0:e6ceb13d2d05 1178 snr;
GregCr 0:e6ceb13d2d05 1179 }
GregCr 0:e6ceb13d2d05 1180 else
GregCr 0:e6ceb13d2d05 1181 {
GregCr 0:e6ceb13d2d05 1182 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 ) +
GregCr 0:e6ceb13d2d05 1183 snr;
GregCr 0:e6ceb13d2d05 1184 }
GregCr 0:e6ceb13d2d05 1185 }
GregCr 0:e6ceb13d2d05 1186 else
GregCr 0:e6ceb13d2d05 1187 {
GregCr 0:e6ceb13d2d05 1188 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 1189 {
GregCr 0:e6ceb13d2d05 1190 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 );
GregCr 0:e6ceb13d2d05 1191 }
GregCr 0:e6ceb13d2d05 1192 else
GregCr 0:e6ceb13d2d05 1193 {
GregCr 0:e6ceb13d2d05 1194 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 );
GregCr 0:e6ceb13d2d05 1195 }
GregCr 0:e6ceb13d2d05 1196 }
GregCr 0:e6ceb13d2d05 1197
GregCr 0:e6ceb13d2d05 1198 this->settings.LoRaPacketHandler.Size = Read( REG_LR_RXNBBYTES );
GregCr 0:e6ceb13d2d05 1199 ReadFifo( rxBuffer, this->settings.LoRaPacketHandler.Size );
GregCr 0:e6ceb13d2d05 1200
GregCr 0:e6ceb13d2d05 1201 if( this->settings.LoRa.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1202 {
GregCr 0:e6ceb13d2d05 1203 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1204 }
GregCr 0:e6ceb13d2d05 1205 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1206
GregCr 0:e6ceb13d2d05 1207 if( ( rxDone != NULL ) )
GregCr 0:e6ceb13d2d05 1208 {
GregCr 0:e6ceb13d2d05 1209 rxDone( rxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue, this->settings.LoRaPacketHandler.SnrValue );
GregCr 0:e6ceb13d2d05 1210 }
GregCr 0:e6ceb13d2d05 1211 }
GregCr 0:e6ceb13d2d05 1212 break;
GregCr 0:e6ceb13d2d05 1213 default:
GregCr 0:e6ceb13d2d05 1214 break;
GregCr 0:e6ceb13d2d05 1215 }
GregCr 0:e6ceb13d2d05 1216 break;
GregCr 0:e6ceb13d2d05 1217 case TX:
GregCr 0:e6ceb13d2d05 1218 txTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1219 // TxDone interrupt
GregCr 0:e6ceb13d2d05 1220 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1221 {
GregCr 0:e6ceb13d2d05 1222 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1223 // Clear Irq
GregCr 0:e6ceb13d2d05 1224 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE );
GregCr 0:e6ceb13d2d05 1225 // Intentional fall through
GregCr 0:e6ceb13d2d05 1226 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1227 default:
GregCr 0:e6ceb13d2d05 1228 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1229 if( ( txDone != NULL ) )
GregCr 0:e6ceb13d2d05 1230 {
GregCr 0:e6ceb13d2d05 1231 txDone( );
GregCr 0:e6ceb13d2d05 1232 }
GregCr 0:e6ceb13d2d05 1233 break;
GregCr 0:e6ceb13d2d05 1234 }
GregCr 0:e6ceb13d2d05 1235 break;
GregCr 0:e6ceb13d2d05 1236 default:
GregCr 0:e6ceb13d2d05 1237 break;
GregCr 0:e6ceb13d2d05 1238 }
GregCr 0:e6ceb13d2d05 1239 }
GregCr 0:e6ceb13d2d05 1240
GregCr 0:e6ceb13d2d05 1241 void SX1276::OnDio1Irq( void )
GregCr 0:e6ceb13d2d05 1242 {
GregCr 0:e6ceb13d2d05 1243 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1244 {
GregCr 0:e6ceb13d2d05 1245 case RX:
GregCr 0:e6ceb13d2d05 1246 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1247 {
GregCr 0:e6ceb13d2d05 1248 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1249 // FifoLevel interrupt
GregCr 0:e6ceb13d2d05 1250 // Read received packet size
GregCr 0:e6ceb13d2d05 1251 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
GregCr 0:e6ceb13d2d05 1252 {
GregCr 0:e6ceb13d2d05 1253 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 1254 {
GregCr 0:e6ceb13d2d05 1255 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
GregCr 0:e6ceb13d2d05 1256 }
GregCr 0:e6ceb13d2d05 1257 else
GregCr 0:e6ceb13d2d05 1258 {
GregCr 0:e6ceb13d2d05 1259 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
GregCr 0:e6ceb13d2d05 1260 }
GregCr 0:e6ceb13d2d05 1261 }
GregCr 0:e6ceb13d2d05 1262
GregCr 0:e6ceb13d2d05 1263 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.FifoThresh )
GregCr 0:e6ceb13d2d05 1264 {
GregCr 0:e6ceb13d2d05 1265 ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.FifoThresh );
GregCr 0:e6ceb13d2d05 1266 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.FifoThresh;
GregCr 0:e6ceb13d2d05 1267 }
GregCr 0:e6ceb13d2d05 1268 else
GregCr 0:e6ceb13d2d05 1269 {
GregCr 0:e6ceb13d2d05 1270 ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1271 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1272 }
GregCr 0:e6ceb13d2d05 1273 break;
GregCr 0:e6ceb13d2d05 1274 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1275 // Sync time out
GregCr 0:e6ceb13d2d05 1276 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1277 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1278 if( ( rxTimeout != NULL ) )
GregCr 0:e6ceb13d2d05 1279 {
GregCr 0:e6ceb13d2d05 1280 rxTimeout( );
GregCr 0:e6ceb13d2d05 1281 }
GregCr 0:e6ceb13d2d05 1282 break;
GregCr 0:e6ceb13d2d05 1283 default:
GregCr 0:e6ceb13d2d05 1284 break;
GregCr 0:e6ceb13d2d05 1285 }
GregCr 0:e6ceb13d2d05 1286 break;
GregCr 0:e6ceb13d2d05 1287 case TX:
GregCr 0:e6ceb13d2d05 1288 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1289 {
GregCr 0:e6ceb13d2d05 1290 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1291 // FifoLevel interrupt
GregCr 0:e6ceb13d2d05 1292 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.ChunkSize )
GregCr 0:e6ceb13d2d05 1293 {
GregCr 0:e6ceb13d2d05 1294 WriteFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.ChunkSize );
GregCr 0:e6ceb13d2d05 1295 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
GregCr 0:e6ceb13d2d05 1296 }
GregCr 0:e6ceb13d2d05 1297 else
GregCr 0:e6ceb13d2d05 1298 {
GregCr 0:e6ceb13d2d05 1299 // Write the last chunk of data
GregCr 0:e6ceb13d2d05 1300 WriteFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1301 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes;
GregCr 0:e6ceb13d2d05 1302 }
GregCr 0:e6ceb13d2d05 1303 break;
GregCr 0:e6ceb13d2d05 1304 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1305 break;
GregCr 0:e6ceb13d2d05 1306 default:
GregCr 0:e6ceb13d2d05 1307 break;
GregCr 0:e6ceb13d2d05 1308 }
GregCr 0:e6ceb13d2d05 1309 break;
GregCr 0:e6ceb13d2d05 1310 default:
GregCr 0:e6ceb13d2d05 1311 break;
GregCr 0:e6ceb13d2d05 1312 }
GregCr 0:e6ceb13d2d05 1313 }
GregCr 0:e6ceb13d2d05 1314
GregCr 0:e6ceb13d2d05 1315 void SX1276::OnDio2Irq( void )
GregCr 0:e6ceb13d2d05 1316 {
GregCr 0:e6ceb13d2d05 1317 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1318 {
GregCr 0:e6ceb13d2d05 1319 case RX:
GregCr 0:e6ceb13d2d05 1320 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1321 {
GregCr 0:e6ceb13d2d05 1322 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1323 if( ( this->settings.FskPacketHandler.PreambleDetected == true ) && ( this->settings.FskPacketHandler.SyncWordDetected == false ) )
GregCr 0:e6ceb13d2d05 1324 {
GregCr 0:e6ceb13d2d05 1325 rxTimeoutSyncWord.detach( );
GregCr 0:e6ceb13d2d05 1326
GregCr 0:e6ceb13d2d05 1327 this->settings.FskPacketHandler.SyncWordDetected = true;
GregCr 0:e6ceb13d2d05 1328
GregCr 0:e6ceb13d2d05 1329 this->settings.FskPacketHandler.RssiValue = -( Read( REG_RSSIVALUE ) >> 1 );
GregCr 0:e6ceb13d2d05 1330
GregCr 0:e6ceb13d2d05 1331 this->settings.FskPacketHandler.AfcValue = ( int32_t )( double )( ( ( uint16_t )Read( REG_AFCMSB ) << 8 ) |
GregCr 0:e6ceb13d2d05 1332 ( uint16_t )Read( REG_AFCLSB ) ) *
GregCr 0:e6ceb13d2d05 1333 ( double )FREQ_STEP;
GregCr 0:e6ceb13d2d05 1334 this->settings.FskPacketHandler.RxGain = ( Read( REG_LNA ) >> 5 ) & 0x07;
GregCr 0:e6ceb13d2d05 1335 }
GregCr 0:e6ceb13d2d05 1336 break;
GregCr 0:e6ceb13d2d05 1337 case MODEM_LORA:
GregCr 6:e7f02929cd3d 1338 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 1339 {
GregCr 6:e7f02929cd3d 1340 // Clear Irq
GregCr 6:e7f02929cd3d 1341 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
GregCr 6:e7f02929cd3d 1342
mluis 13:618826a997e2 1343 if( ( fhssChangeChannel != NULL ) )
mluis 13:618826a997e2 1344 {
mluis 13:618826a997e2 1345 fhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
mluis 13:618826a997e2 1346 }
GregCr 6:e7f02929cd3d 1347 }
GregCr 0:e6ceb13d2d05 1348 break;
GregCr 0:e6ceb13d2d05 1349 default:
GregCr 0:e6ceb13d2d05 1350 break;
GregCr 0:e6ceb13d2d05 1351 }
GregCr 0:e6ceb13d2d05 1352 break;
GregCr 0:e6ceb13d2d05 1353 case TX:
GregCr 0:e6ceb13d2d05 1354 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1355 {
GregCr 0:e6ceb13d2d05 1356 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1357 break;
GregCr 0:e6ceb13d2d05 1358 case MODEM_LORA:
GregCr 6:e7f02929cd3d 1359 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 1360 {
GregCr 6:e7f02929cd3d 1361 // Clear Irq
GregCr 6:e7f02929cd3d 1362 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
GregCr 6:e7f02929cd3d 1363
mluis 13:618826a997e2 1364 if( ( fhssChangeChannel != NULL ) )
mluis 13:618826a997e2 1365 {
mluis 13:618826a997e2 1366 fhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
mluis 13:618826a997e2 1367 }
GregCr 6:e7f02929cd3d 1368 }
GregCr 0:e6ceb13d2d05 1369 break;
GregCr 0:e6ceb13d2d05 1370 default:
GregCr 0:e6ceb13d2d05 1371 break;
GregCr 0:e6ceb13d2d05 1372 }
GregCr 0:e6ceb13d2d05 1373 break;
GregCr 0:e6ceb13d2d05 1374 default:
GregCr 0:e6ceb13d2d05 1375 break;
GregCr 0:e6ceb13d2d05 1376 }
GregCr 0:e6ceb13d2d05 1377 }
GregCr 0:e6ceb13d2d05 1378
GregCr 0:e6ceb13d2d05 1379 void SX1276::OnDio3Irq( void )
GregCr 0:e6ceb13d2d05 1380 {
GregCr 0:e6ceb13d2d05 1381 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1382 {
GregCr 0:e6ceb13d2d05 1383 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1384 break;
GregCr 0:e6ceb13d2d05 1385 case MODEM_LORA:
mluis 13:618826a997e2 1386 if( ( Read( REG_LR_IRQFLAGS ) & 0x01 ) == 0x01 )
mluis 13:618826a997e2 1387 {
mluis 13:618826a997e2 1388 // Clear Irq
mluis 13:618826a997e2 1389 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED_MASK | RFLR_IRQFLAGS_CADDONE);
mluis 13:618826a997e2 1390 if( ( cadDone != NULL ) )
mluis 13:618826a997e2 1391 {
mluis 13:618826a997e2 1392 cadDone( true );
mluis 13:618826a997e2 1393 }
GregCr 12:aa5b3bf7fdf4 1394 }
GregCr 12:aa5b3bf7fdf4 1395 else
mluis 13:618826a997e2 1396 {
mluis 13:618826a997e2 1397 // Clear Irq
mluis 13:618826a997e2 1398 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE );
mluis 13:618826a997e2 1399 if( ( cadDone != NULL ) )
mluis 13:618826a997e2 1400 {
mluis 13:618826a997e2 1401 cadDone( false );
mluis 13:618826a997e2 1402 }
GregCr 7:2b555111463f 1403 }
GregCr 0:e6ceb13d2d05 1404 break;
GregCr 0:e6ceb13d2d05 1405 default:
GregCr 0:e6ceb13d2d05 1406 break;
GregCr 0:e6ceb13d2d05 1407 }
GregCr 0:e6ceb13d2d05 1408 }
GregCr 0:e6ceb13d2d05 1409
GregCr 0:e6ceb13d2d05 1410 void SX1276::OnDio4Irq( void )
GregCr 0:e6ceb13d2d05 1411 {
GregCr 0:e6ceb13d2d05 1412 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1413 {
GregCr 0:e6ceb13d2d05 1414 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1415 {
GregCr 0:e6ceb13d2d05 1416 if( this->settings.FskPacketHandler.PreambleDetected == false )
GregCr 0:e6ceb13d2d05 1417 {
GregCr 0:e6ceb13d2d05 1418 this->settings.FskPacketHandler.PreambleDetected = true;
GregCr 0:e6ceb13d2d05 1419 }
GregCr 0:e6ceb13d2d05 1420 }
GregCr 0:e6ceb13d2d05 1421 break;
GregCr 0:e6ceb13d2d05 1422 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1423 break;
GregCr 0:e6ceb13d2d05 1424 default:
GregCr 0:e6ceb13d2d05 1425 break;
GregCr 0:e6ceb13d2d05 1426 }
GregCr 0:e6ceb13d2d05 1427 }
GregCr 0:e6ceb13d2d05 1428
GregCr 0:e6ceb13d2d05 1429 void SX1276::OnDio5Irq( void )
GregCr 0:e6ceb13d2d05 1430 {
GregCr 0:e6ceb13d2d05 1431 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1432 {
GregCr 0:e6ceb13d2d05 1433 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1434 break;
GregCr 0:e6ceb13d2d05 1435 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1436 break;
GregCr 0:e6ceb13d2d05 1437 default:
GregCr 0:e6ceb13d2d05 1438 break;
GregCr 0:e6ceb13d2d05 1439 }
mluis 13:618826a997e2 1440 }